Semiconductor device and manufacturing method thereof, power module, power conversion circuit, and vehicle

Abstract

The embodiment of the invention discloses a semiconductor device, a manufacturing method, a power module, a power conversion circuit and a vehicle. The manufacturing method of the semiconductor device comprises the steps of providing a first semiconductor body; forming an alignment mark on the second surface; forming a first area on the first surface according to the alignment mark; forming a second semiconductor body on one side of the first semiconductor body away from the second surface at least once; forming a second region on the surface of the second semiconductor body according to the alignment mark; forming a first electrode structure; and forming a second electrode structure. According to the embodiment of the invention, the alignment mark and the second semiconductor body are arranged on different surfaces of the first semiconductor body, so that the existence of the alignment mark imprint does not cause secondary defects in the forming process of the second semiconductor body, and the preset lattice structure and crystal orientation of the second semiconductor body are not influenced; and the influence of the alignment mark on the electrical performance of the semiconductor device is avoided.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a semiconductor device and a manufacturing method thereof, a power module, a power conversion circuit and a vehicle. Background Art

[0002] Semiconductor devices made of third-generation wide bandgap semiconductor materials such as silicon carbide (SiC) and gallium nitride (GaN) have broader application prospects than silicon semiconductor devices due to their wide bandgap, high critical breakdown field strength, high thermal conductivity and high carrier saturation rate.

[0003] In the above-mentioned semiconductor device, the semiconductor body is formed multiple times, and after each formation of the semiconductor body, the doping region of the entire semiconductor body is prepared by forming the doping region in the semiconductor body through an ion doping process. The doping region formed by the latter ion doping process needs to be able to constitute a continuous doping region with the doping region formed by the previous ion doping process, so it is necessary to accurately align the semiconductor body according to the alignment mark before the ion doping process. However, the surface of the side of the bottom semiconductor body where ion doping is performed is provided with an alignment mark. The presence of the mark of the alignment mark will cause secondary defects in the semiconductor body formed subsequently, thereby failing to ensure that the semiconductor device has good electrical properties. Summary of the invention

[0004] The present invention provides a semiconductor device and a manufacturing method, a power module, a power conversion circuit and a vehicle, so as to avoid defects in a semiconductor body caused by the presence of an alignment mark, thereby avoiding the influence on the electrical performance of the semiconductor device.

[0005] According to one aspect of the present invention, there is provided a method for manufacturing a semiconductor device, the method comprising:

[0006] Providing a first semiconductor body, comprising a first surface and a second surface arranged opposite to each other;

[0007] forming at least one alignment mark on the second surface of the first semiconductor body;

[0008] According to the alignment mark, a first region is formed on the first surface of the first semiconductor body, wherein the positions of the first region and the alignment mark are arranged in a one-to-one correspondence;

[0009] forming a second semiconductor body at least once on a side of the first surface of the first semiconductor body away from the second surface;

[0010] After forming the second semiconductor body on the side of the first surface of the first semiconductor body away from the second surface each time, the method further includes: forming a second region on the surface of the second semiconductor body away from the first semiconductor body according to the alignment mark, wherein the positions of the second region and the alignment mark are arranged in a one-to-one correspondence;

[0011] forming a first electrode structure on a side of the second semiconductor body away from the first semiconductor body;

[0012] A second electrode structure is formed on a side of the first semiconductor body away from the second semiconductor body.

[0013] Optionally, before forming the second electrode structure on the side of the first semiconductor body away from the second semiconductor body, the method further includes:

[0014] The second surface of the first semiconductor body is thinned to remove the alignment mark.

[0015] Optionally, forming at least one alignment mark on the second surface of the first semiconductor body includes:

[0016] At least one pattern is formed on the second surface of the first semiconductor body by a laser marking process to form at least one alignment mark.

[0017] Optionally, forming at least one alignment mark on the second surface of the first semiconductor body includes:

[0018] At least one third region is formed on the second surface of the first semiconductor body to form at least one alignment mark.

[0019] Optionally, the first area and the second area are arranged continuously.

[0020] Optionally, the semiconductor device is a metal oxide semiconductor field effect transistor;

[0021] The first region and the second region constitute a well region and / or an active region.

[0022] Optionally, the semiconductor device is a Schottky barrier diode;

[0023] The first region and the second region constitute an active region.

[0024] Optionally, forming a first electrode structure on a side of the second semiconductor body away from the first semiconductor body includes:

[0025] A gate structure is formed on a side of the second semiconductor body away from the first semiconductor body, the gate structure includes a planar gate structure or a trench gate structure, the planar gate structure is located on a surface of the second semiconductor body away from the first semiconductor body, and the trench gate structure extends from the surface of the second semiconductor body away from the first semiconductor body into the second semiconductor body;

[0026] A source structure is formed on a side of the first semiconductor body away from the second semiconductor body, the source structure comprising a planar source structure or a trench source structure, the planar source structure is located on a surface of the second semiconductor body away from the first semiconductor body, and the trench source structure extends from the surface of the second semiconductor body away from the first semiconductor body into the second semiconductor body;

[0027] Forming a second electrode structure on a side of the first semiconductor body away from the second semiconductor body includes:

[0028] A drain is formed on a side of the first semiconductor body away from the second semiconductor body.

[0029] Optionally, forming a first electrode structure on a side of the second semiconductor body away from the first semiconductor body includes:

[0030] forming an anode on a side of the second semiconductor body away from the first semiconductor body;

[0031] Forming a second electrode structure on a side of the first semiconductor body away from the second semiconductor body includes:

[0032] A cathode is formed on a side of the first semiconductor body remote from the second semiconductor body.

[0033] Optionally, forming at least one alignment mark on the second surface of the first semiconductor body includes:

[0034] At least one alignment mark having a light transmittance different from that of the first semiconductor body is formed on the second surface of the first semiconductor body.

[0035] Optionally, the first semiconductor body and the second semiconductor body both include silicon carbide material;

[0036] Alternatively, the first semiconductor body and the second semiconductor body both include gallium nitride material.

[0037] According to another aspect of the present invention, there is provided a semiconductor device, the semiconductor device comprising:

[0038] A first semiconductor body including a first surface and a second surface arranged opposite to each other;

[0039] The second surface of the first semiconductor body is provided with at least one alignment mark;

[0040] The first surface of the first semiconductor body includes a first region, wherein the first region and the position of the alignment mark are arranged in a one-to-one correspondence;

[0041] At least one layer of second semiconductor body is located on the first surface of the first semiconductor body away from the second surface; the surface of each layer of second semiconductor body away from the first semiconductor body includes a second region, wherein the second region and the position of the alignment mark are arranged in a one-to-one correspondence;

[0042] A first electrode structure is located on a side of the second semiconductor body away from the first semiconductor body;

[0043] The second electrode structure is located at a side of the first semiconductor body away from the second semiconductor body.

[0044] According to another aspect of the present invention, a power module is provided. The power module includes a substrate and any semiconductor device described in the embodiments of the present invention. The substrate is used for carrying the semiconductor device.

[0045] According to another aspect of the present invention, there is provided a power conversion circuit, the power conversion circuit being used for one or more of current conversion, voltage conversion, and power factor correction;

[0046] The power conversion circuit includes a circuit board and at least one semiconductor device as described in any of the embodiments of the present invention, and the semiconductor device is electrically connected to the circuit board.

[0047] According to another aspect of the present invention, a vehicle is provided, comprising a load and a power conversion circuit as described in any of the embodiments of the present invention, wherein the power conversion circuit is used to convert alternating current into direct current, convert alternating current into alternating current, convert direct current into direct current, or convert direct current into alternating current and then input it into the load.

[0048] The semiconductor device and manufacturing method, power module, power conversion circuit and vehicle of the embodiments of the present invention form an alignment mark on the second surface of the first semiconductor body, and the alignment mark and the second semiconductor body are located on different surfaces of the first semiconductor body. During the process of forming the second semiconductor body on one side of the first semiconductor body at least once, the presence of the alignment mark will not cause secondary defects in the formation of the second semiconductor body and will not affect the preset lattice structure and crystal orientation of the second semiconductor body, thereby avoiding the influence of the alignment mark on the electrical properties of the semiconductor device.

[0049] It should be understood that the contents described in this section are not intended to identify the key or important features of the embodiments of the present invention, nor are they intended to limit the scope of the present invention. Other features of the present invention will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0050] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0051] Figure 1 is a flow chart of a method for manufacturing a semiconductor device according to an embodiment of the present invention;

[0052] Figure 2-Figure 6 is a cross-sectional view corresponding to each step of a method for manufacturing a semiconductor device provided according to an embodiment of the present invention;

[0053] Figure 7 is a flow chart of another method for manufacturing a semiconductor device according to an embodiment of the present invention;

[0054] Figure 8-Figure 9 is a cross-sectional view corresponding to each step of another method for manufacturing a semiconductor device provided according to an embodiment of the present invention;

[0055] Fig.10 is a flow chart of another method for manufacturing a semiconductor device according to an embodiment of the present invention;

[0056] Figure 11-Figure 14 It is a cross-sectional view corresponding to each step of another method for manufacturing a semiconductor device provided according to an embodiment of the present invention. DETAILED DESCRIPTION

[0057] In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0058] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0059] In order to prevent the presence of the alignment mark from causing defects in the semiconductor body, thereby preventing the electrical performance of the semiconductor device from being affected, the embodiment of the present invention provides the following technical solution:

[0060] Figure 1 FIG. 1 is a flow chart of a method for manufacturing a semiconductor device according to an embodiment of the present invention. Figure 1 As shown, the method for manufacturing the semiconductor device includes:

[0061] S110 , providing a first semiconductor body, comprising a first surface and a second surface arranged opposite to each other.

[0062] The first semiconductor body may include a third generation wide bandgap semiconductor material such as a silicon carbide semiconductor body or a gallium nitride semiconductor body.

[0063] Specifically, in an embodiment of the present invention, the semiconductor device includes but is not limited to an N-type or P-type metal-oxide-semiconductor field-effect transistor (MOSFET) and a Schottky barrier diode (SBD), wherein the structure of the MOSFET semiconductor device includes at least one of a planar type, a single trench, and a double trench.

[0064] For example, in this embodiment, an N-type SBD semiconductor device is taken as an example for description. Figure 2 , the first semiconductor body 10 includes a first surface 101 and a second surface 102 disposed opposite to the first surface 101. Figure 2As shown, the first semiconductor body 10 includes a substrate 300 and an epitaxial layer 301. In some embodiments of the present invention, the first semiconductor body 10 may also include only the epitaxial layer 301. In other embodiments of the present invention, the first semiconductor body 10 may also include a substrate 300 and a semiconductor layer formed by other processes. Among them, the epitaxial layer 301 is a semiconductor layer formed by a single epitaxial process on the basis of the substrate 300, and the epitaxial process includes chemical vapor epitaxy (CVE), molecular beam epitaxy (MBD) and atomic layer epitaxy (ALE) and other processes.

[0065] S120 , forming at least one alignment mark on the second surface of the first semiconductor body.

[0066] Specifically, refer to Figure 2 , at least one alignment mark 20 is formed on the second surface 102 of the first semiconductor body 10. Exemplarily, Figure 2 Four alignment marks 20 formed on the second surface 102 of the first semiconductor body 10 are shown.

[0067] Optionally, the alignment mark 20 may be formed by laser marking or ion doping process to ensure that the transmittance of the alignment mark 20 is different from the transmittance of the first semiconductor body 10 , so as to facilitate the subsequent identification of the alignment mark 20 .

[0068] During the laser marking process, a high-energy laser is used to locally irradiate the second surface 102 of the first semiconductor body 10, causing the surface material to vaporize or undergo a chemical reaction that causes a color change, thereby forming at least one pattern to complete the preparation process of at least one alignment mark 20.

[0069] During the ion doping process, at least one third region is formed on the second surface 102 of the first semiconductor body 10 by ion implantation, ion diffusion or vapor deposition, so as to form at least one alignment mark 20 .

[0070] S130 . Form a first region on the first surface of the first semiconductor body according to the alignment mark, wherein the positions of the first region and the alignment mark are arranged in a one-to-one correspondence.

[0071] refer to Figure 3According to the alignment mark 20, the doping position of the first region 302 can be obtained, and then the first region 302 corresponding to the position of the alignment mark 20 is formed on the first surface 101 of the first semiconductor body 10 by ion implantation, ion diffusion or vapor deposition plasma doping process. Wherein, when the first semiconductor body 10 includes silicon carbide material, the first semiconductor body 10 is a transparent material, and the alignment mark 20 can be identified on the first surface 101 of the first semiconductor body 10. In other embodiments of the present invention, when the first semiconductor body 10 includes gallium nitride material, the alignment mark 20 can be identified by an image acquisition device.

[0072] S140 , forming a second semiconductor body at least once on a side of the first surface of the first semiconductor body away from the second surface.

[0073] For example, the second semiconductor body 303 may include an epitaxial layer. Figure 4 A second semiconductor body 303 is formed on a side of the first surface 101 of the first semiconductor body 10 away from the second surface 102 by an epitaxial process.

[0074] Specifically, an alignment mark 20 is formed on the second surface 102 of the first semiconductor body 10, and the alignment mark 20 and the second semiconductor body 303 are located on different surfaces of the first semiconductor body 10. During the process of forming the second semiconductor body 303 on one side of the first semiconductor body 10 at least once, the presence of the imprint of the alignment mark 20 will not cause secondary defects to be generated during the formation of the second semiconductor body 303, that is, the presence of the alignment mark 20 will not affect the lattice structure and crystal orientation of the second semiconductor body 303.

[0075] S150, each time after forming the second semiconductor body on the side of the first surface of the first semiconductor body away from the second surface, it also includes: forming a second region on the surface of the second semiconductor body away from the first semiconductor body according to the alignment mark, wherein the positions of the second region and the alignment mark are arranged in one-to-one correspondence.

[0076] refer to Figure 5 ,exist Figure 4 On the basis of the structure shown, according to the alignment mark 20, the doping position of the second region 304 can be obtained, and through ion implantation, ion diffusion or vapor deposition plasma doping process, a second region 304 is formed on the surface of the second semiconductor body 303 away from the first semiconductor body 10 and is arranged one-to-one with the position of the alignment mark 20.

[0077] It should be noted that the first area 302 and the second area 304 may be arranged continuously or discontinuously. For example, in the drawings of this embodiment, the first area 302 and the second area 304 are arranged continuously.

[0078] When the first semiconductor body 10 and the second semiconductor body 303 both include third-generation wide bandgap semiconductor materials such as a silicon carbide semiconductor body or a gallium nitride semiconductor body, due to the high hardness of the material itself, after each formation of the second semiconductor body 303, a second region 304 is formed on the second semiconductor body 303, thereby improving the formation quality of the doped region formed each time and reducing the difficulty of forming the doped region each time.

[0079] The orthographic projection of the alignment mark 20 on the first semiconductor body 10 may overlap with the orthographic projection of the first region 302 or the second region 304 on the first semiconductor body 10. Exemplarily, the orthographic projection of the first region 302 or the second region 304 on the first semiconductor body 10 is a 2mm*2mm square, and the orthographic projection of the alignment mark 20 on the first semiconductor body 10 is a 2mm*2mm square. In other optional embodiments of the present invention, the orthographic projection of the alignment mark 20 on the first semiconductor body 10 may also be a "cross" or "rice". The orthographic projection of the alignment mark 20 on the first semiconductor body 10 is not specifically limited here.

[0080] It should be noted that the drawings of the embodiments of the present invention exemplarily show a scheme of forming the second semiconductor body 303 once on the side of the first surface 101 of the first semiconductor body 10 away from the second surface 102. In other embodiments, the number of times the second semiconductor body 303 is formed on one side of the first semiconductor body 10 can be increased, and the number of second regions 304 formed can be increased.

[0081] Exemplarily, for an N-type SBD semiconductor device, the conductivity types of the first semiconductor body 10 and the second semiconductor body 303 are both N-type. The first region 302 and the second region 304 form a continuous P-type doping region.

[0082] In other embodiments of the present invention, for a P-type SBD semiconductor device, the conductivity types of the first semiconductor body 10 and the second semiconductor body 303 are both P-type. The first region 302 and the second region 304 form a continuous N-type doping region.

[0083] S160 , forming a first electrode structure on a side of the second semiconductor body away from the first semiconductor body.

[0084] refer to Figure 6 A first electrode structure 60 is formed on a side of the second semiconductor body 303 away from the first semiconductor body 10. For example, for a SBD semiconductor device, the first electrode structure 60 is an anode.

[0085] S170 , forming a second electrode structure on a side of the first semiconductor body away from the second semiconductor body.

[0086] refer to Figure 6 A second electrode structure 70 is formed on a side of the first semiconductor body 10 away from the second semiconductor body 303. For example, for a SBD semiconductor device, the second electrode structure 70 is a cathode.

[0087] According to the technical solution of the embodiment of the present invention, an alignment mark 20 is formed on the second surface 102 of the first semiconductor body 10, and the alignment mark 20 and the second semiconductor body 303 are located on different surfaces of the first semiconductor body 10. In the process of forming the second semiconductor body 303 on one side of the first semiconductor body 10 at least once, the presence of the mark of the alignment mark 20 will not cause secondary defects in the process of forming the second semiconductor body 303 and will not affect the preset lattice structure and crystal orientation of the second semiconductor body 303, thereby avoiding the influence of the alignment mark 20 on the electrical properties of the semiconductor device. At the same time, according to the alignment mark 20, the first region 302 and at least one second region 304 can also be formed, which reduces the difficulty of forming the doped region each time and improves the formation quality of the doped region.

[0088] Figure 7 FIG. 1 is a flow chart of another method for manufacturing a semiconductor device according to an embodiment of the present invention. Based on the above technical solution, the embodiment of the present invention thins the first semiconductor body and removes the alignment mark before forming the second electrode structure. Figure 7 As shown, the method for manufacturing the semiconductor device includes:

[0089] S210 , providing a first semiconductor body, comprising a first surface and a second surface arranged opposite to each other.

[0090] refer to Figure 2 The first semiconductor body 10 includes a first surface 101 and a second surface 102 arranged opposite to the first surface 101 .

[0091] S220 , forming at least one alignment mark on the second surface of the first semiconductor body.

[0092] refer to Figure 2 , at least one alignment mark 20 is formed on the second surface 102 of the first semiconductor body 10. Exemplarily, Figure 2 Four alignment marks 20 formed on the second surface 102 of the first semiconductor body 10 are shown.

[0093] Optionally, the alignment mark 20 can be formed by laser marking or plasma doping processes such as ion implantation, ion diffusion or vapor deposition to ensure that the transmittance of the alignment mark 20 is different from the transmittance of the first semiconductor body 10 to facilitate subsequent identification of the alignment mark 20.

[0094] S230 . Form a first region on the first surface of the first semiconductor body according to the alignment mark, wherein the positions of the first region and the alignment mark are arranged in a one-to-one correspondence.

[0095] refer to Figure 3 According to the alignment mark 20, the doping position of the first region 302 can be obtained, and then the first region 302 corresponding to the position of the alignment mark 20 is formed on the first surface 101 of the first semiconductor body 10 through ion implantation, ion diffusion or vapor deposition plasma doping process.

[0096] S240 , forming a second semiconductor body at least once on a side of the first surface of the first semiconductor body away from the second surface.

[0097] For example, the second semiconductor body 303 may include an epitaxial layer. Figure 4 A second semiconductor body 303 is formed on a side of the first surface 101 of the first semiconductor body 10 away from the second surface 102 by an epitaxial process.

[0098] Specifically, an alignment mark 20 is formed on the second surface 102 of the first semiconductor body 10, and the alignment mark 20 and the second semiconductor body 303 are located on different surfaces of the first semiconductor body 10. At least once in the process of forming the second semiconductor body 303 on one side of the first semiconductor body 10, the presence of the alignment mark 20 will not cause secondary defects in the formation of the second semiconductor body 303, that is, the presence of the alignment mark 20 will not affect the lattice structure and crystal orientation of the second semiconductor body 303.

[0099] S250, each time after forming the second semiconductor body on the side of the first surface of the first semiconductor body away from the second surface, it also includes: forming a second region on the surface of the second semiconductor body away from the first semiconductor body according to the alignment mark, wherein the positions of the second region and the alignment mark are arranged in one-to-one correspondence.

[0100] refer to Figure 5 ,exist Figure 4 On the basis of the structure shown, according to the alignment mark 20, the doping position of the second region 304 can be obtained, and through ion implantation, ion diffusion or vapor deposition plasma doping process, a second region 304 is formed on the surface of the second semiconductor body 303 away from the first semiconductor body 10 and is arranged one-to-one with the position of the alignment mark 20.

[0101] It should be noted that the first area 302 and the second area 304 may be arranged continuously or discontinuously. For example, in the drawings of this embodiment, the first area 302 and the second area 304 are arranged continuously.

[0102] S260 , forming a first electrode structure on a side of the second semiconductor body away from the first semiconductor body.

[0103] refer to Figure 6 A first electrode structure 60 is formed on a side of the second semiconductor body 303 away from the first semiconductor body 10. For example, for a SBD semiconductor device, the first electrode structure 60 is an anode.

[0104] S270 , thinning the second surface of the first semiconductor body to remove the alignment mark.

[0105] Specifically, refer to Figure 8 Before forming the second electrode structure 70 on the side of the first semiconductor body 10 away from the second semiconductor body 303 , the second surface 102 of the first semiconductor body 10 is thinned to remove the alignment mark 20 .

[0106] S280 , forming a second electrode structure on a side of the first semiconductor body away from the second semiconductor body.

[0107] refer to Fig. 9 A second electrode structure 70 is formed on a side of the first semiconductor body 10 away from the second semiconductor body 303 .

[0108] On the basis of the above technical solution, before forming the second electrode structure 70 on the side of the first semiconductor body 10 away from the second semiconductor body 303, the alignment mark 20 on the side of the first semiconductor body 10 away from the second semiconductor body 303 is thinned and removed, thereby reducing the conductive resistance of the semiconductor device and improving the formation quality of the second electrode structure 70.

[0109] The manufacturing method of the semiconductor device is introduced by taking a Schottky barrier diode semiconductor device as an example. Figure 6 and Fig. 9 As shown, the first region 302 and the second region 304 constitute an active region.

[0110] The semiconductor device is a MOSFET semiconductor device as an example for description below. The first region 302 and the second region 304 constitute a well region and / or an active region.

[0111] Fig.10 FIG. 1 is a flow chart of another method for manufacturing a semiconductor device according to an embodiment of the present invention. Fig.10 As shown, the method for manufacturing the semiconductor device includes:

[0112] S310 , providing a first semiconductor body, comprising a first surface and a second surface arranged opposite to each other.

[0113] The first semiconductor body 10 may include a third generation wide bandgap semiconductor material such as a silicon carbide semiconductor body or a gallium nitride semiconductor body.

[0114] For example, in the embodiments of the present invention, an N-type MOSFET semiconductor device is taken as an example for description. Fig.11 As shown, the first semiconductor body 10 includes a substrate 300 and an epitaxial layer 301. In some embodiments of the present invention, the first semiconductor body 10 may also include only the epitaxial layer 301. In other embodiments of the present invention, the first semiconductor body 10 may also include a substrate 300 and a semiconductor layer formed by other processes. Among them, the epitaxial layer 301 is a semiconductor layer formed by a single epitaxial process on the basis of the substrate 300.

[0115] S320 , forming at least one alignment mark on the second surface of the first semiconductor body.

[0116] like Fig.11 As shown, at least one alignment mark 20 is formed on the second surface 102 of the first semiconductor body 10 by laser marking or ion doping process. Exemplarily, Fig.11 Two alignment marks 20 are shown formed on the second surface 102 of the first semiconductor body 10. The ion doping process includes ion implantation, ion diffusion or vapor deposition.

[0117] S330 , forming a first region on the first surface of the first semiconductor body according to the alignment mark, wherein the positions of the first region and the alignment mark are arranged in a one-to-one correspondence.

[0118] refer to Fig.11 According to the alignment mark 20, the doping position of the first region 302 can be obtained, and then the first region 302, ie, the first P-type doped well region, is formed on the side of the epitaxial layer 301 away from the substrate 300 through ion implantation, ion diffusion or vapor deposition plasma doping process.

[0119] S340 , forming a second semiconductor body at least once on a side of the first surface of the first semiconductor body away from the second surface.

[0120] refer to Fig.12 A second semiconductor body 303 is formed on a side of the first semiconductor body 10 away from the substrate 300. For example, the second semiconductor body 303 may include an epitaxial layer.

[0121] S350, each time after forming the second semiconductor body on the side of the first surface of the first semiconductor body away from the second surface, it also includes: forming a second region on the surface of the second semiconductor body away from the first semiconductor body according to the alignment mark, wherein the positions of the second region and the alignment mark are arranged in a one-to-one correspondence.

[0122] refer to Fig.13 According to the alignment mark 20, the doping position of the second region 304 can be obtained, and then the second region 304, i.e., the second P-type doped well region, is formed in the second semiconductor body 303 by ion implantation, ion diffusion or vapor deposition plasma doping process. The first P-type doped well region and the second P-type doped well region constitute a continuous well region, i.e., the well region needs to be doped multiple times.

[0123] In the embodiment of the present invention, the semiconductor device is a MOSFET as an example, and the first region 302 and the second region 304 constitute a continuous well region as an example for description. In some embodiments of the present invention, the first region 302 and the second region 304 constitute a continuous active region, that is, the active region needs to be doped multiple times. In other embodiments of the present invention, the first region 302 and the second region 304 constitute a well region and an active region, that is, both the well region and the active region need to be doped multiple times to obtain.

[0124] refer to Fig.14 After the well region is prepared, an N+ active region 305 needs to be formed in the well region.

[0125] refer to Fig.14 Before forming the first electrode structure 60 , a P+ active region 306 is formed by photolithography, etching, ion implantation and other processes.

[0126] S360. Form a gate structure on a side of the second semiconductor body away from the first semiconductor body. The gate structure includes a planar gate structure or a trench gate structure. The planar gate structure is located on a surface of the second semiconductor body away from the first semiconductor body. The trench gate structure extends from the surface of the second semiconductor body away from the first semiconductor body to the second semiconductor body.

[0127] refer to Fig.14 , a first electrode structure 60 is formed on a side of the first semiconductor body 10 away from the substrate 300. Exemplarily, for a MOSFET semiconductor device, the first electrode structure 60 includes a gate structure 601 and a source structure 602. The gate structure 601 includes a first insulating layer 6011 and a gate electrode 6012. An interlayer dielectric layer 6013 is used to insulate and space the gate electrode 6012 and the source structure 602. The material of the gate electrode 6012 can be polysilicon.

[0128] S370. Form a source structure on a side of the first semiconductor body away from the second semiconductor body. The source structure includes a planar source structure or a trench source structure. The planar source structure is located on a surface of the second semiconductor body away from the first semiconductor body. The trench source structure extends from the surface of the second semiconductor body away from the first semiconductor body to the second semiconductor body.

[0129] refer to Fig.14 The source structure 602 includes a second insulating layer 6021 , a polysilicon filling layer 6022 and a source metal layer 6023 . Fig.14 A trench type source structure 602 is shown.

[0130] S380 , forming a drain on a side of the first semiconductor body away from the second semiconductor body.

[0131] refer to Fig.14 A second electrode structure 70 is formed on a side of the first semiconductor body 10 away from the second semiconductor body 303. For example, for an N-type MOSFET, the second electrode structure 70 is a drain electrode. The material of the drain electrode may include titanium, nickel or silver.

[0132] Optional, reference Fig.14 Before forming the second electrode structure 70 on the side of the first semiconductor body 10 away from the second semiconductor body 303, the second surface 102 of the first semiconductor body 10 is thinned to remove the alignment mark, thereby reducing the conductive resistance of the semiconductor device and improving the formation quality of the second electrode structure 70.

[0133] Optionally, the first semiconductor body 10 and the second semiconductor body 303 both include silicon carbide materials, and the MOSFET semiconductor device is a silicon carbide MOSFET semiconductor device. Alternatively, the first semiconductor body 10 and the second semiconductor body 303 both include gallium nitride materials, and the MOSFET semiconductor device is a gallium nitride MOSFET semiconductor device.

[0134] Silicon carbide MOSFET semiconductor devices or gallium nitride MOSFET semiconductor devices have the advantages of high withstand voltage, low on-resistance and high frequency, which can further improve the performance of semiconductor devices.

[0135] An embodiment of the present invention provides a semiconductor device. Figure 6Taking the semiconductor device shown as an example, the semiconductor device includes: a first semiconductor body 10, including a first surface 101 and a second surface 102 arranged opposite to each other; the second surface 102 of the first semiconductor body 10 is provided with at least one alignment mark 20; the first surface 101 of the first semiconductor body 10 includes a first area 302, wherein the positions of the first area 302 and the alignment mark 20 are arranged in a one-to-one correspondence; at least one layer of second semiconductor body 303 is located on the first surface 101 of the first semiconductor body 10 away from the second surface 102; the surface of each layer of the second semiconductor body 303 away from the first semiconductor body 10 includes a second area 304, wherein the second area 304 and the position of the alignment mark 20 are arranged in a one-to-one correspondence; a first electrode structure 60 is located on a side of the second semiconductor body 303 away from the first semiconductor body 10; and a second electrode structure 70 is located on a side of the first semiconductor body 10 away from the second semiconductor body 303.

[0136] In the semiconductor device of the embodiment of the present invention, an alignment mark 20 is formed on the second surface 102 of the first semiconductor body 10, and the alignment mark 20 and the second semiconductor body 303 are located on different surfaces of the first semiconductor body 10. During the process of forming the second semiconductor body 303 on one side of the first semiconductor body 10 at least once, the presence of the imprint of the alignment mark 20 will not cause secondary defects in the formation process of the second semiconductor body 303 and will not affect the preset lattice structure and crystal orientation of the second semiconductor body 303, thereby avoiding the influence of the alignment mark 20 on the electrical properties of the semiconductor device.

[0137] An embodiment of the present invention provides a power module, comprising a substrate and at least one semiconductor device according to any embodiment of the present invention, wherein the substrate is used to carry the semiconductor device. Therefore, the beneficial effects of the power module including any semiconductor device according to any embodiment of the present invention are not described in detail here.

[0138] An embodiment of the present invention provides a power conversion circuit, which is used for one or more of current conversion, voltage conversion, and power factor correction; the power conversion circuit includes a circuit board and at least one semiconductor device described in any embodiment of the present invention, and the semiconductor device is electrically connected to the circuit board.

[0139] Therefore, the power conversion circuit includes the beneficial effects of any semiconductor device described in any embodiment of the present invention, which will not be repeated here.

[0140] An embodiment of the present invention further provides a vehicle, comprising a load and the power conversion circuit described in any embodiment of the present invention, wherein the power conversion circuit is used to convert AC power and / or DC power into AC power and / or DC power and then input it into the load.

[0141] It should be understood that the various forms of processes shown above can be used to reorder, add or delete steps. For example, the steps described in the present invention can be executed in parallel, sequentially or in different orders, as long as the desired results of the technical solution of the present invention can be achieved, and this document does not limit this.

[0142] The above specific implementations do not constitute a limitation on the protection scope of the present invention. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modification, equivalent substitution and improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A method for manufacturing a semiconductor device, characterized in that: include: Providing a first semiconductor body, comprising a first surface and a second surface arranged opposite to each other; forming at least one alignment mark on the second surface of the first semiconductor body; According to the alignment mark, a first region is formed on the first surface of the first semiconductor body, wherein the positions of the first region and the alignment mark are arranged in a one-to-one correspondence; forming a second semiconductor body at least once on a side of the first surface of the first semiconductor body away from the second surface; After forming the second semiconductor body on the side of the first surface of the first semiconductor body away from the second surface each time, the method further includes: forming a second region on the surface of the second semiconductor body away from the first semiconductor body according to the alignment mark, wherein the second region and the alignment mark are arranged in a one-to-one correspondence; forming a first electrode structure on a side of the second semiconductor body away from the first semiconductor body; A second electrode structure is formed on a side of the first semiconductor body away from the second semiconductor body.

2. The method for manufacturing a semiconductor device according to claim 1, wherein: Before forming a second electrode structure on a side of the first semiconductor body away from the second semiconductor body, the method further includes: The second surface of the first semiconductor body is thinned to remove the alignment mark.

3. The method for manufacturing a semiconductor device according to claim 1, wherein: Forming at least one alignment mark on the second surface of the first semiconductor body comprises: At least one pattern is formed on the second surface of the first semiconductor body by a laser marking process to form at least one alignment mark.

4. The method for manufacturing a semiconductor device according to claim 1, wherein: Forming at least one alignment mark on the second surface of the first semiconductor body comprises: At least one third region is formed on the second surface of the first semiconductor body to form at least one alignment mark.

5. The method for manufacturing a semiconductor device according to claim 1, wherein: The first region and the second region are disposed continuously.

6. The method for manufacturing a semiconductor device according to claim 5, wherein: The semiconductor device is a metal oxide semiconductor field effect transistor; The first region and the second region constitute a well region and / or an active region.

7. The method for manufacturing a semiconductor device according to claim 5, wherein: The semiconductor device is a Schottky barrier diode; The first region and the second region constitute an active region.

8. The method for manufacturing a semiconductor device according to claim 6, wherein: Forming a first electrode structure on a side of the second semiconductor body away from the first semiconductor body comprises: forming a gate structure on a side of the second semiconductor body away from the first semiconductor body, the gate structure comprising a planar gate structure or a trench gate structure, the planar gate structure being located on a surface of the second semiconductor body away from the first semiconductor body, and the trench gate structure extending from the surface of the second semiconductor body away from the first semiconductor body into the second semiconductor body; A source structure is formed on a side of the first semiconductor body away from the second semiconductor body, the source structure comprising a planar source structure or a trench source structure, the planar source structure is located on a surface of the second semiconductor body away from the first semiconductor body, and the trench source structure extends from the surface of the second semiconductor body away from the first semiconductor body into the second semiconductor body; Forming a second electrode structure on a side of the first semiconductor body away from the second semiconductor body comprises: A drain is formed on a side of the first semiconductor body away from the second semiconductor body.

9. The method for manufacturing a semiconductor device according to claim 7, wherein: Forming a first electrode structure on a side of the second semiconductor body away from the first semiconductor body comprises: forming an anode on a side of the second semiconductor body away from the first semiconductor body; Forming a second electrode structure on a side of the first semiconductor body away from the second semiconductor body comprises: A cathode is formed on a side of the first semiconductor body away from the second semiconductor body.

10. The method for manufacturing a semiconductor device according to claim 1, wherein: Forming at least one alignment mark on the second surface of the first semiconductor body, comprising: At least one alignment mark having a light transmittance different from that of the first semiconductor body is formed on the second surface of the first semiconductor body.

11. The method for manufacturing a semiconductor device according to any one of claims 1 to 10, characterized in that: The first semiconductor body and the second semiconductor body both include silicon carbide material; Alternatively, the first semiconductor body and the second semiconductor body both include gallium nitride material.

12. A semiconductor device, characterized in that: include: A first semiconductor body including a first surface and a second surface arranged opposite to each other; The second surface of the first semiconductor body is provided with at least one alignment mark; The first surface of the first semiconductor body includes a first region, wherein the first region and the alignment mark are arranged in a one-to-one correspondence; At least one layer of second semiconductor body is located on the first surface of the first semiconductor body away from the second surface; the surface of each layer of the second semiconductor body away from the first semiconductor body includes a second region, wherein the second region and the position of the alignment mark are arranged in a one-to-one correspondence; A first electrode structure is located on a side of the second semiconductor body away from the first semiconductor body; The second electrode structure is located on a side of the first semiconductor body away from the second semiconductor body.

13. A power module, characterized in that: It comprises a substrate and the semiconductor device according to claim 12, wherein the substrate is used to carry the semiconductor device.

14. A power conversion circuit, characterized in that: The power conversion circuit is used for one or more of current conversion, voltage conversion, and power factor correction; The power conversion circuit includes a circuit board and at least one semiconductor device as claimed in claim 12, wherein the semiconductor device is electrically connected to the circuit board.

15. A vehicle, characterized in that: It includes a load and a power conversion circuit as described in claim 14, wherein the power conversion circuit is used to convert AC power into DC power, convert AC power into AC power, convert DC power into DC power, or convert DC power into AC power and then input it into the load.

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