Preparation method for improving reliability of metal oxide semiconductor field effect transistor (MOSFET)

Abstract

The invention belongs to the technical field of high-temperature semiconductor devices and radiation hardening, and particularly relates to a preparation method for improving the reliability of an MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor). Comprising the following steps: preparing an epitaxial layer on a high-concentration SOI substrate; growing a field oxide layer on the epitaxial layer; coating photoresist on the surface of the field oxide layer, and etching by adopting photoetching, developing and a wet process to prepare an active region; growing a gate oxide layer in the opened active region at high temperature; gluing and photoetching a gate region on the surface of the gate oxide layer by adopting a Lift-off process, and then depositing a TiO2 dielectric layer with a high dielectric constant by adopting an ALD (Atomic Layer Deposition) mode; carrying out polycrystalline gate deposition on the surface of the TiO2 dielectric layer, and carrying out photoetching corrosion to form a polycrystalline gate; photoetching a pattern, and forming a source-drain region through source-drain injection; completing opening and metal deposition growth of each region, and completing metal wiring through photoetching corrosion; according to the invention, the problem that the threshold temperature drift is too large when the current MOSFET is in a special application environment is solved, and the overall reliability of the MOSFET device is improved.

Description

Technical Field

[0001] The invention belongs to the technical field of high-temperature semiconductor devices and radiation-resistant reinforcement, and in particular relates to a preparation method for improving the reliability of MOSFET. Background Art

[0002] With the rapid development of microelectronics technology, its application areas are constantly expanding, and the requirements for working in harsh environments such as high temperatures are becoming increasingly urgent. For example, in the fields of aerospace, vehicle-mounted equipment, resource exploration, etc., the working environment of the chip is required to be between 125℃ and 300℃. The extreme working temperature puts more requirements on the temperature stability of the device. For radiation-resistant MOSFET devices, the reliability of the gate oxide growth process and the stability of the threshold voltage have become a relatively large challenge.

[0003] The main reason for the temperature drift of the threshold voltage is that the mobility of carriers (electrons and holes) decreases, which causes the threshold voltage to increase with increasing temperature. This is because a higher gate voltage needs to overcome the effect of reduced carrier mobility to maintain the same channel current. In some cases, increased temperature will cause the activation energy of doped atoms to decrease, making more doped atoms become conductive carriers and thus affecting the threshold voltage.

[0004] At the same time, the charge change of the oxide layer will also affect the high temperature stability of the device. The charge (such as trapped charge) that may exist in the gate oxide layer of the MOSFET will change with temperature, which will also cause the temperature drift of the threshold voltage. For example, the temperature increase may cause some trapped charges to be released, thereby affecting the threshold voltage. The impact of threshold voltage temperature drift The temperature drift of the threshold voltage will affect the on and off states of the MOSFET, thereby affecting the performance of the circuit. For example, in digital circuits, the temperature drift of the threshold voltage may cause the threshold voltage of the logic gate to change, affecting the switching speed and power consumption of the logic gate. In analog circuits, the temperature drift of the threshold voltage may affect the gain and bias point of the amplifier, resulting in unstable circuit performance.

[0005] In traditional MOSFET devices, bulk silicon SOI material sheets are usually used to form N or P type channels through injection and annealing. The concentration and uniformity of the injected doping affect the position of the Fermi level in the semiconductor material. The rate of change of the Fermi level at high temperature affects the fluctuation of the threshold voltage. Summary of the invention

[0006] The purpose of the present invention is to overcome the above-mentioned deficiencies in the prior art, to solve the problem of excessive temperature drift of the threshold value of MOSFET in special application environments, and to improve the overall reliability of MOSFET devices.

[0007] In order to solve the above technical problems, the present invention provides a preparation method for improving the reliability of MOSFET, comprising the following steps:

[0008] Step 1: Prepare an epitaxial layer with a thickness of 0.2 μm to 1 μm on a high-concentration SOI substrate;

[0009] Step 2: growing a field oxide layer with a thickness of 0.5 μm to 1 μm on the epitaxial layer at a process temperature of 950° C. to 1150° C.;

[0010] Step 3: coating photoresist on the surface of the field oxide layer, and preparing the active area by photolithography, development and wet etching;

[0011] Step 4: Grow a gate oxide layer at a high temperature in the opened active area. The temperature of the high temperature growth is 900° C. The thickness of the gate oxide layer is

[0012] Step 5: Lift-off process is used to coat the gate region on the surface of the gate oxide layer, and then an ALD method is used to deposit a high dielectric constant TiO2 dielectric layer. The growth thickness of the TiO2 dielectric layer is

[0013] Step 6: depositing a polycrystalline gate on the surface of the TiO2 dielectric layer, and photoetching to form a polycrystalline gate;

[0014] Step 7: Photolithography patterns are formed in the active area outside the gate oxide layer, and source and drain regions are formed by source and drain implantation;

[0015] Step 8: After the surface SiO2 oxide layer is covered, holes are opened and metal is deposited and grown in the areas corresponding to the source and drain regions and the polycrystalline gate, and metal wiring is completed through photolithography and etching.

[0016] Preferably, in step 1, the concentration of the SOI substrate is 5E15cm -3 ~5E16cm -3 The concentration of the epitaxial layer is 1E15cm -3 ~2E16cm -3 .

[0017] Preferably, the SOI substrate is of P type or N type, and the epitaxial layer is of P type or N type.

[0018] Preferably, in step 7, the source-drain injection dose is 1E15 cm -2 ~2E16cm -2 .

[0019] Preferably, the source-drain injection dose is 1E15cm -2 ~1E16cm -2 .

[0020] Preferably, in step 5, the dielectric constant of the TiO2 dielectric layer is 40.

[0021] Preferably, the SOI substrate is composed of a silicon base, a buried oxide layer and a top silicon layer in sequence from bottom to top, and the buried oxide layer is a SiO2 layer.

[0022] Preferably, the implantation depth of the source and drain regions is at the same level as the top of the buried oxide layer.

[0023] Preferably, the high temperature threshold drift of MOSFET is reduced by preparing a uniformly doped channel region, a high-quality gate oxide layer and a high dielectric constant dielectric layer.

[0024] Compared with the prior art, the present invention has the following beneficial effects:

[0025] The present invention prepares an epitaxial layer on the surface of an SOI substrate to replace the traditional P and N type channels, so that the doping concentration and type in the channel can be accurately controlled, so that the problem of uneven channel injection concentration is improved, and the Fermi level changes less under high temperature conditions, and its effect is similar to shallow junction diffusion technology (Shallow Junction Technology). Thereby, the depletion layer is stabilized and the threshold fluctuation is reduced. In addition, the high doping concentration characteristics brought by epitaxy as a well region can reduce the hot carrier effect, because carriers are more easily scattered, thereby reducing the mobility. Since the hot carrier effect will increase the threshold fluctuation, the use of epitaxy as a well structure of MOS can effectively reduce the threshold fluctuation by reducing the hot carrier effect.

[0026] In addition, the present invention uses high-k gate insulating materials, such as TiO2, to increase the thickness of the composite dielectric layer on the gate oxide, thereby reducing the probability of hot carrier crosstalk at high temperatures and reducing the temperature drift of the threshold voltage. ALD (Atomic Layer Deposition) atomic layer deposition is used to prepare the gate insulating material in order to obtain a more uniform and stable oxide layer and reduce the influence of temperature on the threshold voltage. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 It is a schematic diagram of growing an epitaxial layer on a SOI substrate silicon wafer according to the present invention.

[0028] Figure 2 It is a schematic diagram of growing a field oxygen layer and preparing an active region according to the present invention.

[0029] Figure 3 It is a schematic diagram of growing a gate oxide layer in an active area according to the present invention.

[0030] Figure 4 It is a schematic diagram of growing a high-k dielectric layer on a gate oxide layer according to the present invention.

[0031] Figure 5 It is a schematic diagram of preparing a polycrystalline gate according to the present invention.

[0032] Figure 6 It is a schematic diagram of preparing source and drain regions according to the present invention.

[0033] Figure 7 It is a schematic diagram of completing metal wiring in the present invention.

[0034] In the figure: 1-SOI substrate, 2-epitaxial layer, 3-active area, 4-gate oxide layer, 5-high-k dielectric layer, 6-polycrystalline gate, 7-source and drain regions, 8-metal wiring, 9-SiO2 oxide layer, 10-buried oxide layer. DETAILED DESCRIPTION

[0035] The present invention is further described in detail below in conjunction with the accompanying drawings and specific embodiments. The advantages and features of the present invention will become more apparent from the following description. It should be noted that the accompanying drawings are in very simplified form and in non-precise proportions, and are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention.

[0036] like Figures 1 to 7 As shown, an embodiment of the present invention provides a preparation method for improving the reliability of MOSFET, and the process steps are as follows:

[0037] Step 1: Prepare an epitaxial layer 2 on a high-concentration SOI substrate 1, with an epitaxial layer concentration of 1E15cm -3 ~2E16cm -3 ; epitaxial thickness is 0.2μm~1μm, substrate concentration is 5E15cm -3 ~5E16cm -3 The epitaxial concentration can be adjusted according to the threshold voltage change rate. The epitaxial concentration is equivalent to the traditional channel injection concentration, which can improve the concentration unevenness problem in the channel injection process, thereby suppressing the change of the Fermi level at high temperature.

[0038] Step 2: Place the silicon wafer substrate and the oxidant into an oxidation furnace for high-temperature reaction to form a field oxygen layer on the surface of the silicon wafer substrate. The field oxygen layer is a SiO2 oxide layer with a thickness of 0.5μm to 1μm and a process temperature of 950℃ to 1150℃.

[0039] Step 3: Coat the surface with photoresist, and prepare the active area 3 by conventional means such as photolithography, development, and wet etching.

[0040] Step 4: Grow a gate oxide layer 4 at a high temperature of 900°C and a thickness of

[0041]

[0042] Step 5: Use the Lift-off process to photolithography the gate region 4, and then use the ALD method to deposit TiO2 high-k dielectric 5, with a dielectric constant of 40. Various semiconductor high-k value materials including TiO2 can also be used. (The existing gate insulation material SiO2 dielectric has a dielectric constant of 4). The total growth is about TiO2 can improve the reliability of gate oxide.

[0043] Step 6: Polycrystalline gate deposition and photolithography etching are performed to form polycrystalline gate 6.

[0044] Step 7: Photolithography patterning and source and drain injection to form source and drain region 7, with an injection dose of 1E15cm -2 ~2E16cm -2 .

[0045] Step 8: Complete the opening of holes and metal deposition growth in each area, and complete the metal wiring 8 through photolithography and etching.

[0046] The remaining preparation processes are submicron semiconductor MOS device process integration technologies well known to those skilled in the art, so there is no need to describe them one by one in this embodiment.

[0047] In summary, the present invention uses epitaxial wafers to replace traditional bulk silicon wafers, and uses epitaxy for MOSFET channels, thereby reducing the channel adjustment injection steps, optimizing the manufacturing process to achieve precise uniform doping of the channel, and achieving the purpose of uniform doping of the MOSFET surface in a non-injection form, so that it remains relatively stable at different temperatures, reduces threshold temperature drift, and improves device stability. ALD atomic layer deposition is used to prepare a high-k value gate dielectric to reduce the hot carrier crosstalk effect, so that the gate dielectric layer is uniform and stable, and the MOSFET threshold has stable characteristics under high temperature conditions.

[0048] The above description is only a description of the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention. Any changes or modifications made by a person skilled in the art in the field of the present invention based on the above disclosure shall fall within the scope of protection of the claims.

Claims

1. A method for improving the reliability of MOSFET, characterized in that: The steps include: Step 1: Prepare an epitaxial layer with a thickness of 0.2 μm to 1 μm on a high-concentration SOI substrate; Step 2: growing a field oxide layer with a thickness of 0.5 μm to 1 μm on the epitaxial layer at a process temperature of 950° C. to 1150° C.; Step 3: coating photoresist on the surface of the field oxide layer, and preparing the active area by photolithography, development and wet etching; Step 4: Grow a gate oxide layer at a high temperature in the opened active area. The temperature of the high temperature growth is 900° C. The thickness of the gate oxide layer is Step 5: Lift-off process is used to coat the gate region on the surface of the gate oxide layer, and then an ALD method is used to deposit a high dielectric constant TiO2 dielectric layer. The growth thickness of the TiO2 dielectric layer is Step 6: depositing a polycrystalline gate on the surface of the TiO2 dielectric layer, and photoetching to form a polycrystalline gate; Step 7: Photolithography patterns are formed in the active area outside the gate oxide layer, and source and drain regions are formed by source and drain implantation; Step 8: After the surface SiO2 oxide layer is covered, holes are opened and metal is deposited and grown in the areas corresponding to the source and drain regions and the polycrystalline gate, and metal wiring is completed through photolithography and etching.

2. A method for improving the reliability of MOSFET according to claim 1, characterized in that: In step 1, the concentration of the SOI substrate is 5E15cm -3 ~5E16cm -3 The concentration of the epitaxial layer is 1E15cm -3 ~2E16cm -3 .

3. A method for improving the reliability of MOSFET according to claim 1, characterized in that: The SOI substrate is of P type or N type, and the epitaxial layer is of P type or N type.

4. A method for improving the reliability of MOSFET according to claim 1, characterized in that: In step 7, the source and drain implantation dose is 1E15cm -2 ~2E16cm -2 .

5. A method for improving the reliability of MOSFET as claimed in claim 4, characterized in that: The source and drain implantation dose is 1E15cm -2 ~1E16cm -2 .

6. A method for improving the reliability of MOSFET according to claim 1, characterized in that: In step 5, the dielectric constant of the TiO2 dielectric layer is 40.

7. A method for improving the reliability of MOSFET according to claim 1, characterized in that: The SOI substrate is composed of a silicon base, a buried oxide layer and a top silicon layer in sequence from bottom to top, and the buried oxide layer is a SiO2 layer.

8. A method for improving the reliability of MOSFET as claimed in claim 7, characterized in that: The implantation depth of the source and drain regions is at the same level as the top of the buried oxide layer.

9. A method for improving the reliability of MOSFET according to any one of claims 1 to 8, characterized in that: The high temperature threshold drift of MOSFET is reduced by preparing a uniformly doped channel region, a high-quality gate oxide layer and a high dielectric constant dielectric layer.

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