Semiconductor device, manufacturing method thereof and electronic device

Abstract

The invention provides a semiconductor device, a manufacturing method thereof and an electronic device, and the method comprises the steps: providing a substrate, and forming a drift region in the substrate; forming a first field oxide layer on the surface of the substrate; etching to remove a part of the first field oxide layer so as to reserve a part of the first field oxide layer on the drift region; forming a second field oxide layer on the substrate and the first field oxide layer; and etching to remove the second field oxide layer on the substrate, and meanwhile, forming a third field oxide layer with a slope side wall on the drift region. According to the invention, a part of the first field oxide layer is removed by etching, a part of the first field oxide layer on the drift region is reserved, the second field oxide layer is continuously deposited, and the second field oxide layer on the substrate is removed, so that the field plate with the slope side wall is formed, the slope field plate can be formed by only one mask, the technological process is simplified, and the manufacturing cost is reduced. And the process cost is reduced.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and more specifically to a semiconductor device and a manufacturing method thereof, and an electronic device. Background Art

[0002] For power devices in the field of semiconductor device technology, the design of field plates is essential in order to increase the breakdown voltage of the devices. Field plates are common terminal protection structures used to improve the high voltage breakdown resistance of semiconductor devices. By changing the surface potential distribution of the device and increasing the radius of curvature at the main junction, the PN junction electric field is no longer concentrated at the main junction bend, preventing the electric field at the main junction from being too concentrated, thereby increasing the breakdown voltage and the withstand voltage reliability of the device.

[0003] In the related art, in order to increase the breakdown voltage of the device and prevent the occurrence of a spike electric field, a slope field plate is usually used. The slope field plate can reduce the electric field at the PN main junction to prevent the electric field from being too concentrated and causing breakdown. Although the related art can obtain a high breakdown voltage, the current process for preparing the slope field plate requires at least two masks to produce the slope field plate, thereby increasing the complexity and cost of the process. Summary of the invention

[0004] A series of simplified concepts are introduced in the Summary of the Invention section, which will be further described in detail in the Detailed Description of the Invention section. The Summary of the Invention section of this application does not mean to attempt to define the key features and essential technical features of the claimed technical solution, nor does it mean to attempt to determine the scope of protection of the claimed technical solution.

[0005] In response to the current problems, an embodiment of the present application provides a method for manufacturing a semiconductor device, including: providing a substrate, wherein a drift region is formed in the substrate; forming a first field oxide layer on the surface of the substrate; etching and removing a portion of the first field oxide layer to retain a portion of the first field oxide layer on the drift region; forming a second field oxide layer on the substrate and the first field oxide layer; while etching and removing the second field oxide layer located on the substrate, forming a third field oxide layer with a sloped sidewall on the drift region.

[0006] Exemplarily, the method further includes forming a gate dielectric layer and a gate material layer on the substrate and the third field oxide layer, and patterning the gate dielectric layer and the gate material layer to form a gate structure, wherein the gate structure is partially located on the substrate and partially located on the third field oxide layer.

[0007] Exemplarily, the region of the substrate located outside the drift region and under the gate structure constitutes a channel region.

[0008] Exemplarily, wet etching is used to remove the second field oxide layer on the substrate.

[0009] Exemplarily, a body region is formed in the substrate, and the drift region is located in the body region.

[0010] Exemplarily, the first field oxide layer and the second field oxide layer are made of the same material.

[0011] Exemplarily, the gate material layer includes polysilicon, and the gate dielectric layer includes silicon oxide or silicon oxynitride.

[0012] Exemplarily, the semiconductor device includes a power device.

[0013] Another aspect of the present application provides a semiconductor device, which is manufactured using the method described above.

[0014] In yet another aspect, the present application provides an electronic device, which includes the semiconductor device as described above.

[0015] The semiconductor device and its manufacturing method and electronic device provided by the present application remove part of the first field oxide layer by etching, retain part of the first field oxide layer on the drift region, continue to deposit the second field oxide layer, and remove the second field oxide layer on the substrate, thereby forming a field plate with a sloped sidewall. Only one mask plate is needed to form the sloped field plate, which simplifies the process flow and reduces the process cost. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] The following drawings of the present application are used as part of the present application for understanding the present application. The drawings show the embodiments of the present application and their descriptions, and are used to explain the principles of the present application. In the drawings: Figure 1 A schematic flow chart showing a method for manufacturing a semiconductor device according to a specific embodiment of the present application; FIG. 2A to FIG. 2F A cross-sectional schematic diagram of a semiconductor device obtained by sequentially implementing each step of a method for manufacturing a semiconductor device according to an embodiment of the present application is shown. DETAILED DESCRIPTION

[0017] In the following description, a large number of specific details are provided to provide a more thorough understanding of the present application. However, it is apparent to those skilled in the art that the present invention can be implemented without one or more of these details. In other examples, in order to avoid confusion with the present invention, some technical features well known in the art are not described.

[0018] It should be understood that the present application can be implemented in different forms and should not be construed as being limited to the embodiments presented herein. On the contrary, providing these embodiments will make the disclosure thorough and complete, and fully convey the scope of the present invention to those skilled in the art. In the accompanying drawings, the sizes and relative sizes of layers and regions may be exaggerated for clarity. The same reference numerals throughout represent the same elements.

[0019] It should be understood that when an element or layer is referred to as being "on, adjacent to, connected to or coupled to other elements or layers, it may be directly on, adjacent to, connected to or coupled to other elements or layers, or there may be intervening elements or layers. In contrast, when an element is referred to as being "directly on, directly adjacent to, directly connected to or directly coupled to other elements or layers, there may be no intervening elements or layers. It should be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, without departing from the teachings of the present invention, the first element, component, region, layer or part discussed below may be represented as a second element, component, region, layer or part.

[0020] Spatially relative terms such as "under," "below," "below," "under," "above," "above," etc., may be used herein for ease of description to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that in addition to the orientations shown in the figures, the spatially relative terms are intended to include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is flipped, then the elements or features described as "under other elements" or "under" or "under" will be oriented as "on" the other elements or features. Therefore, the exemplary terms "under" and "under" may include both upper and lower orientations. The device may be oriented otherwise (rotated 90 degrees or other orientations) and the spatial descriptors used herein are interpreted accordingly.

[0021] The purpose of the terms used herein is only to describe specific embodiments and is not intended to be limiting of the present invention. When used herein, the singular forms "one", "an" and "said / the" are also intended to include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "consisting of" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0022] In order to thoroughly understand the present application, detailed steps and structures will be presented in the following description to illustrate the technical solution proposed by the present application. The preferred embodiments of the present application are described in detail below, but in addition to these detailed descriptions, the present application may also have other implementations.

[0023] At present, in the related art, in order to prepare a sloped field plate, a process flow is as follows: first, a field oxide layer is grown on a silicon wafer on which a sloped field plate structure is to be prepared, a first photolithography is performed to initially define the active area and the terminal area, the field oxide layer is wet-etched for the first time, and the photoresist is removed; secondly, a second photolithography is performed to finally define the active area and the terminal area, the field oxide layer is wet-etched for the second time, and the photoresist is removed; finally, polysilicon or metal aluminum is deposited, and a sloped field plate structure composed of the field oxide layer after the second wet etching and polysilicon or metal aluminum is formed by photolithography and etching methods. However, the method for preparing a sloped field plate requires the use of two mask plates to produce the sloped field plate, which increases the process complexity and process cost.

[0024] Therefore, in view of the existence of the above-mentioned technical problems, the present application embodiment proposes a method for preparing a semiconductor device, such as Figure 1 As shown, it mainly includes the following steps: In step S101, a substrate is provided, wherein a drift region is formed in the substrate; In step S102, a first field oxide layer is formed on the surface of the substrate; In step S103, a portion of the first field oxide layer is removed by etching to retain a portion of the first field oxide layer on the drift region; In step S104, forming a second field oxide layer on the substrate and the first field oxide layer; In step S105 , while etching away the second field oxide layer on the substrate, a third field oxide layer having a sloped sidewall is formed on the drift region.

[0025] The manufacturing method of the semiconductor device in the embodiment of the present application removes part of the first field oxide layer by etching, retains part of the first field oxide layer on the drift region, continues to deposit the second field oxide layer, and removes the second field oxide layer on the substrate, thereby forming a field plate with a sloped sidewall. Only one mask plate is needed to form the sloped field plate, which simplifies the process flow and reduces the process cost.

[0026] Example 1 Below, reference Figure 1 as well as FIG. 2A to FIG. 2F The manufacturing method of the semiconductor device of the present application is described in detail, wherein: Figure 1 A flowchart of a method for manufacturing a semiconductor device according to a specific embodiment of the present application is shown. FIG. 2A to FIG. 2F A cross-sectional schematic diagram of a device obtained by sequentially implementing a method for manufacturing a semiconductor device according to a specific embodiment of the present application is shown.

[0027] Exemplarily, the method for manufacturing a semiconductor device of the present application includes the following steps: First, step S101 is performed to provide a substrate, in which a drift region is formed.

[0028] In one example, if Figure 2A As shown, the material of the substrate 200 includes but is not limited to at least one of the following materials: silicon (Si), germanium (Ge), silicon germanium (SiGe), silicon carbide (SiC), carbon germanium silicon (SiGeC), indium arsenide (InAs), gallium arsenide (GaAs), indium phosphide (InP), sapphire (Sapphire) or other III / V compound semiconductors, or silicon on dielectric (SOI), stacked silicon on dielectric (SSOI), stacked silicon germanium on dielectric (S-SiGeOI), silicon germanium on dielectric (SiGeOI) and germanium on dielectric (GeOI), or double-side polished silicon wafers (Double Side Polished Wafers, DSP), ceramic substrates of aluminum oxide, quartz or glass substrates, etc. Although several examples of materials that can form the substrate are described here, any material that can be used as the substrate falls within the spirit and scope of the present invention.

[0029] Exemplarily, the semiconductor substrate 200 may be a P-type substrate or an N-type substrate.

[0030] In one example, if Figure 2AAs shown, a drift region 201 is formed in the substrate 200. Exemplarily, a body region is formed in the substrate 200, and the drift region 201 is located in the body region. Exemplarily, the body region and the drift region 201 can be formed by an ion implantation process. The body region and the drift region 201 can have opposite conductivity types, which can be reasonably set according to the type of the actual device, and are not specifically limited to this. For example, for an N-type LDMOS device, the drift region 201 is an N-type drift region, and the body region is a P-type body region.

[0031] Generally speaking, the doping concentration of the drift region 201 is low, which can increase the breakdown voltage and is beneficial to improving the frequency characteristics. Exemplarily, the drift region 201 can be an N-type drift region, such as a lightly doped N-type drift region, or the drift region 201 can also be a P-type drift region, such as a lightly doped P-type drift region, which can be reasonably set according to the type of actual device. The main doping ions of the N-type drift region can include phosphorus ions, arsenic ions, antimony ions, etc., and the main doping ions of the P-type drift region can include boron ions, gallium ions, indium ions, etc. For example, for an N-type LDMOS device, the drift region 201 can be an N-type drift region doped with arsenic ions.

[0032] The depth of the ion implantation can be controlled by controlling the energy of the ion implantation. After the ion implantation, an annealing step can be performed to activate the doped ions in the drift region. The annealing process uses rapid thermal annealing (RTA) or other suitable annealing methods.

[0033] In one example, if Figure 2A As shown, the area of ​​the substrate 200 located outside the drift region 201 and under the gate structure constitutes a channel region 202. Specifically, the channel region can be a part of the above-mentioned body region, or the channel region 202 can be formed by an ion implantation process. Exemplarily, the channel region 202 can be an N-type channel region, or the channel region 202 can also be a P-type channel region, which can be reasonably set according to the type of actual device. The main doping ions of the N-type channel region can include phosphorus ions, arsenic ions, antimony ions, etc., and the main doping ions of the P-type channel region can include boron ions, gallium ions, indium ions, etc.

[0034] Next, step S102 is performed to form a first field oxide layer on the surface of the substrate.

[0035] In one example, if Figure 2AAs shown, a first field oxide layer 203 is formed on the surface of the substrate 200. Exemplarily, the first field oxide layer 203 can be formed by any suitable method known to those skilled in the art, for example, the first field oxide layer 203 can be formed by a deposition process such as chemical vapor deposition (CVD) but not limited thereto, specifically, low pressure chemical vapor deposition (LPCVD), atmospheric pressure chemical vapor deposition (APCVD) or plasma enhanced chemical vapor deposition (PECVD), or the first field oxide layer 203 can be formed by a high temperature furnace thermal oxidation process. Preferably, the first field oxide layer 203 is deposited by low pressure chemical vapor deposition, so that a relatively dense first field oxide layer 203 can be formed.

[0036] In this example, the material of the first field oxide layer 203 can be silicon dioxide (SiO 2 ), the material of the first field oxide layer 203 may also be other suitable materials, such as silicon oxynitride (SiON), which is not specifically limited.

[0037] Next, step S103 is performed to etch away a portion of the first field oxide layer so as to retain a portion of the first field oxide layer on the drift region.

[0038] In one example, if Figure 2BAs shown, a portion of the first field oxide layer 203 is etched away, and a portion of the first field oxide layer 203 on the drift region 201 is retained. Exemplarily, a patterned mask layer is formed on the first field oxide layer 203, and specifically, the patterned mask layer includes a photoresist layer. Exemplarily, etching away a portion of the first field oxide layer 203 may include the following steps: forming a photoresist layer on the upper surface of the first field oxide layer 203 by a coating process, exposing and developing using a photomask, and patterning the photoresist layer by an exposure and development process; etching the first field oxide layer 203 using the photoresist layer as a mask, removing a portion of the first field oxide layer 203, and retaining a portion of the first field oxide layer 203 on the drift region 201; and finally removing the patterned photoresist layer, thereby retaining a portion of the first field oxide layer 203 on the drift region 201. Exemplarily, the first field oxide layer 203 may be etched by conventional etching processes such as dry etching, reactive ion etching (RIE), ion beam etching, and plasma etching, and the method for removing the patterned photoresist layer may be dry etching or ashing processes, etc. Of course, a hard mask layer may be first formed on the surface of the first field oxide layer 203, and then the pattern is transferred to the hard mask layer using the photoresist layer as a mask, and then the hard mask layer is used to etch and remove part of the first field oxide layer 203, leaving part of the first field oxide layer 203 on the drift region 201, and finally removing the hard mask layer. The above-mentioned method of etching and removing the field oxide layer is a common method in the art, and no excessive description or limitation is made here. In short, the methods that can etch and remove the field oxide layer are all within the protection scope of this application.

[0039] Afterwards, step S104 is performed to form a second field oxide layer on the substrate and the first field oxide layer.

[0040] In one example, if Figure 2C As shown, a second field oxide layer 204 is formed on the substrate 200 and the first field oxide layer 203. Exemplarily, the second field oxide layer 204 may be formed by any suitable method known to those skilled in the art. For example, the second field oxide layer 204 may be formed by a deposition process not limited to chemical vapor deposition, etc. Specifically, low pressure chemical vapor deposition, normal pressure chemical vapor deposition or plasma enhanced chemical vapor deposition may be used. Alternatively, the second field oxide layer 204 may be formed by a high temperature furnace thermal oxidation process. Preferably, the second field oxide layer 204 is deposited by low pressure chemical vapor deposition, so that a denser second field oxide layer 204 may be formed.

[0041] In one example, the material of the second field oxide layer 204 may be the same as the material of the first field oxide layer 203. Specifically, the material of the second field oxide layer 204 may be silicon dioxide, and the material of the second field oxide layer 204 may also be other suitable field oxide layer materials, such as silicon oxynitride, which is not specifically limited. In another example, the material of the first field oxide layer 203 and the material of the second field oxide layer 204 may also be different, which is not specifically limited.

[0042] Next, step S104 is performed to etch and remove the second field oxide layer on the substrate, and at the same time, form a third field oxide layer with a sloped sidewall on the drift region.

[0043] In one example, if Figure 2D As shown, the second field oxide layer 204 located on the substrate 200 is etched away, and at the same time, a third field oxide layer 205 with a sloped sidewall is formed on the drift region 201. Exemplarily, the second field oxide layer 204 located on the substrate 200 can be etched away by a wet etching process. Specifically, hydrofluoric acid (HF) and ammonium fluoride (NH 4 F) is used to etch the second field oxide layer 204. Since wet etching is an isotropic etching process, a certain inclination angle will be formed, thereby forming a third field oxide layer 205 (i.e., a sloped field plate) with a sloped sidewall on the drift region 201. The sloped field plate can uniformly control the electric field of the surface area of ​​the semiconductor substrate 200 at the bottom, prevent the occurrence of a peak electric field, thereby eliminating the easy breakdown area, and improving the overall voltage resistance of the device. The above-mentioned wet etching process of the present application to form the third field oxide layer with a sloped sidewall does not require the use of a mask. Therefore, compared with the prior art, the use of a mask can be saved once, which can effectively reduce the process cost.

[0044] In one example, if Figure 2E As shown, a gate dielectric layer 206 and a gate material layer 207 are formed on the substrate 200 and the third field oxide layer 205. Exemplarily, the gate dielectric layer 206 may be formed by any suitable method known to those skilled in the art, for example, the gate dielectric layer 206 may be formed by a deposition process such as chemical vapor deposition but not limited thereto, or the gate dielectric layer 206 may be formed by a high-temperature furnace thermal oxidation process. Exemplarily, the material of the gate dielectric layer 206 may include silicon oxide or silicon oxynitride, and may also be other suitable materials, such as a high dielectric constant material, which is not specifically limited.

[0045] In this example, the gate material layer 207 may be formed by various deposition methods commonly used in the art, such as chemical vapor deposition (CVD), physical vapor deposition (PVD), etc. Exemplarily, the material of the gate material layer 207 may include suitable conductive materials such as polysilicon, tungsten silicide, and titanium, which are not specifically limited.

[0046] In one example, if Figure 2F As shown, the gate dielectric layer 206 and the gate material layer 207 are patterned to form a gate structure, and the gate structure is partially located on the substrate 200 and partially located on the third field oxide layer 205. Exemplarily, the method for forming the gate structure may include: patterning the gate material layer 207, and etching the gate dielectric layer 206 and the gate material layer 207 to form a gate structure, and the gate structure includes the gate dielectric layer 206 and the gate material layer 207. Any existing technology well known to those skilled in the art can be used in this etching step, preferably dry etching, dry etching includes but is not limited to reactive ion etching (RIE), ion beam etching, plasma etching or any combination of these methods. A portion of the formed gate structure is located on the substrate 200, and the other portion is located on the third field oxide layer 205.

[0047] In one example, the formed semiconductor device includes a power device. Exemplarily, the power device is, for example, an LDMOS device.

[0048] It is worth mentioning that the above steps are only examples, and the order of the above steps can be adjusted without conflict.

[0049] At this point, the process steps of the semiconductor device manufacturing method implemented according to an embodiment of the present application have been completed. It can be understood that the semiconductor device manufacturing method of this embodiment not only includes the above steps, but may also include other necessary steps before, during or after the above steps, which are all included in the scope of the manufacturing method of this embodiment.

[0050] In summary, the manufacturing method of the semiconductor device of the present application removes part of the first field oxide layer by etching, retains part of the first field oxide layer on the drift region, continues to deposit the second field oxide layer, and removes the second field oxide layer on the substrate, thereby forming a field plate with a sloped sidewall. Only one mask plate is needed to form the sloped field plate, which simplifies the process flow and reduces the process cost.

[0051] Example 2 The present invention also provides a semiconductor device, which can be prepared by the method in the above-mentioned embodiment 1.

[0052] Below, reference FIG. 2A to FIG. 2FThe semiconductor device in the embodiment of the present application is introduced and described in detail. It is worth mentioning that in order to avoid repetition, only a brief description is given for the components and structures that are the same as in the aforementioned embodiment one. For specific explanations and descriptions, please refer to the description in embodiment one.

[0053] Specifically, FIG. 2A to FIG. 2F The semiconductor device of the embodiment of the present application includes: a substrate 200, in which a drift region 201 is formed; a channel region 202, which is composed of a region of the substrate 200 located outside the drift region 201 and under the gate structure; a third field oxide layer 205 located on the drift region 201; a gate structure, which includes a gate dielectric layer 206 and a gate material layer 207, and the gate structure is partially located on the substrate 200 and partially located on the third field oxide layer 205.

[0054] This completes the introduction to the structure of the semiconductor device of the present application. The complete device may also include other component structures, which will not be described in detail here.

[0055] The semiconductor device provided by the present application removes a portion of the first field oxide layer by etching, retains a portion of the first field oxide layer on the drift region, continues to deposit the second field oxide layer, and removes the second field oxide layer on the substrate, thereby forming a field plate with a sloped sidewall. Only one mask plate is needed to form the sloped field plate, which simplifies the process flow and reduces the process cost.

[0056] Example (III) Another embodiment of the present application provides an electronic device, comprising the aforementioned semiconductor device, wherein the semiconductor device is manufactured according to the aforementioned method.

[0057] The electronic device of this embodiment can be any electronic product or device such as a mobile phone, a tablet computer, a laptop computer, a netbook, a game console, a television, a VCD, a DVD, a navigator, a digital photo frame, a camera, a video camera, a voice recorder, an MP3, an MP4, a PSP, etc., or any intermediate product including a circuit. The electronic device of the embodiment of the present invention has better performance because the above-mentioned semiconductor device is used.

[0058] The present invention has been described by the above embodiments, but it should be understood that the above embodiments are only for the purpose of example and description, and are not intended to limit the present invention to the scope of the described embodiments. In addition, it can be understood by those skilled in the art that the present invention is not limited to the above embodiments, and more variations and modifications can be made according to the teachings of the present invention, and these variations and modifications all fall within the scope of the protection claimed by the present invention. The protection scope of the present invention is defined by the attached claims and their equivalents.

Claims

1. A method for manufacturing a semiconductor device, characterized in that: include: providing a substrate having a drift region formed therein; forming a first field oxide layer on a surface of the substrate; etching and removing a portion of the first field oxide layer to retain a portion of the first field oxide layer on the drift region; forming a second field oxide layer on the substrate and the first field oxide layer; While the second field oxide layer on the substrate is etched away, a third field oxide layer with a sloped sidewall is formed on the drift region.

2. The manufacturing method according to claim 1, characterized in that The method also includes forming a gate dielectric layer and a gate material layer on the substrate and the third field oxide layer, and patterning the gate dielectric layer and the gate material layer to form a gate structure, wherein the gate structure is partially located on the substrate and partially located on the third field oxide layer.

3. The manufacturing method according to claim 2, characterized in that: The area of ​​the substrate located outside the drift region and under the gate structure constitutes a channel region.

4. The manufacturing method according to claim 1, characterized in that: The second field oxide layer located on the substrate is removed by wet etching.

5. The manufacturing method according to claim 1, characterized in that: A body region is formed in the substrate, and the drift region is located in the body region.

6. The manufacturing method according to claim 1, characterized in that: The first field oxide layer and the second field oxide layer are made of the same material.

7. The manufacturing method according to claim 2, characterized in that: The gate material layer includes polysilicon, and the gate dielectric layer includes silicon oxide or silicon oxynitride.

8. The manufacturing method according to claim 1, characterized in that: The semiconductor device includes a power device.

9. A semiconductor device, characterized in that: The method is produced by the production method described in any one of claims 1 to 8.

10. An electronic device, characterized in that: A semiconductor device comprising the semiconductor device according to claim 9.

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