Preparation method of stacked transistor, stacked transistor, device and equipment
By forming an integrated oxide isolation layer and an insulating isolation layer outside the fin-shaped structure of the stacked transistor, the problem of excessive thermal budget during the preparation process of the stacked transistor is solved, achieving a lower thermal budget and higher process efficiency.
Patent Information
- Application Number
- CN202411221468.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-09-02
- Publication Date
- 2025-01-14
AI Technical Summary
The high thermal budget generated during the preparation of stacked transistors has become an urgent problem.
By forming an integrated oxide isolation layer and an insulating isolation layer outside the first fin-shaped structure and the second fin-shaped structure, the oxidation isolation layer is prevented from being formed again during the preparation of the second transistor, and the thermal budget is reduced.
It effectively reduces the thermal budget during the preparation process of stacked transistors, protects the fin structure, and improves the feasibility and efficiency of the process.
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Figure CN119317172A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of semiconductors, and in particular to a method for preparing a stacked transistor, a stacked transistor, a device and an apparatus. Background Art
[0002] As Moore's Law continues to deepen, continuing to promote the miniaturization of transistor size is a hot issue in the current industry research and development. Stacked transistors integrate two or more layers of transistors in a vertical space to further increase the integration density of transistors, becoming one of the important technologies to continue the miniaturization of integrated circuit size.
[0003] Currently, the high thermal budget generated during the preparation of stacked transistors is still a problem that needs to be solved urgently. Summary of the invention
[0004] The present application provides a method for preparing a stacked transistor, a stacked transistor, a device and an apparatus to reduce the thermal budget generated in the process of preparing the stacked transistor.
[0005] In a first aspect, an embodiment of the present application provides a method for preparing a stacked transistor, wherein the stacked transistor includes a first transistor and a second transistor which are stacked; the method includes: forming a fin structure on a substrate; the fin structure includes a first fin structure and a second fin structure; depositing an oxide on the fin structure and the substrate to form an oxide isolation layer; the oxide isolation layer covers the surface of the fin structure and the surface of the substrate; depositing a first insulating material on the oxide isolation layer to form an insulating isolation layer; the insulating isolation layer covers the surface of the oxide isolation layer; forming a first transistor based on the first fin structure; flipping and thinning the substrate until the second fin structure is exposed; A first surface; the first surface is a surface of the second fin structure away from the first fin structure; the second fin structure is etched to a preset height to form a first groove; oxide is deposited in the first groove to form an oxidation isolation structure; the height of the oxidation isolation structure in the horizontal direction is the same as the height of the insulating isolation layer in the horizontal direction; the oxidation isolation structure is etched to a preset height to form a second groove; a first insulating material is deposited in the second groove to form an insulating isolation structure; the insulating isolation structure and the insulating isolation layer are connected as a whole and cover the surface of the oxidation isolation structure and the oxidation isolation layer after etching; based on the second fin structure, a second transistor is formed.
[0006] In some possible embodiments, before forming a first transistor based on the first fin structure, the above method also includes: depositing a second insulating material on the oxidation isolation layer to form a shallow trench isolation structure; the shallow trench isolation structure wraps the fin structure; removing a first portion of the shallow trench isolation structure to expose the insulating isolation layer wrapping the first fin structure; removing the insulating isolation layer wrapping the first fin structure to expose the oxidation isolation layer wrapping the first fin structure.
[0007] In some possible embodiments, before forming a second transistor based on the second fin structure, the above method also includes: removing a second portion of the shallow trench isolation structure to expose the insulating isolation layer and the insulating isolation structure wrapping the second fin structure, and forming a shallow trench isolation layer; the shallow trench isolation layer is located between the first transistor and the second transistor, and is used to isolate the first transistor from the second transistor.
[0008] In some possible embodiments, oxide is deposited in the first groove to form an oxide isolation structure, including: depositing oxide in the first groove and on the oxide isolation layer to form a first oxide isolation structure; the first oxide isolation structure is connected to the oxide isolation layer; and removing the first oxide isolation structure and the oxide isolation layer at a preset height until the insulating isolation layer is exposed to form an oxide isolation structure.
[0009] In some possible embodiments, a first insulating material is deposited in the second groove to form an insulating isolation structure, including: depositing the first insulating material in the second groove and on the insulating isolation layer to form a first insulating isolation structure; the first insulating isolation structure is connected to the insulating isolation layer as an integral whole; and removing the first insulating isolation structure and the insulating isolation layer at a preset height until the shallow trench isolation structure is exposed to form an insulating isolation structure.
[0010] In some possible implementations, during the process of forming the first transistor, the method further includes: performing a gate cut-off process on the first dummy gate structure of the first transistor to form a first gate cut-off structure.
[0011] In some possible implementations, during the process of forming the second transistor, the method further includes: performing a gate cut-off process on the second dummy gate structure of the second transistor to form a second gate cut-off structure.
[0012] In a second aspect, an embodiment of the present application provides a stacked transistor, which is prepared by the method described in the first aspect above, and the stacked transistor includes: a first transistor; a second transistor; the first transistor and the second transistor are stacked; a shallow trench isolation layer, the shallow trench isolation layer is located between the first transistor and the second transistor, and is used to isolate the first transistor from the second transistor; wherein the fin structure of the first transistor and the fin structure of the second transistor are formed by the same process, the surface of the fin structure located in the shallow trench isolation layer is covered by an oxidation isolation layer, and the surface of the oxidation isolation layer is covered by an insulating isolation layer; the oxidation isolation layer is formed by depositing oxide on the surface of the fin structure, and the insulating isolation layer is formed by depositing a first insulating material on the oxidation isolation layer.
[0013] In a third aspect, an embodiment of the present application provides a semiconductor device, which includes: a stacked transistor as described in the second aspect above.
[0014] In a fourth aspect, an embodiment of the present application provides an electronic device, comprising: a circuit board and a semiconductor device as described in the third aspect above, wherein the semiconductor device is arranged on the circuit board.
[0015] In the present application, an oxidation isolation layer and an insulating isolation layer are formed on the outside of the first fin structure and the second fin structure, and the oxidation isolation layer and the insulating isolation layer on the surface of the first fin structure and the second fin structure are integrally formed, which can avoid the formation of an oxidation isolation layer again on the surface of the second fin structure during the preparation of the second transistor, and solves the problem of excessive thermal budget caused by forming oxidation isolation layers in stacked transistors in multiple times.
[0016] Furthermore, the oxidation isolation layer and the insulating isolation layer formed outside the first fin structure and the second fin structure can effectively protect the first fin structure and the second fin structure during the process of preparing the stacked transistor.
[0017] It should be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present application. BRIEF DESCRIPTION OF THE DRAWINGS
[0018] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and, together with the description, serve to explain the principles of the present application.
[0019] Figure 1 A schematic diagram of an implementation process of a method for preparing a stacked transistor in an embodiment of the present application;
[0020] Figure 2 A schematic diagram of a structure of a stacked transistor in an embodiment of the present application;
[0021] FIG. 3A to FIG. 3J A schematic diagram of a preparation process of stacked crystals in an embodiment of the present application;
[0022] Figure 4 This is a design layout of the gate cut-off structure in the embodiment of the present application;
[0023] The above pictures:
[0024] 10. stacked transistor; 11. first transistor; 111. first fin structure; 112. first spacer; 113. first interlayer dielectric layer; 114. first gate cut-off structure; 115. first source-drain structure; 116. first gate dielectric layer; 117. first gate structure; 118. first source-drain metal; 119. first metal interconnect layer; 12. second transistor; 121. second fin structure; 122. second spacer; 123. second interlayer dielectric layer; 124. second gate cut-off structure; 125. second source-drain structure; 126. second Gate dielectric layer; 127, second gate structure; 128, second source and drain metal; 129, second metal interconnection layer; 13, shallow trench isolation layer; 14, insulating layer; 15, carrier wafer; 21, substrate; 22, shallow trench isolation structure; 231, first dummy gate structure; 232, second dummy gate structure; 241, first gate cut-off groove; 31, oxidation isolation layer; 32, insulating isolation layer; 33, first groove; 34, first oxidation isolation structure; 35, oxidation isolation structure; 36, second groove; 37, first insulating isolation structure; 38, insulating isolation structure. DETAILED DESCRIPTION
[0025] Here, exemplary embodiments are described in detail, and examples thereof are shown in the accompanying drawings. When the following description refers to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The implementations described in the following exemplary embodiments do not represent all implementations consistent with the present application.
[0026] As Moore's Law continues to deepen, after the technology node of gate-all-around FET (GAA), continuing to promote the miniaturization of transistor size is a hot issue in the current industry research and development. Stacked transistors can achieve the integration of two or more layers of transistors in a vertical space through three-dimensional transistor stacking, which helps to further improve the integration density of transistors and improve circuit performance. It is considered to be one of the important technologies for continuing the miniaturization of integrated circuit size. At present, the high thermal budget generated during the preparation of stacked transistors is still a problem that needs to be solved urgently.
[0027] In order to solve the above technical problems, an embodiment of the present application provides a method for preparing a stacked transistor to reduce the thermal budget generated during the process of preparing the stacked transistor.
[0028] In the embodiments of the present application, the stacked transistor can be applied to semiconductor devices such as memory and processor.
[0029] In some embodiments, a stacked transistor includes: a first transistor; a second transistor; the first transistor and the second transistor are stacked; a shallow trench isolation layer, the shallow trench isolation layer is located between the first transistor and the second transistor, and is used to isolate the first transistor from the second transistor, wherein the fin structure of the first transistor and the fin structure of the second transistor are formed by the same process, the surface of the fin structure located in the shallow trench isolation layer is covered by an oxidation isolation layer, and the surface of the oxidation isolation layer is covered by an insulating isolation layer; the oxidation isolation layer is formed by depositing oxide on the surface of the fin structure, and the insulating isolation layer is formed by depositing a first insulating material on the oxidation isolation layer.
[0030] In some embodiments, since the first fin structure (i.e., the fin structure of the first transistor) and the second fin structure (i.e., the fin structure of the second transistor) are formed through the same process, the first transistor formed based on the first fin structure and the second transistor formed based on the second fin structure are self-aligned in the direction of the active area.
[0031] In the embodiment of the present application, the active region is a collective name for the source region, the drain region and the channel region.
[0032] In the embodiment of the present application, the first transistor and the second transistor in the stacked transistor may be transistors of the same type, such as a fin field effect transistor.
[0033] Figure 2 It is a stacked transistor composed of fin field effect transistors, and the following is combined Figure 2 The structure of the stacked transistor shown is used to illustrate the method for preparing the stacked transistor provided in the embodiment of the present application.
[0034] Figure 1 FIG. 1 is a schematic diagram of an implementation process of a method for preparing a stacked transistor in an embodiment of the present application, see Figure 1 As shown, the method for preparing the stacked transistor may include:
[0035] S101, forming a fin structure on a substrate; wherein the fin structure includes a first fin structure and a second fin structure.
[0036] It can be understood that a substrate is provided, a fin structure (fin) is patterned on the substrate, and then a plurality of fin structures are formed by etching.
[0037] It should be noted that in Figure 2 In the figure, the number of fin structures being 3 is only an example. The number of fin structures can be designed according to actual needs, and the embodiments of the present application do not make any specific limitation on this.
[0038] In some embodiments, since the fin structures in the two transistors (i.e., the first fin structure and the second fin structure) are formed in the same etching process, a larger etching depth can be selected during the etching process so that the height of the fin structure is sufficient to prepare the two transistors. In one example, the height of the fin structure can be greater than 100 nanometers (nm).
[0039] It should be noted that in the process of forming the fin-shaped structure by etching, a substrate with a preset height needs to be retained, and the retained substrate can play a role in supporting the fin-shaped structure.
[0040] S102, depositing oxide on the fin-shaped structure and the substrate to form an oxide isolation layer; wherein the oxide isolation layer covers the surface of the fin-shaped structure and the surface of the substrate.
[0041] It is understandable that by depositing oxide on the fin structure and the unetched substrate, an oxide isolation layer covering the fin structure and the substrate surface can be formed. The oxide isolation layer can protect the fin structure in subsequent processes.
[0042] In some embodiments, the oxide forming the oxide isolation layer may include any one of the following: silicon monoxide (SiO), silicon dioxide (SiO2), etc., but is not limited to the oxides listed above. Other oxides may also be selected according to actual needs. The embodiments of the present application do not make specific limitations on this.
[0043] In some embodiments, the integrally formed oxide isolation layer can effectively protect the fin structure in subsequent manufacturing processes.
[0044] S103, depositing a first insulating material on the oxidized isolation layer to form an insulating isolation layer, wherein the insulating isolation layer covers the surface of the oxidized isolation layer.
[0045] It can be understood that an insulating material (ie, a first insulating material) is deposited on the surface of the oxidation isolation layer to form an insulating isolation layer, and the insulating isolation layer covers the surface of the oxidation isolation layer. The insulating isolation layer is used to protect the fin structure and the oxidation isolation layer in subsequent processes.
[0046] In some embodiments, the first insulating material forming the insulating isolation layer may be silicon nitride (SiN) or other insulating materials, which is not specifically limited in the embodiments of the present application.
[0047] In some embodiments, the integrally formed insulating isolation layer can play a role in protecting the fin structure together with the oxidation isolation layer in the subsequent preparation process.
[0048] In some embodiments, during the preparation of a conventional stacked transistor, the oxide isolation layer in the first transistor and the oxide isolation layer in the second transistor are formed separately, that is, the oxide isolation layer in the first transistor is formed during the formation of the first transistor, and the oxide isolation layer in the second transistor is formed during the formation of the second transistor; in this way, the high temperature generated when forming the oxide isolation layer in the second transistor may cause damage to the first transistor. The oxide isolation layer integrally formed in the embodiment of the present application can avoid the occurrence of the above-mentioned problem, that is, avoid the thermal damage that may be caused when forming the oxide isolation layer in the second transistor.
[0049] In some possible embodiments, after the above S103 and before the following S104, the above method may further include: depositing a second insulating material on the oxide isolation layer to form a shallow trench isolation structure (STI); the shallow trench isolation structure wraps the fin structure; removing a first portion of the shallow trench isolation structure to expose the insulating isolation layer wrapping the first fin structure; removing the insulating isolation layer wrapping the first fin structure to expose the oxide isolation layer wrapping the first fin structure.
[0050] It can be understood that after the oxide isolation layer is formed, a second insulating material of a preset height is deposited on the oxide isolation layer to form a shallow trench isolation structure. The height of the shallow trench isolation structure is greater than the height of the fin structure, and the shallow trench isolation structure can wrap the insulating isolation layer. Then, the portion of the shallow trench isolation structure that wraps the first insulating isolation layer (i.e., the first portion) is removed through a chemical-mechanical planarization (CMP) process until the first insulating isolation layer is exposed; wherein the first insulating isolation layer is the portion of the insulating isolation layer corresponding to the first fin structure, and correspondingly, the second insulating isolation layer is the portion of the insulating isolation layer corresponding to the second fin structure.
[0051] In some embodiments, the second insulating material may include any of the following: silicon nitride (SiN, Si3N4), SiO2 or silicon oxycarbide (SiCO), etc. The second insulating material is not limited to the materials listed above, and other insulating materials may be selected according to actual needs, which is not specifically limited in the embodiments of the present application.
[0052] S104 , forming a first transistor based on the first fin structure.
[0053] It is understandable that other structures in the first transistor, such as the first source-drain structure, the first gate structure and the first metal interconnection layer, can be prepared based on the first fin structure according to a standard process for preparing transistors.
[0054] S105 , flipping over and thinning the substrate until a first surface of the second fin structure is exposed; wherein the first surface is a surface of the second fin structure away from the first fin structure.
[0055] It can be understood that after forming the first transistor, the first transistor is flipped so that the substrate is placed upward, and then the substrate is thinned until the first surface of the second fin structure and the oxide isolation layer covering the substrate are exposed.
[0056] In some embodiments, the substrate may be thinned by a chemical mechanical planarization process.
[0057] In some possible implementations, before the above S105, the method for preparing the stacked transistor may further include: depositing an insulating material on a surface of the first transistor away from the second fin structure to form an insulating layer; and bonding the insulating layer to the carrier wafer.
[0058] In the embodiment of the present application, the bonded carrier wafer can provide physical support for the flipped first transistor after inversion, thereby effectively preventing the first transistor from being broken by external force during the preparation of the second transistor.
[0059] It should be noted that the insulating material forming the insulating layer can be selected according to actual needs, and the embodiments of the present application do not specifically limit this.
[0060] S106 , etching the second fin structure to a preset height to form a first groove.
[0061] It can be understood that after the first surface of the second fin structure is exposed, a portion of the second fin structure can be removed by selective etching, and the groove formed by etching is the first groove.
[0062] S107, depositing oxide in the first groove to form an oxide isolation structure; wherein the height of the oxide isolation structure in the horizontal direction is the same as the height of the insulating isolation layer in the horizontal direction.
[0063] It can be understood that the same oxide as the oxide isolation layer is deposited in the first groove to form an oxide isolation structure. In the horizontal direction, the height of the oxide isolation structure is consistent with the height of the insulating isolation layer.
[0064] In some possible embodiments, the above S107 may include: depositing oxide in the first groove and on the oxidation isolation layer to form a first oxidation isolation structure; the first oxidation isolation structure is connected to the oxidation isolation layer as an integral whole; and removing the first oxidation isolation structure and the oxidation isolation layer at a preset height until the insulating isolation layer is exposed to form an oxidation isolation structure.
[0065] It can be understood that by depositing oxide in the first groove and on the exposed oxide isolation layer, a first oxide isolation structure can be formed, and the first oxide isolation structure not only fills the first groove, but also covers the above-mentioned exposed oxide isolation layer and is connected to the exposed oxide isolation layer as a whole. Then, the first oxide isolation structure and the exposed oxide isolation layer are removed by selective etching at a preset height until the insulating isolation layer located under the oxide isolation layer is exposed, and the unetched oxide inside the first groove forms an oxide isolation structure.
[0066] S108, etching the oxide isolation structure with a preset height to form a second groove, wherein the oxide isolation structure and the oxide isolation layer are connected as a whole after etching and cover the surface of the second fin structure.
[0067] It is understandable that after the oxide isolation structure is formed, the oxide isolation structure of a preset height can be removed by selective etching, and the groove formed by etching is the second groove. The etched oxide isolation structure is located on the first surface of the second fin structure, and together with the oxide isolation layer located on the sidewall of the second fin structure, covers the surface of the second fin structure to protect the second fin structure in subsequent processes.
[0068] S109, depositing a first insulating material in the second groove to form an insulating isolation structure, wherein the insulating isolation structure and the insulating isolation layer are connected as a whole and cover the surfaces of the etched oxidation isolation structure and the oxidation isolation layer.
[0069] It can be understood that the insulating material same as that of the insulating isolation layer can be deposited in the second groove to form an insulating isolation structure. Since the same material is used, the insulating isolation structure and the insulating isolation layer can be connected as one.
[0070] In some possible embodiments, the above S109 may include: depositing a first insulating material in the second groove and on the insulating isolation layer to form a first insulating isolation structure; the first insulating isolation structure is connected to the insulating isolation layer as an integral whole; and removing the first insulating isolation structure and the insulating isolation layer at a preset height until the shallow trench isolation structure is exposed to form an insulating isolation structure.
[0071] It can be understood that by depositing oxide in the second groove and on the exposed insulating isolation layer, a first insulating isolation structure can be formed, and the first insulating isolation structure not only fills the second groove, but also covers the exposed insulating isolation layer, and is connected to the exposed insulating isolation layer. Then, the first insulating isolation structure and the exposed insulating isolation layer are removed by selective etching to a preset height until the shallow trench isolation structure located under the insulating isolation layer is exposed, and the insulating material inside the second groove that is not etched forms an insulating isolation structure.
[0072] In some possible embodiments, after the above S109 and before the following S110, the above method may further include: removing the second portion of the shallow trench isolation structure to expose the insulating isolation layer and the insulating isolation structure wrapping the second fin structure, and forming a shallow trench isolation layer; the shallow trench isolation layer is located between the first transistor and the second transistor, and is used to isolate the first transistor from the second transistor.
[0073] It can be understood that after the insulating isolation structure is formed, the portion of the shallow trench isolation structure that wraps the second insulating isolation layer (i.e., the second portion) can be removed by selective etching until the second insulating isolation layer and the insulating isolation structure are exposed; in the process of etching the shallow trench isolation structure, the shallow trench isolation structure of a preset height is retained, and the shallow trench isolation structure that has not been etched is the shallow trench isolation layer. The shallow trench isolation layer is located between the first transistor and the second transistor, and can be used to isolate the first transistor from the second transistor.
[0074] S110, forming a second transistor based on the second fin structure
[0075] It can be understood that after the oxidation isolation structure and the insulation isolation structure are formed, the second transistor can be formed according to a standard process for manufacturing a transistor.
[0076] In some embodiments, since the second transistor is formed based on the second fin structure after flipping the first transistor, the second transistor and the first transistor are stacked “back to back” and are self-aligned.
[0077] In some possible implementations, during the process of forming the first transistor, the method may further include: performing a gate cut-off process on the first dummy gate structure of the first transistor to form a first gate cut-off structure.
[0078] It can be understood that in the process of preparing the first transistor, after forming the first dummy gate structure in the first transistor, the first dummy gate structure can be gate cut off to form a first gate cut off groove, and then the first gate cut off groove is filled with insulating material to form a first gate cut off structure.
[0079] In some possible implementations, during the process of forming the second transistor, the method may further include: performing a gate cut-off process on the second dummy gate structure of the second transistor to form a second gate cut-off structure.
[0080] It can be understood that in the process of preparing the second transistor, after forming the second dummy gate structure in the second transistor, the second dummy gate structure can be gate cut off to form a second gate cut off groove, and then the second gate cut off groove is filled with insulating material to form a second gate cut off structure.
[0081] In some possible embodiments, the above S104 may include: photolithography to open the first gate region of the first transistor; deposit polysilicon in the first gate region to form a first dummy gate structure; deposit insulating material on the sidewalls of the first dummy gate structure to form a first spacer; deposit dielectric material in other regions of the first transistor except the first gate region to form a first interlayer dielectric layer; perform gate cut-off processing on the first dummy gate structure to form a first gate cut-off structure; remove the first interlayer dielectric layer; perform source and drain epitaxial growth in the first source and drain region of the first transistor to form a first source and drain structure; re-deposit dielectric material to form a first interlayer dielectric layer; remove the first dummy gate structure and the oxide isolation layer covering the surface of the first fin structure; form a first gate dielectric layer and a first gate structure in the first gate region; form a first source and drain metal above the first source and drain structure; perform a post-process above the first gate structure and the first source and drain metal to form a first metal interconnection layer.
[0082] In some possible embodiments, the above S110 may include: photolithographically opening the second gate region of the second transistor; depositing polysilicon in the second gate region to form a second dummy gate structure; depositing insulating material on the sidewalls of the second dummy gate structure to form a second spacer; depositing dielectric material in other regions of the second transistor except the second gate region to form a second interlayer dielectric layer; performing gate cut-off processing on the second dummy gate structure to form a second gate cut-off structure; removing the second interlayer dielectric layer; performing source and drain epitaxial growth in the second source and drain region of the second transistor to form a second source and drain structure; re-depositing dielectric material to form a second interlayer dielectric layer; removing the second dummy gate structure and the insulating isolation structure, insulating isolation layer, oxidation isolation structure and oxidation isolation layer that wrap the second fin structure; forming a second gate dielectric layer and a second gate structure in the second gate region; forming a second source and drain metal above the second source and drain structure; performing a post-process above the second gate structure and the second source and drain metal to form a second metal interconnection layer.
[0083] In the embodiments of the present application, the first source-drain structure represents the source and / or drain in the first transistor. Accordingly, other expressions related to "source and drain" in the embodiments of the present application are all used to represent "source and / or drain", such as: the second source-drain structure, the first source-drain metal and the second source-drain metal, etc.
[0084] Below, the stacked transistor provided in the embodiment of the present application is described by taking the first transistor and the second transistor as fin-type field effect transistors as an example. Figure 2 This is a schematic diagram of a structure of a stacked transistor in an embodiment of the present application. Figure 2(a) is the design layout of the stacked transistor. It should be noted that, for ease of understanding, only the fin structure, gate structure and source-drain structure are shown in the design layout; (b) is a cross-sectional view of the stacked transistor along the cross-sectional direction of the gate structure (i.e., AA' direction); (c) is a cross-sectional view of the stacked transistor along the cross-sectional direction of the source-drain structure (i.e., BB' direction); (d) is a cross-sectional view of the stacked transistor along the cross-sectional direction of the fin structure (i.e., CC' direction).
[0085] See also Figure 2 As shown, the stacked transistor 10 includes: a first transistor 11, a second transistor 12 and a shallow trench isolation layer 13. The first transistor 11 and the second transistor 12 are stacked "back to back"; the shallow trench isolation layer 13 is located between the first transistor 11 and the second transistor 12, and is used to isolate the first transistor 11 and the second transistor 12, wherein the fin structure of the first transistor 11 and the fin structure of the second transistor 12 are formed by the same process, the surface of the fin structure located in the shallow trench isolation layer 13 is covered by an oxidation isolation layer 31, and the surface of the oxidation isolation layer 31 is covered by an insulating isolation layer 32; the oxidation isolation layer 31 is formed by depositing oxide on the surface of the fin structure, and the insulating isolation layer 32 is formed by depositing a first insulating material on the oxidation isolation layer 31.
[0086] Figure 2 The stacked transistor 10 shown may be FIG. 3A to FIG. 3J The process shown is prepared FIG. 3A to FIG. 3J A schematic diagram of the preparation process of stacked crystals in an embodiment of the present application.
[0087] In one example, the manufacturing process of the stacked transistor 10 may include the following steps:
[0088] Step 1: Provide a substrate 21 (see Figure 3A (a) in the figure). The substrate may be a silicon (Si) substrate.
[0089] Step 2: Etching the substrate 21 to form a first fin structure 111 and a second fin structure 121 (see Figure 3A (b) in the figure.
[0090] Step 3: Depositing oxide on the unetched substrate 21 and the surfaces of the first fin structure 111 and the second fin structure 121 to form an oxide isolation layer 31 (see Figure 3A (c) in the figure.
[0091] Step 4: Deposit a first insulating material on the oxide isolation layer 31 to form an insulating isolation layer 32 (see Figure 3B (a) in the figure.
[0092] Step 5: Deposit a second insulating material on the insulating isolation layer 32 to form a shallow trench isolation structure 22. The height of the shallow trench isolation structure 22 is greater than the height of the fin structure (see Figure 3B (b) in the figure.
[0093] Step 6: Remove the portion of the shallow trench isolation structure 22 that wraps the first fin structure 111 by etching until the portion of the insulating isolation layer 32 corresponding to the first fin structure 111 is exposed (see Figure 3B (c) in the figure.
[0094] Step 7: Remove the portion of the insulating isolation layer 32 corresponding to the first fin structure 111 to expose the portion of the oxidized isolation layer 31 corresponding to the first fin structure 111 (see Figure 3C (a) in the figure.
[0095] Step 8: Photolithography opens the first gate region of the first transistor 11, and deposits polysilicon in the first gate region to form a first dummy gate structure 231 (see Figure 3C (b) in the figure.
[0096] Step 9: Deposit an insulating material on the sidewall of the first dummy gate structure 231 to form a first spacer 112; deposit an interlayer dielectric in the region other than the first gate region in the first transistor 11 to form a first interlayer dielectric layer 113 (see Figure 3C (c) in the figure.
[0097] Step 10: Perform gate cutting processing on the first dummy gate structure 231 to form a first gate cutting groove 241 (see Figure 3D (a) in the figure.
[0098] Step 11: Deposit an insulating material in the first gate cutting groove 241 to form a first gate cutting structure 114 (see Figure 3D (b) in the figure.
[0099] Step 12: Remove the first interlayer dielectric layer 113 (see Figure 3D (c) in the figure.
[0100] Step 13: Etching the first fin structure 111 to form a first source-drain groove, performing source-drain epitaxial growth in the first source-drain groove to form a first source-drain structure 115; re-depositing an interlayer dielectric in the area other than the first gate area in the first transistor 11 to form a first interlayer dielectric layer 113 (see Figure 3E (a) in the figure.
[0101] Step 14: remove the first dummy gate structure 231 and the portion of the oxide isolation layer 31 covering the surface of the first fin structure 111, deposit an insulating material in the first gate region to form a first gate dielectric layer 116; fill the first gate region with a metal material to form a first gate structure 117 (see Figure 3E (b) in the figure.
[0102] Step 15: Form a first source-drain metal 118 on the first source-drain structure 115; perform a back-end process on the first gate structure 117 and the first source-drain metal 118 to form a first metal interconnect layer 119 (see Figure 3E (c) in the figure.
[0103] Step 16: Deposit insulating material on the first metal interconnect layer 119 to form an insulating layer 14, bond the insulating layer 14 to the carrier wafer 15, and then flip the first transistor 11 so that the substrate 21 is placed upward (see Figure 3F (a) in the figure.
[0104] Step 17: Perform chemical mechanical planarization on the substrate 21 so that the oxide isolation layer 31 and the first surface of the second fin structure 121 are exposed (see Figure 3F (b) in the figure.
[0105] Step 18: Etch a portion of the second fin structure to form a first groove 33 (see Figure 3F (c) in the figure.
[0106] Step 19: Deposit oxide on the first groove 33 and the oxide isolation layer 31 to form a first oxide isolation structure 34 (see Figure 3G (a) in the figure.
[0107] Step 20: Remove a portion of the first oxide isolation structure 34 through a chemical mechanical planarization process, leaving only the oxide filled in the first groove 33, exposing the insulating isolation layer 32, and forming an oxide isolation structure 35 (see Figure 3G (b) in the figure.
[0108] Step 21: Etching the oxide isolation structure 35 of a preset height. The etched oxide isolation structure 35 is connected to the oxide isolation layer to cover the surface of the second fin structure 121 and form a second groove 36 (see Figure 3G (c) in the figure.
[0109] Step 22: Deposit a first insulating material in the second groove 36 and on the insulating isolation layer 32 to form a first insulating isolation structure 37 (see Figure 3H (a) in the figure.
[0110] Step 23: A portion of the first insulating isolation structure 37 is removed by chemical mechanical planarization process, and only the first insulating material in the second groove 36 is retained until the shallow trench isolation structure 22 is exposed, and an insulating isolation structure 38 is formed. The insulating isolation structure 38 and the insulating isolation layer 32 are connected as a whole, and together cover the surface of the etched oxide isolation structure 35 and the oxide isolation layer 31 (see Figure 3H (b) in the figure.
[0111] Step 24: remove the portion of the shallow trench isolation structure 22 that wraps the second fin structure 121, expose the portion of the insulating isolation layer 32 that is connected to the second fin structure 121, and retain the shallow trench isolation structure 22 of a preset height. The retained shallow trench isolation structure 22 is the shallow trench isolation layer 13 (see Figure 3H (c) in the figure.
[0112] Step 25: Photolithography opens the second gate region of the second transistor 12, and deposits polysilicon in the second gate region to form a second dummy gate structure 232 (see Fig. 3I (a) in the figure.
[0113] Step 26: Deposit an insulating material on the sidewall of the second dummy gate structure 232 to form a second spacer 122; deposit an interlayer dielectric in the area other than the first gate area in the second transistor 12 to form a second interlayer dielectric layer 123 (see Fig. 3I (b) in the figure.
[0114] Step 27: Form a second gate cut-off structure 124 in the second transistor 12 (refer to steps 10 and 11 for the specific process) (refer to Fig. 3I (c) in the figure.
[0115] Step 28: Form a second source-drain structure 125 in the second transistor 12 (refer to step 13 for the specific process) (refer to step 13 for the specific process) Figure 3J (a) in the figure.
[0116] Step 29: remove the second dummy gate structure 232, the insulating isolation structure 38, the portion of the insulating isolation layer 32 corresponding to the second fin structure 121, the oxidation isolation structure 35, and the portion of the oxidation isolation layer 31 covering the surface of the second fin structure 121, deposit an insulating material in the second gate region to form a second gate dielectric layer 126; fill the second gate region with a metal material to form a second gate structure 127 (see Figure 3J (b) in the figure.
[0117] Step 30: Form a second source-drain metal 128 on the second source-drain structure 125; perform a back-end process on the second gate structure 127 and the second source-drain metal 128 to form a second metal interconnect layer 129 (see Figure 3J (c) in the figure.
[0118] At this point, the stacked transistor 10 is manufactured according to the above manufacturing method.
[0119] In some embodiments, the gate cut-off structure (i.e., the first gate cut-off structure and the second gate cut-off structure) can be designed as a gate cut-off hole or a gate cut-off line according to actual needs, and the present application embodiment does not specifically limit this. In one example, different forms of the first gate cut-off structure and the second gate cut-off structure can be formed according to different design layouts; Figure 4 This is a design layout of the gate cut-off structure in the embodiment of the present application; Figure 4 (a) shows a gate cut-off structure in the form of a gate cut-off hole, Figure 4 (b) in FIG. 1 shows a gate cutoff structure in the form of a gate cutoff line.
[0120] In some embodiments, a semiconductor device may include multiple stacked transistors, and the multiple stacked transistors play different roles in the semiconductor device. According to the difference in function, the stacked transistors in the semiconductor device can be divided into logic transistors and input-output transistors. Among them, logic transistors are mainly used to build digital logic circuits and are distributed in the internal logic area of the semiconductor device; input-output transistors are used for the input and output interfaces of integrated circuits and are mainly distributed in the edge or peripheral area of the semiconductor device.
[0121] In some embodiments, when the stacked transistor is a logic transistor, the structure of the stacked transistor is as follows: Figure 2 As shown, there is no oxidation isolation layer and insulation isolation layer on the surface of the first fin structure and the second fin structure; the surface of the fin structure located in the shallow trench isolation layer is covered with the oxidation isolation layer and insulation isolation layer.
[0122] In some embodiments, when the stacked transistor is an input and output transistor, since a higher withstand voltage value needs to be provided, there is no need to remove the oxide isolation layer and the oxide isolation structure during the preparation of the first transistor and the second transistor. In the stacked transistor finally formed, the surface of the first fin structure is covered with the oxide isolation layer, and the surface of the second fin structure is covered with the oxide isolation layer and the oxide isolation structure (not shown in the figure); the surface of the fin structure located in the shallow trench isolation layer is covered with the oxide isolation layer and the insulating isolation layer.
[0123] It should be noted that the difference between the stacked transistors being logic transistors and the stacked transistors being input / output transistors is only reflected in the setting of the oxide isolation layer, and the other structures in the transistors are the same, which will not be elaborated in the embodiments of the present application.
[0124] In an embodiment of the present application, an oxidation isolation layer and an insulating isolation layer are formed outside the first fin structure and the second fin structure, and the oxidation isolation layer and the insulating isolation layer on the surface of the first fin structure and the second fin structure are integrally formed, which can avoid the formation of an oxidation isolation layer again on the surface of the second fin structure during the preparation of the second transistor, and solves the problem of excessive thermal budget caused by forming the oxidation isolation layer multiple times in the stacked transistor.
[0125] Furthermore, the oxidation isolation layer and the insulating isolation layer formed outside the first fin structure and the second fin structure can effectively protect the first fin structure and the second fin structure during the process of preparing the stacked transistor.
[0126] Furthermore, the method for preparing the stacked transistor described in the embodiment of the present application is also an organic fusion of the current sequential and monolithic stacked transistor solutions. The mature technology has high reuse, can avoid a large amount of expensive process development to save costs, and has high feasibility. At the same time, in the embodiment of the present application, the stacked transistor adopts a self-aligned "back-to-back" active area and metal gate design, and the front and back transistors (i.e., the first transistor and the second transistor) have independent signal and power supply networks, and are connected through local interconnection. Without changing the extremely miniaturized 4T track unit design, the metal wiring resources are greatly released (can be increased by more than 60%), and there is huge space in the direction of collaborative optimization of process design. Finally, the preparation method of the stacked transistor is compatible with the existing mainstream device architecture, and can realize the front and back stacking of planar transistors, fin field effect transistors, nanosheet field effect transistors and even vertical field effect transistors (VTFETs) without the need for special process development for specific device architectures. It has strong flexibility and is highly extensible from the perspective of semiconductor process node iteration. The inverted stacked transistor is very advanced in concept, has important industrial value, and has strong practicality and broad prospects for expansion.
[0127] Furthermore, the structure of the stacked transistor provided in the embodiment of the present application can be detected using a detection and analysis instrument, such as a scanning electron microscope (SEM), a transmission electron microscope (TEM), a scanning transmission electron microscope (STEM), etc. Taking TEM as an example, the stacked transistor provided in the embodiment of the present application can be detected by TEM slicing. For example, the oxide isolation layer and the insulating isolation layer located on the side wall of the fin structure can be observed in the shallow trench isolation layer.
[0128] The present application embodiment provides a semiconductor device, including: a stacked transistor as described in the above embodiment. The specific definition of the stacked transistor can be found in the above Figure 2 The stacked transistors shown are not described in detail here.
[0129] The present application embodiment provides an electronic device, including: a circuit board and a semiconductor device as described in the above embodiment, wherein the semiconductor device is arranged on the circuit board. The semiconductor device includes the above stacked transistor. The specific definition of the stacked transistor can be found in the above Figure 2 , I will not go into details here.
[0130] In the description of the present application, the description with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the embodiments of the present application. In the present application, the schematic representation of the above terms is not necessarily for the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine different embodiments or examples described in the present application and the features of different embodiments or examples without contradiction.
[0131] The above are only preferred embodiments of the present application and are not intended to limit the present application. For those skilled in the art, the present application may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.
Claims
1. A method for preparing a stacked transistor, characterized in that: The stacked transistor includes a first transistor and a second transistor arranged in a stacked manner; the method includes: forming a fin structure on a substrate; the fin structure comprises a first fin structure and a second fin structure; Depositing oxide on the fin-shaped structure and the substrate to form an oxide isolation layer; the oxide isolation layer covers the surface of the fin-shaped structure and the surface of the substrate; Depositing a first insulating material on the oxidation isolation layer to form an insulating isolation layer; the insulating isolation layer covers the surface of the oxidation isolation layer; Based on the first fin structure, forming the first transistor; Flipping and thinning the substrate until a first surface of the second fin structure is exposed; the first surface is a surface of the second fin structure that is away from the first fin structure; Etching the second fin-shaped structure to a preset height to form a first groove; Depositing the oxide in the first groove to form an oxidation isolation structure; the height of the oxidation isolation structure in the horizontal direction is the same as the height of the insulating isolation layer in the horizontal direction; Etching the oxide isolation structure to a preset height to form a second groove; Depositing the first insulating material in the second groove to form an insulating isolation structure; the insulating isolation structure and the insulating isolation layer are connected as a whole and cover the surfaces of the etched oxidized isolation structure and the oxidized isolation layer; Based on the second fin structure, the second transistor is formed.
2. The method according to claim 1, characterized in that: Before forming the first transistor based on the first fin structure, the method further includes: Depositing a second insulating material on the oxide isolation layer to form a shallow trench isolation structure; the shallow trench isolation structure wraps the fin structure; removing a first portion of the shallow trench isolation structure to expose an insulating isolation layer wrapping the first fin-shaped structure; The insulating isolation layer surrounding the first fin structure is removed to expose the oxidized isolation layer surrounding the first fin structure.
3. The method according to claim 2, characterized in that Before forming the second transistor based on the second fin structure, the method further includes: The second portion of the shallow trench isolation structure is removed to expose the insulating isolation layer and the insulating isolation structure wrapping the second fin-shaped structure, and to form a shallow trench isolation layer; the shallow trench isolation layer is located between the first transistor and the second transistor, and is used to isolate the first transistor from the second transistor.
4. The method according to claim 3, characterized in that The step of depositing the oxide in the first groove to form an oxide isolation structure comprises: Depositing the oxide in the first groove and on the oxide isolation layer to form a first oxide isolation structure; the first oxide isolation structure is integrally connected with the oxide isolation layer; The first oxidation isolation structure and the oxidation isolation layer of a preset height are removed until the insulating isolation layer is exposed to form the oxidation isolation structure.
5. The method according to claim 4, characterized in that The step of depositing the first insulating material in the second groove to form an insulating isolation structure includes: Depositing the first insulating material in the second groove and on the insulating isolation layer to form a first insulating isolation structure; the first insulating isolation structure is integrally connected with the insulating isolation layer; The first insulating isolation structure and the insulating isolation layer of a preset height are removed until the shallow trench isolation structure is exposed to form the insulating isolation structure.
6. The method according to claim 1, characterized in that During the process of forming the first transistor, the method further includes: performing a gate cut-off process on a first dummy gate structure of the first transistor to form a first gate cut-off structure.
7. The method according to claim 1, characterized in that During the process of forming the second transistor, the method further includes: performing a gate cut-off process on the second dummy gate structure of the second transistor to form a second gate cut-off structure.
8. A stacked transistor, characterized in that: Prepared by the method according to any one of claims 1 to 7, the stacked transistor comprises: a first transistor; a second transistor; the first transistor and the second transistor are stacked; a shallow trench isolation layer, wherein the shallow trench isolation layer is located between the first transistor and the second transistor and is used to isolate the first transistor from the second transistor; Among them, the fin structure of the first transistor and the fin structure of the second transistor are formed by the same process, the surface of the fin structure located in the shallow trench isolation layer is covered by an oxidation isolation layer, and the surface of the oxidation isolation layer is covered by an insulating isolation layer; the oxidation isolation layer is formed by depositing oxide on the surface of the fin structure, and the insulating isolation layer is formed by depositing a first insulating material on the oxidation isolation layer.
9. A semiconductor device, characterized in that: include: The stacked transistor as claimed in claim 8.
10. An electronic device, characterized in that: include: A circuit board and a semiconductor device as claimed in claim 9, wherein the semiconductor device is arranged on the circuit board.