Method and structure for integrating thick and thin gate oxide CMOS (Complementary Metal Oxide Semiconductor) device in double polycrystal self-aligned bipolar junction transistor process

Abstract

The invention discloses a method and a structure for integrating thick and thin gate oxide CMOS (Complementary Metal Oxide Semiconductor) devices in a double polycrystal self-aligned bipolar junction transistor process. The method comprises the following steps of: providing an SOI (Silicon On Insulator) silicon substrate; sequentially forming an N-type primary buried layer (103) of the double polycrystal self-aligned bipolar junction transistor, a P-type primary buried layer (104) of the thin gate oxide NMOS and a P-type secondary buried layer (105) of the thick gate oxide NMOS; forming an epitaxial layer (106) on the SOI silicon substrate; and forming a P-type primary well region (107) of the thin gate oxide NMOS and a P-type secondary well region (108) of the thick gate oxide NMOS in the epitaxial layer. According to the semiconductor device, various combinations of high-performance NPN / PNP and thick and thin gate oxide CMOS devices can be achieved, the overall device characteristics of the process are effectively improved, the application technical field with wider and higher requirements is met, and the electrical performance of a chip is improved.

Description

Technical Field

[0001] The invention relates to the technical field of semiconductor devices, in particular to a method and structure for integrating thick-thin gate oxide CMOS devices in a dual polycrystalline self-aligned bipolar junction transistor process. Background Art

[0002] As an indispensable part of the circuit system currently in use, analog integrated circuits and mixed analog and digital circuits will find increasing uses in application fields that require high-speed and high-performance communications or external interfaces. With the further intensification of the demand for higher-performance products such as high density, low power consumption and high-speed and large driving capabilities, as well as the continuous reduction of line width and the advantages of CMOS voltage drive and the need for related high-precision AD / DA products, the integration of CMOS in the bipolar process platform has become a new direction. Bipolar circuits have the characteristics of high speed, strong current driving capability and high analog accuracy, while CMOS circuits have incomparable advantages in high integration and low power consumption. In today's integrated circuit manufacturing industry that is constantly pursuing higher performance and more perfection, the perfect combination of the complementary advantages of these two processes has produced a new BiCMOS process.

[0003] The high-speed BiCMOS process platform is a long-term blank area in the domestic bipolar process platform. It plays an irreplaceable role in the manufacturing of high-end high-speed amplifiers, high-precision AD / DA and other chips. Such chips are widely used in various precision communication equipment, high-precision test instruments, and automotive electronics. Currently, such products are all imported from abroad. In particular, high-speed BiCMOS currently faces many challenges, such as high process integration, complex manufacturing process, high cost, and difficulty in ensuring yield. In order to overcome the challenges, it is necessary to continuously research and improve the manufacturing process technology to improve the performance and reliability of the circuit.

[0004] Therefore, there is an urgent need for a method that can integrate high-speed bipolar transistors and CMOS devices in a single manufacturing process without increasing the complexity of the process. Summary of the invention

[0005] The object of the present invention is to provide a method for integrating thick-thin gate oxide CMOS devices in a dual poly self-aligned bipolar junction transistor process, characterized in that it comprises the following steps:

[0006] 1) Provide an SOI silicon substrate.

[0007] 2) An N-type primary buried layer of a dual polycrystalline self-aligned bipolar junction transistor, a P-type primary buried layer of a thin gate oxide NMOS, and a P-type secondary buried layer of a thick gate oxide NMOS are sequentially formed.

[0008] 3) Form an epitaxial layer on the SOI silicon substrate.

[0009] 4) Forming a P-type primary well region of a thin-gate oxide NMOS and a P-type secondary well region of a thick-gate oxide NMOS in the epitaxial layer.

[0010] 5) Forming full dielectric island isolation of dual polycrystalline self-aligned bipolar junction transistor and thin gate oxide NMOS / thick gate oxide NMOS, including trench isolation oxide layer and trench isolation polysilicon.

[0011] 6) Performing N-type penetration implantation on the collector of the dual poly self-aligned bipolar junction transistor to connect with the N-type primary buried layer.

[0012] 7) Forming a field oxide layer of a selective oxidation structure, rinsing away excess silicon nitride, and forming an active region and a field region in the double poly self-aligned bipolar junction transistor and thin gate oxide NMOS / thick gate oxide NMOS regions, respectively.

[0013] 8) Remove the pre-oxidation layer in the thin-gate-oxide NMOS / thick-gate-oxide NMOS region.

[0014] 9) Growing a thick gate oxide layer to form a thick gate oxide layer.

[0015] 10) Remove the gate oxide of the thin-gate-oxide NMOS and retain the gate oxide of the bipolar transistor and the thick-gate-oxide NMOS region.

[0016] 11) Grow a gate oxide layer to form a thin gate oxide.

[0017] 12) Deposit the first layer of polysilicon and perform gate poly implantation.

[0018] 13) Remove excess polycrystalline to form a polysilicon gate region of a thin-gate-oxide NMOS and a polysilicon gate region of a thick-gate-oxide NMOS.

[0019] 14) Perform source-drain heavy doping for thin-gate oxide NMOS and LDD implantation and source-drain heavy doping for thick-gate oxide NMOS.

[0020] 15) Deposit the first dielectric layer before TEOS metal and remove the oxide layer in the bipolar transistor area.

[0021] 16) Deposit a second layer of polysilicon, perform external base region and collector contact implantation, remove excess polycrystalline, and form a polysilicon collector and polysilicon base.

[0022] 17) Deposit the second dielectric layer before TEOS metal, remove the oxide layer and polycrystalline, and form the base window of the bipolar transistor.

[0023] 18) P-type base region is implanted and connected to the P heavily doped external base region 132 diffused into silicon by polycrystalline to form a double base region through the polysilicon base.

[0024] 19) An L-shaped sidewall structure emission region window is formed by multiple deposition and etching steps, including a sidewall oxide layer and a sidewall silicon nitride layer.

[0025] 20) Forming a polysilicon emitter of a double poly self-aligned bipolar junction transistor and an N-type heavily doped emitter region.

[0026] 21) Depositing metal to form a double polycrystalline self-aligned bipolar junction transistor metal structure.

[0027] Furthermore, the P-type primary buried layer of the NMOS is located between the N-type primary buried layer and the N-type secondary buried layer of the PMOS, and is not in contact with the N-type primary buried layer and the N-type secondary buried layer of the PMOS.

[0028] Furthermore, the trench isolation oxide layer at the bottom of the trench isolation contacts the oxide layer on the SOI substrate.

[0029] Furthermore, in step 7), a field oxide layer of a selective oxidation structure is formed using a photoresist.

[0030] In step 8), the pre-oxidation layer in the thin-gate-oxide NMOS / thick-gate-oxide NMOS region is removed by wet etching using a photoresist.

[0031] In step 10), the gate oxide of the thin gate oxide NMOS is removed by wet etching using a photoresist.

[0032] In step 13), excess polycrystalline is removed by dry etching using a photoresist.

[0033] In step 15), the oxide layer in the bipolar transistor region is removed by wet etching using a photoresist.

[0034] In step 16), a photomask is used to perform external base region and collector contact implantation, and the photomask is used to remove excess polycrystalline by dry etching.

[0035] In step 17), the oxide layer and the polycrystalline are removed by dry etching using a photoresist.

[0036] Further, in step 14), after the source and drain heavy doping of the thin gate oxide NMOS and the LDD injection and source and drain heavy doping of the thick gate oxide NMOS are performed, a P-type primary well heavy doping, an N-type source region, and an N-type drain region of the thin gate oxide NMOS are formed, and a P-type secondary well heavy doping, a source region LDD, a drain region LDD, an N-type source region, and an N-type drain region of the thick gate oxide NMOS are formed.

[0037] Further, in step 20), the steps of forming the polysilicon emitter of the dual poly self-aligned bipolar junction transistor and the N-type heavily doped emitter region are:

[0038] A third layer of polysilicon is deposited, and an emitter region of a double polysilicon self-aligned bipolar junction transistor is formed by implantation using a photoresist.

[0039] The redundant polycrystalline is etched out by dry etching using a photomask to form a polysilicon emitter of a double polycrystalline self-aligned bipolar junction transistor.

[0040] An N-type heavily doped emitter region is formed by annealing the emitter region.

[0041] Further, the step of depositing metal to form a dual polycrystalline self-aligned bipolar junction transistor metal structure includes:

[0042] Holes are opened on the polycrystals of the collector region and the double base region of the double polycrystal self-aligned bipolar junction transistor and metal is deposited to form collector metal and base metal.

[0043] Metal is deposited on the polysilicon emitter of the double poly self-aligned bipolar junction transistor to form an emitter metal.

[0044] Holes are opened on the heavily doped silicon substrate of the N-type source region, drain region and P-well of the thin-gate oxide NMOS and metal is deposited to form source metal, drain metal and BACK terminal metal.

[0045] A hole is opened on the gate polycrystalline of the thin-gate oxide NMOS and metal is deposited to form a gate metal. A hole is opened on the P-type source region, drain region, and N-well heavily doped silicon substrate of the thick-gate oxide NMOS and metal is deposited to form a source metal, a drain metal, and a BACK terminal metal.

[0046] A hole is opened on the gate polycrystalline of the thick gate oxide NMOS and metal is deposited to form a gate metal.

[0047] Furthermore, the SOI silicon substrate includes a P-type substrate, an oxide layer on the substrate, and silicon on the oxide layer, or the SOI silicon substrate is a single crystal silicon substrate.

[0048] The material of the SOI silicon substrate includes bulk silicon, silicon carbide, gallium arsenide, indium phosphide or silicon germanium.

[0049] The dual poly self-aligned bipolar junction transistor is NPN, PNP and a combination of the two.

[0050] The thin-gate-oxide NMOS / thick-gate-oxide NMOS are NMOS, PMOS and a combination of the two.

[0051] Furthermore, the polysilicon collector, polysilicon base and polysilicon emitter are composed of one or more repeated structural units.

[0052] A method for integrating thick-thin gate oxide CMOS devices in a dual polycrystalline self-aligned bipolar junction transistor process. The dual polycrystalline self-aligned bipolar junction transistor integrating thick-thin gate oxide CMOS devices is prepared by the method.

[0053] The technical effect of the present invention is unquestionable. The present invention provides a method and structure for integrating thick-thin gate oxide CMOS devices in a dual-poly self-aligned bipolar junction transistor process. Under the premise that the overall process complexity and process technology difficulty are not significantly increased, the integration of dual-poly self-aligned polysilicon emitter transistors and thick-thin gate oxide CMOS devices is achieved in the same process flow.

[0054] The beneficial effects of the present invention are as follows:

[0055] 1) The present invention proposes a method and structure for integrating thick-thin-gate-oxide CMOS devices in a dual-poly self-aligned bipolar junction transistor process. Under the premise that the overall process complexity and process technology difficulty are not significantly increased, the integration of dual-poly self-aligned polysilicon emitter transistors and thick-thin-gate-oxide CMOS devices is achieved in the same process flow, the process cost is reduced, the processing efficiency is improved, and the method is particularly suitable for the development of high-speed BiCMOS related processes.

[0056] 2) The semiconductor device of the present invention can realize various combinations of high-performance NPN / PNP and thick-thin gate oxide CMOS devices, effectively improving the overall device characteristics of the process to meet wider and higher demand application technology fields and improve the electrical performance of the chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0057] Figure 1 It is a schematic diagram of the steps of the method for integrating thick-thin gate oxide CMOS devices in a dual poly self-aligned bipolar junction transistor process in the present invention.

[0058] Figure 2-Figure 16 It shows a process flow chart of a method for integrating thick-thin-gate-oxide CMOS devices in a dual-poly self-aligned bipolar junction transistor process according to an embodiment of the present invention.

[0059] In the figure: P-type substrate 100, oxide layer 101 on substrate, silicon 102 on oxide layer, N-type primary buried layer 103, P-type primary buried layer 104, P-type secondary buried layer 105, epitaxial layer 106, P-type primary well region 107, P-type secondary well region 108, trench isolation oxide layer 109, trench isolation polysilicon 110, N-type penetration 111, field oxide layer 112, thick gate oxide layer 113, thin gate oxide layer 114, thin gate oxide NMOS polysilicon gate 115, thick gate oxide NMOS polysilicon gate 116, thick gate oxide NMOS source region LDD117, thick gate oxide NMOS drain region LDD118, P-type primary well heavily doped 119, thin gate oxide NMOS N-type source region 120, thin gate oxide NMOS N-type drain region 121, P-type secondary well heavily doped 122, thick gate oxide NMOS N-type source region 123, thick gate oxide NMOS N-type drain region 124, the first dielectric layer before TEOS metal 125, the polysilicon collector 126, the polysilicon base 127, the second dielectric layer before TEOS metal 128, the sidewall oxide layer 129, the sidewall silicon nitride 130, the polysilicon emitter 131, the P heavily doped external base region 132, the P-type base region 133, the N-type heavily doped emitter region 134, the collector metal 135, the base metal 136, the emitter metal 137, the thin gate oxide NMOS BACK terminal metal 138, the thin gate oxide NMOS source metal 139, the thin gate oxide NMOS gate metal 140, the thin gate oxide NMOS drain metal 141, the thick gate oxide NMOS BACK terminal metal 142, the thick gate oxide NMOS source metal 143, the thick gate oxide NMOS gate metal 144, and the thick gate oxide NMOS drain metal 145. DETAILED DESCRIPTION

[0060] The present invention is further described below in conjunction with the embodiments, but it should not be understood that the above subject matter of the present invention is limited to the following embodiments. Without departing from the above technical ideas of the present invention, various substitutions and changes are made according to the common technical knowledge and customary means in the art, which should all be included in the protection scope of the present invention.

[0061] Embodiment 1:

[0062] See also Figure 1-Figure 16 , a method for integrating thick-thin-gate oxide CMOS devices in a dual poly self-aligned bipolar junction transistor process, comprising the following steps:

[0063] 1) Provide an SOI silicon substrate.

[0064] 2) An N-type primary buried layer 103 of a dual poly self-aligned bipolar junction transistor, a P-type primary buried layer 104 of a thin gate oxide NMOS, and a P-type secondary buried layer 105 of a thick gate oxide NMOS are sequentially formed.

[0065] 3) An epitaxial layer 106 is formed on the SOI silicon substrate.

[0066] 4) A P-type primary well region 107 of a thin-gate-oxide NMOS and a P-type secondary well region 108 of a thick-gate-oxide NMOS are formed in the epitaxial layer.

[0067] 5) Full dielectric island isolation of dual polycrystalline self-aligned bipolar junction transistor and thin-gate oxide NMOS / thick-gate oxide NMOS is formed, including trench isolation oxide layer 109 and trench isolation polysilicon 110.

[0068] 6) Performing N-type penetration 111 implantation on the collector of the dual poly self-aligned bipolar junction transistor to connect with the N-type primary buried layer 103 .

[0069] 7) Form a field oxide layer 112 of a selective oxidation structure, rinse off excess silicon nitride, and form active regions and field regions in the dual poly self-aligned bipolar junction transistor and thin gate oxide NMOS / thick gate oxide NMOS regions, respectively.

[0070] 8) Remove the pre-oxidation layer 146 in the thin-gate-oxide NMOS / thick-gate-oxide NMOS region.

[0071] 9) Grow a thick gate oxide layer to form a thick gate oxide layer 113 .

[0072] 10) Remove the gate oxide of the thin-gate-oxide NMOS and retain the gate oxide of the bipolar transistor and the thick-gate-oxide NMOS region.

[0073] 11) Grow a gate oxide layer to form a thin gate oxide 114.

[0074] 12) Deposit the first layer of polysilicon and perform gate poly implantation.

[0075] 13) Remove excess polycrystalline to form a polysilicon gate region 115 of a thin-gate-oxide NMOS and a polysilicon gate region 116 of a thick-gate-oxide NMOS.

[0076] 14) Perform source-drain heavy doping for thin-gate oxide NMOS and LDD implantation and source-drain heavy doping for thick-gate oxide NMOS.

[0077] 15) Deposit the first dielectric layer 125 before TEOS metal, and remove the oxide layer in the bipolar transistor area.

[0078] 16) Deposit a second layer of polysilicon, perform external base region and collector contact implantation, remove excess polycrystalline, and form a polysilicon collector 126 and a polysilicon base 127.

[0079] 17) Deposit the second dielectric layer 128 before TEOS metal, remove the oxide layer and polycrystalline, and form the base window of the bipolar transistor.

[0080] 18) The P-type base region 133 is implanted and connected to the P heavily doped external base region 132 diffused into the silicon by polycrystalline to form a double base region through the polysilicon base.

[0081] 19) An L-shaped sidewall structure emission region window is formed by multiple deposition and etching steps, including a sidewall oxide layer 129 and a sidewall silicon nitride layer 130.

[0082] 20) Forming a polysilicon emitter 131 and an N-type heavily doped emitter region 134 of a double poly self-aligned bipolar junction transistor.

[0083] 21) Depositing metal to form a double polycrystalline self-aligned bipolar junction transistor metal structure.

[0084] The P-type primary buried layer 104 of NMOS is located between the N-type primary buried layer 103 and the N-type secondary buried layer 105 of PMOS, and is not in contact with the N-type primary buried layer 103 and the N-type secondary buried layer 105 of PMOS.

[0085] The trench isolation oxide layer 109 at the bottom of the trench isolation contacts the oxide layer 101 on the SOI substrate.

[0086] In step 7), a field oxide layer 112 of a selective oxidation structure is formed using a photoresist.

[0087] In step 8), the pre-oxidation layer 146 in the thin-gate-oxide NMOS / thick-gate-oxide NMOS region is removed by wet etching using a photoresist.

[0088] In step 10), the gate oxide of the thin gate oxide NMOS is removed by wet etching using a photoresist.

[0089] In step 13), excess polycrystalline is removed by dry etching using a photoresist.

[0090] In step 15), the oxide layer in the bipolar transistor region is removed by wet etching using a photoresist.

[0091] In step 16), a photomask is used to perform external base region and collector contact implantation, and the photomask is used to remove excess polycrystalline by dry etching.

[0092] In step 17), the oxide layer and the polycrystalline are removed by dry etching using a photoresist.

[0093] In step 14), after the source and drain heavy doping of the thin gate oxide NMOS and the LDD injection and source and drain heavy doping of the thick gate oxide NMOS, a P-type primary well heavy doping 119, an N-type source region 120, and an N-type drain region 121 of the thin gate oxide NMOS are formed, and a P-type secondary well heavy doping 122, a source region LDD117, a drain region LDD118, an N-type source region 123, and an N-type drain region 124 of the thick gate oxide NMOS are formed.

[0094] In step 20), the steps of forming the polysilicon emitter 131 of the dual poly self-aligned bipolar junction transistor and the N-type heavily doped emitter region 134 are as follows:

[0095] A third layer of polysilicon is deposited, and an emitter region of a double polysilicon self-aligned bipolar junction transistor is formed by implantation using a photoresist.

[0096] The redundant polycrystalline is etched out by dry etching using a photomask to form a polysilicon emitter 131 of a dual-poly self-aligned bipolar junction transistor.

[0097] By annealing the emitter region, an N-type heavily doped emitter region 134 is formed.

[0098] The steps of depositing metal to form a dual polycrystalline self-aligned bipolar junction transistor metal structure include:

[0099] Holes are opened on the polycrystalline of the collector region and the double base region of the double polycrystalline self-aligned bipolar junction transistor and metal is deposited to form collector metal 135 and base metal 136.

[0100] Metal is deposited on the polysilicon emitter of the double poly self-aligned bipolar junction transistor to form an emitter metal 137.

[0101] Holes are opened on the heavily doped silicon substrate of the N-type source region, drain region, and P-well of the thin-gate oxide NMOS, and metal is deposited to form source metal 139 , drain metal 141 , and BACK terminal metal 138 .

[0102] A hole is opened on the gate polycrystalline of the thin gate oxide NMOS and metal is deposited to form a gate metal 136. A hole is opened on the P-type source region, drain region, and N-well heavily doped silicon substrate of the thick gate oxide NMOS and metal is deposited to form a source metal 143, a drain metal 145, and a BACK terminal metal 142.

[0103] A hole is opened on the gate poly of the thick gate oxide NMOS and metal is deposited to form a gate metal 144.

[0104] The SOI silicon substrate includes a P-type substrate 100, an oxide layer 101 on the substrate, and silicon 102 on the oxide layer, or the SOI silicon substrate is a single crystal silicon substrate.

[0105] The material of the SOI silicon substrate includes bulk silicon, silicon carbide, gallium arsenide, indium phosphide or silicon germanium.

[0106] The dual poly self-aligned bipolar junction transistor is NPN, PNP and a combination of the two.

[0107] The thin-gate-oxide NMOS / thick-gate-oxide NMOS are NMOS, PMOS and a combination of the two.

[0108] The polysilicon collector, polysilicon base and polysilicon emitter are composed of one or more repeated structural units.

[0109] Embodiment 2:

[0110] A method for integrating thick-thin gate oxide CMOS devices in a dual poly self-aligned bipolar junction transistor process comprises the following steps:

[0111] 1) Provide an SOI silicon substrate.

[0112] 2) An N-type primary buried layer 103 of a dual poly self-aligned bipolar junction transistor, a P-type primary buried layer 104 of a thin gate oxide NMOS, and a P-type secondary buried layer 105 of a thick gate oxide NMOS are sequentially formed.

[0113] 3) An epitaxial layer 106 is formed on the SOI silicon substrate.

[0114] 4) A P-type primary well region 107 of a thin-gate-oxide NMOS and a P-type secondary well region 108 of a thick-gate-oxide NMOS are formed in the epitaxial layer.

[0115] 5) Full dielectric island isolation of dual polycrystalline self-aligned bipolar junction transistor and thin-gate oxide NMOS / thick-gate oxide NMOS is formed, including trench isolation oxide layer 109 and trench isolation polysilicon 110.

[0116] 6) Performing N-type penetration 111 implantation on the collector of the dual poly self-aligned bipolar junction transistor to connect with the N-type primary buried layer 103 .

[0117] 7) Form a field oxide layer 112 of a selective oxidation structure, rinse off excess silicon nitride, and form active regions and field regions in the dual poly self-aligned bipolar junction transistor and thin gate oxide NMOS / thick gate oxide NMOS regions, respectively.

[0118] 8) Remove the pre-oxidation layer 146 in the thin-gate-oxide NMOS / thick-gate-oxide NMOS region.

[0119] 9) Grow a thick gate oxide layer to form a thick gate oxide layer 113 .

[0120] 10) Remove the gate oxide of the thin-gate-oxide NMOS and retain the gate oxide of the bipolar transistor and the thick-gate-oxide NMOS region.

[0121] 11) Grow a gate oxide layer to form a thin gate oxide 114.

[0122] 12) Deposit the first layer of polysilicon and perform gate poly implantation.

[0123] 13) Remove excess polycrystalline to form a polysilicon gate region 115 of a thin-gate-oxide NMOS and a polysilicon gate region 116 of a thick-gate-oxide NMOS.

[0124] 14) Perform source-drain heavy doping for thin-gate oxide NMOS and LDD implantation and source-drain heavy doping for thick-gate oxide NMOS.

[0125] 15) Deposit the first dielectric layer 125 before TEOS metal, and remove the oxide layer in the bipolar transistor area.

[0126] 16) Deposit a second layer of polysilicon, perform external base region and collector contact implantation, remove excess polycrystalline, and form a polysilicon collector 126 and a polysilicon base 127.

[0127] 17) Deposit the second dielectric layer 128 before TEOS metal, remove the oxide layer and polycrystalline, and form the base window of the bipolar transistor.

[0128] 18) The P-type base region 133 is implanted and connected to the P heavily doped external base region 132 diffused into the silicon by polycrystalline to form a double base region through the polysilicon base.

[0129] 19) An L-shaped sidewall structure emission region window is formed by multiple deposition and etching steps, including a sidewall oxide layer 129 and a sidewall silicon nitride layer 130.

[0130] 20) Forming a polysilicon emitter 131 and an N-type heavily doped emitter region 134 of a double poly self-aligned bipolar junction transistor.

[0131] 21) Depositing metal to form a double polycrystalline self-aligned bipolar junction transistor metal structure.

[0132] Embodiment 3:

[0133] A method for integrating thick-thin gate oxide CMOS devices in a dual polycrystalline self-aligned bipolar junction transistor process, the technical content of which is the same as that of Example 2, and further, the P-type primary buried layer 104 of the NMOS is located between the N-type primary buried layer 103 and the N-type secondary buried layer 105 of the PMOS, and does not contact the N-type primary buried layer 103 and the N-type secondary buried layer 105 of the PMOS.

[0134] Embodiment 4:

[0135] A method for integrating thick-thin gate oxide CMOS devices in a dual poly self-aligned bipolar junction transistor process, the technical content of which is the same as any one of embodiments 2-3, and further, the trench isolation oxide layer 109 at the bottom of the trench isolation contacts the oxide layer 101 on the SOI substrate.

[0136] Embodiment 5:

[0137] A method for integrating thick-thin gate oxide CMOS devices in a dual poly self-aligned bipolar junction transistor process, the technical content of which is the same as any one of embodiments 2-4, and further, in step 7, a field oxide layer 112 of a selective oxidation structure is formed using a photomask.

[0138] In step 8, the pre-oxidation layer 146 in the thin-gate-oxide NMOS / thick-gate-oxide NMOS region is removed by wet etching using a photoresist.

[0139] In step 10, the gate oxide of the thin gate oxide NMOS is removed by wet etching using a photoresist.

[0140] In step 13, the excess polycrystalline is removed by dry etching using a photoresist.

[0141] In step 15, the oxide layer in the bipolar transistor region is removed by wet etching using a photoresist.

[0142] In step 16, a photomask is used to perform external base region and collector contact implantation, and the photomask is used to remove excess polycrystalline by dry etching.

[0143] In step 17, the oxide layer and the polycrystalline are removed by dry etching using a photoresist.

[0144] Embodiment 6:

[0145] A method for integrating thick-and-thin-gate oxide CMOS devices in a dual-poly self-aligned bipolar junction transistor process, the technical content of which is the same as any one of embodiments 2-5, and further, in step 14, after performing source-drain heavy doping of thin-gate oxide NMOS and LDD injection and source-drain heavy doping of thick-gate oxide NMOS, a P-type primary well heavy doping 119, an N-type source region 120, and an N-type drain region 121 of the thin-gate oxide NMOS is formed, and a P-type secondary well heavy doping 122, a source region LDD117, a drain region LDD118, an N-type source region 123, and an N-type drain region 124 of the thick-gate oxide NMOS are formed.

[0146] Embodiment 7:

[0147] A method for integrating a thick-thin gate oxide CMOS device in a dual poly self-aligned bipolar junction transistor process, the technical content of which is the same as any one of embodiments 2-6, and further, in step 20, the steps of forming a polysilicon emitter 131 of the dual poly self-aligned bipolar junction transistor and an N-type heavily doped emitter region 134 are:

[0148] A third layer of polysilicon is deposited, and an emitter region of a double polysilicon self-aligned bipolar junction transistor is formed by implantation using a photoresist.

[0149] The redundant polycrystalline is etched out by dry etching using a photomask to form a polysilicon emitter 131 of a dual-poly self-aligned bipolar junction transistor.

[0150] By annealing the emitter region, an N-type heavily doped emitter region 134 is formed.

[0151] Embodiment 8:

[0152] A method for integrating a thick-thin gate oxide CMOS device in a dual polycrystalline self-aligned bipolar junction transistor process, the technical content of which is the same as any one of embodiments 2-7, and further, the step of depositing metal to form a dual polycrystalline self-aligned bipolar junction transistor metal structure comprises:

[0153] Holes are opened on the polycrystalline of the collector region and the double base region of the double polycrystalline self-aligned bipolar junction transistor and metal is deposited to form collector metal 135 and base metal 136.

[0154] Metal is deposited on the polysilicon emitter of the double poly self-aligned bipolar junction transistor to form an emitter metal 137.

[0155] Holes are opened on the heavily doped silicon substrate of the N-type source region, drain region, and P-well of the thin-gate oxide NMOS, and metal is deposited to form source metal 139 , drain metal 141 , and BACK terminal metal 138 .

[0156] A hole is opened on the gate polycrystalline of the thin gate oxide NMOS and metal is deposited to form a gate metal 136. A hole is opened on the P-type source region, drain region, and N-well heavily doped silicon substrate of the thick gate oxide NMOS and metal is deposited to form a source metal 143, a drain metal 145, and a BACK terminal metal 142.

[0157] A hole is opened on the gate poly of the thick gate oxide NMOS and metal is deposited to form a gate metal 144.

[0158] Embodiment 9:

[0159] A method for integrating thick-thin gate oxide CMOS devices in a dual polycrystalline self-aligned bipolar junction transistor process, the technical content of which is the same as any one of Examples 2-8, and further, the SOI silicon substrate includes a P-type substrate 100, an oxide layer 101 on the substrate, and silicon 102 on the oxide layer, or the SOI silicon substrate is a single crystal silicon substrate.

[0160] The material of the SOI silicon substrate includes bulk silicon, silicon carbide, gallium arsenide, indium phosphide or silicon germanium.

[0161] The dual poly self-aligned bipolar junction transistor is NPN, PNP and a combination of the two.

[0162] The thin-gate-oxide NMOS / thick-gate-oxide NMOS are NMOS, PMOS and a combination of the two.

[0163] Embodiment 10:

[0164] A method for integrating thick-thin gate oxide CMOS devices in a dual polycrystalline self-aligned bipolar junction transistor process, the technical content of which is the same as any one of Examples 2-9, and further, the polysilicon collector, polysilicon base, and polysilicon emitter are composed of one or more repeated structural units.

[0165] Embodiment 11:

[0166] A method for integrating a thick-thin gate oxide CMOS device in a dual poly self-aligned bipolar junction transistor process. The dual poly self-aligned bipolar junction transistor integrating the thick-thin gate oxide CMOS device is prepared by the method described in any one of embodiments 1-10.

[0167] Embodiment 12:

[0168] A method and structure for integrating thick-thin gate oxide CMOS devices in a dual poly self-aligned bipolar junction transistor process, the technical solution is as follows:

[0169] 1) Provide an SOI silicon substrate (including a P-type substrate 100, an oxide layer 101 on the substrate, and silicon 102 on the oxide layer).

[0170] 2) Then, an N-type primary buried layer 103 of the dual poly self-aligned bipolar junction transistor (left), a P-type primary buried layer 104 of the thin gate oxide NMOS (middle), and a P-type secondary buried layer 105 of the thick gate oxide NMOS (right) are formed.

[0171] 3) Forming an epitaxial layer 106 on the substrate.

[0172] 4) Forming a P-type primary well region 107 of a thin-gate oxide NMOS and a P-type secondary well region 108 of a thick-gate oxide NMOS in the epitaxial layer.

[0173] 5) Forming full dielectric island isolation of dual polycrystalline self-aligned bipolar junction transistor and thin gate oxide NMOS / thick gate oxide NMOS, including trench isolation oxide layer 109 and trench isolation polysilicon 110. The trench isolation oxide layer 109 at the bottom of the trench isolation contacts the oxide layer 101 on the SOI substrate.

[0174] 6) Performing N-type penetration 111 implantation on the collector of the dual poly self-aligned bipolar junction transistor to connect with the N-type primary buried layer 103 .

[0175] 7) Using a photomask, a field oxide layer 112 of a selective oxidation structure is formed, and excess silicon nitride is rinsed off to form an active region and a field region in the double poly self-aligned bipolar junction transistor and thin gate oxide NMOS / thick gate oxide NMOS regions, respectively.

[0176] 8) Use a photomask to remove the pre-oxidation layer 146 in the thin-gate-oxide NMOS / thick-gate-oxide NMOS region by wet etching.

[0177] 9) Grow a thick gate oxide layer to form a thick gate oxide layer 113 .

[0178] 10) Use a photomask to remove the gate oxide of the thin-gate-oxide NMOS by wet etching, and retain the gate oxide of the bipolar transistor and the thick-gate-oxide NMOS region.

[0179] 11) Grow a gate oxide layer to form a thin gate oxide 114.

[0180] 12) Deposit the first layer of polysilicon and perform gate polysilicon implantation.

[0181] 13) Use a photomask to remove excess polycrystalline by dry etching to form a polysilicon gate region 115 of a thin-gate-oxide NMOS and a polysilicon gate region 116 of a thick-gate-oxide NMOS.

[0182] 14) On this basis, the source and drain heavy doping of the thin gate oxide NMOS and the LDD injection and source and drain heavy doping of the thick gate oxide NMOS are performed. The P-type primary well heavy doping 119, N-type source region 120, and N-type drain region 121 of the thin gate oxide NMOS are formed, and the P-type secondary well heavy doping 122, source region LDD117, drain region LDD118, N-type source region 123, and N-type drain region 124 of the thick gate oxide NMOS are formed.

[0183] 15) Deposit the first dielectric layer 125 before TEOS metal, and use a photomask to remove the oxide layer in the bipolar transistor area by wet etching.

[0184] 16) Deposit a second layer of polysilicon, use a photomask to perform external base region and collector contact implantation, use the photomask to remove excess polycrystalline by dry etching to form a polysilicon collector 126 and a polysilicon base 127.

[0185] 17) Deposit the second dielectric layer 128 before TEOS metal, and use a photomask to remove the oxide layer and polycrystalline by dry etching to form a base window of a bipolar transistor.

[0186] 18) A P-type base region 133 is injected and connected to a P-type heavily doped external base region 132 diffused into silicon by polycrystalline to form a double base region through a polysilicon base.

[0187] 19) Then, an L-shaped sidewall structure emission region window is formed through multiple deposition and etching, including a sidewall oxide layer 129 and a sidewall silicon nitride 130.

[0188] 20) Deposit a third layer of polysilicon, use a photomask to form an emitter region of a dual poly self-aligned bipolar junction transistor by injection, use the photomask to perform dry etching to etch out excess polycrystalline to form a polysilicon emitter 131 of the dual poly self-aligned bipolar junction transistor, and form an N-type heavily doped emitter region 134 by annealing the emitter region.

[0189] 21) A hole is opened on the polycrystalline of the collector region and the double base region of the double polycrystalline self-aligned bipolar junction transistor and metal is deposited to form a collector metal 135 and a base metal 136; a metal is deposited on the polysilicon emitter of the double polycrystalline self-aligned bipolar junction transistor to form an emitter metal 137; a hole is opened on the N-type source region, drain region and P-well heavily doped silicon substrate of the thin gate oxide NMOS and metal is deposited to form a source metal 139, a drain metal 141 and a BACK terminal metal 138; a hole is opened on the gate polycrystalline of the thin gate oxide NMOS and metal is deposited to form a gate metal 136; a hole is opened on the P-type source region, drain region and N-well heavily doped silicon substrate of the thick gate oxide NMOS and metal is deposited to form a source metal 143, a drain metal 145 and a BACK terminal metal 142; a hole is opened on the gate polycrystalline of the thick gate oxide NMOS and metal is deposited to form a gate metal 144.

[0190] The SOI silicon substrate (including the P-type substrate, the oxide layer on the substrate, and the silicon on the oxide layer) may also be a single crystal silicon substrate.

[0191] The material of the SOI silicon substrate includes bulk silicon, silicon carbide, gallium arsenide, indium phosphide or silicon germanium.

[0192] The dual poly self-aligned bipolar junction transistor can be NPN, PNP, or a combination of the two.

[0193] The thin-gate-oxide NMOS / thick-gate-oxide NMOS may be NMOS, PMOS, or a combination of the two. The polysilicon collector, polysilicon base, and polysilicon emitter are composed of one or more repeated structural units.

Claims

1. A method for integrating thick-thin gate oxide CMOS devices in a dual poly self-aligned bipolar junction transistor process, characterized in that: The following steps are involved: 1) Provide an SOI silicon substrate. 2) sequentially forming an N-type primary buried layer (103) of a dual polycrystalline self-aligned bipolar junction transistor, a P-type primary buried layer (104) of a thin gate oxide NMOS, and a P-type secondary buried layer (105) of a thick gate oxide NMOS. 3) forming an epitaxial layer (106) on an SOI silicon substrate; 4) forming a P-type primary well region (107) of a thin-gate oxide NMOS and a P-type secondary well region (108) of a thick-gate oxide NMOS in the epitaxial layer; 5) forming a full dielectric island isolation of a dual polycrystalline self-aligned bipolar junction transistor and a thin gate oxide NMOS / thick gate oxide NMOS, including a trench isolation oxide layer (109) and a trench isolation polysilicon (110); 6) performing collector N-type penetration (111) implantation of the dual polycrystalline self-aligned bipolar junction transistor to connect with the N-type primary buried layer (103); 7) forming a field oxide layer (112) of a selective oxidation structure, rinsing away excess silicon nitride, and forming an active region and a field region in the double polycrystalline self-aligned bipolar junction transistor and the thin gate oxide NMOS / thick gate oxide NMOS regions respectively; 8) removing the pre-oxidation layer (146) in the thin-gate-oxide NMOS / thick-gate-oxide NMOS region; 9) growing a thick gate oxide layer to form a thick gate oxide layer (113); 10) Remove the gate oxide of the thin-gate oxide NMOS and retain the gate oxide of the bipolar transistor and the thick-gate oxide NMOS region; 11) growing a gate oxide layer to form a thin gate oxide (114); 12) Depositing the first layer of polysilicon and performing gate polysilicon implantation; 13) removing excess polycrystalline to form a polysilicon gate region (115) of a thin-gate-oxide NMOS and a polysilicon gate region (116) of a thick-gate-oxide NMOS; 14) Performing source-drain heavy doping of thin-gate oxide NMOS and LDD implantation and source-drain heavy doping of thick-gate oxide NMOS; 15) depositing the first dielectric layer (125) before the TEOS metal, and removing the oxide layer in the bipolar transistor region; 16) depositing a second layer of polysilicon, performing external base region and collector contact implantation, removing excess polycrystalline, and forming a polysilicon collector (126) and a polysilicon base (127); 17) depositing a second dielectric layer (128) before TEOS metal, removing the oxide layer and polycrystalline, and forming a base window of a bipolar transistor; 18) P-type base region (133) is implanted and connected to the P heavily doped external base region 132 diffused into silicon by polycrystalline to form a double base region through the polysilicon base electrode; 19) forming an L-shaped sidewall structure emission region window by multiple deposition and etching, including a sidewall oxide layer (129) and a sidewall silicon nitride (130); 20) forming a polysilicon emitter (131) of a double polycrystalline self-aligned bipolar junction transistor and an N-type heavily doped emitter region (134); 21) Depositing metal to form a double polycrystalline self-aligned bipolar junction transistor metal structure.

2. A method for integrating thick-thin-gate oxide CMOS devices in a dual poly self-aligned bipolar junction transistor process according to claim 1, characterized in that: The P-type primary buried layer (104) of the NMOS is located between the N-type primary buried layer (103) and the N-type secondary buried layer (105) of the PMOS, and is not in contact with the N-type primary buried layer (103) and the N-type secondary buried layer (105) of the PMOS.

3. A method for integrating thick-thin-gate oxide CMOS devices in a dual poly self-aligned bipolar junction transistor process according to claim 1, characterized in that: The trench isolation bottom trench isolation oxide layer (109) is in contact with the oxide layer (101) on the SOI substrate.

4. The method of integrating thick-thin-gate-oxide CMOS devices in a dual-poly self-aligned bipolar junction transistor process according to claim 1, characterized in that: In step 7), a field oxide layer (112) of a selective oxidation structure is formed using a photoresist; In step 8), the pre-oxidation layer (146) in the thin-gate-oxide NMOS / thick-gate-oxide NMOS region is removed by wet etching using a photoresist; In step 10), the gate oxide of the thin gate oxide NMOS is removed by wet etching using a photomask; In step 13), excess polycrystalline is removed by dry etching using a photomask; In step 15), the oxide layer in the bipolar transistor region is removed by wet etching using a photomask; In step 16), a photomask is used to perform external base region and collector contact implantation, and the photomask is used to remove excess polycrystalline by dry etching; In step 17), the oxide layer and the polycrystalline are removed by dry etching using a photoresist.

5. The method of integrating thick-thin-gate-oxide CMOS devices in a dual-poly self-aligned bipolar junction transistor process according to claim 1, characterized in that: In step 14), after performing source-drain heavy doping of the thin-gate oxide NMOS and LDD injection and source-drain heavy doping of the thick-gate oxide NMOS, a P-type primary well heavy doping (119), an N-type source region (120), and an N-type drain region (121) of the thin-gate oxide NMOS is formed, and a P-type secondary well heavy doping (122), a source region LDD (117), a drain region LDD (118), an N-type source region (123), and an N-type drain region (124) of the thick-gate oxide NMOS is formed.

6. The method of integrating thick-thin-gate-oxide CMOS devices in a dual-poly self-aligned bipolar junction transistor process according to claim 1, characterized in that: In step 20), the steps of forming the polysilicon emitter (131) of the dual poly self-aligned bipolar junction transistor and the N-type heavily doped emitter region (134) are as follows: Depositing a third layer of polysilicon, and forming an emitter region of a double polycrystalline self-aligned bipolar junction transistor by implantation using a photomask; Using a photomask to perform dry etching to etch out excess polycrystalline to form a polysilicon emitter (131) of a double polycrystalline self-aligned bipolar junction transistor; An N-type heavily doped emitter region (134) is formed by annealing the emitter region.

7. The method of integrating thick-thin-gate-oxide CMOS devices in a dual-poly self-aligned bipolar junction transistor process according to claim 1, characterized in that: The steps of depositing metal to form a dual polycrystalline self-aligned bipolar junction transistor metal structure include: Opening holes in the polycrystalline of the collector region and the double base region of the double polycrystalline self-aligned bipolar junction transistor and depositing metal to form collector metal (135) and base metal (136); Depositing metal on the polysilicon emitter of the double poly self-aligned bipolar junction transistor to form an emitter metal (137); Opening holes on the heavily doped silicon substrate of the N-type source region, drain region, and P-well of the thin-gate oxide NMOS and depositing metal to form source metal (139), drain metal (141), and BACK terminal metal (138); A hole is opened on the gate polycrystalline of the thin-gate oxide NMOS and metal is deposited to form a gate metal (136); a hole is opened on the P-type source region, drain region, and N-well heavily doped silicon substrate of the thick-gate oxide NMOS and metal is deposited to form a source metal (143), a drain metal (145), and a BACK terminal metal (142); A hole is opened on the gate polycrystalline of the thick gate oxide NMOS and metal is deposited to form a gate metal (144).

8. The method of integrating thick-thin-gate-oxide CMOS devices in a dual-poly self-aligned bipolar junction transistor process according to claim 1, characterized in that: The SOI silicon substrate comprises a P-type substrate (100), an oxide layer (101) on the substrate, and silicon (102) on the oxide layer, or the SOI silicon substrate is a single crystal silicon substrate. The material of the SOI silicon substrate includes bulk silicon, silicon carbide, gallium arsenide, indium phosphide or silicon germanium. The dual poly self-aligned bipolar junction transistor is NPN, PNP and a combination of the two. The thin-gate-oxide NMOS / thick-gate-oxide NMOS are NMOS, PMOS and a combination of the two.

9. The method of integrating thick-thin-gate-oxide CMOS devices in a dual-poly self-aligned bipolar junction transistor process according to claim 1, characterized in that: The polysilicon collector, polysilicon base and polysilicon emitter are composed of one or more repeated structural units.

10. A method for integrating thick-thin gate oxide CMOS devices in a dual poly self-aligned bipolar junction transistor process, characterized in that: The dual polycrystalline self-aligned bipolar junction transistor integrating thick and thin gate oxide CMOS devices is prepared by the method according to any one of claims 1 to 9.

Images