Method and structure for integrating CMOS (Complementary Metal Oxide Semiconductor) device in double polycrystal self-aligned bipolar junction transistor process

Abstract

The invention discloses a method and a structure for integrating a CMOS (Complementary Metal Oxide Semiconductor) device in a double polycrystal self-aligned bipolar junction transistor process. The method comprises the following steps of: sequentially forming an N-type primary buried layer (103) of a double polycrystal self-aligned bipolar junction transistor, a P-type primary buried layer (104) of an NMOS (N-channel Metal Oxide Semiconductor) and an N-type secondary buried layer (105) of a PMOS (P-channel Metal Oxide Semiconductor); forming an epitaxial layer (106) on the SOI silicon substrate; forming a P-type well region (107) of an NMOS (N-channel Metal Oxide Semiconductor) and an N-type well region (108) of a PMOS (P-channel Metal Oxide Semiconductor) in the epitaxial layer (106); and forming all-dielectric island isolation of the double polycrystal self-aligned bipolar junction transistor and the NMOS / PMOS. According to the semiconductor device, various combinations of high-performance NPN / PNP and CMOS devices can be achieved, the overall device characteristics of the process are effectively improved, the application technical field with wider and higher requirements is met, and the electrical performance of a chip is improved.

Description

Technical Field

[0001] The invention relates to the technical field of semiconductor devices, in particular to a method and structure for integrating CMOS devices in a double polycrystalline self-aligned bipolar junction transistor process. Background Art

[0002] As an indispensable part of the circuit system currently in use, analog integrated circuits and mixed analog and digital circuits will find increasing uses in application fields that require high-speed and high-performance communications or external interfaces. With the further intensification of the demand for higher-performance products such as high density, low power consumption and high-speed and large driving capabilities, as well as the continuous reduction of line width and the advantages of CMOS voltage drive and the need for related high-precision AD / DA products, the integration of CMOS in the bipolar process platform has become a new direction. Bipolar circuits have the characteristics of high speed, strong current driving capability and high analog accuracy, while CMOS circuits have incomparable advantages in high integration and low power consumption. In today's integrated circuit manufacturing industry that is constantly pursuing higher performance and more perfection, the perfect combination of the complementary advantages of these two processes has produced a new BiCMOS process.

[0003] The high-speed BiCMOS process platform is a long-term blank area in the domestic bipolar process platform. It plays an irreplaceable role in the manufacturing of high-end high-speed amplifiers, high-precision AD / DA and other chips. Such chips are widely used in various precision communication equipment, high-precision test instruments, and automotive electronics. Currently, such products are all imported from abroad. In particular, high-speed BiCMOS currently faces many challenges, such as high process integration, complex manufacturing process, high cost, and difficulty in ensuring yield. In order to overcome the challenges, it is necessary to continuously research and improve the manufacturing process technology to improve the performance and reliability of the circuit.

[0004] Therefore, there is an urgent need for a method that can integrate high-speed bipolar transistors and CMOS devices in a single manufacturing process without increasing the complexity of the process. Summary of the invention

[0005] The object of the present invention is to provide a method for integrating CMOS devices in a dual polycrystalline self-aligned bipolar junction transistor process, comprising the following steps:

[0006] 1) Provide an SOI silicon substrate.

[0007] 2) An N-type primary buried layer of a dual polycrystalline self-aligned bipolar junction transistor, a P-type primary buried layer of an NMOS, and an N-type secondary buried layer of a PMOS are sequentially formed.

[0008] 3) Form an epitaxial layer on the SOI silicon substrate.

[0009] 4) Forming a P-type well region of NMOS and an N-type well region of PMOS in the epitaxial layer.

[0010] 5) Forming full dielectric island isolation of dual polycrystalline self-aligned bipolar junction transistor and NMOS / PMOS, including trench isolation oxide layer and trench isolation polysilicon.

[0011] 6) Performing N-type penetration implantation on the collector of the dual poly self-aligned bipolar junction transistor and connecting it to the N-type primary buried layer.

[0012] 7) Forming a field oxide layer of a selective oxidation structure, rinsing away excess silicon nitride and oxide layers, and forming an active region and a field region in the dual polycrystalline self-aligned bipolar junction transistor and NMOS / PMOS regions, respectively.

[0013] 8) Grow a gate oxide layer to form a gate oxide layer.

[0014] 9) Remove the gate oxide in the dual poly self-aligned bipolar junction transistor region and retain the gate oxide in the NMOS / PMOS region.

[0015] 10) Deposit the first layer of polysilicon, perform general implantation first, and then use a photomask to perform gate poly implantation of the N-type / P-type bipolar transistor and NMOS / PMOS in sequence.

[0016] 11) Etching to remove excess polycrystalline to form a polysilicon collector, a polysilicon base, a polysilicon gate of the NMOS, and a polysilicon gate of the PMOS.

[0017] 12) Perform heavy doping of the source and drain of NMOS / PMOS and heavy doping of the BACK end well to form heavy doping of P well and N well, N-type source region and N-type drain region of NMOS, and P-type source region and P-type drain region of PMOS.

[0018] 13) Deposit a TEOS metal pre-dielectric layer, remove the oxide layer and polycrystalline, and form a base window of the bipolar transistor.

[0019] 14) P-type base region is implanted and connected to the P heavily doped external base region 128 diffused into silicon by polycrystalline to form a double base region through the polysilicon base.

[0020] 15) An L-shaped sidewall structure emission area window is formed by multiple deposition and etching.

[0021] 16) Deposit a second layer of polysilicon, use a photomask to form an emitter region of a dual poly self-aligned bipolar junction transistor by implantation, etch out excess polysilicon to form a polysilicon emitter of the dual poly self-aligned bipolar junction transistor, and anneal the emitter region to form an N-type heavily doped emitter region.

[0022] 17) Deposit metal to form the collector, emitter, source, drain, gate, and BACK metal structures of the integrated CMOS device.

[0023] Furthermore, the P-type primary buried layer of the NMOS is located between the N-type primary buried layer and the N-type secondary buried layer of the PMOS, and is not in contact with the N-type primary buried layer and the N-type secondary buried layer of the PMOS.

[0024] Furthermore, the trench isolation oxide layer at the bottom of the trench isolation contacts the oxide layer on the SOI substrate.

[0025] Further, in step 7), a field oxide layer of the selective oxidation structure is formed by a photoresist.

[0026] In step 9), a photomask is used to remove the gate oxide in the double poly self-aligned bipolar junction transistor region by wet etching.

[0027] In step 11), excess polycrystalline is removed by dry etching using a photoresist.

[0028] In step 12), the oxide layer and the polycrystalline are removed by dry etching using a photoresist.

[0029] In step 16), a photomask is used to perform dry etching to etch out excess polycrystalline to form a polysilicon emitter of a double polycrystalline self-aligned bipolar junction transistor.

[0030] Furthermore, the sidewall structure emission region window includes a sidewall oxide layer and a sidewall silicon nitride layer.

[0031] Further, the steps of depositing metal to form the collector, emitter, source, drain, gate, and BACK metal structures of the integrated CMOS device include:

[0032] Holes are opened on the polycrystals of the collector region and the double base region of the double polycrystal self-aligned bipolar junction transistor and metal is deposited to form collector metal and base metal.

[0033] Metal is deposited on the polysilicon emitter of the double poly self-aligned bipolar junction transistor to form an emitter metal.

[0034] Holes are opened on the heavily doped silicon substrate of the N-type source region, drain region, and P-well of the NMOS, and metal is deposited to form source metal, drain metal, and BACK terminal metal.

[0035] A hole is opened on the gate polycrystalline of the NMOS and metal is deposited to form a gate metal.

[0036] Holes are opened on the heavily doped silicon substrate of the PMOS P-type source region, drain region, and N-well, and metal is deposited to form source metal, drain metal, and BACK terminal metal.

[0037] A hole is opened on the gate polycrystalline of the PMOS and metal is deposited to form a gate metal.

[0038] Furthermore, the SOI silicon substrate includes a P-type substrate, an oxide layer on the substrate, and silicon on the oxide layer, or the SOI silicon substrate is a single crystal silicon substrate.

[0039] The material of the SOI silicon substrate includes bulk silicon, silicon carbide, gallium arsenide, indium phosphide or silicon germanium.

[0040] Furthermore, the dual polycrystalline self-aligned bipolar junction transistor is NPN, PNP, or a combination of NPN and PNP.

[0041] Furthermore, the polysilicon collector, polysilicon base and polysilicon emitter are composed of one or more repeated structural units.

[0042] A CMOS device is integrated in a dual polycrystalline self-aligned bipolar junction transistor process. The dual polycrystalline self-aligned bipolar junction transistor integrated with the CMOS device is prepared by the method.

[0043] The technical effect of the present invention is unquestionable. The present invention provides a method and structure for integrating CMOS devices in a dual poly self-aligned bipolar junction transistor process, and realizes the integration of dual poly self-aligned polysilicon emitter transistors and CMOS devices in the same process flow without significantly increasing the overall process complexity and process technology difficulty.

[0044] The beneficial effects of the present invention are as follows:

[0045] 1) The present invention proposes a method and structure for integrating CMOS devices in a dual poly self-aligned bipolar junction transistor process. Under the premise that the overall process complexity and process technology difficulty are not significantly increased, the integration of dual poly self-aligned polysilicon emitter transistors and CMOS devices is achieved in the same process flow, the process cost is reduced, the processing efficiency is improved, and it is particularly suitable for the development of high-speed BiCMOS related processes.

[0046] 2) The semiconductor device of the present invention can realize various combinations of high-performance NPN / PNP and CMOS devices, effectively improving the overall device characteristics of the process to meet wider and higher demand application technology fields and improve the electrical performance of the chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0047] Figure 1 It is a schematic diagram of the steps of the method for integrating CMOS devices in a dual poly self-aligned bipolar junction transistor process in the present invention.

[0048] Figure 2-Figure 10The flowchart is a method for integrating CMOS devices in a dual poly self-aligned bipolar junction transistor process according to an embodiment of the present invention.

[0049] In the figure: P-type substrate 100, oxide layer 101 on substrate, silicon 102 on oxide layer, N-type primary buried layer 103, P-type primary buried layer 104, N-type secondary buried layer 105, epitaxial layer 106, P-type well region 107, N-type well region 108, trench isolation oxide layer 109, trench isolation polysilicon 110, N-type penetration 111, field oxide layer 112, gate oxide layer 113, polysilicon collector 114, polysilicon base 115, NMOS polysilicon gate 116, PMOS Polysilicon gate 117, P-well heavily doped 118, N-well heavily doped 121, N-type source region 119, N-type drain region 120, P-type source region 122, P-type drain region 123, TEOS metal pre-dielectric layer 124, sidewall oxide layer 125, sidewall silicon nitride 126, polysilicon emitter 127, P-heavily doped external base region 128, P-type base region 129, N-type heavily doped emitter region 130, collector metal 131, base metal 132, emitter metal 133, NMOS BACK terminal metal 134, NMOS source metal 135, NMOS gate metal 136, NMOS drain metal 137, PMOS BACK terminal metal 138, PMOS source metal 139, PMOS gate metal 140, PMOS drain metal 141. DETAILED DESCRIPTION

[0050] The present invention is further described below in conjunction with the embodiments, but it should not be understood that the above subject matter of the present invention is limited to the following embodiments. Without departing from the above technical ideas of the present invention, various substitutions and changes are made according to the common technical knowledge and customary means in the art, which should all be included in the protection scope of the present invention.

[0051] Embodiment 1:

[0052] See also Figures 1 to 10 , a method for integrating CMOS devices in a dual poly self-aligned bipolar junction transistor process, comprising the following steps:

[0053] 1) Provide an SOI silicon substrate.

[0054] 2) An N-type primary buried layer 103 of a dual poly self-aligned bipolar junction transistor, a P-type primary buried layer 104 of an NMOS, and an N-type secondary buried layer 105 of a PMOS are sequentially formed.

[0055] 3) An epitaxial layer 106 is formed on the SOI silicon substrate.

[0056] 4) A P-type well region 107 of NMOS and an N-type well region 108 of PMOS are formed in the epitaxial layer 106 .

[0057] 5) Forming full dielectric island isolation of dual polycrystalline self-aligned bipolar junction transistor and NMOS / PMOS, including trench isolation oxide layer 109 and trench isolation polysilicon 110.

[0058] 6) Performing N-type penetration 111 implantation on the collector of the dual poly self-aligned bipolar junction transistor and connecting it to the N-type primary buried layer 103 .

[0059] 7) Forming a field oxide layer 112 of a selective oxidation structure, rinsing away excess silicon nitride and oxide layers, and forming active regions and field regions in the dual poly self-aligned bipolar junction transistor and NMOS / PMOS regions, respectively.

[0060] 8) Grow a gate oxide layer to form a gate oxide layer 113 .

[0061] 9) Remove the gate oxide in the dual poly self-aligned bipolar junction transistor region and retain the gate oxide in the NMOS / PMOS region.

[0062] 10) Deposit the first layer of polysilicon, perform general implantation first, and then use a photomask to perform gate poly implantation of the N-type / P-type bipolar transistor and NMOS / PMOS in sequence.

[0063] 11) Etching to remove excess polycrystalline, forming a polysilicon collector 114, a polysilicon base 115, a polysilicon gate 116 of the NMOS, and a polysilicon gate 117 of the PMOS of the dual polycrystalline self-aligned bipolar junction transistor.

[0064] 12) Perform heavy doping of the source and drain of NMOS / PMOS and heavy doping of the BACK end well to form a P-well heavy doping 118, an N-well heavy doping 121, an N-type source region 119 and an N-type drain region 120 of the NMOS, and a P-type source region 122 and a P-type drain region 123 of the PMOS.

[0065] 13) Deposit a TEOS metal pre-dielectric layer 124, remove the oxide layer and polycrystalline, and form a base window of the bipolar transistor.

[0066] 14) The P-type base region 129 is implanted and connected to the P heavily doped external base region 128 diffused into the silicon by polycrystalline to form a double base region through the polysilicon base.

[0067] 15) An L-shaped sidewall structure emission region window is formed by multiple deposition and etching steps.

[0068] 16) Deposit a second layer of polysilicon, use a photomask to form an emitter region of the dual poly self-aligned bipolar junction transistor by implantation, etch out excess polycrystalline to form a polysilicon emitter 127 of the dual poly self-aligned bipolar junction transistor, and form an N-type heavily doped emitter region 130 by annealing the emitter region.

[0069] 17) Deposit metal to form the collector, emitter, source, drain, gate, and BACK metal structures of the integrated CMOS device.

[0070] The P-type primary buried layer 104 of NMOS is located between the N-type primary buried layer 103 and the N-type secondary buried layer 105 of PMOS, and is not in contact with the N-type primary buried layer 103 and the N-type secondary buried layer 105 of PMOS.

[0071] The trench isolation oxide layer 109 at the bottom of the trench isolation contacts the oxide layer 101 on the SOI substrate.

[0072] In step 7), a field oxide layer 112 of a selective oxidation structure is formed by photolithography.

[0073] In step 9), a photomask is used to remove the gate oxide in the double poly self-aligned bipolar junction transistor region by wet etching.

[0074] In step 11), excess polycrystalline is removed by dry etching using a photoresist.

[0075] In step 13), the oxide layer and the polycrystalline are removed by dry etching using a photoresist.

[0076] In step 16), a photomask is used to perform dry etching to etch out excess polycrystalline to form a polysilicon emitter 127 of a dual-poly self-aligned bipolar junction transistor.

[0077] The sidewall structure emission region window includes a sidewall oxide layer 125 and a sidewall silicon nitride 126 .

[0078] The steps of depositing metal to form the collector, emitter, source, drain, gate, and BACK metal structures of the integrated CMOS device include:

[0079] Holes are opened on the polycrystalline of the collector region and the double base region of the double polycrystalline self-aligned bipolar junction transistor and metal is deposited to form collector metal 131 and base metal 132.

[0080] Metal is deposited on the polysilicon emitter of the double poly self-aligned bipolar junction transistor to form an emitter metal 133.

[0081] Holes are opened on the heavily doped silicon substrate of the N-type source region, drain region, and P-well of the NMOS, and metal is deposited to form source metal 135 , drain metal 137 , and BACK terminal metal 134 .

[0082] A hole is opened on the gate poly of the NMOS and metal is deposited to form a gate metal 136.

[0083] Holes are opened on the heavily doped silicon substrate of the PMOS's P-type source region, drain region, and N-well, and metal is deposited to form source metal 139 , drain metal 141 , and BACK terminal metal 138 .

[0084] A hole is opened on the gate poly of the PMOS and metal is deposited to form a gate metal 140 .

[0085] The SOI silicon substrate includes a P-type substrate 100, an oxide layer 101 on the substrate, and silicon 102 on the oxide layer, or the SOI silicon substrate is a single crystal silicon substrate.

[0086] The material of the SOI silicon substrate includes bulk silicon, silicon carbide, gallium arsenide, indium phosphide or silicon germanium.

[0087] The dual polycrystalline self-aligned bipolar junction transistor is NPN, PNP, or a combination of NPN and PNP.

[0088] The polysilicon collector, polysilicon base and polysilicon emitter are composed of one or more repeated structural units.

[0089] Embodiment 2:

[0090] A method for integrating CMOS devices in a dual poly self-aligned bipolar junction transistor process comprises the following steps:

[0091] 1) Provide an SOI silicon substrate.

[0092] 2) An N-type primary buried layer 103 of a dual poly self-aligned bipolar junction transistor, a P-type primary buried layer 104 of an NMOS, and an N-type secondary buried layer 105 of a PMOS are sequentially formed.

[0093] 3) An epitaxial layer 106 is formed on the SOI silicon substrate.

[0094] 4) A P-type well region 107 of NMOS and an N-type well region 108 of PMOS are formed in the epitaxial layer 106 .

[0095] 5) Forming full dielectric island isolation of dual polycrystalline self-aligned bipolar junction transistor and NMOS / PMOS, including trench isolation oxide layer 109 and trench isolation polysilicon 110.

[0096] 6) Performing N-type penetration 111 implantation on the collector of the dual poly self-aligned bipolar junction transistor and connecting it to the N-type primary buried layer 103 .

[0097] 7) Form a field oxide layer 112 of a selective oxidation structure, rinse off excess silicon nitride and oxide layers, and form active regions and field regions in the dual poly self-aligned bipolar junction transistor and NMOS / PMOS regions, respectively.

[0098] 8) Grow a gate oxide layer to form a gate oxide layer 113 .

[0099] 9) Remove the gate oxide in the dual poly self-aligned bipolar junction transistor region and retain the gate oxide in the NMOS / PMOS region.

[0100] 10) Deposit the first layer of polysilicon, perform general implantation first, and then use a photomask to perform gate poly implantation of the N-type / P-type bipolar transistor and NMOS / PMOS in sequence.

[0101] 11) Etching to remove excess polycrystalline, forming a polysilicon collector 114, a polysilicon base 115, a polysilicon gate 116 of the NMOS, and a polysilicon gate 117 of the PMOS of the dual polycrystalline self-aligned bipolar junction transistor.

[0102] 12) Perform heavy doping of the source and drain of NMOS / PMOS and heavy doping of the BACK end well to form a P-well heavy doping 118, an N-well heavy doping 121, an N-type source region 119 and an N-type drain region 120 of the NMOS, and a P-type source region 122 and a P-type drain region 123 of the PMOS.

[0103] 13) Deposit a TEOS metal pre-dielectric layer 124, remove the oxide layer and polycrystalline, and form a base window of the bipolar transistor.

[0104] 14) The P-type base region 129 is implanted and connected to the P heavily doped external base region 128 diffused into the silicon by polycrystalline to form a double base region through the polysilicon base.

[0105] 15) An L-shaped sidewall structure emission region window is formed by multiple deposition and etching steps.

[0106] 16) Deposit a second layer of polysilicon, use a photomask to form an emitter region of the dual poly self-aligned bipolar junction transistor by implantation, etch out excess polycrystalline to form a polysilicon emitter 127 of the dual poly self-aligned bipolar junction transistor, and form an N-type heavily doped emitter region 130 by annealing the emitter region.

[0107] 17) Deposit metal to form the collector, emitter, source, drain, gate, and BACK metal structures of the integrated CMOS device.

[0108] Embodiment 3:

[0109] A method for integrating CMOS devices in a dual polycrystalline self-aligned bipolar junction transistor process, the technical content of which is the same as that of Example 2, further, the P-type primary buried layer 104 of the NMOS is located between the N-type primary buried layer 103 and the N-type secondary buried layer 105 of the PMOS, and does not contact the N-type primary buried layer 103 and the N-type secondary buried layer 105 of the PMOS.

[0110] Embodiment 4:

[0111] A method for integrating CMOS devices in a dual polycrystalline self-aligned bipolar junction transistor process, the technical content of which is the same as any one of embodiments 2-3, and further, the trench isolation oxide layer 109 at the bottom of the trench isolation is in contact with the oxide layer 101 on the SOI substrate.

[0112] Embodiment 5:

[0113] A method for integrating CMOS devices in a dual polycrystalline self-aligned bipolar junction transistor process, the technical content of which is the same as any one of embodiments 2-4, and further, in step 7), a field oxide layer 112 of a selective oxidation structure is formed by a photolithography plate.

[0114] In step 9), a photomask is used to remove the gate oxide in the double poly self-aligned bipolar junction transistor region by wet etching.

[0115] In step 11), excess polycrystalline is removed by dry etching using a photoresist.

[0116] In step 13), the oxide layer and the polycrystalline are removed by dry etching using a photoresist.

[0117] In step 16), a photomask is used to perform dry etching to etch out excess polycrystalline to form a polysilicon emitter 127 of a dual-poly self-aligned bipolar junction transistor.

[0118] Embodiment 6:

[0119] A method for integrating CMOS devices in a dual polycrystalline self-aligned bipolar junction transistor process, the technical content of which is the same as any one of embodiments 2-5, and further, the sidewall structure emission region window includes a sidewall oxide layer 125 and a sidewall silicon nitride 126.

[0120] Embodiment 7:

[0121] A method for integrating a CMOS device in a dual polycrystalline self-aligned bipolar junction transistor process, the technical content of which is the same as any one of embodiments 2-6, and further, the step of depositing metal to form a collector, emitter, source, drain, gate, and BACK terminal metal structure of the integrated CMOS device comprises:

[0122] Holes are opened on the polycrystalline of the collector region and the double base region of the double polycrystalline self-aligned bipolar junction transistor and metal is deposited to form collector metal 131 and base metal 132.

[0123] Metal is deposited on the polysilicon emitter of the double poly self-aligned bipolar junction transistor to form an emitter metal 133.

[0124] Holes are opened on the heavily doped silicon substrate of the N-type source region, drain region, and P-well of the NMOS, and metal is deposited to form source metal 135 , drain metal 137 , and BACK terminal metal 134 .

[0125] A hole is opened on the gate poly of the NMOS and metal is deposited to form a gate metal 136.

[0126] Holes are opened on the heavily doped silicon substrate of the PMOS's P-type source region, drain region, and N-well, and metal is deposited to form source metal 139 , drain metal 141 , and BACK terminal metal 138 .

[0127] A hole is opened on the gate poly of the PMOS and metal is deposited to form a gate metal 140 .

[0128] Embodiment 8:

[0129] A method for integrating CMOS devices in a dual polycrystalline self-aligned bipolar junction transistor process, the technical content of which is the same as any one of Examples 2-7, and further, the SOI silicon substrate includes a P-type substrate 100, an oxide layer 101 on the substrate, and silicon 102 on the oxide layer, or the SOI silicon substrate is a single crystal silicon substrate.

[0130] The material of the SOI silicon substrate includes bulk silicon, silicon carbide, gallium arsenide, indium phosphide or silicon germanium.

[0131] Embodiment 9:

[0132] A method for integrating CMOS devices in a dual polycrystalline self-aligned bipolar junction transistor process, the technical content of which is the same as any one of embodiments 2-8, and further, the dual polycrystalline self-aligned bipolar junction transistor is NPN, PNP, or a combination of NPN and PNP.

[0133] Embodiment 10:

[0134] A method for integrating CMOS devices in a dual polycrystalline self-aligned bipolar junction transistor process, the technical content of which is the same as any one of Examples 2-9, and further, the polysilicon collector, polysilicon base, and polysilicon emitter are composed of one or more repeated structural units.

[0135] Embodiment 11:

[0136] A CMOS device is integrated in a dual polycrystalline self-aligned bipolar junction transistor process, wherein the dual polycrystalline self-aligned bipolar junction transistor integrated with the CMOS device is prepared by the method described in any one of embodiments 1-10.

[0137] Embodiment 12:

[0138] A method for integrating CMOS devices in a dual poly self-aligned bipolar junction transistor process, the technical solution is as follows:

[0139] 1) Provide an SOI silicon substrate (including a P-type substrate 100, an oxide layer 101 on the substrate, and silicon 102 on the oxide layer).

[0140] 2) Then, an N-type primary buried layer 103 of the dual poly self-aligned bipolar junction transistor (left), a P-type primary buried layer 104 of the NMOS (middle), and an N-type secondary buried layer 105 of the PMOS (right) are formed.

[0141] 3) An epitaxial layer 106 is formed on the substrate.

[0142] 4) A P-type well region 107 of NMOS and an N-type well region 108 of PMOS are formed in the epitaxial layer.

[0143] 5) Forming full dielectric island isolation of dual polycrystalline self-aligned bipolar junction transistor and NMOS / PMOS, including trench isolation oxide layer 109 and trench isolation polysilicon 110. The trench isolation oxide layer 109 at the bottom of the trench isolation contacts the oxide layer 101 on the SOI substrate.

[0144] 6) Performing N-type penetration 111 implantation on the collector of the dual poly self-aligned bipolar junction transistor to connect with the N-type primary buried layer 103 .

[0145] 7) Using a photomask, a field oxide layer 112 of a selective oxidation structure is formed, and the excess silicon nitride and oxide layer are rinsed off to form an active region and a field region in the dual poly self-aligned bipolar junction transistor and the NMOS / PMOS region, respectively.

[0146] 8) Then, a gate oxide layer is grown to form a gate oxide layer 113 .

[0147] 9) Using a photomask, remove the gate oxide in the dual poly self-aligned bipolar junction transistor region by wet etching, and retain the gate oxide in the NMOS / PMOS region.

[0148] 10) Deposit the first layer of polysilicon, perform general implantation first, and then use a photomask to perform gate poly implantation of the N-type / P-type bipolar transistor and NMOS / PMOS in sequence.

[0149] 11) Use a photomask to remove excess polycrystalline by dry etching to form a polysilicon collector 114, a polysilicon base 115, a polysilicon gate 116 of the NMOS, and a polysilicon gate 117 of the PMOS of the dual polycrystalline self-aligned bipolar junction transistor.

[0150] 12) On this basis, the source and drain of NMOS / PMOS are heavily doped and the BACK end well is heavily doped to form a P well heavily doped 118, an N well heavily doped 121, an N-type source region 119 and an N-type drain region 120 of NMOS, and a P-type source region 122 and a P-type drain region 123 of PMOS.

[0151] 13) A TEOS metal pre-dielectric layer 124 is deposited, and the oxide layer and polycrystalline are removed by dry etching using a photomask to form a base window of the bipolar transistor.

[0152] 14) The P-type base region 129 is implanted and connected to the P heavily doped external base region 128 diffused into the silicon by polycrystalline to form a double base region through the polysilicon base.

[0153] 15) Then, an L-shaped sidewall structure emission region window is formed through multiple deposition and etching, including a sidewall oxide layer 125 and a sidewall silicon nitride 126.

[0154] 16) Deposit a second layer of polysilicon, and use a photomask to form an emitter region of a dual poly-Si self-aligned bipolar junction transistor by injection. Use the photomask to perform dry etching to etch out excess polycrystalline to form a polysilicon emitter 127 of the dual poly-Si self-aligned bipolar junction transistor. Anneal the emitter region to form an N-type heavily doped emitter region 130.

[0155] 17) A hole is opened on the polycrystalline of the collector region and the double base region of the double polycrystalline self-aligned bipolar junction transistor and metal is deposited to form a collector metal 131 and a base metal 132; a metal is deposited on the polysilicon emitter of the double polycrystalline self-aligned bipolar junction transistor to form an emitter metal 133; a hole is opened on the N-type source region, the drain region, and the P-well heavily doped silicon substrate of the NMOS and metal is deposited to form a source metal 135, a drain metal 137, and a BACK terminal metal 134; a hole is opened on the gate polycrystalline of the NMOS and metal is deposited to form a gate metal 136; a hole is opened on the P-type source region, the drain region, and the N-well heavily doped silicon substrate of the PMOS and metal is deposited to form a source metal 139, a drain metal 141, and a BACK terminal metal 138; a hole is opened on the gate polycrystalline of the PMOS and metal is deposited to form a gate metal 140.

[0156] The SOI silicon substrate (including the P-type substrate, the oxide layer on the substrate, and the silicon on the oxide layer) may also be a single crystal silicon substrate.

[0157] The material of the SOI silicon substrate includes bulk silicon, silicon carbide, gallium arsenide, indium phosphide or silicon germanium.

[0158] The dual poly self-aligned bipolar junction transistor can be NPN, PNP, or a combination of the two.

[0159] The polysilicon collector, polysilicon base and polysilicon emitter are composed of one or more repeated structural units.

Claims

1. A method for integrating CMOS devices in a dual poly self-aligned bipolar junction transistor process, characterized in that: The following steps are involved: 1) Provide an SOI silicon substrate. 2) sequentially forming an N-type primary buried layer (103) of a dual polycrystalline self-aligned bipolar junction transistor, a P-type primary buried layer (104) of an NMOS, and an N-type secondary buried layer (105) of a PMOS; 3) An epitaxial layer (106) is formed on the SOI silicon substrate. 4) forming a P-type well region (107) of NMOS and an N-type well region (108) of PMOS in the epitaxial layer (106); 5) forming a full dielectric island isolation of a dual polycrystalline self-aligned bipolar junction transistor and NMOS / PMOS, including a trench isolation oxide layer (109) and a trench isolation polysilicon (110); 6) performing N-type penetration (111) implantation of the collector of the dual polycrystalline self-aligned bipolar junction transistor and connecting it to the N-type primary buried layer (103); 7) forming a field oxide layer (112) of a selective oxidation structure, rinsing away excess silicon nitride and oxide layers, and forming an active region and a field region in the dual polycrystalline self-aligned bipolar junction transistor and the NMOS / PMOS region, respectively; 8) growing a gate oxide layer to form a gate oxide layer (113); 9) removing the gate oxide in the dual poly self-aligned bipolar junction transistor region and retaining the gate oxide in the NMOS / PMOS region; 10) Deposit the first layer of polysilicon, perform general implantation first, and then use a photomask to perform gate poly implantation of the N-type / P-type bipolar transistor and NMOS / PMOS in sequence; 11) etching to remove excess polycrystals, forming a polysilicon collector (114), a polysilicon base (115), a polysilicon gate (116) of an NMOS, and a polysilicon gate (117) of a PMOS of a dual polycrystalline self-aligned bipolar junction transistor; 12) performing heavy doping of the source and drain of NMOS / PMOS and heavy doping of the BACK end well to form heavy doping of P well (118), heavy doping of N well (121), N type source region (119), N type drain region (120) of NMOS, P type source region (122), P type drain region (123) of PMOS; 13) depositing a TEOS metal pre-dielectric layer (124), removing the oxide layer and polycrystalline, and forming a base window of a bipolar transistor; 14) P-type base region (129) is implanted and connected to the P heavily doped external base region 128 diffused into silicon by polycrystalline to form a double base region through the polysilicon base electrode; 15) forming an L-shaped sidewall structure emission region window by multiple deposition and etching steps; 16) depositing a second layer of polysilicon, using a photomask to form an emitter region of a dual polycrystalline self-aligned bipolar junction transistor by implantation, etching out excess polycrystalline to form a polysilicon emitter (127) of the dual polycrystalline self-aligned bipolar junction transistor, and annealing the emitter region to form an N-type heavily doped emitter region (130); 17) Deposit metal to form the collector, emitter, source, drain, gate, and BACK metal structures of the integrated CMOS device.

2. A method for integrating CMOS devices in a dual poly self-aligned bipolar junction transistor process according to claim 1, characterized in that: The P-type primary buried layer (104) of the NMOS is located between the N-type primary buried layer (103) and the N-type secondary buried layer (105) of the PMOS, and is not in contact with the N-type primary buried layer (103) and the N-type secondary buried layer (105) of the PMOS.

3. The method of integrating CMOS devices in a dual poly self-aligned bipolar junction transistor process according to claim 1, characterized in that: The trench isolation bottom trench isolation oxide layer (109) is in contact with the oxide layer (101) on the SOI substrate.

4. The method of integrating CMOS devices in a dual poly self-aligned bipolar junction transistor process according to claim 1, characterized in that: In step 7), a field oxide layer (112) of the selective oxidation structure is formed by photolithography; In step 9), the gate oxide in the double poly self-aligned bipolar junction transistor region is removed by wet etching using a photomask; In step 11), excess polycrystalline is removed by dry etching using a photomask; In step 13), the oxide layer and polycrystalline are removed by dry etching using a photomask; In step 16), a photomask is used to perform dry etching to etch out excess polycrystalline to form a polysilicon emitter (127) of a dual polycrystalline self-aligned bipolar junction transistor.

5. The method of integrating CMOS devices in a dual poly self-aligned bipolar junction transistor process according to claim 1, characterized in that: The sidewall structure emission region window comprises a sidewall oxide layer (125) and a sidewall silicon nitride (126).

6. The method for integrating CMOS devices in a dual poly self-aligned bipolar junction transistor process according to claim 1, characterized in that: The steps of depositing metal to form the collector, emitter, source, drain, gate, and BACK metal structures of the integrated CMOS device include: Opening holes in the polycrystals of the collector region and the double base region of the double polycrystal self-aligned bipolar junction transistor and depositing metal to form collector metal (131) and base metal (132); Depositing metal on the polysilicon emitter of the double poly self-aligned bipolar junction transistor to form an emitter metal (133); Opening holes on the heavily doped silicon substrate of the N-type source region, drain region and P-well of the NMOS and depositing metal to form source metal (135), drain metal (137) and BACK terminal metal (134); Opening a hole on the gate polycrystalline of the NMOS and depositing metal to form a gate metal (136); Opening holes on the heavily doped silicon substrate of the PMOS P-type source region, drain region, and N-well and depositing metal to form source metal (139), drain metal (141), and BACK terminal metal (138); A hole is opened on the gate polycrystalline of the PMOS and metal is deposited to form a gate metal (140).

7. The method of integrating CMOS devices in a dual poly self-aligned bipolar junction transistor process according to claim 1, characterized in that: The SOI silicon substrate comprises a P-type substrate (100), an oxide layer (101) on the substrate, and silicon (102) on the oxide layer, or the SOI silicon substrate is a single crystal silicon substrate. The material of the SOI silicon substrate includes bulk silicon, silicon carbide, gallium arsenide, indium phosphide or silicon germanium.

8. The method of integrating CMOS devices in a dual poly self-aligned bipolar junction transistor process according to claim 1, characterized in that: The dual polycrystalline self-aligned bipolar junction transistor is NPN, PNP, or a combination of NPN and PNP.

9. The method of integrating CMOS devices in a dual poly self-aligned bipolar junction transistor process according to claim 1, characterized in that: The polysilicon collector, polysilicon base and polysilicon emitter are composed of one or more repeated structural units.

10. A CMOS device integrated in a dual poly self-aligned bipolar junction transistor process, characterized in that: The dual polycrystalline self-aligned bipolar junction transistor integrated with a CMOS device is prepared by the method according to any one of claims 1 to 9.

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