Solar cell and manufacturing method thereof

Abstract

The invention provides a solar cell and a manufacturing method thereof, and mainly relates to the field of photovoltaic technology. According to the manufacturing method of the solar cell, a tunneling oxide layer and a doping layer are formed on the front face and the back face of a silicon substrate, protection layers are formed on the front face and the back face of the silicon substrate, and then the protection layers in a front face non-grid line area and a back face non-grid line area of the silicon substrate are removed. At least part of the front doping layer in the front non-grid line area of the silicon substrate and at least part of the back doping layer in the back non-grid line area of the silicon substrate are removed, the thickness of the grid line area is reserved, and the thickness of the non-grid line area is reduced, so that the passivation performance of the grid line area of the solar cell can be guaranteed, the open-circuit voltage is improved, and the performance of the solar cell is improved. And parasitic absorption of a non-grid line region can be reduced, and short-circuit current is improved, so that the battery efficiency is improved. Similarly, the solar cell provided by the invention also has the above advantages.

Description

Technical Field

[0001] The present application mainly relates to the field of photovoltaic technology, and in particular to a solar cell and a method for manufacturing the same. Background Art

[0002] The tunnel oxide passivated contact (TOPCon) battery has a tunnel oxide passivation structure as its core and has good passivation performance.

[0003] The bifacial TOPCon cell deposits a tunnel oxide layer and a P-type polysilicon layer on the front side, and a tunnel oxide layer and an N-type polysilicon layer on the back side to improve the passivation effect on the front and back sides, increase the opening voltage, and thus improve the cell efficiency. However, a thicker polysilicon layer may cause parasitic absorption, resulting in current loss and affecting cell efficiency. Therefore, thinning the polysilicon layer is one of the effective means to achieve efficiency improvement. However, since the back side of the bifacial TOPCon cell is often used with corrosive slurry, the thinner polysilicon layer is difficult to prevent the silver grains in the slurry from piercing, resulting in an increase in the metal reverse current density and a deterioration in the passivation performance. Summary of the invention

[0004] In order to solve the above technical problems, the present application provides a solar cell and a method for manufacturing the same, so as to take into account both passivation performance and parasitic absorption reduction.

[0005] In a first aspect, the present application provides a method for manufacturing a solar cell, comprising the following steps:

[0006] A front tunneling oxide layer and a front doping layer are sequentially formed on the front side of the silicon substrate, and a first protective layer is formed on the front side and the back side of the silicon substrate;

[0007] removing the first protective layer on the back side of the silicon substrate;

[0008] Forming a back tunneling oxide layer and a back doping layer in sequence on the back side of the silicon substrate, and forming a second protective layer on the front side and the back side of the silicon substrate;

[0009] Removing the first protective layer and the second protective layer in the non-gate line area on the front side of the silicon substrate, and removing the second protective layer in the non-gate line area on the back side of the silicon substrate;

[0010] Removing at least a portion of the front doped layer in the front non-gate line region of the silicon substrate and at least a portion of the back doped layer in the back non-gate line region of the silicon substrate;

[0011] forming a front passivation layer on the front side of the silicon substrate, and forming a back passivation layer on the back side of the silicon substrate;

[0012] A first electrode contacting the front doped layer is formed on the front side of the silicon substrate, and a second electrode contacting the back doped layer is formed on the back side of the silicon substrate, wherein the front doped layer and the back doped layer have opposite doping types.

[0013] In a possible implementation, the first protective layer and the second protective layer in the non-gate line area on the front side of the silicon substrate and the second protective layer in the non-gate line area on the back side of the silicon substrate are removed by laser grooving.

[0014] In a possible implementation, the width of the front non-gate line region and / or the back non-gate line region is 650-700 nm.

[0015] In a possible implementation, an alkali solution with a mass concentration of 3-3.5% is used to remove at least a portion of the front doped layer in the front non-gate line area of ​​the silicon substrate and at least a portion of the back doped layer in the back non-gate line area of ​​the silicon substrate.

[0016] In a possible implementation, before removing at least a portion of the front doped layer in the front non-gate line region of the silicon substrate and at least a portion of the back doped layer in the back non-gate line region of the silicon substrate, the method further includes:

[0017] Removing the second protective layer on the front side of the silicon substrate by pickling;

[0018] When removing at least part of the front doped layer in the non-gate line area of ​​the front side of the silicon substrate and at least part of the back doped layer in the non-gate line area of ​​the back side of the silicon substrate, the back doped layer coated around the front side of the silicon substrate is also removed.

[0019] In a possible implementation, after removing at least a portion of the front doped layer in the front non-gate line region of the silicon substrate and at least a portion of the back doped layer in the back non-gate line region of the silicon substrate, the method further includes:

[0020] The first protective layer and the second protective layer on the front side of the silicon substrate, and the second protective layer on the back side of the silicon substrate are removed by pickling.

[0021] In a possible implementation, the front doped layer is boron-doped polysilicon, the back doped layer is phosphorus-doped polysilicon, the first protective layer is borosilicate glass, and the second protective layer is phosphorus-silicate glass; or,

[0022] The front doped layer is phosphorus-doped polysilicon, the back doped layer is boron-doped polysilicon, the first protective layer is phosphorus-silicate glass, and the second protective layer is borosilicate glass.

[0023] In a second aspect, the present application provides a solar cell, comprising:

[0024] A silicon substrate having a front side and a back side opposite to each other, wherein the front side has a front gate line region and a front non-gate line region, and the back side has a back gate line region and a back non-gate line region;

[0025] A front tunneling oxide layer covering the front gate line region and the front non-gate line region;

[0026] A front doped layer covering the front tunneling oxide layer in the front gate line region;

[0027] A front passivation layer covering the front doped layer and the front tunneling oxide layer in the front non-gate line area;

[0028] A back tunneling oxide layer, covering the back gate line region and the back non-gate line region;

[0029] A back doping layer covering the back tunneling oxide layer in the back gate line region;

[0030] A back passivation layer covering the back doped layer and the back tunneling oxide layer in the back non-gate line area;

[0031] A first electrode and a second electrode, wherein the first electrode contacts the front doped layer, and the second electrode contacts the back doped layer, wherein the front doped layer and the back doped layer have opposite doping types.

[0032] In a possible implementation, the front doped layer also covers the front non-gate line region, and the thickness of the front doped layer in the front non-gate line region is lower than the thickness of the front doped layer in the front gate line region; and / or

[0033] The back doping layer also covers the back non-gate line region, and the thickness of the back doping layer in the back non-gate line region is lower than the thickness of the back doping layer in the back gate line region.

[0034] In a possible implementation, in the front non-gate line region, the front passivation layer contacts the front tunneling oxide layer; and / or

[0035] In the back non-gate line region, the back passivation layer contacts the back tunneling oxide layer.

[0036] In a possible implementation, the width of the front non-gate line region and / or the back non-gate line region is 650-700 nm.

[0037] Compared with the prior art, this application has the following advantages:

[0038] The manufacturing method of the solar cell provided by the present application first forms a tunneling oxide layer and a doping layer on the front and back of a silicon substrate, and forms a protective layer on the front and back of the silicon substrate, then removes the protective layer of the front non-gridline area and the back non-gridline area of ​​the silicon substrate, and then removes at least part of the front doping layer of the front non-gridline area of ​​the silicon substrate and at least part of the back doping layer of the back non-gridline area of ​​the silicon substrate, retains the thickness of the gridline area, and thins the thickness of the non-gridline area, which can not only ensure the passivation performance of the gridline area of ​​the solar cell and improve the open-circuit voltage, but also reduce the parasitic absorption of the non-gridline area, increase the short-circuit current, and thus improve the battery efficiency. Similarly, the solar cell provided by the present application also has the above advantages. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] The accompanying drawings are included to provide a further understanding of the present application. They are included and constitute a part of the present application. The accompanying drawings illustrate embodiments of the present application and together with the present specification serve to explain the principles of the present application. In the accompanying drawings:

[0040] Figure 1 It is a schematic flow chart of a method for manufacturing a solar cell provided in an embodiment of the present application;

[0041] Figure 2(a)-Figure 2(h) It is a schematic diagram of the structure of a solar cell in different steps of a method for manufacturing a solar cell provided in an embodiment of the present application;

[0042] Figure 3 is a schematic structural diagram of a solar cell provided in an embodiment of the present application;

[0043] Figure 4 It is a schematic diagram of the structure of another solar cell provided in an embodiment of the present application. DETAILED DESCRIPTION

[0044] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following is a brief introduction to the drawings required for the description of the embodiments. Obviously, the drawings described below are only some examples or embodiments of the present application. For ordinary technicians in this field, the present application can also be applied to other similar scenarios based on these drawings without creative work. Unless it is obvious from the language environment or otherwise explained, the same reference numerals in the figures represent the same structure or operation.

[0045] As shown in this application, unless the context clearly indicates an exception, the words "a", "an", "a kind" and / or "the" do not refer to the singular, but also include the plural. Generally speaking, the terms "include" and "comprise" only indicate the inclusion of the steps and elements that have been clearly identified, and these steps and elements do not constitute an exclusive list. The method or device may also include other steps or elements.

[0046] Unless otherwise specifically stated, the relative arrangement, numerical expressions and numerical values ​​of the parts and steps set forth in these embodiments do not limit the scope of the application. Meanwhile, it should be understood that, for ease of description, the sizes of the various parts shown in the accompanying drawings are not drawn according to actual proportional relationships. The technology, methods and equipment known to those of ordinary skill in the relevant art may not be discussed in detail, but in appropriate cases, the technology, methods and equipment should be considered as a part of the specification. In all examples shown and discussed here, any specific value should be interpreted as being merely exemplary, rather than as a limitation. Therefore, other examples of exemplary embodiments may have different values. It should be noted that similar reference numerals and letters represent similar items in the following drawings, and therefore, once a certain item is defined in an accompanying drawing, it does not need to be further discussed in subsequent drawings.

[0047] In addition, although the terms used in this application are selected from well-known and commonly used terms, some of the terms mentioned in this application specification may be selected by the applicant at his or her discretion, and their detailed meanings are explained in the relevant parts of the description of this article. In addition, it is required to understand this application not only by the actual terms used, but also by the meaning implied by each term.

[0048] It should be understood that when a component is referred to as being “on another component,” “connected to another component,” “coupled to another component,” or “contacting another component,” it can be directly on, connected to, coupled to, or contacting the other component, or intervening components may be present. In contrast, when a component is referred to as being “directly on another component,” “directly connected to,” “directly coupled to,” or “directly contacting” another component, there are no intervening components present.

[0049] Flowcharts are used in the present application to illustrate the operations performed by the methods according to the embodiments of the present application. It should be understood that the preceding or following operations are not necessarily performed accurately in order. On the contrary, various steps may be processed in reverse order or simultaneously. At the same time, other operations may be added to these processes, or one or more operations may be removed from these processes.

[0050] Please refer to Figure 1 - Figure 2, the method for manufacturing a solar cell comprises the following:

[0051] Step 101: forming a front tunneling oxide layer and a front doping layer in sequence on the front side of a silicon substrate, and forming a first protective layer on the front side and the back side of the silicon substrate.

[0052] Specifically, N-type single crystal silicon or P-type single crystal silicon can be selected as the silicon substrate 201. The silicon substrate 201 has a front side and a back side in the thickness direction thereof. When the solar cell is working, the front side faces the sun. A front tunneling oxide layer 211 and a front doping layer 212 are sequentially formed on the front side of the silicon substrate 201, and a first protective layer 2001 is formed on the front side and the back side of the silicon substrate 201, as shown in FIG. 2(a).

[0053] In some embodiments, the front doped layer 212 may be a doped polysilicon layer. For example, a front tunneling oxide layer and a boron-doped polysilicon layer may be formed on the front side of the silicon substrate. When forming the boron-doped polysilicon layer, a borosilicate glass (BSG) layer with a thickness of about 10-15 nm may be formed on the front and back sides of the silicon substrate as a protective layer for subsequent wet etching. A front tunneling oxide layer and a phosphorus-doped polysilicon layer may also be formed on the front side of the silicon substrate. When forming the phosphorus-doped polysilicon layer, a phosphorus-silicate glass (PSG) layer with a thickness of about 10-15 nm may be formed on the front and back sides of the silicon substrate as a protective layer for subsequent wet etching.

[0054] In some embodiments, before step 101, the silicon substrate may be pretreated to remove impurities and damage on the surface of the silicon substrate, and then the silicon substrate may be double-sided textured to obtain a silicon substrate with a textured surface, thereby reducing the reflection of light by the battery.

[0055] Step 102: removing the first protective layer on the back side of the silicon substrate.

[0056] For example, the first protective layer 2001 on the back side of the silicon substrate 201 can be removed by acid washing, as shown in Fig. 2(b). Furthermore, the back side of the silicon substrate 201 can be subjected to alkali polishing.

[0057] Step 103: forming a back tunneling oxide layer and a back doping layer in sequence on the back side of the silicon substrate, and forming a second protective layer on the front side and the back side of the silicon substrate.

[0058] Specifically, as shown in FIG. 2( c ), a back tunneling oxide layer 221 and a back doping layer 222 are sequentially formed on the back side of the silicon substrate 201 , and a second protective layer 2002 is formed on the front and back sides of the silicon substrate 201 .

[0059] In some embodiments, the back doped layer 222 may be a doped polysilicon layer. For example, a back tunneling oxide layer 221 and a phosphorus-doped polysilicon layer may be formed on the back of the silicon substrate 201. When the phosphorus-doped polysilicon layer is formed, a phosphorus-silicate glass (PSG) layer with a thickness of about 10-15 nm may be formed on the front and back of the silicon substrate 201 as a protective layer for subsequent wet etching. A back tunneling oxide layer 221 and a boron-doped polysilicon layer may also be formed on the back of the silicon substrate 201. When the boron-doped polysilicon layer is formed, a borosilicate glass (BSG) layer with a thickness of about 10-15 nm may be formed on the front and back of the silicon substrate 201 as a protective layer for subsequent wet etching.

[0060] It should be noted that the doping types of the front doping layer 212 and the back doping layer 222 are opposite. For example, if the front doping layer 212 is boron-doped polysilicon, then the back doping layer 222 is phosphorus-doped polysilicon.

[0061] In the embodiment of the present application, a front tunneling oxide layer and a front doped polysilicon layer are formed on the front side of the silicon substrate, and a back tunneling oxide layer and a back doped polysilicon layer are formed on the back side of the silicon substrate. Double-sided polysilicon can improve the overall passivation effect of the battery and increase the opening voltage Voc.

[0062] Step 104 , removing the first protective layer and the second protective layer in the non-gate line region of the front side of the silicon substrate, and removing the second protective layer in the non-gate line region of the back side of the silicon substrate.

[0063] Specifically, as shown in FIG. 2( d ), the first protective layer 2001 and the second protective layer 2002 in the front non-gate line region 203 of the silicon substrate 201 and the second protective layer 2002 in the back non-gate line region 205 of the silicon substrate 201 are removed.

[0064] In some embodiments, laser grooving can be used to remove the first protective layer 2001 and the second protective layer 2002 in the non-gridline area 203 on the front side of the silicon substrate 201, and the second protective layer 2002 in the non-gridline area 205 on the back side of the silicon substrate 201. Optionally, the power of the laser is about 5-20W, such as 10-15W or 15-20W, for example, the power of the laser is 5W, 10W, 12W, 15W, 18W or 20W, to ensure that the protective layer in the non-gridline area can be removed, while preventing excessive laser power from causing mechanical damage to the silicon substrate.

[0065] In some embodiments, the width of the laser groove is about 650-700nm, that is, the width of the non-gate line area is about 650-700nm, such as 650nm, 680nm or 700nm, so that the width of the gate line area is appropriate, reducing the parasitic absorption of the film layer and increasing the short-circuit current. Further, the depth of the laser groove is the thickness of the first protective layer 2001 and the second protective layer 2002 or the second protective layer 2002, such as the groove depth can be about 20-25nm.

[0066] Step 105 , removing at least a portion of the front doped layer in the front non-gate line region of the silicon substrate and at least a portion of the back doped layer in the back non-gate line region of the silicon substrate.

[0067] Specifically, as shown in FIG2(e), at least a portion of the front doped layer 212 (all removed in the figure) in the front non-gate line region 203 of the silicon substrate 201 and at least a portion of the back doped layer 222 (all removed in the figure) in the back non-gate line region 205 of the silicon substrate 201 are removed. Further, the first protective layer 2001 and the second protective layer 2002 on the front of the silicon substrate 201 and the second protective layer 2002 on the back of the silicon substrate 201 can also be removed by pickling, as shown in FIG2(f), to further improve the efficiency of the battery.

[0068] In some embodiments, an alkali solution with a mass concentration of 3-3.5% may be used to remove at least a portion of the front doped layer 212 in the front non-gate line region 203 of the silicon substrate 201 and at least a portion of the back doped layer 222 in the back non-gate line region 205 of the silicon substrate 201 .

[0069] In step 104, the protective layer in the non-gate line area is removed, and the protective layer in the gate line area is retained. When the silicon substrate 201 is cleaned with an alkaline solution, only the doping layer in the non-gate line area is removed, and part of the doping layer can be removed, or the doping layer in the non-gate line area can be completely removed. There is a tunneling oxide layer blocking under the doping layer, which can prevent over-etching, realize the thinning of the doping layer in the non-gate line area, reduce the parasitic absorption of the film layer, and increase the short-circuit current. The doping layer in the gate line area is retained to ensure the effective transmission of carriers and ensure the stability of the opening voltage Voc and the filling factor FF.

[0070] Step 106: forming a front passivation layer on the front side of the silicon substrate, and forming a back passivation layer on the back side of the silicon substrate.

[0071] Specifically, as shown in FIG. 2( g ), a front passivation layer 213 is formed on the front surface of the silicon substrate 201 , and a back passivation layer 223 is formed on the back surface of the silicon substrate 201 .

[0072] In some embodiments, both the front passivation layer 213 and the back passivation layer 223 include a silicon nitride layer. Further, the front passivation layer 213 may also include an aluminum oxide layer, and then an aluminum oxide layer is first formed on the front of the silicon substrate 201, and then a silicon nitride layer is formed on the aluminum oxide layer to improve the passivation effect.

[0073] Step 107 : forming a first electrode on the front side of the silicon substrate and contacting the front doped layer, and forming a second electrode on the back side of the silicon substrate and contacting the back doped layer.

[0074] Specifically, as shown in FIG. 2( h ), a first electrode 214 contacting the front doped layer 212 is formed on the front surface of the silicon substrate 201 , and a second electrode 224 contacting the back doped layer 222 is formed on the back surface of the silicon substrate 201 .

[0075] In some embodiments, before step 105, the second protective layer 2002 on the front side of the silicon substrate 201 is also removed by pickling. In this embodiment, when removing the doping layer in the non-gate line region of the silicon substrate 201, if the front side of the silicon substrate 201 is coated with a back doping layer, the back doping layer coated on the front side of the silicon substrate 201 can also be removed, thereby further improving the efficiency of the battery. Accordingly, when removing the protective layer in the gate line region of the silicon substrate 201, since the second protective layer 2002 on the front side of the silicon substrate 201 has been removed, it is only necessary to remove the first protective layer 2001 on the front side of the silicon substrate 201 and the second protective layer 2002 on the back side of the silicon substrate 201.

[0076] Please refer to Figure 3 The solar cell manufactured according to the above embodiment includes a silicon substrate 201, a front grid line region 202 and a front non-grid line region 203 located on the front side of the silicon substrate 201, and a back grid line region 204 and a back non-grid line region 205 located on the back side of the silicon substrate 201. The front tunneling oxide layer 211 covers the front grid line region 202 and the front non-grid line region 203. The front doping layer 212 covers the front tunneling oxide layer 211 of the front grid line region 202. The front passivation layer 213 covers the front doping layer 212 and the front tunneling oxide layer 211 of the front non-grid line region 203.

[0077] In some embodiments, the front doping layer 212 also covers the front non-gate line region 203, and the thickness of the front doping layer in the front non-gate line region 203 is lower than the thickness of the front doping layer in the front gate line region 202. Figure 3 In some other embodiments, in the front non-gate line region 203, the front passivation layer contacts the front tunneling oxide layer 211, such as Figure 3 (b) as shown.

[0078] The back tunneling oxide layer 221 covers the back gate line region 204 and the back non-gate line region 205. The back doped layer 222 covers the back tunneling oxide layer 221 of the back gate line region 204. The back passivation layer 223 covers the back doped layer 222 and the back tunneling oxide layer 221 of the back non-gate line region 205.

[0079] In some embodiments, the back doping layer 222 also covers the back non-gate line region 205, and the back doping layer thickness of the back non-gate line region 205 is lower than the back doping layer thickness of the back gate line region 204. Figure 3 In some other embodiments, in the back non-gate line region 205, the back passivation layer contacts the back tunneling oxide layer 221, such as Figure 3 (b) as shown.

[0080] The first electrode 214 contacts the front doped layer 212 , and the second electrode 224 contacts the back doped layer 222 .

[0081] In order to better understand the present application, a specific embodiment is described in detail below.

[0082] Please combine Figure 4 The front gate line region 202 of the solar cell includes, from the inside to the outside, a front tunneling oxide layer 211, a boron-doped polysilicon layer 2121, an aluminum oxide layer 2131, and a front silicon nitride layer 2132. The front non-gate line region 203 includes, from the inside to the outside, a front tunneling oxide layer 211, an aluminum oxide layer 2131, and a front silicon nitride layer 2132. The first electrode 214 is located in the front gate line region 202 and is connected to the boron-doped polysilicon layer 2121. The back gate line region 204 includes, from the inside to the outside, a back tunneling oxide layer 221, a phosphorus-doped polysilicon layer 2221, and a back silicon nitride layer 2231. The back non-gate line region 205 includes, from the inside to the outside, a back tunneling oxide layer 221 and a back silicon nitride layer 2231. The second electrode 224 is located in the back gate line region 204 and is in contact with the phosphorus-doped polysilicon layer 2221.

[0083] For example, Figure 4 The manufacturing method of the solar cell shown includes the following:

[0084] Step 1001, double-sided texturing. An N-type single crystal silicon substrate is selected as the silicon substrate, with a resistivity of about 0.8-1.3 ohm·cm and a thickness of about 120 nm. Pre-treatment is first performed in a mixed solution of KOH and H2O2 to remove impurities and damage on the surface of the silicon substrate, and then texturing is performed in a NaOH solution to obtain a silicon substrate 201 with a pyramid texture on the surface.

[0085] Step 1002: Prepare a front tunneling oxide layer 211 and a boron-doped polysilicon layer 2121 on the front side of the silicon substrate.

[0086] Specifically, a front tunneling oxide layer 211 (such as a SiO2 layer with a thickness of about 1.2-2.5 nm) and a boron-doped polysilicon layer 2121 (with a thickness of about 85-90 nm) are deposited on the front of the silicon substrate by low pressure chemical vapor deposition LPCVD and boron diffusion, with a square resistance of about 260 Ω / sq and a doping concentration of about 6E19-7E19 atoms / cm 3 The junction depth is about 100-120nm. This process will form a BSG layer with a thickness of about 10-15nm on the surface of the silicon substrate as a protective layer for subsequent wet etching.

[0087] Step 1003: Remove the BSG layer on the back of the silicon substrate by chain HF pickling, the concentration of the HF solution is about 60-65%. Polish the back of the silicon substrate by tank alkali etching, the alkali solution is a NaOH solution with a concentration of about 3-3.5%.

[0088] Step 1004: prepare a back tunneling oxide layer 221 and a phosphorus-doped polysilicon layer 2221 on the back side of the silicon substrate.

[0089] Specifically, a back tunneling oxide layer 221 (such as a SiO2 layer with a thickness of about 1.2-2.5 nm) and a phosphorus-doped polysilicon layer 2221 (with a thickness of about 95-100 nm) are deposited on the back of the silicon substrate by low pressure chemical vapor deposition LPCVD and phosphorus diffusion, with a square resistance of about 50 Ω / sq and a doping concentration of about 2E21-4E21 atoms / cm 3 The junction depth is about 130-150nm. This process will form a PSG layer with a thickness of about 15-20nm on the surface of the silicon substrate as a protective layer for subsequent wet etching.

[0090] Step 1005, groove the front and back sides, and remove the BSG layer and PSG layer in the non-gate line area of ​​the front and back sides of the silicon substrate by laser. The groove depth is about 20-25nm and the width is about 650-700nm.

[0091] Step 1006, RC cleaning, using chain HF pickling to remove the PSG coated on the front side, the concentration of the HF solution is about 60-65%. Use a slot-type alkaline etching method to remove the polysilicon layer coated on the front side and the polysilicon layer in the front and back grooved areas. The alkaline solution is NaOH with a concentration of about 3-3.5%. This step is the same as the alkaline solution used in step 1003. It can not only etch away the polysilicon layer of the target thickness, but also reduce production costs. In some embodiments, the thickness of the etched polysilicon layer in the front and back grooved areas is about 85-100nm. There is a tunneling oxide layer blocking the bottom of the polysilicon layer, which mainly plays a passivation role and can prevent over-etching. Use slot-type HF pickling to remove the BSG layer and PSG layer in the front gate line area of ​​the silicon substrate, and the PSG layer in the back gate line area of ​​the silicon substrate. The concentration of the HF solution is about 30-35%.

[0092] Step 1007: Prepare an aluminum oxide layer 2131 on the front side of the silicon substrate.

[0093] Specifically, an aluminum oxide layer 2131 may be deposited on the front side of the silicon substrate by atomic layer deposition (ALD), and the thickness of the aluminum oxide layer 2131 is about 5-8 nm.

[0094] Step 1008: prepare a front silicon nitride layer 2132 on the front side of the silicon substrate, and prepare a back silicon nitride layer 2231 on the back side of the silicon substrate.

[0095] Specifically, a front silicon nitride layer 2132 and a back silicon nitride layer 2231 may be deposited on the front and back sides of the silicon substrate respectively by plasma enhanced chemical vapor deposition (PECVD), and the thickness of the front silicon nitride layer 2132 and the back silicon nitride layer 2231 are both about 75-80 nm.

[0096] Step 1009: perform double-sided metallization on the silicon substrate to produce a solar cell.

[0097] Specifically, the first electrode 224 and the second electrode 215 may be formed by sequentially printing silver paste on the back side and the front side of the silicon substrate and performing sintering treatment.

[0098] Table 1 shows the comparative data of electrical performance parameters of the above specific embodiment (hereinafter referred to as the test group) and the existing solar cell in which the polysilicon layer in the non-gate line region is not thinned (hereinafter referred to as the comparison group).

[0099] Table 1

[0100]

[0101] It can be seen from Table 1 that the solar cell prepared in the above specific embodiment improves the open voltage (ie, open circuit voltage), short circuit current and fill factor of the cell to a certain extent.

[0102] The basic concepts have been described above. Obviously, for those skilled in the art, the above invention disclosure is only used as an example and does not constitute a limitation of the present application. Although not explicitly stated herein, those skilled in the art may make various modifications, improvements and amendments to the present application. Such modifications, improvements and amendments are suggested in the present application, so such modifications, improvements and amendments still belong to the spirit and scope of the exemplary embodiments of the present application.

[0103] At the same time, the present application uses specific words to describe the embodiments of the present application. For example, "one embodiment", "an embodiment", and / or "some embodiments" refer to a certain feature, structure or characteristic related to at least one embodiment of the present application. Therefore, it should be emphasized and noted that "one embodiment" or "an embodiment" or "an alternative embodiment" mentioned twice or more in different positions in this specification does not necessarily refer to the same embodiment. In addition, some features, structures or characteristics in one or more embodiments of the present application can be appropriately combined.

[0104] Similarly, it should be noted that in order to simplify the description of the disclosure of this application and thus help understand one or more embodiments of the invention, in the above description of the embodiments of the present application, multiple features are sometimes combined into one embodiment, figure or description thereof. However, this disclosure method does not mean that the subject of the present application requires more features than the features mentioned. In fact, the features of the embodiment are less than all the features of the single embodiment disclosed above.

[0105] In some embodiments, numbers describing the number of components and attributes are used. It should be understood that such numbers used in the description of the embodiments are modified by the modifiers "about", "approximately" or "substantially" in some examples. Unless otherwise specified, "about", "approximately" or "substantially" indicate that the numbers are allowed to vary by ±20%. Accordingly, in some embodiments, the numerical parameters used in the specification are approximate values, which may change according to the required features of individual embodiments. In some embodiments, the numerical parameters should take into account the specified significant digits and adopt the general method of retaining the digits. Although the numerical domains and parameters used to confirm the breadth of the range in some embodiments of the present application are approximate values, in specific embodiments, the setting of such numerical values ​​is as accurate as possible within the feasible range.

[0106] Although the present application has been described with reference to the current specific embodiments, ordinary technicians in this technical field should recognize that the above embodiments are only used to illustrate the present application, and various equivalent changes or substitutions may be made without departing from the spirit of the present application. Therefore, as long as the changes and modifications to the above embodiments are within the essential spirit of the present application, they will fall within the scope of the present application.

Claims

1. A method for manufacturing a solar cell, characterized in that: The following steps are involved: Sequentially forming a front tunneling oxide layer and a front doping layer on the front side of the silicon substrate, and forming a first protective layer on the front side and the back side of the silicon substrate; removing the first protective layer on the back side of the silicon substrate; Forming a back tunneling oxide layer and a back doping layer in sequence on the back side of the silicon substrate, and forming a second protective layer on the front side and the back side of the silicon substrate; Removing the first protective layer and the second protective layer in the non-gate line area on the front side of the silicon substrate, and removing the second protective layer in the non-gate line area on the back side of the silicon substrate; Removing at least a portion of the front doped layer in the front non-gate line region of the silicon substrate and at least a portion of the back doped layer in the back non-gate line region of the silicon substrate; forming a front passivation layer on the front side of the silicon substrate, and forming a back passivation layer on the back side of the silicon substrate; A first electrode contacting the front doped layer is formed on the front side of the silicon substrate, and a second electrode contacting the back doped layer is formed on the back side of the silicon substrate, wherein the front doped layer and the back doped layer have opposite doping types.

2. The method for manufacturing a solar cell according to claim 1, wherein: The first protective layer and the second protective layer in the non-gate line area on the front side of the silicon substrate and the second protective layer in the non-gate line area on the back side of the silicon substrate are removed by laser grooving.

3. The method for manufacturing a solar cell according to claim 2, wherein: The width of the front non-gate line region and / or the back non-gate line region is 650-700 nm.

4. The method for manufacturing a solar cell according to claim 1, wherein: At least part of the front doped layer in the front non-gate line area of ​​the silicon substrate and at least part of the back doped layer in the back non-gate line area of ​​the silicon substrate are removed using an alkali solution with a mass concentration of 3-3.5%.

5. The method for manufacturing a solar cell according to claim 1 or 4, characterized in that: Before removing at least a portion of the front doped layer in the front non-gate line region of the silicon substrate and at least a portion of the back doped layer in the back non-gate line region of the silicon substrate, the method further includes: Removing the second protective layer on the front side of the silicon substrate by pickling; When removing at least part of the front doped layer in the non-gate line area of ​​the front side of the silicon substrate and at least part of the back doped layer in the non-gate line area of ​​the back side of the silicon substrate, the back doped layer coated around the front side of the silicon substrate is also removed.

6. The method for manufacturing a solar cell according to claim 1 or 4, characterized in that: After removing at least a portion of the front doped layer in the front non-gate line region of the silicon substrate and at least a portion of the back doped layer in the back non-gate line region of the silicon substrate, the method further includes: The first protective layer and the second protective layer on the front side of the silicon substrate, and the second protective layer on the back side of the silicon substrate are removed by pickling.

7. The method for manufacturing a solar cell according to claim 1, wherein: The front doped layer is boron-doped polysilicon, the back doped layer is phosphorus-doped polysilicon, the first protective layer is borosilicate glass, and the second protective layer is phosphorus-silicate glass; or The front doped layer is phosphorus-doped polysilicon, the back doped layer is boron-doped polysilicon, the first protective layer is phosphorus-silicate glass, and the second protective layer is borosilicate glass.

8. A solar cell, characterized in that: include: A silicon substrate having a front side and a back side opposite to each other, wherein the front side has a front gate line region and a front non-gate line region, and the back side has a back gate line region and a back non-gate line region; A front tunneling oxide layer, covering the front gate line region and the front non-gate line region; A front doped layer covering the front tunneling oxide layer in the front gate line region; A front passivation layer covering the front doped layer and the front tunneling oxide layer in the front non-gate line area; A back tunneling oxide layer, covering the back gate line region and the back non-gate line region; A back doping layer covering the back tunneling oxide layer in the back gate line region; A back passivation layer covering the back doped layer and the back tunneling oxide layer in the back non-gate line area; A first electrode and a second electrode, wherein the first electrode contacts the front doped layer, and the second electrode contacts the back doped layer, wherein the front doped layer and the back doped layer have opposite doping types.

9. The solar cell according to claim 8, characterized in that The front doped layer also covers the front non-gate line region, and the thickness of the front doped layer in the front non-gate line region is lower than the thickness of the front doped layer in the front gate line region; and / or The back doping layer also covers the back non-gate line region, and the thickness of the back doping layer in the back non-gate line region is lower than the thickness of the back doping layer in the back gate line region.

10. The solar cell according to claim 8, characterized in that In the front non-gate line area, the front passivation layer contacts the front tunneling oxide layer; and / or In the back non-gate line region, the back passivation layer contacts the back tunneling oxide layer.

11. The solar cell according to any one of claims 8 to 10, characterized in that: The width of the front non-gate line region and / or the back non-gate line region is 650-700 nm.

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