Flip light emitting diode chip and preparation method thereof

Abstract

The invention provides a flip light-emitting diode chip and a preparation method thereof, and the method comprises the steps: providing a substrate for growth, and sequentially depositing an N-type semiconductor layer, an active light-emitting layer and a P-type semiconductor layer on the substrate; preparing an N-type conductive through hole in the P-type semiconductor; preparing a current expansion layer on the P-type semiconductor layer and the N-type conductive through hole; preparing an isolation groove on the N-type conductive through hole and the current expansion layer; preparing a first semiconductor layer on the P-type semiconductor layer, the N-type conductive through hole, the current expansion layer and the isolation groove; preparing a third insulating layer on the first semiconductor layer; preparing a heat-conducting metal layer on the third insulating layer; preparing a fourth insulating layer on the heat-conducting metal layer; preparing a bonding pad layer on the fourth insulating layer; and the semi-finished product obtained after the step S9 is completed is welded to a support through the eutectic welding technology.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a flip-chip light emitting diode chip and a preparation method thereof. Background Art

[0002] In recent years, the light-emitting diode chip technology has developed rapidly under the competition of major manufacturers and has been widely used in various fields such as general lighting, special lighting, direct display screens, backlight display screens, and car lights.

[0003] In the prior art, the operating temperature of the existing flip-chip LED chips is high. When multiple flip-chip LED chips are used in series in a car lamp or other device, the operating temperature of the entire lamp bead will increase dramatically, seriously affecting the service life of the flip-chip LED chips. Summary of the invention

[0004] Based on this, the purpose of the present invention is to provide a flip-chip light emitting diode chip and a preparation method thereof, which can effectively solve the deficiencies in the above-mentioned prior art.

[0005] A method for preparing a flip-chip light-emitting diode chip, the method comprising: S1, providing a substrate required for growth, and sequentially depositing an N-type semiconductor layer, an active light-emitting layer, and a P-type semiconductor layer on the substrate; S2, preparing an N-type conductive through hole on the P-type semiconductor; S3, preparing a current spreading layer on the P-type semiconductor layer and the N-type conductive through hole; S4, preparing an isolation groove on the N-type conductive through hole and the current spreading layer; S5, preparing a first semiconductor layer on the P-type semiconductor layer, the N-type conductive via, the current spreading layer and the isolation trench; S6, preparing a third insulating layer on the first semiconductor layer; S7, preparing a thermally conductive metal layer on the third insulating layer, and then preparing an N-type thermally conductive metal layer through hole and a P-type thermally conductive metal layer through hole on the thermally conductive metal layer; Wherein, the thickness of the thermally conductive metal layer is between 2000Å and 20000Å, and the area of ​​the thermally conductive metal layer is larger than the area of ​​the N-type semiconductor layer; S8, preparing a fourth insulating layer on the thermally conductive metal layer, the N-type thermally conductive metal layer through hole, and the P-type thermally conductive metal layer through hole, and then preparing an N-type fourth insulating layer through hole, a P-type fourth insulating layer through hole, and a fourth insulating layer connecting through hole disposed between the N-type fourth insulating layer through hole and the P-type fourth insulating layer through hole on the fourth insulating layer; S9, preparing a pad layer on the fourth insulating layer, the N-type fourth insulating layer through hole, the P-type fourth insulating layer through hole, and the fourth insulating layer connecting through hole, the pad layer comprising an N-type pad, a P-type pad, and a thermally conductive pad located between the P-type pad and the N-type pad; The fourth insulating layer connecting through hole is used to connect the thermally conductive pad and the thermally conductive metal layer, the area of ​​the fourth insulating layer connecting through hole is larger than the area of ​​the thermally conductive pad, the area of ​​the thermally conductive pad is larger than the sum of the areas of the N-type pad and the P-type pad, and the area of ​​the thermally conductive pad is larger than half the area of ​​the thermally conductive metal layer; S10, welding the semi-finished product after step S9 onto the bracket using a eutectic welding process; The support has an area larger than that of the semi-finished product, a heat dissipation pad and a heat dissipation metal are arranged on the support, the thermal conductive pad is connected to the heat dissipation pad, and the heat dissipation pad is connected to the heat dissipation metal.

[0006] Furthermore, the first semiconductor layer includes a first insulating layer, a Bragg reflective layer, a Bragg reflective layer through hole, a first insulating layer through hole, a metal reflective layer, a second insulating layer, a second insulating layer through hole, and a metal connecting layer, which are sequentially arranged on the P-type semiconductor layer.

[0007] Furthermore, the specific process for preparing the first insulating layer is: SiO2 is deposited as a first insulating layer on the surface of the P-type semiconductor layer, the N-type conductive via, the current spreading layer and the isolation groove using a PECVD process, wherein the thickness of the first insulating layer is greater than 5000Å.

[0008] Furthermore, the specific process for preparing the Bragg reflection layer and the through hole of the Bragg reflection layer is: 2-10 groups of TiO2 and SiO2 stacks are deposited on the surface of the first insulating layer by electron beam evaporation process as a Bragg reflection layer, then photoresist is coated on the surface of the Bragg reflection layer, and then the photoresist on a part of the Bragg reflection layer is removed by exposure and development, and then the exposed Bragg reflection layer is removed by inductively coupled plasma etching process to form a Bragg reflection layer through hole, and then the photoresist is removed; Wherein, the Bragg reflection layer through hole includes an N-type Bragg reflection layer through hole and a P-type Bragg reflection layer through hole.

[0009] Furthermore, the specific process for preparing the first insulating layer through hole is: Applying photoresist on the surface of the Bragg reflective layer and the through hole of the Bragg reflective layer, then removing part of the photoresist in the through hole of the Bragg reflective layer by exposure and development to expose the first insulating layer under the through hole of the Bragg reflective layer, then removing the exposed first insulating layer by BOE etching solution to form the through hole of the first insulating layer, and then removing the photoresist; The first insulating layer through-holes include N-type first insulating layer through-holes and P-type first insulating layer through-holes.

[0010] Furthermore, the specific process for preparing the metal reflective layer is: A negative photoresist is coated on the P-type first insulating layer through hole, the P-type Bragg reflective layer through hole and the Bragg reflective layer, and then part of the photoresist is removed by exposure and development, and then Ag metal, Ni metal, Ti metal, Ni metal and Ti metal are sequentially evaporated by electron beam evaporation process as the metal reflective layer, and then the metal layer located above the photoresist is removed by lift-off process, and then the photoresist is removed.

[0011] Furthermore, the specific process for preparing the second insulating layer and the through hole of the second insulating layer is: Depositing Al2O3 on the metal reflective layer and the area not covered by the metal reflective layer by using an ALD process, then depositing SiO2 on the deposited Al2O3 by using a PECVD process as the second insulating layer, then coating the surface of the second insulating layer with a photoresist, then removing part of the photoresist by exposing and developing, exposing the second insulating layer under the part of the photoresist, then removing the exposed second insulating layer by using an inductively coupled plasma etching process, forming a through hole in the second insulating layer, and then removing the photoresist; The second insulating layer through-holes include N-type second insulating layer through-holes and P-type second insulating layer through-holes.

[0012] Furthermore, the specific process for preparing the metal connection layer is: A negative photoresist is coated on the second insulating layer and the surface of the through hole of the second insulating layer, and then a part of the photoresist is removed by exposure and development, and then Cr metal, Al metal, Ti metal, Cu metal, Ti metal, Ni metal, Ti metal, Ni metal and Ti metal are sequentially evaporated by an electron beam evaporation process as the metal connection layer; Wherein, the metal connection layer includes an N-type metal connection layer and a P-type metal connection layer.

[0013] Furthermore, the specific process for preparing the third insulating layer is: A layer of AlN film is deposited on the metal connection layer and the area not covered by the metal connection layer by using a CVD process to serve as the third insulating layer.

[0014] The present invention also provides a flip-chip light emitting diode chip, which is prepared by the method for preparing the flip-chip light emitting diode chip as described above.

[0015] Compared with the prior art, the present invention has the following beneficial effects: by preparing a third insulating layer on the first semiconductor layer, by preparing a heat-conducting metal layer with an area larger than that of the N-type semiconductor layer on the third insulating layer, by preparing a fourth insulating layer on the heat-conducting metal layer, the N-type heat-conducting metal layer through hole and the P-type heat-conducting metal layer through hole, the third insulating layer, the fourth insulating layer and the heat-conducting metal layer arranged between the third insulating layer and the fourth insulating layer together constitute a heat sink structure, thereby evenly distributing the heat of the flip-chip light-emitting diode chip on the heat sink structure; by setting the area of ​​the heat-conducting pad to be larger than the sum of the areas of the N-type pad and the P-type pad, And the area of ​​the thermally conductive pad is larger than half of the area of ​​the thermally conductive metal layer, thereby increasing the area of ​​the thermally conductive pad. The larger the area, the better the thermal conductivity, and the lower the operating temperature of the flip-chip LED chip. By welding the semi-finished product after completing step S9 on the bracket, part of the heat of the flip-chip LED chip can be transferred from the thermally conductive metal layer through the thermally conductive pad to the bracket with an area larger than the chip area and then to the heat dissipation metal of the bracket. Such an arrangement can further reduce the operating temperature of the flip-chip LED chip, reduce the thermal resistance of the flip-chip LED chip, and increase the service life of the flip-chip LED chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 This is a flow chart of a method for preparing a flip-chip light-emitting diode chip in Example 1 of the present invention; Figure 2 is a cross-sectional schematic diagram of a semi-finished product formed in step S9 in Example 1 of the present invention; Figure 3 is a cross-sectional schematic diagram of a flip-chip light-emitting diode chip in Embodiment 1 of the present invention; Description of main component symbols:

[0017] The following specific implementation manner will further illustrate the present invention in conjunction with the above-mentioned drawings. DETAILED DESCRIPTION

[0018] In order to facilitate the understanding of the present invention, the present invention will be described more fully below with reference to the relevant drawings. Several embodiments of the present invention are given in the drawings. However, the present invention can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present invention more thorough and comprehensive.

[0019] It should be noted that when an element is referred to as being "fixed to" another element, it may be directly on the other element or there may be a central element. When an element is considered to be "connected to" another element, it may be directly connected to the other element or there may be a central element at the same time. The terms "vertical", "horizontal", "left", "right" and similar expressions used herein are for illustrative purposes only.

[0020] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which the present invention belongs. The terms used herein in the specification of the present invention are only for the purpose of describing specific embodiments and are not intended to limit the present invention. The term "and / or" used herein includes any and all combinations of one or more of the related listed items.

[0021] Example 1 See also Figures 1 to 3 , the method for preparing a flip-chip light-emitting diode chip in an embodiment of the present invention comprises: S1, providing a substrate 10 required for growth, and sequentially depositing an N-type semiconductor layer 111, an active light-emitting layer 112, and a P-type semiconductor layer 113 on the substrate 10; Furthermore, the substrate 10 may be a GaN substrate, an Al2O3 substrate, or a Si substrate.

[0022] S2, preparing an N-type conductive through hole 114 on the P-type semiconductor layer 113; Specifically in this embodiment, the specific process for preparing the N-type conductive via 114 is: A photoresist is coated on the surface of the P-type semiconductor layer 113, and then a portion of the photoresist is removed by exposure and development processes to expose a portion of the P-type semiconductor layer. Then, an inductively coupled plasma etching process is used to remove the exposed P-type semiconductor layer and the active light-emitting layer under this portion of the P-type semiconductor to form the N-type conductive through hole 114, and then the photoresist is removed.

[0023] S3, preparing a current spreading layer 12 on the P-type semiconductor layer 113 and the N-type conductive via 114; Specifically in this embodiment, the specific process for preparing the current spreading layer 12 is: Indium tin oxide is deposited on the surface of the P-type semiconductor layer 113 and the N-type conductive via 114 by using a magnetron sputtering process, and then a photoresist is coated on the surface of the indium tin oxide. Then, part of the photoresist is removed by exposure and development to expose part of the indium tin oxide. Then, the exposed indium tin oxide is removed by an indium tin oxide etching solution, and then the photoresist is removed to form the current spreading layer 12.

[0024] S4, preparing an isolation groove 115 on the N-type conductive through hole 114 and the current spreading layer 12; Specifically in this embodiment, the specific process for preparing the isolation trench 115 is: Photoresist is coated on the surface of the N-type conductive via 114 and the current spreading layer 12, and then part of the photoresist is removed by exposure and development to expose the N-type conductive vias located around, and then the exposed N-type conductive vias are removed by ICP etching process to form the isolation groove 115, and then the photoresist is removed.

[0025] S5, preparing a first semiconductor layer on the P-type semiconductor layer 113, the N-type conductive via 114, the current spreading layer 12 and the isolation trench 115; Furthermore, the first semiconductor layer includes a first insulating layer 13, a Bragg reflective layer 14, a Bragg reflective layer through hole, a first insulating layer through hole, a metal reflective layer 15, a second insulating layer 16, a second insulating layer through hole, and a metal connecting layer, which are sequentially arranged on the P-type semiconductor layer 113.

[0026] Furthermore, the specific process for preparing the first insulating layer 13 is: SiO2 is deposited as a first insulating layer on the surface of the P-type semiconductor layer 113, the N-type conductive via 114, the current spreading layer 12 and the isolation groove 115 using a PECVD process, wherein the thickness of the first insulating layer is greater than 5000Å.

[0027] Furthermore, the specific process for preparing the Bragg reflection layer 14 and the Bragg reflection layer through hole is as follows: 2-10 groups of TiO2 and SiO2 stacked layers are deposited on the surface of the first insulating layer 13 by electron beam evaporation process as the Bragg reflection layer 14, then photoresist is coated on the surface of the Bragg reflection layer 14, and then the photoresist on part of the Bragg reflection layer is removed by exposure and development, and then the exposed Bragg reflection layer is removed by inductively coupled plasma etching process to form a Bragg reflection layer through hole, and then the photoresist is removed; The Bragg reflection layer through holes include an N-type Bragg reflection layer through hole 141 and a P-type Bragg reflection layer through hole 142 .

[0028] Furthermore, the specific process for preparing the first insulating layer through hole is: Applying photoresist on the surface of the Bragg reflection layer 14 and the through hole of the Bragg reflection layer, then removing part of the photoresist in the through hole of the Bragg reflection layer by exposure and development, exposing the first insulating layer under the through hole of the Bragg reflection layer, then removing the exposed first insulating layer by BOE etching solution, forming the through hole of the first insulating layer, and then removing the photoresist; The first insulating layer through holes include an N-type first insulating layer through hole 131 and a P-type first insulating layer through hole 132 .

[0029] Furthermore, the specific process for preparing the metal reflective layer 15 is as follows: A negative photoresist is coated on the P-type first insulating layer through hole 132, the P-type Bragg reflective layer through hole 142 and the Bragg reflective layer 14, and then a portion of the photoresist is removed by exposure and development. Then, an electron beam evaporation process is used to sequentially evaporate Ag metal, Ni metal, Ti metal, Ni metal and Ti metal as the metal reflective layer 15, and then a lift-off process is used to remove the metal layer above the photoresist, and then the photoresist is removed.

[0030] Furthermore, the specific process for preparing the second insulating layer 16 and the through hole of the second insulating layer is: Al2O3 is deposited on the metal reflective layer 15 and the area not covered by the metal reflective layer 15 by using an ALD process, and then SiO2 is deposited on the deposited Al2O3 by using a PECVD process to serve as the second insulating layer 16, and then a photoresist is coated on the surface of the second insulating layer 16, and then a part of the photoresist is removed by exposure and development to expose the second insulating layer under the part of the photoresist, and then the exposed second insulating layer is removed by an inductively coupled plasma etching process to form a through hole in the second insulating layer, and then the photoresist is removed; The second insulating layer through holes include an N-type second insulating layer through hole 161 and a P-type second insulating layer through hole 162 .

[0031] Furthermore, the specific process for preparing the metal connection layer is: A negative photoresist is coated on the surface of the second insulating layer 16 and the through hole of the second insulating layer, and then a part of the photoresist is removed by exposure and development, and then Cr metal, Al metal, Ti metal, Cu metal, Ti metal, Ni metal, Ti metal, Ni metal and Ti metal are sequentially evaporated by electron beam evaporation process as the metal connection layer; The metal connection layer includes an N-type metal connection layer 171 and a P-type metal connection layer 172 .

[0032] S6, preparing a third insulating layer 18 on the first semiconductor layer; Furthermore, the specific process for preparing the third insulating layer 18 is as follows: A layer of AlN film is deposited on the metal connection layer and the area not covered by the metal connection layer by using a CVD process to serve as the third insulating layer 18 .

[0033] S7, forming a heat-conducting metal layer 19 on the third insulating layer 18, and then forming an N-type heat-conducting metal layer through hole 191 and a P-type heat-conducting metal layer through hole 192 on the heat-conducting metal layer 19; Specifically in this embodiment, the specific process for preparing the thermally conductive metal layer 19 is: A negative photoresist is coated on the surface of the third insulating layer 18 , and then a portion of the photoresist is removed by exposure and development, and then a layer of Cu metal is evaporated by electron beam evaporation process as the thermal conductive metal layer 19 .

[0034] The thickness of the heat-conducting metal layer 19 is between 2000Å and 20000Å, and the area of ​​the heat-conducting metal layer 19 is larger than the area of ​​the N-type semiconductor layer 111; Specifically in this embodiment, the specific process for preparing the N-type thermal conductive metal layer through hole 191 and the P-type thermal conductive metal layer through hole 192 is: A photoresist is coated on the surface of the thermally conductive metal layer 19, and then a portion of the photoresist is removed by exposure and development to expose the thermally conductive metal layer under the portion of the photoresist. Then, the exposed thermally conductive metal layer is removed by an inductively coupled plasma etching process to form the N-type thermally conductive metal layer through hole 191 and the P-type thermally conductive metal layer through hole 192, and then the photoresist is removed.

[0035] S8, preparing a fourth insulating layer 20 on the thermally conductive metal layer 19, the N-type thermally conductive metal layer through hole 191, and the P-type thermally conductive metal layer through hole 192, and then preparing an N-type fourth insulating layer through hole 201, a P-type fourth insulating layer through hole 202, and a fourth insulating layer connecting through hole 203 disposed between the N-type fourth insulating layer through hole 201 and the P-type fourth insulating layer through hole 202 on the fourth insulating layer 20; Specifically in this embodiment, the specific process for preparing the fourth insulating layer is: An AlN film is deposited on the thermal conductive metal layer 19 , the N-type thermal conductive metal layer through hole 191 , and the P-type thermal conductive metal layer through hole 192 by using a CVD process to serve as the fourth insulating layer 20 .

[0036] Specifically in this embodiment, the specific process for preparing the N-type fourth insulating layer through hole 201, the P-type fourth insulating layer through hole 202 and the fourth insulating layer connecting through hole 203 is: Photoresist is coated on the surface of the fourth insulating layer 20, and then a portion of the photoresist is removed by exposure and development to expose the fourth insulating layer under the portion of the photoresist, and then the exposed fourth insulating layer is removed by an inductively coupled plasma etching process, and then the remaining photoresist is removed to form the N-type fourth insulating layer through hole 201, the P-type fourth insulating layer through hole 202, and the fourth insulating layer connecting through hole 203 arranged between the N-type fourth insulating layer through hole 201 and the P-type fourth insulating layer through hole 202.

[0037] S9, preparing a pad layer on the fourth insulating layer 20, the N-type fourth insulating layer through hole 201, the P-type fourth insulating layer through hole 202 and the fourth insulating layer connecting through hole 203, the pad layer comprising an N-type pad 211, a P-type pad 212 and a thermal conductive pad 213 located between the P-type pad 212 and the N-type pad 211; Specifically in this embodiment, the specific process for preparing the pad layer is: Negative photoresist is coated on the surface of the fourth insulating layer 20, the N-type fourth insulating layer through hole 201, the P-type fourth insulating layer through hole 202 and the fourth insulating layer connecting through hole 203, and then part of the photoresist is removed by exposure and development, and then Ti metal, Ni metal, Ti metal, Ni metal and AuSn metal are sequentially evaporated using an electron beam evaporation process, and then part of the metal is removed using a blue film stripping process to form a pad layer.

[0038] The fourth insulating layer connecting through hole 203 is used to connect the thermally conductive pad 213 and the thermally conductive metal layer 19, the area of ​​the fourth insulating layer connecting through hole 203 is larger than the area of ​​the thermally conductive pad 213, the area of ​​the thermally conductive pad 213 is larger than the sum of the areas of the N-type pad 211 and the P-type pad 212, and the area of ​​the thermally conductive pad 213 is larger than half of the area of ​​the thermally conductive metal layer 19; Specifically in this embodiment, the area of ​​the thermal conductive pad 213 is 70% of the area of ​​the thermal conductive metal layer 19 , and the area of ​​the thermal conductive pad 213 is six times the sum of the areas of the N-type pad 211 and the P-type pad 212 .

[0039] S10, using a eutectic welding process, welding the semi-finished product after step S9 onto the bracket 22; The area of ​​the bracket 22 is larger than that of the semi-finished product. A heat dissipation pad 221 and a heat dissipation metal 222 are provided on the bracket 22 . The thermal conductive pad 213 is connected to the heat dissipation pad 221 , and the heat dissipation pad 221 is connected to the heat dissipation metal 222 .

[0040] It can be understood that, by using a CVD process to deposit a layer of ALN film on the metal connection layer and the area not covered by the metal connection layer as the third insulating layer 18, by preparing a heat-conducting metal layer with a larger area than the N-type semiconductor layer on the third insulating layer, by using a CVD process to deposit an ALN ​​film on the heat-conducting metal layer 19, the N-type heat-conducting metal layer through hole 191 and the P-type heat-conducting metal layer through hole 192 as the fourth insulating layer 20, so that the third insulating layer 18, the fourth insulating layer 20 and the heat-conducting metal layer 19 disposed between the third insulating layer 18 and the fourth insulating layer 20 together constitute a heat sink structure, thereby evenly distributing the heat of the flip-chip light-emitting diode chip on the heat sink structure; by increasing the area of ​​the thermal conductive pad 213 to be larger than that of the N-type semiconductor layer, the heat-conducting metal layer 19 is formed on the heat-conducting metal layer 19, and the heat-conducting metal layer 19 is formed on the heat-conducting metal layer 19. The area of ​​the N-type pad 211 and the P-type pad 212 is set, and the area of ​​the thermally conductive pad 213 is larger than half of the area of ​​the thermally conductive metal layer 19, thereby increasing the area of ​​the thermally conductive pad 213. The larger the area, the better the thermal conductivity, and the lower the operating temperature of the flip-chip LED chip; by welding the semi-finished product after completing step S9 on the bracket 22, so that part of the heat of the flip-chip LED chip can be transferred from the thermally conductive metal layer 19 through the thermally conductive pad 213 to the bracket 22 whose area is larger than the chip area, and then to the heat dissipation metal 222 of the bracket 22. Such a setting can further reduce the operating temperature of the flip-chip LED chip, reduce the thermal resistance of the flip-chip LED chip, and increase the service life of the flip-chip LED chip.

[0041] See also Figure 3 , shown is a cross-sectional schematic diagram of a flip-chip light-emitting diode chip prepared by the method for preparing a flip-chip light-emitting diode chip in an embodiment of the present invention.

[0042] Example 2 A flip-chip light-emitting diode chip, which is different from the flip-chip light-emitting diode chip prepared in Example 1 in that: Specifically in this embodiment, the specific process for preparing the thermally conductive metal layer is: A negative photoresist is coated on the surface of the third insulating layer, and then a part of the photoresist is removed by exposure and development, and then a layer of AL metal is evaporated by electron beam evaporation process as the heat conductive metal layer.

[0043] Example 3 A flip-chip light-emitting diode chip, which is different from the flip-chip light-emitting diode chip prepared in Example 1 in that: Specifically in this embodiment, the area of ​​the thermally conductive pad is 52% of the area of ​​the thermally conductive metal layer, and the area of ​​the thermally conductive pad is twice the sum of the areas of the N-type pad and the P-type pad.

[0044] Comparative Example 1 A flip-chip light-emitting diode chip, which is different from the flip-chip light-emitting diode chip prepared in Example 1 in that: The flip-chip light-emitting diode chip in Comparative Example 1 does not include the third insulating layer, the thermally conductive metal layer, and the thermally conductive pad.

[0045] Specifically in this comparative example, the specific process for preparing the fourth insulating layer is: A layer of SiO2 film is deposited on the metal connection layer and the area not covered by the metal connection layer by using a CVD process to serve as the third insulating layer.

[0046] Based on the flip-chip light-emitting diode chips prepared in the above-mentioned embodiments 1, 2 and 3 and the flip-chip light-emitting diode chips in comparative example 1, a rapid deterioration test was performed on the flip-chip light-emitting diode chips prepared in embodiments 1, 2 and 3 and the flip-chip light-emitting diode chips in comparative example 1. The chips were first packaged on a bracket, and then placed in a closed space at 150°C, and the chips were powered on with a current of 1.5 times the rated working current of the chips. After that, the brightness of the chips was measured every 12 hours, and the brightness decay of the chips was recorded (the brightness was 100% before the start of the deterioration test until the brightness was lower than 90%). The longer the time, the better the thermal conductivity of the chips. The corresponding test results are shown in the following table: It should be noted that the chip area of ​​this test is 1300um*1300um.

[0047]

[0048] In summary, the flip-chip light-emitting diode chip and the preparation method thereof in the above-mentioned embodiments of the present invention are provided by preparing a third insulating layer on the first semiconductor layer, preparing a heat-conducting metal layer with an area larger than that of the N-type semiconductor layer on the third insulating layer, and preparing a fourth insulating layer on the heat-conducting metal layer, the N-type heat-conducting metal layer through hole, and the P-type heat-conducting metal layer through hole, so that the third insulating layer, the fourth insulating layer, and the heat-conducting metal layer arranged between the third insulating layer and the fourth insulating layer together constitute a heat sink structure, thereby evenly distributing the heat of the flip-chip light-emitting diode chip on the heat sink structure; by making the area of ​​the heat-conducting pad larger than that of the N-type pad and the P-type pad, The sum of the products is set, and the area of ​​the thermally conductive pad is larger than half of the area of ​​the thermally conductive metal layer, thereby increasing the area of ​​the thermally conductive pad. The larger the area, the better the thermal conductivity, and the lower the operating temperature of the flip-chip light-emitting diode chip; by welding the semi-finished product after completing step S9 on the bracket, so that part of the heat of the flip-chip light-emitting diode chip can be transferred from the thermally conductive metal layer through the thermally conductive pad to the bracket with an area larger than the chip area and then to the heat dissipation metal of the bracket, such a setting can further reduce the operating temperature of the flip-chip light-emitting diode chip, reduce the thermal resistance of the flip-chip light-emitting diode chip, and increase the service life of the flip-chip light-emitting diode chip.

[0049] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "examples", "specific examples", or "some examples" means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner.

[0050] The above-mentioned embodiments only express several implementation methods of the present invention, and the description thereof is relatively specific and detailed, but it cannot be understood as limiting the scope of the patent of the present invention. It should be pointed out that, for ordinary technicians in this field, several variations and improvements can be made without departing from the concept of the present invention, which all belong to the protection scope of the present invention. Therefore, the protection scope of the patent of the present invention shall be subject to the attached claims.

Claims

1. A method for preparing a flip-chip light-emitting diode chip, characterized in that: The preparation method comprises: S1, providing a substrate required for growth, and sequentially depositing an N-type semiconductor layer, an active light-emitting layer, and a P-type semiconductor layer on the substrate; S2, preparing an N-type conductive through hole on the P-type semiconductor; S3, preparing a current spreading layer on the P-type semiconductor layer and the N-type conductive through hole; S4, preparing an isolation groove on the N-type conductive through hole and the current spreading layer; S5, preparing a first semiconductor layer on the P-type semiconductor layer, the N-type conductive via, the current spreading layer and the isolation trench; S6, preparing a third insulating layer on the first semiconductor layer; S7, preparing a thermally conductive metal layer on the third insulating layer, and then preparing an N-type thermally conductive metal layer through hole and a P-type thermally conductive metal layer through hole on the thermally conductive metal layer; Wherein, the thickness of the thermally conductive metal layer is between 2000Å and 20000Å, and the area of ​​the thermally conductive metal layer is larger than the area of ​​the N-type semiconductor layer; S8, preparing a fourth insulating layer on the thermally conductive metal layer, the N-type thermally conductive metal layer through hole, and the P-type thermally conductive metal layer through hole, and then preparing an N-type fourth insulating layer through hole, a P-type fourth insulating layer through hole, and a fourth insulating layer connecting through hole disposed between the N-type fourth insulating layer through hole and the P-type fourth insulating layer through hole on the fourth insulating layer; S9, preparing a pad layer on the fourth insulating layer, the N-type fourth insulating layer through hole, the P-type fourth insulating layer through hole, and the fourth insulating layer connecting through hole, the pad layer comprising an N-type pad, a P-type pad, and a thermally conductive pad located between the P-type pad and the N-type pad; The fourth insulating layer connecting through hole is used to connect the thermally conductive pad and the thermally conductive metal layer, the area of ​​the fourth insulating layer connecting through hole is larger than the area of ​​the thermally conductive pad, the area of ​​the thermally conductive pad is larger than the sum of the areas of the N-type pad and the P-type pad, and the area of ​​the thermally conductive pad is larger than half the area of ​​the thermally conductive metal layer; S10, welding the semi-finished product after step S9 onto the bracket using a eutectic welding process; The support has an area larger than that of the semi-finished product, a heat dissipation pad and a heat dissipation metal are arranged on the support, the thermal conductive pad is connected to the heat dissipation pad, and the heat dissipation pad is connected to the heat dissipation metal.

2. The method for preparing a flip-chip light-emitting diode chip according to claim 1, characterized in that: The first semiconductor layer includes a first insulating layer, a Bragg reflection layer, a Bragg reflection layer through hole, a first insulating layer through hole, a metal reflection layer, a second insulating layer, a second insulating layer through hole, and a metal connection layer which are sequentially arranged on the P-type semiconductor layer.

3. The method for preparing a flip-chip light emitting diode chip according to claim 2, characterized in that: The specific process for preparing the first insulating layer is: SiO2 is deposited as a first insulating layer on the surface of the P-type semiconductor layer, the N-type conductive via, the current spreading layer and the isolation groove using a PECVD process, wherein the thickness of the first insulating layer is greater than 5000Å.

4. The method for preparing a flip-chip light emitting diode chip according to claim 3, characterized in that: The specific process of preparing the Bragg reflection layer and the Bragg reflection layer through hole is as follows: 2-10 groups of TiO2 and SiO2 stacks are deposited on the surface of the first insulating layer by electron beam evaporation process as a Bragg reflection layer, then photoresist is coated on the surface of the Bragg reflection layer, and then the photoresist on a part of the Bragg reflection layer is removed by exposure and development, and then the exposed Bragg reflection layer is removed by inductively coupled plasma etching process to form a Bragg reflection layer through hole, and then the photoresist is removed; Wherein, the Bragg reflection layer through hole includes an N-type Bragg reflection layer through hole and a P-type Bragg reflection layer through hole.

5. The method for preparing a flip-chip light emitting diode chip according to claim 3, characterized in that: The specific process of preparing the first insulating layer through hole is: Applying photoresist on the surface of the Bragg reflective layer and the through hole of the Bragg reflective layer, then removing part of the photoresist in the through hole of the Bragg reflective layer by exposure and development to expose the first insulating layer under the through hole of the Bragg reflective layer, then removing the exposed first insulating layer by BOE etching solution to form the through hole of the first insulating layer, and then removing the photoresist; The first insulating layer through-holes include N-type first insulating layer through-holes and P-type first insulating layer through-holes.

6. The method for preparing a flip-chip light emitting diode chip according to claim 5, characterized in that: The specific process for preparing the metal reflective layer is: A negative photoresist is coated on the P-type first insulating layer through hole, the P-type Bragg reflective layer through hole and the Bragg reflective layer, and then part of the photoresist is removed by exposure and development, and then Ag metal, Ni metal, Ti metal, Ni metal and Ti metal are sequentially evaporated by electron beam evaporation process as the metal reflective layer, and then the metal layer located above the photoresist is removed by lift-off process, and then the photoresist is removed.

7. The method for preparing a flip-chip light emitting diode chip according to claim 6, characterized in that: The specific process of preparing the second insulating layer and the through hole of the second insulating layer is: Depositing Al2O3 on the metal reflective layer and the area not covered by the metal reflective layer by using an ALD process, then depositing SiO2 on the deposited Al2O3 by using a PECVD process as the second insulating layer, then coating the surface of the second insulating layer with a photoresist, then removing part of the photoresist by exposing and developing, exposing the second insulating layer under the part of the photoresist, then removing the exposed second insulating layer by using an inductively coupled plasma etching process, forming a through hole in the second insulating layer, and then removing the photoresist; The second insulating layer through-holes include N-type second insulating layer through-holes and P-type second insulating layer through-holes.

8. The method for preparing a flip-chip light emitting diode chip according to claim 7, characterized in that: The specific process for preparing the metal connection layer is: A negative photoresist is coated on the second insulating layer and the surface of the through hole of the second insulating layer, and then a part of the photoresist is removed by exposure and development, and then Cr metal, Al metal, Ti metal, Cu metal, Ti metal, Ni metal, Ti metal, Ni metal and Ti metal are sequentially evaporated by an electron beam evaporation process as the metal connection layer; Wherein, the metal connection layer includes an N-type metal connection layer and a P-type metal connection layer.

9. The method for preparing a flip-chip light emitting diode chip according to claim 8, characterized in that: The specific process for preparing the third insulating layer is: A layer of AlN film is deposited on the metal connection layer and the area not covered by the metal connection layer by using a CVD process to serve as the third insulating layer.

10. A flip-chip light emitting diode chip, characterized in that: The flip-chip light-emitting diode chip is prepared by the method for preparing the flip-chip light-emitting diode chip according to any one of claims 1 to 9.

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