Semiconductor package

Abstract

A semiconductor package according to an embodiment includes an insulating layer; a pad portion provided on the insulating layer; and a protective layer disposed on the insulating layer and including an opening region overlapping the pad portion in a vertical direction, in which a width of the opening region of the protective layer in a horizontal direction satisfies a range of 10 [mu] m to 30 [mu] m, and the surface roughness of the upper surface of the protective layer is different from the surface roughness of the inner surface of the opening area of the protective layer.

Description

Technical Field

[0001] Embodiments relate to a circuit board and a semiconductor package including the same. Background Art

[0002] Generally, a printed circuit board (PCB) is a stacked structure in which insulating layers and conductor layers are alternately stacked, and the conductor layers may be formed into a circuit pattern by patterning.

[0003] Printed circuit boards such as this are provided with a solder resist (SR) which protects the circuits formed on the outermost sides of the laminated structure, prevents oxidation of the conductor layer, and also serves as an insulator when electrically connecting to a chip or other substrate mounted on the printed circuit board.

[0004] Typically, solder resist forms an opening area (SRO (Solder Resist Opening): solder resist opening), which becomes an electrical connection path by combining a connection means such as solder or bump. In addition, as the performance and density of printed circuit boards become higher, I / O (input / output) performance continues to improve, requiring a larger number of opening areas for the solder resist, and therefore requiring a smaller bump pitch of the opening area. Here, the bump pitch of the opening area refers to the distance between the centers of adjacent opening areas.

[0005] Meanwhile, the solder resist opening area (SRO) includes an SMD (Solder Mask Defined type) type and an NSMD (Non-Solder Mask Defined Type) type.

[0006] The SMD type is characterized in that the width of an open region (SRO) is smaller than the width of a pad exposed through the open region (SRO), and thus at least a portion of an upper surface of the pad of the SMD type is covered with a solder resist.

[0007] In addition, the NSMD type is characterized in that the width of the open area (SRO) is greater than the width of the pad exposed through the open area (SRO). Therefore, in the NSMD type, the solder resist is disposed at a certain distance from the pad so that both the upper surface and the side surface of the pad are exposed.

[0008] However, in the case of the SMD type, after combining the semiconductor package with the main board, when performing a solder ball bonding reliability test for the bonding strength of the solder balls, there is a problem that the solder balls are separated from the pads exposed through the opening area (SRO). In addition, in the case of the NSMD type, there is a problem that the pads on which the solder balls are provided are separated from the circuit board. Therefore, conventionally, the SMD type and the NSMD type are appropriately combined and applied to one circuit board.

[0009] However, in the case of a circuit board including an opening area (SRO) of a conventional SMD type and NSMD type, there is a problem that during the process of exposing the solder resist layer, light cannot be sufficiently transmitted to the lower area of ​​the exposure area of ​​the solder resist layer, and therefore, the lower area of ​​the exposure area cannot be sufficiently cured. In addition, when a development process is performed in a state where the lower area of ​​the exposure area is not sufficiently cured, there is a problem of undercutting that occurs in which the lower area of ​​the exposure area is removed together. In addition, as the thickness of the solder resist layer increases, the width of the undercut increases, and therefore, there is a problem of reduced reliability of the circuit board.

[0010] In addition, when the solder mask is exposed to form an opening area, the size of the opening area is determined according to the exposure resolution of the solder mask. However, the size of the opening area that can be formed in the solder mask is about 70μm for general resolution and up to 50μm for high resolution.

[0011] However, due to the advancement of technology, the amount of data processing is rapidly increasing. For this reason, the number of terminals of semiconductor devices installed in semiconductor packages is increasing. Therefore, a new structure is needed that can reduce the size of the opening area formed on the solder resist layer while eliminating undercuts. Summary of the invention

[0012]

Technical issues

[0013] Embodiments provide a circuit board capable of reducing the size of an opening area formed in a protection layer and a semiconductor package including the same.

[0014] Furthermore, the embodiment provides a circuit board capable of eliminating an undercut formed at a side wall of an opening region of a protection layer and a semiconductor package including the same.

[0015] Furthermore, the embodiment provides a circuit board capable of reducing a tolerance (SRR) between a center of an opening region of a protection layer and a center of a pad, and a semiconductor package including the same.

[0016] Furthermore, the embodiments provide a circuit board having improved electrical and mechanical characteristics and a semiconductor package including the same.

[0017] Furthermore, the embodiment provides a circuit board capable of improving bonding strength with a molding layer and a semiconductor package including the same.

[0018] The technical problems to be solved by the proposed embodiments are not limited to the above-mentioned technical problems, and those skilled in the art may clearly understand other technical problems not mentioned through the embodiments proposed in the following description.

[0019]

Technical solution

[0020] According to one embodiment, a semiconductor package includes an insulating layer; a pad portion arranged on the insulating layer; and a protective layer, which is arranged on the insulating layer and includes an opening area overlapping the pad portion in a vertical direction, wherein a width of the opening area of ​​the protective layer in a horizontal direction satisfies a range of 10 μm to 30 μm, and a surface roughness of an upper surface of the protective layer is different from a surface roughness of an inner surface of the opening area of ​​the protective layer.

[0021] Furthermore, the surface roughness of the upper surface of the protective layer is greater than the surface roughness of the inner surface of the opening region of the protective layer.

[0022] Furthermore, the protective layer includes a resin and a plurality of fillers dispersed in the resin, and at least one of the plurality of fillers is exposed through an upper surface of the protective layer.

[0023] Furthermore, the pad portion includes a first pad, and the opening region includes a first opening region partially overlapping the first pad in a vertical direction, and a width of the first opening region is smaller than a width of the first pad.

[0024] Furthermore, the pads include a second pad, and the opening region includes a second opening region completely overlapping the second pad in a vertical direction, and a width of the second opening region is greater than a width of the second pad.

[0025] Furthermore, an inner surface of the opening region has a slope in which a width of the opening region decreases from an upper surface of the protective layer toward a lower surface of the protective layer.

[0026] Furthermore, an inner surface of the opening region has a slope in which a width of the opening region increases from an upper surface of the protective layer toward a lower surface of the protective layer.

[0027] Furthermore, the difference between the maximum width and the minimum width in the horizontal direction along the thickness direction of the opening region is 3 μm or less.

[0028] Furthermore, the center of the opening region and the center of the pad portion are offset in the vertical direction.

[0029] Furthermore, the width between the center of the opening region and the center of the pad portion in the horizontal direction is 10 μm or less.

[0030]

Beneficial Effects

[0031] An embodiment includes an insulating layer, a pad disposed on the insulating layer, and a protective layer disposed on the insulating layer, and the protective layer includes an opening area overlapping the pad in a vertical direction.

[0032] In this case, the width of the opening region of the protective layer of the embodiment is 30 μm or less. For example, the width of the opening region of the protective layer of the embodiment may satisfy the range of 10 μm to 30 μm, 12 μm to 28 μm, or 13 μm to 25 μm.

[0033] In addition, the width of the opening area of ​​the protective layer of the embodiment changes little along the thickness direction. For example, in the entire area of ​​the opening area of ​​the embodiment in the thickness direction, the difference in width between the area with the maximum width and the area with the minimum width can be 3μm or less, 2.5μm or less, 2μm or less, 1.5μm or less, 1μm or less, or 0.5μm or less. That is, in the embodiment, the undercut of the inner surface of the opening area of ​​the protective layer at the lower end can be eliminated, or the horizontal distance of the undercut can be significantly reduced compared with the comparative example.

[0034] This is because the opening area of ​​the protective layer is not formed by exposing and developing the protective layer, but a separate resist pattern is used. That is, in an embodiment, the protective layer is set in a state where the resist pattern is formed using a photosensitive film. Therefore, an opening area corresponding to the resist pattern can be formed in the protective layer. In this case, the photosensitive film does not contain a filler. Therefore, generally, the minimum size of the resist pattern formed by exposing and developing the photosensitive film is smaller than the minimum size of the resist pattern formed by exposing and developing the solder resist containing the filler.

[0035] Therefore, the present invention does not expose and develop the protective layer (such as solder resist), but exposes and develops the photosensitive film that can achieve a relatively fine pattern to form an anti-etching pattern. Then the embodiment uses the anti-etching pattern to form an opening area in the protective layer. Therefore, compared with the comparative example, the embodiment can reduce the size of the opening area formed on the protective layer, thereby improving the circuit integration.

[0036] In addition, since the embodiment does not expose and develop the protective layer, undercuts that may be formed at the inner surface of the opening region of the protective layer can be eliminated. Therefore, the embodiment can further reduce the spacing between the circuit pattern layers.

[0037] Meanwhile, in an embodiment, in a case where an anti-etching pattern is provided, the thickness of the protective layer is made greater than the thickness of the anti-etching pattern, and then a thinning process of the protective layer is performed. That is, in an embodiment, the protective layer may have a target thickness by thinning. In this case, the application process of the protective layer may also be performed without performing a thinning process to make it have a target thickness. However, if the thinning process is not performed, there is a problem of an increased thickness deviation of the protective layer, resulting in a decrease in the flatness of the protective layer.

[0038] On the other hand, since the embodiment performs a thinning process, the flatness of the protection layer can be improved. Therefore, the embodiment can improve the overall physical reliability and electrical reliability of the circuit board and the semiconductor package.

[0039] In addition, the filler can be completely exposed on the upper surface of the protective layer of the embodiment. In addition, the exposed filler increases the surface roughness of the upper surface of the protective layer. Therefore, in the molding process after the semiconductor device is mounted on the circuit board, the present invention can increase the bonding area between the protective layer and the molding layer, thereby improving the bonding strength. Therefore, the embodiment can further improve product reliability.

[0040] Meanwhile, in the embodiment, since the protective layer is not exposed and developed, a photoinitiator is not required in the protective layer. For example, a general solder resist contains a photoinitiator for exposure and development. In this case, the photoinitiator is a factor that deteriorates the physical and electrical properties of the circuit board. In this case, the embodiment can improve the physical and electrical properties of the circuit board because the photoinitiator is not included in the protective layer.

[0041] Furthermore, since the embodiment does not include a photoinitiator in the protective layer, the types of insulating layers that can be used as the protective layer can be expanded, and thus the unit cost required for developing the protective layer can be reduced.

[0042] In addition, compared with the comparative example, the embodiment can significantly reduce the tolerance between the center of the opening area of ​​the protection layer and the center of the pad. Therefore, the embodiment can improve the mounting performance of the semiconductor device, thereby improving the physical reliability and electrical reliability of the circuit board and the semiconductor package. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] Figure 1 is a cross-sectional view showing a circuit board according to a comparative example.

[0044] Figure 2 is a cross-sectional view showing a circuit board according to the first embodiment.

[0045] Figure 3 is shown in more detail Figure 2 A cross-sectional view of a circuit pattern layer.

[0046] Figure 4 It is shown Figure 3 Scanning electron microscope image of the upper surface of the first protective layer.

[0047] Figure 5 It is shown Figure 3 Scanning electron microscope image of the sidewalls of the opening area of ​​the first protective layer.

[0048] Figure 6 : is a view showing a resist pattern for forming an opening region of the first protective layer of the present invention.

[0049] Figure 7 It is a plan view explaining the tolerance (SRR (Solder Resist Registration)) according to the comparative example.

[0050] Figure 8 2 is a view for explaining the tolerance according to the first embodiment.

[0051] Fig. 9 is a cross-sectional view showing a circuit board according to a second embodiment.

[0052] Fig.10 is a cross-sectional view showing a circuit board according to a third embodiment.

[0053] Fig.11 is a cross-sectional view showing a semiconductor package according to an embodiment.

[0054] Figures 12 to 19 are cross-sectional views showing a method for manufacturing a circuit board according to an embodiment in process order. DETAILED DESCRIPTION

[0055] Hereinafter, the embodiments disclosed in this specification will be described in detail with reference to the accompanying drawings, but regardless of the figure numbers, the same or similar components are represented by the same figure numerals, and their repeated descriptions will be omitted. The component suffixes "module" and "component" used in the following description are given or mixed together only for the convenience of writing the specification, and they themselves do not have meanings or functions that distinguish each other. In addition, when describing the embodiments disclosed in this specification, when it is determined that the detailed description of the relevant known technology will unnecessarily obscure the main purpose of the embodiments disclosed in this specification, its detailed description will be omitted. In addition, the drawings are only for the convenience of understanding the embodiments disclosed in this specification, and the technical scope disclosed in this specification is not limited by the drawings, and should be understood to include all modifications, equivalent technical solutions and alternative technical solutions that fall within the spirit and scope of the present invention.

[0056] It should be understood that although the terms “first”, “second”, etc. are used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another.

[0057] It should be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element or there can be intervening elements. However, when an element is referred to as being "directly connected" or "directly coupled" to another element, there are no intervening elements. Other words used to describe the relationship between elements (i.e., "between" versus "directly between," "adjacent" versus "directly adjacent," etc.) should be interpreted in a similar manner.

[0058] As used herein, the singular forms “a”, “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise.

[0059] It should be further understood that the terms “include” and / or “comprises” used herein specify the existence of the described features, integers, steps, operations, elements and / or components, but do not exclude the existence or addition of one or more other features, integers, steps, operations, elements, components and / or combinations thereof.

[0060] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

[0061] -Comparative Example-

[0062] Before explaining the embodiment of the present invention, the problem of the comparative example will be explained.

[0063] Figure 1 is a cross-sectional view of a circuit board according to a comparative example.

[0064] Reference Figure 1 The circuit board of the comparative example includes an insulating layer 10 , a circuit pattern layer and a protective layer 30 .

[0065] The circuit pattern layer is disposed on the upper surface of the insulating layer 10 .

[0066] The circuit pattern layer includes a plurality of circuit patterns spaced apart from each other. The circuit patterns include pads and traces.

[0067] For example, the circuit pattern layer includes a first pad 21 , a second pad 22 , and a trace 23 .

[0068] The protection layer 30 includes a plurality of opening areas.

[0069] For example, the protection layer 30 includes a first opening region 31 vertically overlapping the first pad 21 .

[0070] The first opening region 31 partially opens the upper surface of the first pad 21. For example, the first opening region 31 is an SMD type opening region.

[0071] Depending on the exposure resolution (e.g., high resolution) of the protective layer 30, the width (w1) of the first opening region 31 exceeds at least 50 μm. Specifically, depending on the exposure resolution (e.g., general resolution) of the protective layer 30, the width (w1) of the first opening region 31 exceeds at least 70 μm. Therefore, the width of the first pad 21 vertically overlapping the first opening region 31 exceeds 70 μm, which is greater than the width (w1) of the first opening region 31. For example, the width of the first pad 21 exceeds 90 μm, which is greater than the width (w1) of the first opening region 31. This takes into account the process deviation in the process of forming the first opening region 31.

[0072] As described above, the first opening region 31 is at least 50 μm or greater than 70 μm, and therefore, the width of the first pad 21 is greater than 70 μm or greater than 90 μm. Therefore, the comparative example has a limitation in reducing the spacing between the plurality of first pads. That is, the comparative example has a limitation in miniaturizing the width (w1) of the first opening region 31, and also has a limitation in miniaturizing the width of the first pad 21.

[0073] The protection layer 30 includes a second opening region 32 vertically overlapping the second pad 22. The second opening region 32 completely opens the upper surface of the second pad 22. That is, the second opening region 32 is a NSMD type opening region.

[0074] The width (w2) of the second opening region 32 exceeds 50 μm or 70 μm depending on the exposure resolution of the protective layer 30 . That is, the protective layer 30 has a limitation in minimizing the width (w2) of the second opening region 32 .

[0075] In addition, the protective layer 30 forms the first opening region 31 and the second opening region 32 by performing exposure and curing processes. At this time, there is a problem that the lower region of the protective layer 30 is not completely cured in the process of exposing and curing the protective layer 30. In addition, if curing is not completely performed, in the process of forming the second opening region 32, there is a problem that an undercut 33 is formed at the lower region of the side wall of the second opening region 32.

[0076] At this time, the horizontal distance (w3) of the undercut 33 of the comparative example exceeds 15 μm or 20 μm. The horizontal distance (w3) of the undercut 33 refers to the horizontal distance from the innermost end to the outermost end in the lower region of the sidewall of the second opening region 32 .

[0077] At this time, the circuit pattern layer includes a trace 23 disposed adjacent to the second pad 22. In addition, when the trace 23 is disposed, the comparative example must consider the horizontal distance (w3) of the undercut 33. That is, if the comparative example does not consider the horizontal distance (w3) of the undercut 33, one side of the trace 23 will be exposed by the undercut 33. In this case, the solder ball disposed on the second pad 22 diffuses to the undercut 33, and therefore, a circuit short circuit problem due to contact with the trace 23 may occur. Therefore, in the comparative example, the distance between the second pad 22 and the trace 23 is determined by considering the width (w2) of the second opening area 32 and the horizontal distance (w3) of the undercut 33. Therefore, the comparative example has a problem that the distance increases and the circuit integration is correspondingly reduced.

[0078] In addition, as the performance of electrical / electronic products has been improved recently, a technology for attaching a large number of semiconductor devices to a substrate of a limited size has been studied, and therefore, miniaturization of circuit patterns is required. In the case of a semiconductor package using the circuit board of the comparative example, the minimum width of the opening area that can be formed in the protective layer 30 and the horizontal distance of the undercut must be considered, and therefore, there is a limit to the miniaturization of the circuit pattern.

[0079] In addition, recently, the number of functions processed in a logic chip such as an application processor (AP) has increased. Therefore, it has become difficult to implement all functions in one logic chip. Therefore, a space for mounting multiple logic chips is required on a circuit board. However, it is difficult to mount multiple logic chips with different functions in a limited space using a circuit board of a comparative example.

[0080] The embodiment aims to solve this problem and significantly reduce the width of the opening area formed in the protective layer compared to the comparative example. In addition, the embodiment minimizes the horizontal distance of the undercut formed at the side wall of the opening area of ​​the protective layer, or eliminates the undercut. In addition, the embodiment can reduce the tolerance (SRR: solder resist registration) between the center of the opening area of ​​the protective layer and the center of the pad. In addition, the present invention can improve electrical and mechanical characteristics while improving the bonding strength with the molding layer.

[0081] -Electronic equipment-

[0082] Before describing the embodiments, an electronic device including a semiconductor package of the embodiments will be briefly described. The electronic device includes a mainboard (not shown). The mainboard can be physically and / or electrically connected to various components. For example, the mainboard can be connected to the semiconductor package of the embodiments. Various semiconductor devices can be installed in the semiconductor package.

[0083] Semiconductor devices may include active devices and / or passive devices. Active devices may be semiconductor chips in the form of integrated circuits (ICs), in which hundreds to millions of devices are integrated into one chip. Semiconductor chips may be logic chips, memory chips, etc. Logic chips may be central processing units (CPUs), graphics processing units (GPUs), etc. For example, a logic chip may be an AP, which includes at least one of a central processing unit (CPU), a graphics processing unit (GPU), a digital signal processor, an encryption processor, a microprocessor, a microcontroller, an analog-to-digital converter, an application-specific IC (ASIC), or a chipset including a specific combination of the above chips.

[0084] The memory chip may be a stacked memory, such as HBM. In addition, the memory chip may include a memory chip such as a volatile memory (eg, DRAM), a non-volatile memory (eg, ROM), a flash memory, and the like.

[0085] Meanwhile, a product group of a semiconductor package to which the embodiment is applied may be any one of CSP (Chip Scale Package), FC-CSP (Flip Chip-Chip Scale Package), FC-BGA (Flip Chip Ball Grid Array), POP (Package On Package), and SIP (System In Package), but is not limited thereto.

[0086] In addition, the electronic device may be a smart phone, a personal digital assistant, a digital video camera, a digital camera, a network system, a computer, a monitor, a tablet computer, a laptop computer, a netbook, a television, a video game console, a smart watch, a car, etc. However, the present invention is not limited thereto and may be any other electronic device that processes data.

[0087] -Circuit Boards-

[0088] Hereinafter, a circuit board of one embodiment will be described.

[0089] A circuit board refers to a board before semiconductor devices or chips are mounted.

[0090] Figure 2 is a cross-sectional view showing a circuit board according to a first embodiment, Figure 3 is shown in more detail Figure 2 A cross-sectional view of the circuit pattern layer, Figure 4 It is shown Figure 3 Scanning electron microscope image of the upper surface of the first protective layer, Figure 5 It is shown Figure 3 A scanning electron microscope image of the side wall of the opening region of the first protective layer, and Figure 6 : is a view showing a resist pattern for forming an opening region of a first protective layer according to an embodiment.

[0091] In the following, reference will be made to Figures 2 to 6 The circuit board according to the first embodiment will be described in detail.

[0092] The circuit board of the first embodiment provides a mounting space in which at least one semiconductor device can be mounted.

[0093] For example, the circuit board of the first embodiment may provide a mounting space for mounting one semiconductor device, or alternatively, may provide a plurality of mounting spaces for mounting two or more semiconductor devices.

[0094] In addition, one logic chip may be mounted on the circuit board of the first embodiment. In addition, the circuit board of the first embodiment may be mounted with at least two different types of logic chips. In addition, the circuit board of the first embodiment may be mounted with at least one logic chip and at least one memory chip.

[0095] The circuit board 100 of the first embodiment includes an insulating layer 110. The insulating layer 110 may have one or more layers. The insulating layer 110 preferably has a multilayer structure. In this case, the insulating layer 110 is shown in the figure as being composed of one layer, but is not limited thereto. For example, the insulating layer 110 may include a plurality of insulating layers having a vertically stacked structure.

[0096] Hereinafter, for convenience of explanation, the insulating layer 110 is shown as one layer.

[0097] The insulating layer 110 may be rigid or flexible.

[0098] For example, the insulating layer 110 may include a prepreg. For example, the insulating layer 110 may be a prepreg in which glass fibers are impregnated in a resin. The resin may be an epoxy resin, but is not limited thereto.

[0099] In addition, the insulating layer 110 may include chemically strengthened / semi-strengthened glass, such as soda-lime glass or aluminosilicate glass. For example, the insulating layer 110 may include strengthened or flexible plastics, such as polyimide (PI), polyethylene terephthalate (PET), propylene glycol (PPG), or polycarbonate (PC). For example, the insulating layer 110 may include sapphire. For example, the insulating layer 110 may include an optically isotropic film. For example, the insulating layer 110 may include COC (cyclic olefin copolymer), COP (cyclic olefin polymer), optically isotropic polycarbonate (PC), or optically isotropic polymethyl methacrylate (PMMA). For example, the insulating layer 110 may be formed of a material containing an inorganic filler and an insulating resin. For example, the insulating layer 110 may have a structure in which an inorganic filler such as silicon dioxide or aluminum oxide is disposed in a thermosetting resin or a thermoplastic resin. For example, the insulating layer 110 may use ABF (Ajinomoto stacked film), FR-4, BT (bismaleimide triazine), PID (photosensitive imaging dielectric resin), BT, etc. For example, the insulating layer 110 may include RCC (resin coated copper).

[0100] The thickness of the insulating layer 110 may be in the range of 10 μm to 60 μm. For example, when the insulating layer 110 includes a plurality of layers, the thickness of each of the plurality of layers may satisfy the range of 10 μm to 60 μm. Preferably, the thickness of the insulating layer 110 may satisfy the range of 15 μm to 55 μm. More preferably, the thickness of the insulating layer 110 may satisfy the range of 18 μm to 52 μm.

[0101] The thickness of the insulating layer 110 may represent a vertical distance between a plurality of circuit pattern layers disposed adjacent to each other in a thickness direction. For example, the thickness of the insulating layer 110 may represent a vertical distance between a first circuit pattern layer and a second circuit pattern layer 130. For example, the thickness of the insulating layer 110 may represent a vertical distance between a lower surface of the first circuit pattern layer 120 and an upper surface of the second circuit pattern layer 130.

[0102] If the thickness of the insulating layer 110 is less than 10 μm, the warpage characteristics of the circuit board 100 may be deteriorated. For example, if the thickness of the insulating layer 110 is less than 10 μm, the first circuit pattern layer 120 and the second circuit pattern layer 130 disposed on the surface of the insulating layer 110 cannot be stably protected, and therefore, electrical reliability and / or physical reliability problems may occur. In addition, if the thickness of the insulating layer 110 is less than 10 μm, processability in a process of forming the first circuit pattern layer 120 or the second circuit pattern layer 130 on the insulating layer 110 may be deteriorated.

[0103] In addition, if the thickness of the insulating layer 110 exceeds 60 μm, the total thickness of the circuit board 100 may increase, and thus the thickness of the semiconductor package may increase. In addition, if the thickness of the insulating layer 110 exceeds 60 μm, it may be difficult to miniaturize the first circuit pattern layer and / or the second circuit pattern layer 130. For example, if the thickness of the insulating layer 110 exceeds 60 μm, it may be difficult to form the width of the first circuit pattern layer and / or the second circuit pattern layer 130 and the spacing between adjacent patterns to 12 μm or less, 10 μm or less, 8 μm or less, or 6 μm or less. In addition, if it is difficult to miniaturize the first circuit pattern layer and / or the second circuit pattern layer 130, the circuit integration degree will be reduced, and therefore, the signal transmission distance may increase, which may increase the signal transmission loss.

[0104] The circuit board 100 of the first embodiment includes a circuit pattern layer provided on an insulating layer 110 .

[0105] For example, the circuit board 100 of the first embodiment includes the first circuit pattern layer 120 disposed on the upper surface of the insulating layer 110. In addition, the circuit board 100 includes the second circuit pattern layer 130 disposed on the lower surface of the insulating layer 110.

[0106] The first circuit pattern layer 120 may be divided into a plurality of circuit patterns according to position or function. For example, the first circuit pattern layer 120 may include a first pad 120-1 and a second pad 120-2. At least one of the first pad 120-1 and the second pad 120-2 may be formed to correspond to a mounting area of ​​a semiconductor device. For example, at least one of the first pad 120-1 and the second pad 120-2 may represent a mounting pad connected to a terminal of a semiconductor device. Alternatively, at least one of the first pad 120-1 and the second pad 120-2 may also refer to a terminal pad coupled to an external substrate. For example, at least one of the first pad 120-1 and the second pad 120-2 may represent a terminal pad coupled to an interposer or a mainboard of an electronic device.

[0107] At this time, as the functions provided by semiconductor devices increase recently, the number of terminals provided in the semiconductor devices or the number of semiconductor devices mounted increases.

[0108] Therefore, the first pad 120-1 and the second pad 120-2 of the first circuit pattern layer 120 need to be miniaturized. However, in the comparative example, due to the size limitation of the opening area and the undercut of the protective layer, there are limitations in miniaturizing the first circuit pattern layer 120. At this time, the embodiment minimizes the size of the opening area of ​​the protective layer and the horizontal distance of the undercut, so that the first circuit pattern layer 120 can be miniaturized. This can be achieved by the method of forming the opening area in the protective layer described below.

[0109] Meanwhile, when the insulating layer 110 of the circuit board 100 includes a plurality of layers, the first circuit pattern layer 120 may be disposed on an upper surface of an insulating layer disposed at an uppermost side among the plurality of layers of the insulating layer 110, and the second circuit pattern layer 130 may be disposed on a lower surface of an insulating layer disposed at a lowermost side among the plurality of layers of the insulating layer 110. For example, the first circuit pattern layer 120 and the second circuit pattern layer 130 may refer to outer circuit pattern layers, but are not limited thereto.

[0110] Meanwhile, when the insulating layer 110 includes a plurality of layers, an additional internal circuit pattern layer may be disposed between the plurality of layers.

[0111] The first circuit pattern layer 120 and the second circuit pattern layer 130 may each have a multi-layer structure.

[0112] The first circuit pattern layer 120 may include a first metal layer 121 and a second metal layer 122. That is, each of the first pad 120-1 and the second pad 120-2 of the first circuit pattern layer 120 may include the first metal layer 121 and the second metal layer 122.

[0113] The first metal layer 121 of the first circuit pattern layer 120 may be disposed on the upper surface of the insulating layer 110. For example, the first metal layer 121 of the first circuit pattern layer 120 may protrude above the upper surface of the insulating layer 110.

[0114] The first metal layer 121 of the first circuit pattern layer 120 may be formed by chemical plating. For example, the first metal layer 121 may be formed by chemical copper plating, but is not limited thereto. For example, the first metal layer 121 may also be formed by sputtering.

[0115] The thickness of the first metal layer 121 of the first circuit pattern layer 120 may satisfy the range of 0.2 μm to 3.0 μm. Preferably, the thickness of the first metal layer 121 of the first circuit pattern layer 120 may satisfy the range of 0.3 μm to 2.8 μm. More preferably, the thickness of the first metal layer 121 of the first circuit pattern layer 120 may satisfy the range of 0.5 μm to 2.5 μm.

[0116] If the thickness of the first metal layer 121 of the first circuit pattern layer 120 is less than 0.2 μm, the first metal layer 121 of the first circuit pattern layer 120 may not function as a seed layer. If the thickness of the first metal layer 121 of the first circuit pattern layer 120 is less than 0.2 μm, it may be difficult to form the first metal layer 121 having a uniform thickness on the upper surface of the insulating layer 110.

[0117] If the thickness of the first metal layer 121 of the first circuit pattern layer 120 exceeds 3.0 μm, the processing time for forming the first metal layer 121 of the first circuit pattern layer 120 may increase, and thus the yield may decrease. In addition, if the thickness of the first metal layer 121 of the first circuit pattern layer 120 exceeds 3.0 μm, the etching time of the first metal layer 121 in the process of forming the first circuit pattern layer 120 may increase. In addition, if the thickness of the first metal layer 121 of the first circuit pattern layer 120 exceeds 3.0 μm, deformation of the second metal layer 122 of the first circuit pattern layer 120 may occur when etching the first metal layer 121 of the first circuit pattern layer 120. Here, the deformation of the second metal layer 122 of the first circuit pattern layer 120 means that as one side of the second metal layer 122 is also etched when etching the first metal layer 121, the difference between the width of the upper surface and the width of the lower surface of the second metal layer 122 increases. For example, the deformation of the second metal layer 122 of the first circuit pattern layer 120 means that the shape of a vertical cross section of the second metal layer 122 is changed from a square to a trapezoid.

[0118] In addition, if the thickness of the first metal layer 121 of the first circuit pattern layer 120 exceeds 3.0 μm, the etching amount in the process of etching the first metal layer 121 increases, and therefore, the depth of the recess (e.g., undercut) formed at one side of the first metal layer 121 and one side of the second metal layer 122 may increase. For example, if the etching amount in the etching process of the first metal layer 121 increases, the difference between the width of the first metal layer 121 and the width of the second metal layer 122 may increase. In addition, when the difference between the width of the first metal layer 121 and the width of the second metal layer 122 increases, the electrical characteristics may be degraded due to the increase in signal transmission loss. In addition, when the difference between the width of the first metal layer 121 and the width of the second metal layer 122 increases, dendrites may be formed due to electromigration, thereby degrading the electrical characteristics and / or physical characteristics of the first circuit pattern layer 120.

[0119] The second metal layer 122 of the first circuit pattern layer 120 may be an electroplated layer formed by using the first metal layer 121 as a seed layer. The second metal layer 122 of the first circuit pattern layer 120 may be formed on the first metal layer 121 with a certain thickness. The second metal layer 122 of the first circuit pattern layer 120 may include the same metal as the first metal layer 121 of the first circuit pattern layer 120, but is not limited thereto. For example, the first metal layer 121 and the second metal layer 122 of the first circuit pattern layer 120 may each include copper.

[0120] The thickness of the second metal layer 122 of the first circuit pattern layer 120 may be greater than the thickness of the first metal layer 121 of the first circuit pattern layer 120 .

[0121] The thickness of the second metal layer 122 of the first circuit pattern layer 120 may satisfy the range of 3.5 μm to 25 μm. Preferably, the thickness of the second metal layer 122 of the first circuit pattern layer 120 may satisfy the range of 4.0 μm to 23 μm. More preferably, the thickness of the second metal layer 122 of the first circuit pattern layer 120 may satisfy the range of 4.5 μm to 22 μm.

[0122] If the thickness of the second metal layer 122 of the first circuit pattern layer 120 is less than 3.5 μm, the second metal layer 122 may also be etched during the etching process of the first metal layer 121. If the thickness of the second metal layer 122 of the first circuit pattern layer 120 is less than 3.5 μm, the allowed current of the signal transmitted through the first circuit pattern layer may be reduced, and thus the electrical characteristics may be degraded. If the thickness of the second metal layer 122 of the first circuit pattern layer 120 exceeds 25 μm, it may be difficult to miniaturize the first circuit pattern layer 120. For example, if the thickness of the second metal layer 122 of the first circuit pattern layer 120 exceeds 25 μm, the width and spacing of the pattern constituting the first circuit pattern layer 120 may not meet the required conditions. Therefore, the circuit integration may be reduced, or the volume of the circuit board and the semiconductor package may be increased.

[0123] Meanwhile, the second circuit pattern layer 130 of the circuit board 100 of the first embodiment may include a first metal layer 131 and a second metal layer 132 corresponding to the first circuit pattern layer 120. The first metal layer 131 of the second circuit pattern layer 130 of the circuit board 100 of the first embodiment corresponds to the first metal layer 121 of the first circuit pattern layer 120. In addition, the second metal layer 132 of the second circuit pattern layer 130 of the circuit board 100 of the first embodiment corresponds to the second metal layer 122 of the first circuit pattern layer 120. Therefore, the second circuit pattern layer 130 of the circuit board 100 of the first embodiment may have the characteristics of the first circuit pattern layer 120 described above. Therefore, a detailed description of the second circuit pattern layer 130 of the first embodiment is omitted.

[0124] The circuit board 100 of the first embodiment may include a through electrode 140. The through electrode 140 may penetrate the insulating layer 110. Preferably, the through electrode 140 may penetrate the insulating layer 110 to electrically connect the first circuit pattern layer 120 and the second circuit pattern layer 130. At this time, when the circuit board 100 has a multi-layer structure, the through electrodes 140 may be vertically spaced apart from each other and electrically connect adjacent circuit pattern layers.

[0125] The through electrode 140 may be formed by filling the inside of a through hole penetrating the insulating layer 110 with a conductive material.

[0126] The through hole can be formed by any of mechanical, laser and chemical processing methods. When the through hole is formed by mechanical processing, methods such as milling, drilling and wiring can be used. In addition, when the through hole is formed by laser processing, a UV or CO2 laser method can be used. In addition, when the through hole is formed by chemical processing, chemicals containing aminosilane, ketone, etc. can be used. However, the embodiment is not limited to this.

[0127] For example, a through hole for providing the through electrode 140 may be formed using a method for forming an opening region provided in the first protective layer 150 of the embodiment. Therefore, the width of the through electrode 140 may hardly change from the upper surface of the through electrode 140 to the lower surface of the through electrode 140. For example, the width of the upper surface of the through electrode 140 may be the same as the width of the lower surface of the through electrode 140.

[0128] The through electrode 140 includes a plurality of metal layers.

[0129] The through electrode 140 includes a first metal layer 141 and a second metal layer 142. The first metal layer 141 of the through electrode 140 may correspond to the first metal layer 121 of the first circuit pattern layer 120. In addition, the second metal layer 142 of the through electrode 140 may correspond to the second metal layer 122 of the first circuit pattern layer 120. Therefore, a detailed description of the first metal layer 141 and the second metal layer 142 of the through electrode 140 is omitted.

[0130] Meanwhile, in the above, the first circuit pattern layer 120 and the second circuit pattern layer 130 of the present embodiment are described as including the first metal layer and the second metal layer manufactured by the SAP process, but are not limited thereto.

[0131] For example, the first circuit pattern layer 120 and the second circuit pattern layer 130 may be manufactured by the MSAP process. Therefore, each of the first circuit pattern layer 120 and the second circuit pattern layer 130 may additionally have a third metal layer disposed between the first metal layer and the insulating layer. The third metal layer may refer to a copper layer attached when laminating the insulating layer, but is not limited thereto.

[0132] Meanwhile, the circuit board 100 of the first embodiment may include a protection layer.

[0133] For example, the circuit board 100 may include a first protective layer 150 disposed on the insulating layer 110. For example, the circuit board 100 may include a second protective layer 160 disposed under the insulating layer 110.

[0134] The first protective layer 150 and the second protective layer 160 may be an anti-corrosion layer. Preferably, the first protective layer 150 and the second protective layer 160 may be a solder resist layer containing an organic polymer material. For example, the first protective layer 150 and the second protective layer 160 may include an epoxy acrylate series resin. Specifically, the first protective layer 150 and the second protective layer 160 may include a resin, a curing agent, a pigment, a solvent, a filler, an additive, an acrylic monomer, etc.

[0135] The thickness of each of the first protective layer 150 and the second protective layer 160 may be greater than the thickness of each of the first circuit pattern layer 120 and the second circuit pattern layer 130 .

[0136] That is, the thickness of the first protective layer 150 may be greater than the thickness of the first circuit pattern layer. In addition, the thickness of the second protective layer 160 may be greater than the thickness of the second circuit pattern layer 130.

[0137] The thickness of the first protective layer 150 may represent a vertical distance from a lower surface of the first protective layer 150 to an upper surface of the first protective layer 150. For example, the first protective layer 150 is disposed on an upper surface of the insulating layer 110. Therefore, the thickness of the first protective layer 150 may represent a vertical distance from an upper surface of the insulating layer 110 to an upper surface of the first protective layer 150.

[0138] The thickness of the first protective layer 150 may be within a range of 6.7 μm to 35.0 μm. Preferably, the thickness of the first protective layer 150 may be within a range of 7.3 μm to 32 μm. More preferably, the thickness of the first protective layer 150 may be within a range of 8.0 μm to 30 μm.

[0139] If the thickness of the first protective layer 150 exceeds 30 μm, the thickness of the circuit board and the thickness of the semiconductor package may increase. In addition, if the thickness of the first protective layer 150 is less than 6.7 μm, the first circuit pattern layer may not be stably protected and thus electrical reliability or physical reliability may deteriorate.

[0140] In addition, the second protective layer 160 may have a thickness corresponding to that of the first protective layer 150 , but is not limited thereto.

[0141] At the same time, the first protective layer 150 includes at least one opening region. In addition, the second protective layer 160 includes at least one opening region. At this time, the width of the opening region formed in the first protective layer 150 and the second protective layer 160 of the present embodiment may be smaller than the width of the opening region of the comparative example. This can be achieved by forming the opening regions of the first protective layer 150 and the second protective layer 160 using separate resist patterns, rather than forming the opening regions by exposing and developing the first protective layer 150 and the second protective layer 160.

[0142] Hereinafter, the opening region formed in the first protective layer 150 will be described in detail. However, the description of the opening region formed in the second protective layer 160 is omitted below. For example, the opening region formed in the second protective layer 160 may have a structure corresponding to the opening region formed in the first protective layer 150 described below.

[0143] The first protective layer 150 includes an opening region, and the opening region may be formed as a through hole penetrating the upper and lower surfaces of the first protective layer 150 .

[0144] The first protective layer 150 includes a first opening area 151. For example, the first protective layer 150 may include the first opening area 151 vertically overlapping the first pad 120-1 of the first circuit pattern layer 120.

[0145] At this time, the first opening region 151 of the first protection layer 150 may partially overlap the upper surface of the first pad 120-1 in the vertical direction. For example, the first opening region 151 of the first protection layer 150 may be an SMD type opening region.

[0146] That is, the width (W1) of the first opening region 151 of the first protection layer 150 may be smaller than the width of the upper surface of the first pad 120-1. For example, the first protection layer 150 may include the first opening region 151 covering at least a portion of the upper surface of the first pad 120-1 while exposing the remaining portion of the upper surface of the first pad 120-1.

[0147] At this time, the width (W1) of the first opening region 151 of the first protective layer 150 may be 30 μm or less. Preferably, the width (W1) of the first opening region 151 of the first protective layer 150 may be 28 μm or less. More preferably, the width (W1) of the first opening region 151 of the first protective layer 150 may be 25 μm or less.

[0148] For example, the width (W1) of the first opening region 151 of the first protective layer 150 may be within a range of 10 μm to 30 μm. Preferably, the width (W1) of the first opening region 151 of the first protective layer 150 may be within a range of 12 μm to 28 μm. More preferably, the width (W1) of the first opening region 151 of the first protective layer 150 may be within a range of 13 μm to 25 μm.

[0149] If the width (W1) of the first opening region 151 of the first protective layer 150 is less than 10 μm, the amount of solder balls or other connection portions disposed in the first opening region 151 is reduced, and thus the bonding strength with the semiconductor device may be reduced. If the width (W1) of the first opening region 151 of the first protective layer 150 exceeds 30 μm, the width of the first pad 120-1 may increase accordingly, thus reducing the circuit integration.

[0150] At this time, the width of the first opening region 151 of the first protective layer 150 in the first embodiment hardly changes from the region adjacent to the upper surface of the first protective layer 150 to the region adjacent to the lower surface of the first protective layer 150. Here, the width hardly changes, which means that the slope of the first inner surface 151S of the first protective layer 150 constituting the first opening region 151 is close to vertical. For example, the width hardly changes, which means that in the entire region of the first opening region 151 in the thickness direction, the width difference between the region having the maximum width and the region having the minimum width is 3 μm or less, 2.5 μm or less, 2 μm or less, 1.5 μm or less, 1 μm or less, or 0.5 μm or less.

[0151] That is, the first opening region 151 of the first protective layer 150 of the first embodiment does not include a region whose width increases rapidly from the upper region to the lower region. That is, the lower end of the first inner surface 151S of the first opening region 151 of the first protective layer 150 of the first embodiment does not include an undercut.

[0152] This is because the first opening region 151 of the first protective layer 150 is not formed by exposing and developing the first protective layer 150, but is formed by using a separate resist pattern. That is, in the first embodiment, before forming the first protective layer 150, a first resist pattern (DFR1-F, see Figure 6 ). In addition, in the first embodiment, the first protective layer 150 is formed in a state where the first resist pattern DFR1-F is provided. Therefore, the first opening region 151 corresponding to the first resist pattern DFR1-F is formed in the first protective layer 150.

[0153] Here, refer to Figure 6 , the first resist pattern DFR1-F can be formed using a photosensitive film. Therefore, the photosensitive film can form a fine pattern compared to forming a pattern in a solder resist.

[0154] In the first embodiment, when the first protective layer 150 is formed while the first resist pattern DFR1-F is provided, the first protective layer 150 completely covers the first resist pattern DFR1-F. Thereafter, the first embodiment performs a thinning process on the first protective layer 150 to reduce the thickness of the first protective layer 150 to a target thickness. At this time, in a state where the first resist pattern DFR1-F is provided, the first protective layer 150 can have a target thickness without covering the first resist pattern DFR1-F. That is, in a state where the first resist pattern DFR1-F is provided, the first protective layer 150 can have a certain thickness without performing a thinning process. However, if the thinning process is not performed as described above, the first protective layer 150 may have a thickness deviation in the first region adjacent to the first resist pattern DFR1-F and the second region excluding the first region. For example, in the case where the thinning process is not performed as described above, the flatness of the upper surface 150T of the first protective layer 150 may deteriorate. Therefore, the present embodiment performs a process of thinning the first protective layer 150 to a target thickness while maintaining a certain thickness.

[0155] Therefore, the upper surface 150T of the first protective layer 150 of the first embodiment may have a surface roughness different from the surface roughness of the first inner surface 151S of the first open region 151 .

[0156] On the contrary, however, the first inner surface 151S of the first opening region 151 of the first protective layer 150 is an unthinned surface. For example, the first inner surface 151S of the first opening region 151 of the first protective layer 150 may correspond to the surface roughness of the first resist pattern DFR1-F.

[0157] That is, the upper surface 150T of the first protective layer 150 may have a shape similar to the inner surface (150S, see Figure 5 The inner surface 150S of the opening region may include a first inner surface 151S of the first opening region 151 and a second inner surface 152S of the second opening region 152.

[0158] The surface roughness of the upper surface 150T of the first protective layer 150 may be greater than the surface roughness of the inner surface of the opening region of the first protective layer 150 .

[0159] That is to say, reference Figure 4, the first protective layer 150 includes a resin and a filler 150F dispersed in the resin. At this time, when the first protective layer 150 is thinned, the filler 150F provided in the first protective layer 150 is exposed to the upper surface 150T of the first protective layer 150 due to the thinning. On the contrary, the filler 150F is not exposed on the inner surface 150S of the opening area of ​​the first protective layer 150, or the amount of the exposed filler may be less than the amount of the filler exposed to the upper surface 150T. Therefore, due to the presence of the filler 150F, the upper surface 150T of the first protective layer 150 may have a greater surface roughness than the inner surface of the opening area of ​​the first protective layer 150. Preferably, the filler 150F may not be exposed to the inner surface 150S of the opening area of ​​the first protective layer 150.

[0160] At the same time, the filler 150F can be completely exposed to the upper surface 150T of the first protective layer 150. That is, the present embodiment performs thinning on the entire area of ​​the surface of the first protective layer 150. Therefore, the entire area of ​​the upper surface 150T of the first protective layer 150 can be a thinned surface. Therefore, the filler 150F can be completely exposed to the upper surface 150T of the first protective layer 150. In addition, the present embodiment can increase the surface roughness of the upper surface 150T of the first protective layer 150 by using the filler 150F exposed to the upper surface 150T of the first protective layer 150. Thus, in the molding process after the semiconductor device is mounted on the circuit board, the present embodiment can increase the bonding area between the first protective layer 150 and the molding layer, thereby improving the bonding strength.

[0161] Meanwhile, the first protective layer 150 includes the second opening region 152. For example, the first protective layer 150 may include the second opening region 152 vertically overlapping the second pad 120-2 of the first circuit pattern layer 120.

[0162] At this time, the second opening region 152 of the first protection layer 150 may entirely vertically overlap with the upper surface of the second pad 120 - 2 . For example, the second opening region 152 of the first protection layer 150 may be a NSMD type opening region.

[0163] That is, the width (W2) of the second opening region 152 of the first protection layer 150 may be greater than the width of the upper surface of the second pad 120-2. For example, the first protection layer 150 may completely expose the upper surface and the inner surface of the second pad 120-2. For example, the second inner surface 152S of the second opening region 152 of the first protection layer 150 may be spaced apart from and not in contact with the second pad 120-2. For example, the second pad 120-2 may not be in contact with the first protection layer 150.

[0164] At this time, the width (W2) of the second opening region 152 of the first protective layer 150 may be 30 μm or less. Preferably, the width (W2) of the second opening region 152 of the first protective layer 150 may be 28 μm or less. More preferably, the width (W2) of the second opening region 152 of the first protective layer 150 may be 25 μm or less.

[0165] For example, the width (W2) of the second opening region 152 of the first protective layer 150 may be within a range of 10 μm to 30 μm. Preferably, the width (W2) of the second opening region 152 of the first protective layer 150 may be within a range of 12 μm to 28 μm. More preferably, the width (W2) of the second opening region 152 of the first protective layer 150 may be within a range of 13 μm to 25 μm.

[0166] If the width (W2) of the second opening region 152 of the first protective layer 150 is less than 10 μm, the amount of the connection portion (e.g., solder ball) disposed in the second opening region 152 is reduced, and thus the bonding strength with the semiconductor device may be reduced. If the width (W2) of the second opening region 152 of the first protective layer 150 exceeds 30 μm, the distance between the second pad 120-2 and the circuit pattern (e.g., trace) adjacent to the second pad increases, and thus the circuit integration may be reduced.

[0167] At this time, the width of the second opening region 152 of the first protective layer 150 in the first embodiment hardly changes from the region adjacent to the upper surface of the first protective layer 150 to the region adjacent to the lower surface of the first protective layer 150. For example, the slope of the second inner surface 152S of the first protective layer 150 constituting the second opening region 152 may be close to vertical. For example, in the entire region of the second opening region 152 in the thickness direction, the width difference between the region having the maximum width and the region having the minimum width may be 3 μm or less, 2.5 μm or less, 2 μm or less, 1.5 μm or less, 1 μm or less, or 0.5 μm or less.

[0168] That is, the second opening region 152 of the first protective layer 150 of the first embodiment does not include a region whose width increases rapidly from the upper region to the lower region. That is, the lower end of the second inner surface 152S of the second opening region 152 of the first protective layer 150 of the first embodiment does not include an undercut.

[0169] That is, in the first embodiment, before forming the first protective layer 150, a resist pattern DFR1-F may be further formed in the region where the second opening region 152 is to be formed to correspond to the second opening region 152. Thus, the second opening region 152 may be formed in the first protective layer 150 corresponding to the resist pattern DFR1-F.

[0170] In addition, the second inner surface 152S of the second opening region 152 is also a surface on which thinning is not performed. Therefore, the surface roughness of the second inner surface 152S of the second opening region 152 may be less than the surface roughness of the upper surface 150T of the first protective layer 150 .

[0171] As described above, the first protective layer 150 in the first embodiment includes an opening region. At this time, the opening region may be formed in the first protective layer 150 using a separate resist pattern DFR1-F.

[0172] At this time, the resist pattern DFR1-F may be a photosensitive film (DFR: Dry Film Photoresist). At this time, the photosensitive film does not contain fillers. Therefore, the minimum size of the resist pattern formed by exposing and developing the photosensitive film is generally smaller than the resist pattern formed by exposing and developing the solder resist containing fillers.

[0173] Therefore, the present embodiment does not expose and develop the protective layer (e.g., solder resist) itself, but exposes and develops the photosensitive film capable of realizing relatively fine patterns to form an anti-etching pattern. In addition, the present embodiment uses the anti-etching pattern to form an opening region in the first protective layer 150. Therefore, compared with the comparative example, the present embodiment can reduce the size of the opening region formed in the first protective layer 150, thereby improving the circuit integration.

[0174] At this time, since the present embodiment does not perform exposure and development on the first protective layer 150, the first protective layer 150 does not need to contain a photoinitiator. For example, a general solder resist contains a photoinitiator for exposure and development. At this time, the photoinitiator is a factor that deteriorates the physical and electrical properties of the circuit board.

[0175] Here, since the first protective layer 150 is not exposed and developed in this embodiment, the first protective layer 150 does not include a photoinitiator. Therefore, since the first protective layer 150 does not include a photoinitiator, this embodiment can improve physical and electrical properties of the circuit board.

[0176] In addition, since the first protective layer 150 does not include a photoinitiator, the present embodiment can expand the types of insulating layers that can be used as the first protective layer 150 and further reduce the unit cost required for developing the protective layer.

[0177] For example, the first protective layer 150 of the present embodiment may be a solder resist that does not contain a photoinitiator. Alternatively, the first protective layer 150 of the present embodiment may use an insulating layer in which an inorganic filler of silicon dioxide or aluminum oxide is provided in a thermosetting resin or a thermoplastic resin and does not include glass fiber. For example, the first protective layer 150 may use ABF (Ajinomoto deposited film), FR-4, BT (bismaleimide triazine), PID (photoimageable dielectric resin), BT, etc.

[0178] However, according to one embodiment, the first protective layer 150 and the second protective layer 160 of the present invention may also be implemented by using a solder resist used in a general circuit board. For example, according to one embodiment, the first protective layer 150 and the second protective layer 160 may include a photoinitiator.

[0179] Figure 7 is a plan view for explaining the tolerance (SRR: Solder Resist Registration) according to the comparative example, Figure 8 2 is a view for explaining the tolerance according to the first embodiment.

[0180] refer to Figure 7 In (a), in the case of the comparative example, the first pad 21 includes a first portion 21a exposed by the first opening region 31 of the protective layer 30 and a second portion 21b covered with the protective layer 30. At this time, in the comparative example, the protective layer 30 is exposed and developed to form the first opening region 31. At this time, the protective layer 30 has an exposure resolution much lower than that of the DFR. Therefore, in the comparative example, it can be determined that the center 21C of the first pad 21 and the center 31C of the first opening region 31 are misaligned, with a difference of the first tolerance (d1). Specifically, in the comparative example, the first tolerance (d1) between the center 21C of the first pad 21 and the center 31C of the first opening region 31 exceeds 12.5μm, or exceeds 14μm, or exceeds 15μm. Therefore, in the comparative example, an alignment reliability problem may occur in which at least a portion of the first opening region 31 does not overlap vertically with the first pad 21.

[0181] refer to Figure 7(b), in the comparative example, the second pad 22 is completely exposed through the second opening area 32 of the protective layer 30. At this time, in the comparative example, in order to form the second opening area 32, the protective layer 30 is exposed and developed. At this time, the protective layer 30 has an exposure resolution much lower than the DFR. Therefore, in the comparative example, it can be determined that the center 22C of the second pad 22 and the center 32C of the second opening area 32 are offset by a second tolerance (d2). Specifically, in the comparative example, the second tolerance (d2) between the center 22C of the second pad 22 and the center 32C of the second opening area 32 exceeds 12.5μm, or exceeds 14μm, or exceeds 15μm. Therefore, in the comparative example, an alignment reliability problem may occur in which at least a portion of the upper surface of the second pad 22 is covered by the protective layer 30.

[0182] In contrast, the present embodiment can significantly reduce the tolerance compared to the comparative example.

[0183] For example, refer to Figure 8 (a), in the case of this embodiment, the first pad 120-1 includes a first portion 120-1a exposed by the first opening region 151 of the first protective layer 150 and a second portion 120-1b covered with the first protective layer 150. At this time, in this embodiment, instead of exposing and developing the first protective layer 150, the first opening region 151 is formed using a resist pattern DFR1-F formed by DFR. Therefore, in this embodiment, it can be determined that the center 120-1C of the first pad 120-1 and the center 151C of the first opening region 151 are offset by a third tolerance (D1), which is significantly reduced compared to the first tolerance (d1) of the comparative example. Specifically, the third tolerance (D1) between the center 120-1C of the first pad 120-1 and the center 151C of the first opening region 151 of the present embodiment is 10μm or less, or 9μm or less, or 8μm or less. Therefore, the present embodiment can improve the alignment accuracy between the first opening area 151 and the first pad 120 - 1 . Thus, the present embodiment can further improve the electrical reliability and / or physical reliability of the circuit board.

[0184] In addition, reference Figure 8(b), in the case of this embodiment, the second pad 120-2 is completely exposed through the second opening area 152 of the first protective layer 150. At this time, in this embodiment, in order to form the second opening area 152, the first protective layer 150 is not exposed and developed, but the resist pattern DFR1-F formed by DFR is used. Therefore, in this embodiment, it can be determined that the center 120-2C of the second pad 120-2 and the center 152C of the second opening area 152 are offset, and the difference is a fourth tolerance (D2), which is significantly reduced compared with the second tolerance (d2) of the comparative example. Specifically, the fourth tolerance (D2) between the center 120-1C of the second pad 120-2 of the present embodiment and the center 152C of the second opening area 152 is 10μm or less, or 9μm or less, or 8μm or less. Therefore, this embodiment can improve the alignment accuracy between the second opening area 152 and the second pad 120-2. Therefore, this embodiment can further improve the electrical reliability and / or physical reliability of the circuit board.

[0185] This embodiment includes an insulating layer, a pad disposed on the insulating layer, and a protection layer disposed on the insulating layer, wherein the protection layer includes an opening area overlapping the pad in a vertical direction.

[0186] In this case, the width of the opening region of the protective layer of this embodiment is 30 μm or less. For example, the width of the opening region of the protective layer of this embodiment may satisfy the range of 10 μm to 30 μm, 12 μm to 28 μm, or 13 μm to 25 μm.

[0187] In addition, the width of the opening area of ​​the protective layer of the present embodiment in the thickness direction varies little. For example, in the entire area of ​​the opening area of ​​the present embodiment in the thickness direction, the difference between the width of the area with the maximum width and the area with the minimum width can be 3μm or less, 2.5μm or less, 2μm or less, 1.5μm or less, 1μm or less, or 0.5μm or less. That is, in one embodiment, the undercut at the lower end of the inner surface of the opening area of ​​the protective layer can be eliminated, or the horizontal distance of the undercut can be significantly reduced compared with the comparative example.

[0188] This is because the opening area of ​​the protective layer is not formed by exposing and developing the protective layer, but a separate resist pattern is used. That is, in one embodiment, the protective layer is provided when the resist pattern is formed using a photosensitive film. Therefore, an opening area corresponding to the resist pattern can be formed in the protective layer. In this case, the photosensitive film does not contain fillers. Therefore, in general, the minimum size of the resist pattern formed by exposing and developing the photosensitive film is smaller than the minimum size of the resist pattern formed by exposing and developing the solder resist containing fillers.

[0189] Therefore, the present embodiment does not expose and develop the protective layer (such as solder resist), but exposes and develops the photosensitive film that can realize relatively fine patterns to form an anti-etching pattern. Then, the present embodiment forms an opening area in the protective layer by using the anti-etching pattern. Therefore, compared with the comparative example, the present embodiment can reduce the size of the opening area formed on the protective layer, thereby improving the circuit integration.

[0190] In addition, since the present embodiment does not expose and develop the protective layer, undercuts that may be formed at the inner surface of the opening region of the protective layer can be eliminated. Therefore, the present embodiment can further reduce the spacing between the circuit pattern layers.

[0191] Meanwhile, in the present embodiment, in a state where the resist pattern is provided, the thickness of the protective layer is made greater than the thickness of the resist pattern, and then the protective layer is subjected to a thinning process. That is, in the present embodiment, the protective layer can have a target thickness by thinning. In this case, the application process of the protective layer can be performed without performing a thinning process to have a target thickness. However, if the thinning process is not performed, there is a problem of an increase in the thickness deviation of the protective layer, and therefore, the flatness of the protective layer is reduced.

[0192] On the other hand, since the present embodiment performs a thinning process, the flatness of the protective layer can be improved. Therefore, the present embodiment can improve the overall physical reliability and electrical reliability of the circuit board and the semiconductor package.

[0193] In addition, the filler can be completely exposed on the upper surface of the protective layer of this embodiment. In addition, the exposed filler increases the surface roughness of the upper surface of the protective layer. Therefore, in the molding process after the semiconductor device is mounted on the circuit board, this embodiment can increase the bonding area between the protective layer and the molding layer, thereby improving the bonding strength. Therefore, this embodiment can further improve product reliability.

[0194] Meanwhile, in one embodiment, since the protective layer is not exposed and developed, a photoinitiator is not required in the protective layer. For example, a general solder resist contains a photoinitiator for exposure and development. In this case, the photoinitiator is a factor that deteriorates the physical and electrical properties of the circuit board. In this case, the present embodiment can improve the physical and electrical properties of the circuit board because the protective layer does not contain a photoinitiator.

[0195] Furthermore, since the present embodiment does not include a photoinitiator in the protective layer, the types of insulating layers that can be used as the protective layer can be expanded, and thus the unit cost required for developing the protective layer can be reduced.

[0196] In addition, compared with the comparative example, the present embodiment can significantly reduce the tolerance between the center of the opening area of ​​the protective layer and the center of the pad. Therefore, the present embodiment can improve the mounting performance of the semiconductor device, thereby improving the physical reliability and electrical reliability of the circuit board and the semiconductor package.

[0197] Fig. 9 is a cross-sectional view showing a circuit board according to a second embodiment.

[0198] Reference Fig. 9 A circuit board according to a second embodiment is described.

[0199] The circuit board of the second embodiment includes an insulating layer 210 .

[0200] In addition, the circuit board of the second embodiment includes a first circuit pattern layer 220 disposed on the insulating layer 210. In addition, the circuit board of the second embodiment includes a second circuit pattern layer 230 disposed below the insulating layer 210. In addition, the circuit board of the second embodiment includes a through electrode 240 penetrating the insulating layer 210. In addition, the circuit board of the second embodiment includes a first protective layer 250 disposed on the insulating layer 210. In addition, the circuit board of the second embodiment includes a second protective layer 260 disposed below the insulating layer 210.

[0201] The first circuit pattern layer 220 , the second circuit pattern layer 230 , and the through-electrode 240 include first metal layers 221 , 231 , and 241 and second metal layers 222 , 232 , and 242 , respectively.

[0202] The first protection layer 250 and the second protection layer 260 each include at least one opening region.

[0203] At this time, the circuit board of the second embodiment has a difference in opening areas formed in the first protection layer 250 and the second protection layer 260 compared to the circuit board of the first embodiment.

[0204] Therefore, the following description will focus on the opening region formed in the first protective layer 250 .

[0205] The inner surface of the opening region in the first embodiment has a slope that is substantially perpendicular to the upper surface of the insulating layer.

[0206] In contrast, the inner surface of the opening region in the second embodiment has a slope with respect to the upper surface of the insulating layer.

[0207] For example, the first circuit pattern layer 220 includes a first pad 220-1 and a second pad 220-2. In addition, the first protection layer 250 includes a first opening area 251 vertically overlapping the first pad 220-1. In addition, the first protection layer 250 includes a second opening area 252 vertically overlapping the second pad 220-2.

[0208] At this time, the basic structure of the first opening region 251 and the second opening region 252 is the same as that of the first embodiment, and a detailed description thereof is omitted.

[0209] The width of the first opening area 251 may change from the upper surface of the first protective layer 250 to the lower surface of the first protective layer 250. For example, the first inner surface 251S of the first protective layer 250 may have a slope whose width decreases toward the bottom. That is, in the second embodiment, the photosensitive film used to form the first opening area 251 is a negative type, and the negative photosensitive film can be used to form the resist pattern DFR1-F. Thus, the resist pattern DFR1-F may have a shape whose width decreases toward the bottom. In addition, the first inner surface 251S of the first opening area 251 of the first protective layer 250 formed by the resist pattern DFR1-F may have a slope whose width decreases toward the bottom. The characteristic of the negative photosensitive film is that during exposure and development, the unexposed portion is developed and removed.

[0210] Accordingly, the second inner surface 252S of the second opening region 252 of the first protection layer 250 may also have a slope whose width decreases downward.

[0211] At this time, in the present embodiment, the first inner surface 251S and the second inner surface 252S do not include undercuts. Therefore, each of the first inner surface 251S and the second inner surface 252S has a slope in which the width decreases from the upper end toward the lower end. At this time, the first opening area 251 and the second opening area 252 only include a slope in which the width decreases from the upper end toward the lower end of the first inner surface 251S and the second inner surface 252S, respectively, and do not include a slope in which the width remains unchanged or a slope in which the width increases. That is, a slope in which the width remains unchanged or a slope in which the width increases indicates the presence of an undercut. In addition, since the present embodiment does not include an undercut, each of the first inner surface 251S and the second inner surface 252S of the first opening area 251 and the second opening area 252 may only include a slope in which the width decreases, and do not include a slope in which the width remains unchanged or a slope in which the width increases.

[0212] At this time, as described above, the present embodiment uses a negative photosensitive film to form an opening region in the first protective layer 250. Thus, the present embodiment can ensure that the removal of the resist pattern DFR1-F is smoothly performed in the process of removing the resist pattern DFR1-F after the opening region is formed in the first protective layer 250. Thus, the present embodiment can solve the problem of separation of the first protective layer 250 from the insulating layer 210 in the process of removing the resist pattern DFR1-F.

[0213] Fig.10 is a cross-sectional view showing a circuit board according to a third embodiment.

[0214] Reference Fig.10 A circuit board according to a third embodiment is described.

[0215] The circuit board of the third embodiment includes an insulating layer 310 .

[0216] In addition, the circuit board of the third embodiment includes a first circuit pattern layer 320 disposed on the insulating layer 310. In addition, the circuit board of the third embodiment includes a second circuit pattern layer 330 disposed below the insulating layer 310. In addition, the circuit board of the third embodiment includes a through electrode 340 penetrating the insulating layer 310. In addition, the circuit board of the third embodiment includes a first protective layer 350 disposed on the insulating layer 310. In addition, the circuit board of the third embodiment includes a second protective layer 360 disposed below the insulating layer 310.

[0217] The first circuit pattern layer 320 , the second circuit pattern layer 330 , and the through-electrode 340 include first metal layers 321 , 331 , and 341 and second metal layers 322 , 332 , and 342 , respectively.

[0218] The first protection layer 350 and the second protection layer 360 include at least one opening region respectively.

[0219] At this time, the circuit board of the third embodiment has a difference in opening areas formed in the first protection layer 350 and the second protection layer 360 compared to the circuit board of the first embodiment.

[0220] Therefore, the following description will focus on the opening region formed in the first protective layer 350 .

[0221] The inner surface of the opening region in the first embodiment has a slope substantially perpendicular to the upper surface of the insulating layer, and the inner surface of the opening region in the second embodiment has a slope whose width decreases downward.

[0222] However, the inner surface of the opening region of the third embodiment may have a slope in which the width thereof increases toward the downward direction.

[0223] For example, the first circuit pattern layer 320 includes a first pad 320-1 and a second pad 320-2. In addition, the first protection layer 350 includes a first opening area 351 vertically overlapping the first pad 320-1. In addition, the first protection layer 350 includes a second opening area 352 vertically overlapping the second pad 320-2.

[0224] At this time, the basic structure of the first opening region 351 and the second opening region 352 is the same as that of the first embodiment, and a detailed description thereof is omitted.

[0225] The width of the first opening area 351 may vary from the upper surface to the lower surface of the first protective layer 350. For example, the first inner surface 351S of the first opening area 351 of the first protective layer 350 may have a slope whose width increases downward. That is, in the third embodiment, the photosensitive film used to form the first opening area 351 is a positive type, and the resist pattern DFR1-F may be formed using the positive type photosensitive film. Thus, the resist pattern DFR1-F may have a shape whose width increases downward. In addition, the first inner surface 351S of the first opening area 351 of the first protective layer 350 formed by the resist pattern DFR1-F may have a slope whose width increases downward. The characteristic of the positive type photosensitive film is that during exposure and development, the illuminated portion is developed and removed.

[0226] Accordingly, the second inner surface 352S of the second opening region 352 of the first protective layer 350 may also have a slope whose width decreases downward. At this time, in the third embodiment, as the width of the opening region increases downward, when a connection portion (such as a solder ball) is disposed in the opening region, the opening region can be used as an anchor point. Thus, this embodiment can improve the bonding characteristics with the connection portion.

[0227] -Semiconductor packaging-

[0228] Fig.11 is a cross-sectional view showing a semiconductor package according to the present invention.

[0229] refer to Fig.11 , the semiconductor package of the present invention may include Figure 2 , Fig. 9 and Fig.10 Any of the circuit boards shown in . In addition, the circuit board can have a multilayer structure.

[0230] The semiconductor package of the present invention includes a first connection portion 410. That is, the circuit pattern layer of the circuit pattern includes a pad provided to correspond to the mounting area of ​​the semiconductor device 420. The pad may refer to a first pad of the first circuit pattern layer, or differently, may refer to a second pad of the first circuit pattern layer.

[0231] The first connection portion 410 may include a hexahedron. The cross-section of the first connection portion 410 may also include a square. The cross-section of the first connection portion 410 may also include a rectangle or a square. For example, the first connection portion 410 may include a spherical shape. For example, the cross-section of the first connection portion 410 may also include a circle or a semicircle. For example, the cross-section of the first connection portion 410 may also include a partial or complete circle. The cross-sectional shape of the first connection portion 410 may be flat on one side and curved on the other side. The first connection portion 410 may be a solder ball, but is not limited thereto.

[0232] The semiconductor package of the present invention includes a component disposed on the first connection portion 410. The component disposed on the first connection portion 410 may be a semiconductor device, or alternatively an interposer. Hereinafter, the component disposed on the first connection portion 410 is described as a semiconductor device 420.

[0233] The semiconductor device 420 may be a logic chip, but is not limited thereto. For example, the semiconductor device 420 may be a central processing unit (e.g., CPU), a graphics processor (e.g., GPU), a digital signal processor, an encryption processor, a microprocessor, and an application processor (AP) chip in a microcontroller. The semiconductor device 420 includes a terminal 425 disposed on the lower surface of the semiconductor device 420. In addition, the terminal 425 of the semiconductor device 420 is connected to the circuit pattern layer of the circuit board through the first connection portion 410.

[0234] In addition, the semiconductor package may include an underfill 430. The underfill 430 may be arranged to cover the periphery of the semiconductor device 420 on the circuit board. However, the underfill 430 may be optionally omitted. For example, the semiconductor package may implement the function of the underfill 430 in the molding layer 450 while omitting the underfill 430.

[0235] The semiconductor package may include a second connection portion 440. The second connection portion 440 is disposed on a circuit pattern layer of a circuit board.

[0236] The second connection portion 440 may be a bump. For example, the second connection portion 440 may be a solder bump, but is not limited thereto. For example, the second connection portion 440 may be a columnar bump. For example, the second connection portion 440 may include a copper column and a solder bump disposed on the copper column. The upper surface of the second connection portion 440 may be positioned higher than the upper surface of the semiconductor device 420. Therefore, during the bonding process in which the external substrate 500 is disposed on the second connection portion 440, the semiconductor device 420 may be prevented from being damaged.

[0237] The semiconductor package may include a molding layer 450. The molding layer 450 may mold components disposed on a circuit board.

[0238] The molding layer 450 may be EMC (epoxy molding compound), but is not limited thereto. The molding layer 450 may have a low dielectric constant. For example, the dielectric constant (Dk) of the molding layer 450 may be 0.2 to 10. For example, the dielectric constant (Dk) of the molding layer 450 may be 0.5 to 8. For example, the dielectric constant (Dk) of the molding layer 450 may be 0.8 to 5. Therefore, in the present embodiment, the molding layer 450 may have a low dielectric constant, thereby improving the heat dissipation characteristics of the heat generated by the semiconductor device 420. The molding layer 450 may include an opening. For example, the molding layer 450 may include an opening that overlaps with the upper surface of the second connection portion 440 in a vertical direction.

[0239] The semiconductor package includes a third connection portion 460 .

[0240] The third connection portion 460 may be disposed below the circuit pattern layer at the bottom of the circuit board. The third connection portion 460 may be a solder joint for connecting the semiconductor package of this embodiment to an independent external substrate (eg, a main board of an electronic device), but is not limited thereto.

[0241] The semiconductor package includes an external substrate 500. The external substrate 500 may represent an independent substrate combined with the circuit board of the present embodiment. For example, the semiconductor device 420 provided on the circuit board may be a logic chip such as a CPU or a GPU, and the external substrate 500 may represent a memory substrate on which a memory chip connected to the logic chip is provided. The external substrate 500 may also be an interposer connected between a memory substrate and a circuit board, on which a semiconductor device 420 corresponding to the memory chip is provided.

[0242] The external substrate 500 may include an insulating layer 510, a circuit layer 520, a through electrode 530, an upper protective layer 540, and a lower protective layer 550. In addition, the external substrate 500 may include a fourth connection portion 560. The fourth connection portion 560 may be disposed between the external substrate 500 and the third connection portion 440.

[0243] In addition, the semiconductor package may include a fifth connection portion 570 . The fifth connection portion 570 may be provided on the external substrate 500 .

[0244] The semiconductor package may include a semiconductor device 580. The semiconductor device 580 may be mounted on the external substrate 500 through the fifth connection portion 570. The semiconductor device 580 may be a memory chip, but is not limited thereto. The terminal 585 of the semiconductor device 580 may be electrically connected to the external substrate 500 through the fifth connection portion 570. At this time, the semiconductor device 580 is shown as being mounted in a flip chip manner, but is not limited thereto. The semiconductor device 580 may be a stacked memory chip, and therefore, may be electrically connected to the external substrate 500 through a separate connection component (e.g., a wire).

[0245] -Manufacturing method-

[0246] Hereinafter, a circuit board manufacturing method according to one embodiment will be described.

[0247] Figures 12 to 19 1 and 2 are cross-sectional views showing the wiring board manufacturing method according to the present embodiment in the order of processes.

[0248] refer to Fig.12 In this embodiment, an insulating layer 110 is prepared.

[0249] Thereafter, the present embodiment forms a through hole VH penetrating the upper and lower surfaces of the insulating layer 110 .

[0250] Next, refer to Fig.13 , the present invention can form a through electrode 140 filling the through hole VH on the insulating layer 110. In addition, the present embodiment can form a first circuit pattern layer 120 including a first pad 120-1 and a second pad 120-2 on the upper surface of the insulating layer 110. In addition, the present invention can form a second circuit pattern layer 130 on the lower surface of the insulating layer 120.

[0251] Afterwards, refer to Fig.14 In the present invention, the first dry film DFR1 is formed on the insulating layer 120. At this time, the first dry film DFR1 may be disposed to completely cover the first circuit pattern layer 120.

[0252] In addition, the present invention forms the second dry film DFR2 under the insulating layer 120. At this time, the second dry film DFR2 may be disposed to completely cover the second circuit pattern layer 130.

[0253] Next, refer to Fig.15 The present invention can perform a process of forming the first exposure pattern ER1 by exposing and curing the first dry film DFR1. At this time, the first dry film DFR1 may be a negative type. Therefore, the unexposed portion may be removed by subsequent development, and the exposed first exposure pattern ER1 may not be removed.

[0254] In addition, the present invention can perform a process of forming the second exposure pattern ER2 by exposing and curing the second dry film DFR2. At this time, the second dry film DFR2 may be a negative type. Therefore, the unexposed portion is removed by subsequent development, and the exposed second exposure pattern ER2 may not be removed.

[0255] Next, refer to Fig.16 The present invention can perform a process of forming a first resist pattern DFR1-F by removing an area other than the first exposure pattern ER1 from the first dry film DFR1. At this time, the first resist pattern DFR1-F can be formed to correspond to an area on the insulating layer 120 where an opening area of ​​the first protective layer 150 is to be formed.

[0256] In addition, the present invention can perform a process of forming a second resist pattern DFR2-F by removing the area other than the second exposure pattern ER2 from the second dry film DFR2. At this time, the second resist pattern DFR2-F can be formed to correspond to the area on the insulating layer 120 where the opening area of ​​the second protective layer 160 is to be formed.

[0257] Next, refer to Fig.17 The present invention may form a first protective layer 150R covering the first resist pattern DFR1-F on the insulating layer 120. In addition, the present invention may form a second protective layer 160R covering the second resist pattern DFR2-F under the insulating layer 120.

[0258] Next, refer to Fig.18 , the present invention can remove the first protective layer 150R through a thinning process, thereby performing a process of reducing the thickness of the first protective layer 150R to a target thickness.

[0259] Thinning can be performed using an organic alkaline compound containing tetramethylammonium hydroxide (TMAH) or trimethyl-2-hydroxyethylammonium hydroxide (choline).

[0260] In addition, the present invention may remove the second protective layer 160R through the thinning process, thereby performing a process of reducing the thickness of the second protective layer 160R to a target thickness.

[0261] Next, refer to Fig.19 The present invention can perform a process of removing the first resist pattern DFR1-F and the second resist pattern DFR2-F. As a result, the present invention can form opening regions corresponding to the first resist pattern DFR1-F and the second resist pattern DFR2-F in the first protective layer 150 and the second protective layer 160, respectively.

[0262] On the other hand, when the circuit board having the above-mentioned features of the present invention is used for IT equipment or household appliances (such as smart phones, server computers, TVs, etc.), functions such as signal transmission or power supply can be stably performed. For example, when the circuit board having the features of the present invention performs the semiconductor packaging function, it can safely protect the semiconductor chip from external moisture or pollutants, or, it can solve the problems of leakage current, short circuit and disconnection of the terminals of the semiconductor chip. In addition, when responsible for the signal transmission function, the noise problem can be solved. Thus, the circuit board having the above-mentioned features of the present invention can keep the functions of IT equipment or household appliances stable, so that the entire product and circuit board applying the present invention can achieve functional unification or technical interlocking with each other.

[0263] When the circuit board having the above features of the present invention is used in a transportation device such as a vehicle, the problem of signal distortion transmitted to the transportation device can be solved, or the safety of the transportation device can be further improved by safely protecting the semiconductor chip controlling the transportation device from the outside and solving the problem of leakage current or short circuit between the terminals of the semiconductor chip or open circuit of the terminals. Therefore, the transportation device and the circuit board applying the present invention can achieve functional integrity or technical interlocking with each other.

[0264] The features, structures and effects described in the above embodiments are included in at least one embodiment, but are not limited to one embodiment. In addition, those skilled in the art can even combine or modify the features, structures and effects shown in each embodiment relative to other embodiments. Therefore, it should be understood that the contents related to such combination and such modification are also included in the scope of this embodiment.

[0265] The above description focuses on the embodiments, but it is merely illustrative and not limiting. It will be appreciated by those skilled in the art that various modifications and applications not shown above are possible without departing from the basic features of the embodiments. For example, each component specifically represented in the embodiments can be modified and implemented. In addition, it should be understood that the changes associated with these modifications and applications are also included within the scope of the embodiments defined in the appended claims.

Claims

1. A semiconductor package, comprising: Insulation layer; A pad portion, the pad portion being disposed on the insulating layer; a protective layer disposed on the insulating layer and including an opening region overlapping the pad portion in a vertical direction, The width of the opening area of ​​the protective layer in the horizontal direction meets the range of 10 μm to 30 μm, and The surface roughness of the upper surface of the protection layer is different from the surface roughness of the inner surface of the opening area of ​​the protection layer. 2 . The semiconductor package according to claim 1 , wherein a surface roughness of the upper surface of the protection layer is greater than a surface roughness of the inner surface of the opening region of the protection layer.

3. The semiconductor package according to claim 2, wherein the protective layer comprises a resin and a plurality of fillers dispersed in the resin, and At least one of the plurality of fillers is exposed through the upper surface of the protective layer.

4. The semiconductor package according to any one of claims 1 to 3, wherein the pad portion comprises a first pad, wherein the opening region includes a first opening region partially overlapping the first pad in a vertical direction, and The width of the first opening area is smaller than the width of the first pad.

5. The semiconductor package according to any one of claims 1 to 3, wherein the pad comprises a second pad, wherein the opening region includes a second opening region that completely overlaps the second pad in a vertical direction, and The width of the second opening area is greater than the width of the second pad. 6 . The semiconductor package according to claim 1 , wherein the inner surface of the open region has a slope, wherein a width of the open region decreases from the upper surface of the protection layer toward a lower surface of the protection layer. 7 . The semiconductor package according to claim 1 , wherein the inner surface of the open region has a slope, wherein a width of the open region increases from the upper surface of the protection layer toward a lower surface of the protection layer. 8 . The semiconductor package according to claim 1 , wherein a difference between a maximum width and a minimum width in a horizontal direction along a thickness direction of the opening region is 3 μm or less. 9 . The semiconductor package according to claim 1 , wherein a center of the opening region and a center of the pad portion are offset in a vertical direction. 10 . The semiconductor package according to claim 9 , wherein a width between a center of the opening region and a center of the pad portion in a horizontal direction is 10 μm or less.

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