Self-aligned backside contact with increased contact area

Abstract

A first source drain region (254) and a second source drain region (254), an upper source drain contact (266) connected to the first source drain region, a bottom source drain contact (282) connected to the second source drain region, a dielectric spacer (280) surrounds opposite vertical side surfaces of the bottom source drain contact and overlaps the vertical side surfaces and the lower horizontal surface of the bottom isolation region. A width of the bottom source drain contact (282) is wider than a width of the second source drain (254). Forming an undoped silicon buffer epitaxy (250) in the openings between and below the first and second nanosheet stacks (212, 264, 234), forming a contact to the first source drain adjacent thereto, removing the undoped silicon buffer epitaxy below the second source drain between the first and second nanosheet stacks, forming a bottom contact, and removing the bottom contact from the bottom contact. A width of the bottom contact portion is wider than a width of the second source drain electrode.

Description

Background Art

[0001] The present invention relates generally to the field of semiconductor manufacturing and, more particularly, to backside contacts.

[0002] Complementary metal oxide semiconductor (CMOS) technology is commonly used for field effect transistors (hereinafter referred to as "FETs") as part of advanced integrated circuits (hereinafter referred to as "ICs"), such as central processing units (hereinafter referred to as "CPUs"), memories, storage devices, etc. As the demand for reducing the size of transistor devices continues, nanosheet FETs help achieve reduced FET device footprints while maintaining FET device performance. Nanosheet devices include one or more layers of semiconductor channel material portions having a vertical thickness that is substantially less than its width. Nanosheet FETs include multiple stacked nanosheets extending between a pair of source / drain epitaxial regions. The device can be a gate-all-around device or a transistor, in which the gate surrounds a portion of the nanosheet channel. Summary of the invention

[0003] According to an embodiment, a semiconductor device is provided. The semiconductor device includes a first source-drain region, a second source-drain region, an upper source-drain contact vertically aligned above the first source-drain region and electrically connected to the first source-drain region, and a bottom source-drain contact vertically aligned below the second source-drain region and electrically connected to the second source-drain region, wherein the bottom source-drain contact and the upper source-drain contact are located on opposite sides of the semiconductor device, wherein a dielectric spacer surrounds opposite vertical side surfaces of the bottom source-drain contact, wherein the dielectric spacer overlaps the vertical side surfaces and the lower horizontal surface of the bottom isolation region.

[0004] According to an embodiment, a semiconductor device is provided. The semiconductor device includes a first source-drain region, a second source-drain region, an upper source-drain contact vertically aligned above the first source-drain region and electrically connected to the first source-drain region, and a bottom source-drain contact vertically aligned below the second source-drain region and electrically connected to the second source-drain region, wherein the bottom source-drain contact and the upper source-drain contact are located on opposite sides of the semiconductor device, wherein a dielectric spacer surrounds opposite vertical side surfaces of the bottom source-drain contact, wherein the dielectric spacer overlaps the vertical side surface and the lower horizontal surface of the bottom isolation region, and wherein a width of the bottom source-drain contact is wider than a width of the second source-drain.

[0005] According to an embodiment, a method is provided. The method includes: forming a double nanosheet stack on a substrate, forming shallow trench isolation between adjacent double nanosheet stacks, dividing the double nanosheet stack into a first nanosheet stack and a second nanosheet stack, forming shallow trench isolation in the divided double nanosheet stacks, forming a non-doped silicon buffer epitaxial in an opening between and below the first nanosheet stack and the second nanosheet stack, forming a top source-drain contact to an upper horizontal plane of a first source-drain region adjacent to the first nanosheet stack, bonding a carrier wafer to an upper surface of the substrate above the first nanosheet stack and the second nanosheet stack, removing the non-doped silicon buffer epitaxial below the second source-drain region between the first nanosheet stack and the second nanosheet stack, forming a bottom source-drain contact to a lower horizontal plane of the second source-drain region, the bottom source-drain contact being vertically aligned with the second source-drain region, wherein a width of the bottom source-drain contact is wider than a width of the second source-drain region. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] These and other objects, features and advantages of the present invention will become apparent from the following detailed description of illustrative embodiments thereof read in conjunction with the accompanying drawings. The various features of the drawings are not to scale, as for the sake of clarity, the illustrations are intended to facilitate understanding of the present invention by those skilled in the art in conjunction with the detailed description. In the drawings:

[0007] Figure 1 illustrates a top view of a semiconductor structure at an intermediate stage of fabrication according to an exemplary embodiment;

[0008] Figure 2 and Figure 3 Each illustrates a Figure 1 Cross-sectional views of the semiconductor structure along section lines XX and YY respectively;

[0009] Figure 4 and Figure 5 Each illustrates a cross-sectional view of a semiconductor structure according to an exemplary embodiment along section lines XX and YY, respectively, and illustrates the formation of a sacrificial layer and a semiconductor layer;

[0010] Figure 6 and Figure 7 each illustrates a cross-sectional view of a semiconductor structure according to an exemplary embodiment along section lines XX and YY, respectively, and illustrates the formation of a trench;

[0011] Figure 8 and Fig. 9 each illustrating a cross-sectional view of a semiconductor structure according to an exemplary embodiment along section lines XX and YY, respectively, and illustrating the formation of a liner;

[0012] Fig.10 and Fig.11each illustrating a cross-sectional view of a semiconductor structure according to an exemplary embodiment along section lines XX and YY, respectively, and illustrating removal of a portion of a silicon germanium layer;

[0013] Fig.12 and Fig.13 each illustrates a cross-sectional view of a semiconductor structure according to an exemplary embodiment along section lines XX and YY, respectively, and illustrates the formation of shallow trench isolation;

[0014] Fig.14 illustrates a cross-sectional view of a semiconductor structure along a cross-sectional line YY according to an exemplary embodiment, and illustrates the formation of yet another shallow trench isolation;

[0015] Fig.15 and Fig.16 each illustrates a cross-sectional view of a semiconductor structure according to an exemplary embodiment along section lines XX and YY, respectively, and illustrates the formation of a trench;

[0016] Fig.17 illustrates a cross-sectional view of a semiconductor structure along a cross-sectional line XX according to an exemplary embodiment, and illustrates the formation of a sacrificial layer gate and a gate cap;

[0017] Fig.18 and Fig.19 Each illustrates a cross-sectional view of a semiconductor structure according to an exemplary embodiment along section lines XX and YY, respectively, and illustrates removal of a sacrificial layer and formation of a bottom isolation region;

[0018] Fig. 20 and Fig.21 each illustrating a cross-sectional view of a semiconductor structure according to an exemplary embodiment along section lines XX and YY, respectively, and illustrating selective removal of layers and internal spacer formation;

[0019] Fig. 22 and Fig.23 each illustrating a cross-sectional view of a semiconductor structure according to an exemplary embodiment along section lines XX and YY, respectively, and illustrating the formation of an organic planarization layer;

[0020] Fig.24 and Fig.25 each illustrates a cross-sectional view of a semiconductor structure according to an exemplary embodiment along section lines XX and YY, respectively, and illustrates the formation of a backside contact trench;

[0021] Fig.26 and Fig. 27 each illustrates a cross-sectional view of a semiconductor structure according to an exemplary embodiment along section lines XX and YY, respectively, and illustrates the formation of a sacrificial silicon germanium epitaxy;

[0022] Fig.28 and Fig.29 Each illustrates a cross-sectional view of a semiconductor structure according to an exemplary embodiment along section lines XX and YY, respectively, and illustrates the formation of an undoped silicon buffer epitaxy and a source / drain;

[0023] Fig.30 and Fig.31 Each illustrates a cross-sectional view of a semiconductor structure according to an exemplary embodiment along section lines XX and YY, respectively, and illustrates the formation of an interlayer dielectric, the removal of a sacrificial gate, and the formation of a metal gate;

[0024] Fig.32 and Fig.33 each illustrating a cross-sectional view of a semiconductor structure according to an exemplary embodiment along section lines XX and YY, respectively, and illustrating the formation of contacts, the formation of back-end process layers, and the bonding of a carrier wafer to the semiconductor structure;

[0025] Fig.34 and Fig.35 Each illustrates a cross-sectional view of a semiconductor structure according to an exemplary embodiment along section lines XX and YY, respectively, and illustrates flipping of the semiconductor structure and removal of a portion of a substrate of the semiconductor structure;

[0026] Fig.36 and Fig.37 each illustrating a cross-sectional view of a semiconductor structure according to an exemplary embodiment along section lines XX and YY, respectively, and illustrating the formation of an opening;

[0027] Fig.38 and Fig.39 each illustrates a cross-sectional view of a semiconductor structure according to an exemplary embodiment along section lines XX and YY, respectively, and illustrates the removal of a sacrificial silicon germanium epitaxy;

[0028] Fig.40 and Fig.41 each illustrates a cross-sectional view of a semiconductor structure according to an exemplary embodiment along section lines XX and YY, respectively, and illustrates the removal of selected materials to increase an opening;

[0029] Fig.42 and Fig.43 each illustrates a cross-sectional view of a semiconductor structure according to an exemplary embodiment along section lines XX and YY, respectively, and illustrates the formation of an inner liner;

[0030] Fig.44 and Fig.45 each illustrates a cross-sectional view of a semiconductor structure according to an exemplary embodiment along section lines XX and YY, respectively, and illustrates the removal of an undoped silicon buffer epitaxy;

[0031] Fig.46 and Fig.47 each illustrating a cross-sectional view of a semiconductor structure according to an exemplary embodiment along section lines XX and YY, respectively, and illustrating the formation of a backside contact; and

[0032] Fig.48 and Fig.49 Each illustrates a cross-sectional view of a semiconductor structure along section lines XX and YY, respectively, according to an exemplary embodiment, and illustrates forming an interlayer dielectric, a backside power rail, and a backside power distribution network.

[0033] It should be understood that for simplicity and clarity of illustration, the elements shown in the figures are not necessarily drawn to scale. For example, for clarity, the size of some elements may be enlarged relative to other elements. In addition, where deemed appropriate, reference numerals may be repeated in the drawings to indicate corresponding or similar features. DETAILED DESCRIPTION

[0034] Detailed embodiments of the claimed structures and methods are disclosed herein; however, it is understood that the disclosed embodiments are merely illustrative of the claimed structures and methods that may be implemented in various forms. However, the present invention may be implemented in many different forms and should not be construed as limited to the exemplary embodiments set forth herein. In the description, details of well-known features and techniques may be omitted to avoid unnecessarily obscuring the presented embodiments.

[0035] References in the specification to "one embodiment," "an embodiment," "an example embodiment," etc. indicate that the described embodiment may include a particular feature, structure, or characteristic, but every embodiment may not necessarily include the particular feature, structure, or characteristic. Furthermore, these phrases do not necessarily refer to the same embodiment. Furthermore, when a particular feature, structure, or characteristic is described in conjunction with an embodiment, it is considered to be within the knowledge of those skilled in the art to affect such feature, structure, or characteristic in conjunction with other embodiments, whether or not explicitly described.

[0036] It should be understood that when an element as a layer, region, or substrate is referred to as being "on" or "above" another element, it can be directly on the other element, or there can be intervening elements. Conversely, when an element is referred to as being "directly on" or "directly above" another element, there are no intervening elements. It will also be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element, or there can be intervening elements. Conversely, when an element is referred to as being "directly connected" or "directly coupled" to another element, there are no intervening elements.

[0037] In order not to obscure the presentation of embodiments of the present invention, in the following detailed description, some processing steps or operations known in the art may be combined together for presentation and for illustration purposes, and may not be described in detail in some instances. In other cases, some processing steps or operations known in the art may not be described at all. It should be understood that the following description is more focused on the distinguishing features or elements of various embodiments of the present invention.

[0038] A nanosheet field effect transistor (hereinafter referred to as a "FET") can be formed. A stacked nanosheet layer is formed on a substrate, and mutually parallel grooves are formed in the stacked nanosheet layer to form a double-width fin and a shallow trench isolation region formed between the double-width fins. A groove is formed in each double-width fin to divide it into two fins, and a shallow trench isolation region is formed between the two fins. A sacrificial gate is then formed perpendicular to the groove. An additional groove perpendicular to the original groove is formed between the sacrificial gates. A dielectric spacer surrounding the nanosheet stack and a bottom isolation region formed below the nanosheet stack can be formed. The outer portion of the sacrificial layer of the stacked nanosheet can be removed, and an internal spacer is formed at a position where the outer portion of the sacrificial layer of the stacked nanosheet is removed. In an embodiment of the present invention, the groove can extend into the substrate, and a sacrificial layer is formed in a portion of the groove in the substrate. The groove can be formed at a position where a backside contact to the source drain can be formed later. Undoped silicon buffer epitaxy can be formed between adjacent nanosheet stacks. A source drain region of a positive FET (p-FET) or a negative FET (n-FET) is formed extending from the exposed channel layer of the nanosheet stack. The sacrificial gate is removed, and the remaining portion of the sacrificial layer is removed. A metal gate can be formed around the channel layer at the location where the sacrificial gate and the remaining portion of the sacrificial layer were removed. Contacts can be formed to the metal gate and to each source drain, specifically, to source drain regions that do not have a sacrificial layer below the source drain. Back end of line (BEOL) layers of wiring and vias can be further formed.

[0039] Embodiments of forming a backside contact may include bonding a carrier substrate to an upper surface of a formed nanosheet FET with BEOL layers, above the BEOL layers; turning the structure upside down, then forming a backside opening above a sacrificial layer and removing the sacrificial layer. A self-aligned sacrificial backside contact in the opening may be formed through the backside opening to the source drain. Additional layers of lines and vias may be formed above and connected to the backside contacts.

[0040] There are several advantages to forming self-aligned sacrificial backside contacts, including the flexibility of forming source drain contacts from above or below the structure, and forming contacts with greater spacing because fewer contacts may be required overall on the nanosheet device. Having self-aligned contacts is an additional advantage due to the relative backside lithography alignment accuracy compared to frontside lithography due to wafer distortion or thickness inconsistencies. Self-aligned contacts are formed by forming sacrificial backside contact placeholders below the source drain epitaxy so that the position of the backside contact is predefined and the formation is no longer dependent on the coverage performance of the backside lithography process.

[0041] The present invention relates generally to the field of semiconductor manufacturing and, more particularly, to backside contacts.

[0042] Reference now Figure 1 , Figure 2 and Figure 3 , illustrates a semiconductor structure 200 (hereinafter “structure”) at an intermediate stage of fabrication according to an exemplary embodiment. Figure 1 is a top view of structure 200 . Figure 2 is a cross-sectional view of the structure 200 along the section line XX; Figure 3 is a cross-sectional view of the structure 200 along the section line YY and perpendicular to the section line XX. Figure 1 Structure 200.

[0043] The structure 200 may include a substrate 202 , a silicon germanium layer 204 on the substrate 202 , and a thin silicon layer 206 on the silicon germanium layer 204 .

[0044] Substrate 202 may be, for example, a bulk substrate that may be made of any of several known semiconductor materials, such as, for example, silicon, germanium, silicon-germanium alloys, and compound (e.g., III-V and II-VI) semiconductor materials. Non-limiting examples of compound semiconductor materials include gallium arsenide, indium arsenide and indium phosphide, or indium gallium arsenide. Typically, substrate 202 may be approximately, but not limited to, several hundred microns thick.

[0045] Silicon germanium layer 204 may be epitaxially grown and conformally cover the upper surface of substrate 202 on structure 200. Silicon germanium layer 204 may be, for example, silicon germanium having a germanium concentration of approximately 30 atomic percent, although percentages greater than 30% and less than 30% may be used.

[0046] The terms "epitaxial growth and / or deposition" and "epitaxially grown and / or deposited" refer to growing semiconductor material on a deposition surface of the semiconductor material, wherein the grown semiconductor material has the same crystal properties as the semiconductor material of the deposition surface. In epitaxial deposition techniques, the chemical reactants provided by the source gases are controlled and the system parameters are set so that the deposited atoms arrive at the deposition surface of the semiconductor substrate with sufficient energy to move around on the surface and orient themselves to the crystal arrangement of atoms of the deposition surface. Thus, the epitaxial semiconductor material has the same crystal properties as the deposition surface on which the epitaxial semiconductor material is formed.

[0047] Examples of various epitaxial growth techniques include, for example, rapid thermal chemical vapor deposition (RTCVD), low energy plasma deposition (LEPD), ultra-high vacuum chemical vapor deposition (UHVCVD), low pressure chemical vapor deposition (LPCVD), atmospheric pressure chemical vapor deposition (APCVD), and molecular beam epitaxy (MBE). The temperature of epitaxial deposition is generally in the range of about 550° C. to about 900° C. Although higher temperatures generally result in faster deposition, faster deposition may result in crystal defects and film cracking.

[0048] The thin silicon layer 206 may be epitaxially grown and conformally cover the upper surface of the silicon germanium layer 206 .

[0049] Reference now Figure 4 and Figure 5 , shows a structure 200 according to an exemplary embodiment. Figure 4 and Figure 5 Each is a cross-sectional view of the structure 200 along the section lines XX and YY, respectively. Figure 4 and Figure 5 A stacked sacrificial layer 208 may be formed, and stacked nanosheets may be formed.

[0050] The stacked sacrificial layer 208 may be, for example, silicon germanium having a germanium concentration of about 55 atomic percent, although percentages greater than 55% and less than 55% may be used. The stacked sacrificial layer 208 may be epitaxially grown on the structure 200 .

[0051] The alternating layers of sacrificial semiconductor material and semiconductor channel material may be collectively referred to as stacked nanosheets. The alternating layers of sacrificial semiconductor material and semiconductor channel material may include a sacrificial semiconductor material layer 210 (hereinafter referred to as a "sacrificial layer"), which is covered by a semiconductor channel material layer 212 (hereinafter referred to as a "channel layer"), which is covered by the sacrificial layer 210, which is covered by the channel layer 212, which is covered by the sacrificial layer 210, which is covered by the channel layer 212.

[0052] The alternating layers of sacrificial layer 210 and channel layer 212 can be formed by sequential epitaxial growth of alternating layers of a first semiconductor material and a second semiconductor material on a substrate, wherein the alternating layers of the first semiconductor material and the second semiconductor material are stacked one on top of the other. It should be noted that although a limited number of alternating layers are described, any number of alternating layers can be formed. The epitaxial growth of the first and second semiconductor materials that provide the sacrificial semiconductor material layer and the semiconductor channel material layer, respectively, can be performed using any well-known precursor gas or gas mixture. Carrier gases such as hydrogen, nitrogen, helium, and argon can be used.

[0053] Each sacrificial layer 210 is composed of a first semiconductor material that is different in composition from at least the upper portion of the thin silicon layer 206, the channel layer 212, and the stacked sacrificial layer 208. In an embodiment, each sacrificial layer 210 may be a silicon-germanium semiconductor alloy and have a germanium concentration of less than 50 atomic percent. In another example, each sacrificial layer 210 may have a germanium concentration ranging from about 20 atomic percent to about 40 atomic percent. Each sacrificial layer 210 may be formed using known deposition techniques or epitaxial growth techniques as described above.

[0054] Each channel layer 212 is composed of a second semiconductor material that is different in composition from at least the upper portion of the thin silicon layer 206, the sacrificial layer 210, and the stacked sacrificial layer 208. Each channel layer 212 has an etch rate different from the first semiconductor material of the sacrificial layer 210, and has an etch rate different from the stacked sacrificial layer 208. The second semiconductor material can be, for example, silicon. The second semiconductor material for each channel layer 212 can be formed using known deposition techniques or epitaxial growth techniques as described above.

[0055] The sacrificial layer 210 may have a thickness ranging from about 5 nm to about 15 nm, and the channel layer 212 may have a thickness ranging from about 4 nm to about 12 nm. Each sacrificial layer 210 may have a thickness that is the same as or different from the thickness of each channel layer 212. In one embodiment, each sacrificial layer 210 has the same thickness. In one embodiment, each channel layer 212 has the same thickness. The stacked sacrificial layers 208 may each have a thickness ranging from about 5 nm to about 12 nm.

[0056] Each channel layer 212 is composed of a second semiconductor material that is different in composition from at least the upper portion of the thin silicon layer 206, the silicon germanium layer 204, the sacrificial layer 210, and the stacked sacrificial layer 208. Each channel layer 212 has a different etching rate than the first semiconductor material of the sacrificial layer 210, and has a different etching rate than the stacked sacrificial layer 208.

[0057] Reference now Figure 6 and Figure 7 , shows a structure 200 according to an exemplary embodiment. Figure 6 and Figure 7 Each is a cross-sectional view of the structure 200 along the section lines XX and YY, respectively. Figure 6 and Figure 7 A hard mask 214 may be formed. A trench 216 may be formed to separate the structure 200 into the region 201 and the region 203.

[0058] A hard mask 214 may be conformally formed on the structure 200 by methods known in the art. The stacked sacrificial layer 208 and the alternating layers of the sacrificial layer 210 and the channel layer 212 may be formed into a double-width fin by methods known in the art. The double-width fin may be further divided into two separate fins in subsequent processing steps. The double-width fin may have a length perpendicular to the cross-sectional line YY and parallel to the cross-sectional line XX. The fin may be formed by methods known in the art and include steps such as forming a hard mask on the alternating layers, patterning the hard mask, and then forming one or more grooves 216 by removing portions of each layer of the stacked nanosheets. The grooves 216 may be formed into a double-width fin by an anisotropic etching technique, such as, for example, reactive ion etching (RIE), and stopping when etching a portion of the thin silicon layer 206 between each nanosheet stack.

[0059] Each double-wide fin of the nanosheet stack may include a stacked sacrificial layer 208, which is covered by a sacrificial layer 210, which is covered by a channel layer 212, which is covered by a sacrificial layer 210, which is covered by a channel layer 212, which is covered by a sacrificial layer 210, which is covered by a channel layer 212, which is covered by a hard mask 214. For illustration, two double-wide fins are depicted in the drawings of the present application, but any number of fins may be formed.

[0060] The material stacks that can be used in embodiments of the present invention are not limited to Figure 6 and Figure 7 The specific embodiment shown in FIG. Figure 6 and Figure 7 , and by way of example only, the nanosheet stack includes three sacrificial layers 210 alternating with three channel layers 212. The nanosheet stack may include any number of sacrificial layers 210 and channel layers 212. The nanosheet stack is used to fabricate a gate-all-around device that includes vertically stacked nanosheets of semiconductor channel material for a p-FET or n-FET.

[0061] In an embodiment, the double-width fins of region 201 may be formed as p-FET nanosheets, while the double-width fins of region 203 may be formed as n-FET nanosheets. The trenches 216 may separate the p-FET nanosheets from the n-FET nanosheets. Alternatively, the trenches 216 may separate adjacent p-FET nanosheets or may separate adjacent n-FET nanosheets.

[0062] Reference now Figure 8 and Fig. 9 , shows a structure 200 according to an exemplary embodiment. Figure 8 and Fig. 9 Each is a cross-sectional view of the structure 200 along the section lines XX and YY, respectively. Figure 8 and Fig. 9 A liner 218 may be formed, and the groove 216 may be enlarged.

[0063] The liner 218 may be conformally formed on the structure 200, followed by an anisotropic etching technique to remove the horizontal portion of the liner 218 and deepen the trench 216 until it is etched into the substrate 202. The liner 218 may cover the vertical surface of the hard mask 214 and the vertical side surface of the channel layer 212, the sacrificial layer 210, and a portion of the vertical side surface of the stacked sacrificial layer 206. The liner 218 may be deposited using typical deposition techniques, such as atomic layer deposition (ALD), molecular layer deposition (MLD), chemical vapor deposition (CVD), physical vapor deposition (PVD), and spin coating techniques. In one embodiment, the liner 218 may include SiO2, SiN, SiC, AlOx, TiN, TiOx, etc. In one embodiment, the liner 218 may have a thickness of about 2nm to 20nm, and varies therebetween, although thicknesses less than 2nm and greater than 20nm are also acceptable.

[0064] The liner 218 can protect the sacrificial layer 210 and the channel layer 212 of the nanosheet stack from being subsequently damaged. The trench 216 can be enlarged by removing the vertically aligned portion of the thin silicon layer 206, the silicon germanium layer 204, and a portion of the substrate 202. The trench 216 can be enlarged by methods known in the art. In one embodiment, the trench 216 can be enlarged by an anisotropic etching technique, such as, for example, reactive ion etching (RIE).

[0065] Reference now Fig.10 and Fig.11 , shows a structure 200 according to an exemplary embodiment. Fig.10 and Fig.11 Each is a cross-sectional view of the structure 200 along the section lines XX and YY, respectively. Fig.10 and Fig.11 The silicon germanium layer 204 may be recessed.

[0066] The silicon germanium layer 204 can be recessed by methods known in the art. For example, a dry etching technique can be used to selectively remove portions of the silicon germanium layer 204, such as, for example, dry etching using gas phase HCl. The silicon germanium layer 204 can be selectively recessed to the substrate 202, the thin silicon layer 206, the channel layer 212, the sacrificial layer 210, the stacked sacrificial layer 206, and the liner 218.

[0067] Reference now Fig.12 and Fig.13 , shows a structure 200 according to an exemplary embodiment. Fig.12 and Fig.13 Each is a cross-sectional view of the structure 200 along the section lines XX and YY, respectively. Fig.12 and Fig.13 perpendicular to each other. The liner 218 may be removed. The liner 222 may be formed. The shallow trench isolation (hereinafter referred to as "STI") 224 may be formed.

[0068] The liner 218 may be removed using methods known in the art. The liner 218 may be removed selectively to the hard mask 218, the channel layer 212, the sacrificial layer 210, the stacked sacrificial layer 208, the thin silicon layer 206, the silicon germanium layer 204, and the substrate 202.

[0069] The liner 222 may be conformally formed on the structure 200. The liner 222 may cover the upper horizontal and vertical surfaces of the hard mask 214 and the vertical side surfaces of the channel layer 212, the sacrificial layer 210, the thin silicon layer 206, the silicon germanium layer 204, and the stacked sacrificial layer 208, the vertical side surfaces and a portion of the lower horizontal surface of the thin silicon layer 206, and the vertical side surfaces and upper horizontal surface of the silicon germanium layer 204. The liner 222 may be deposited using typical deposition techniques, such as atomic layer deposition (ALD), molecular layer deposition (MLD), chemical vapor deposition (CVD), physical vapor deposition (PVD), and spin coating techniques. In one embodiment, the liner 222 may include SiN, SiBCN, SiOCN, SiOC, etc. In one embodiment, the liner 222 may have a thickness of about 3 nm to 20 nm, and varies therebetween, although thicknesses less than 3 nm and greater than 20 nm are also acceptable.

[0070] The STI 224 may be conformally formed on the structure 200. The STI 224 may fill the space between adjacent double-wide fins of the structure 200. The STI may fill the space between the pads 222, wherein the pads 222 cover the double-wide fins.

[0071] STI 224 can be a dielectric material and can be formed using known deposition, planarization and etching techniques. STI 224 can be formed by conformal deposition of dielectric material, followed by a combination of dry and wet anisotropic etching and recessing steps. STI 224 can be deposited using typical deposition techniques, such as atomic layer deposition (ALD), molecular layer deposition (MLD), chemical vapor deposition (CVD), physical vapor deposition (PVD), high density plasma (HDP) deposition and spin coating techniques, followed by an anisotropic vertical etching process, such as reactive ion etching (RIE) or any suitable etching process. In one embodiment, STI 224 can each include one or more layers. STI 224 can each include any dielectric material, such as SiO2. The lower horizontal surface of STI 224 can be below a portion of the upper horizontal surface of substrate 202.

[0072] Chemical mechanical polishing (CMP) techniques may be used to remove excess material and polish the upper surface of structure 200 to expose the upper horizontal surfaces of hard mask 214 , liner 222 , and STI 224 .

[0073] Reference now Fig.14 , shows a structure 200 according to an exemplary embodiment. Fig.14 is a cross-sectional view of the structure 200 along the section line YY. Fig.12 The process steps remain unchanged for the double-width fins. The double-width fins can be repeated using another photolithography mask. Figures 6 to 13 The remaining portion of the silicon germanium layer 204 may be removed.

[0074] A trench (not shown) may be formed longitudinally in the double-wide fin. A liner 222 may be formed in the trench (not shown). An STI 224 may be formed within the liner 222. A CMP may be performed. The structure 200 may no longer have a double-wide fin. The structure 200 may now have fins of nanosheet stacks isolated from each other by the STI 224.

[0075] Reference now Fig.15 and Fig.16 , shows a structure 200 according to an exemplary embodiment. Fig.15 and Fig.16 Each is a cross-sectional view of the structure 200 along the section lines XX and YY, respectively. Fig.15 and Fig.16 The portions of the liner 222 and the STI 224 are removed. The hard mask 214 is removed.

[0076] Relative to the hard mask 214, the channel layer 212, the sacrificial layer 210, the stacked sacrificial layer 208, and the thin silicon layer 206, a portion of the liner 222 and a portion of the STI 224 are selectively removed. The portion of the liner 222 and the portion of the STI 224 can be selectively removed by methods known in the art. For example, an isotropic wet or dry etching process. A portion of the vertical side surfaces of the channel layer 212, the sacrificial layer 210, the stacked sacrificial layer 208, and the vertical side surfaces of the thin silicon layer 206 can be exposed. In one embodiment, the upper surface of the liner 222 and the upper surface of the STI 224 can be aligned with the upper surface of the thin silicon layer 206. The STI 224 and the STI liner 222 remain in the thin silicon layer 206, between adjacent nanosheet stacks, providing physical and electrical isolation between adjacent nanosheet stacks.

[0077] Region 201 illustrates two p-FET nanosheet fins and region 203 illustrates two n-FET nanosheet fins. There may be any number of nanosheet fins in region 201 or region 203.

[0078] Reference now Fig.17 , shows a structure 200 according to an exemplary embodiment. Fig.17 is a cross-sectional view of the structure 200 along the section line XX. Fig.16 The process steps remain unchanged. A sacrificial gate 226 and a gate cap 228 may be formed.

[0079] A sacrificial gate 226 and a gate cap 228 are formed orthogonal (perpendicular) to the fin. As an illustration, three sacrificial gates 226 are depicted in the drawings of the present application, but any number of sacrificial gates 226 may be formed. The sacrificial gate 226 may include a single sacrificial material or a stack of two or more sacrificial materials. The at least one sacrificial material may be formed by forming a blanket layer (or a plurality of layers) of a material (or a variety of materials) and then patterning the material (or a variety of materials) by photolithography and etching. The sacrificial gate 226 may include any material, including, for example, polycrystalline silicon, amorphous silicon, or a multilayer combination thereof. In one embodiment using amorphous silicon as the material of the sacrificial gate 226, a thin layer of SiO2 is first deposited to separate the nanosheet stack from the amorphous silicon. The sacrificial gate 226 may be formed using any deposition technique, including, for example, chemical vapor deposition (CVD), physical vapor deposition (PVD), high density plasma (HDP) deposition, and spin coating techniques. Optionally, a gate cap 228 may be formed as part of the sacrificial gate 226 according to known techniques.

[0080] In one embodiment, the sacrificial gate 226 is deposited to have a thickness sufficient to fill or substantially fill the space between adjacent nanosheet structures and cover the horizontal upper surface of the uppermost channel layer 212 of the nanosheet stack. The sacrificial gate 226 may be adjacent to the vertical side surface of the nanosheet stack or fin. The sacrificial gate 226 may cover the upper horizontal surface of the BOX SiO2104 between adjacent nanosheet stacks. The height of the sacrificial gate 226 may be much thicker than the underlying structure and may have a height between 100nm and 150nm with respect to the nanosheet stack. The gate cap 228 may cover the upper horizontal surface of the sacrificial gate 226. The gate patterning may be performed by conventional photolithography and etching processes so that portions of the gate cap 228 and portions of the sacrificial gate 226 are removed from subsequently formed source and drain regions.

[0081] Reference now Fig.18 and Fig.19 , shows a structure 200 according to an exemplary embodiment. Fig.18 and Fig.19 Each is a cross-sectional view of the structure 200 along the section lines XX and YY, respectively. Fig.18 and Fig.19 The stacked sacrificial layer 208 may be removed. A bottom dielectric isolation 234 (hereinafter referred to as "BDI") and a dielectric spacer 232 may be formed.

[0082] The stacked sacrificial layer 208 may be selectively removed by methods known in the art. For example, a dry etching technique may be used to selectively remove the stacked sacrificial layer 208, such as, for example, dry etching using gaseous HCl. The stacked sacrificial layer 208 may be selectively removed relative to the substrate 202, the thin silicon layer 206, the channel layer 212, the sacrificial layer 210, the sacrificial gate 226, and the gate cap 228.

[0083] BDI 234 may be formed where the stack sacrificial layer 208 is removed. BDI 234 may be formed below the lowermost sacrificial layer 210 of the nanosheet stack and above the thin silicon layer 206. This may be achieved by first conformally depositing a BDI dielectric liner and then isotropically etching back the dielectric liner.

[0084] Dielectric spacers 232 may be formed on vertical side surfaces of the nanosheet stack, including vertical side surfaces of the channel layer 210 and vertical side surfaces of the sacrificial layer 212. Dielectric spacers 232 may be formed on vertical side surfaces of the sacrificial gate 226 and the gate cap 228.

[0085] The BDI 234 and the dielectric spacer 232 may be formed by conformal deposition of dielectric material followed by a combination of dry and wet anisotropic etching and recessing steps. The BDI 234 and the dielectric spacer 232 may be formed simultaneously or sequentially. The BDI 234 and the dielectric spacer 232 may be deposited using typical deposition techniques, such as atomic layer deposition (ALD), molecular layer deposition (MLD), chemical vapor deposition (CVD), physical vapor deposition (PVD), high density plasma (HDP) deposition, and spin coating techniques, followed by an anisotropic vertical etching process such as reactive ion etching (RIE) or any suitable etching process. In one embodiment, the BDI 234 and the dielectric spacer 232 may each include one or more layers. BDI 234 and dielectric spacer 232 may each include any dielectric material, such as silicon nitride (SiN), silicon boron carbon nitride (SiBCN), silicon oxide carbon nitride (SiOCN), aluminum oxide (AlOx), SiC, and may include a single layer or may include multiple layers of dielectric material. BDI 234 and dielectric spacer 232 may each include the same material or different materials.

[0086] Reference now Fig. 20 and Fig.21 , shows a structure 200 according to an exemplary embodiment. Fig. 20 and Fig.21 Each is a cross-sectional view of the structure 200 along the section lines XX and YY, respectively. Fig. 20 and Fig.21 A source / drain trench 236 may be formed. An inner spacer 240 may be formed.

[0087] The alternating layers of sacrificial layer 210, channel layer 212, and BDI 234 may be formed into a nanosheet stack by methods known in the art. The source / drain trench 236 may have a length perpendicular to the cross-sectional line XX and parallel to the cross-sectional line YY and perpendicular to the fin. The source / drain trench 236 may be formed between each sacrificial gate 226 with surrounding dielectric spacers 232 by an anisotropic etching technique such as, for example, reactive ion etching (RIE), and stop when etching a portion of the thin silicon layer 206 between each nanosheet stack.

[0088] Each nanosheet stack may include a BDI 234 covered by a sacrificial layer 210, covered by a channel layer 212, covered by a sacrificial layer 210, covered by a channel layer 212, covered by a sacrificial layer 210, covered by a channel layer 212. Above the nanosheet stack is a sacrificial gate 226 and a gate cap 228 with dielectric spacers 232 on opposite vertical sides. The nanosheet stack may be vertically aligned with the dielectric spacers 232 surrounding the sacrificial gate 226 and the gate cap 228.

[0089] like Fig. 20 As shown, portions of the nanosheet stack may be removed between adjacent sacrificial gates 226, gate caps 228, and dielectric spacers 232. Dielectric spacers 232 may remain vertically at locations where the nanosheet stack is removed along section line XX.

[0090] The outer portions of the sacrificial layer 210 may be selectively removed using known techniques. For example, a wet or dry etching process may be used, utilizing appropriate chemistries to remove portions of each sacrificial layer 210. The materials used for the etching process may be selective, such that the channel layer 212, BDI 234, dielectric spacer 232, gate cap 228, sacrificial gate 226, thin silicon layer 206, and substrate 202 remain and are not etched. After etching, the portions of the sacrificial layer 210 covered by the sacrificial gate 226 on the opposite side may remain as part of the nanosheet stack.

[0091] The internal spacer 240 may be formed by conformal deposition or growth of a dielectric material followed by a combination of dry and wet isotropic etching and recessing steps. The internal spacer 240 may be deposited using typical deposition techniques, such as atomic layer deposition (ALD), molecular layer deposition (MLD), chemical vapor deposition (CVD), physical vapor deposition (PVD), high density plasma (HDP) deposition, and spin coating techniques, followed by an isotropic etching process, such as a wet etching process, or any suitable etching process. In one embodiment, the internal spacer 240 may include one or more layers. In one embodiment, the internal spacer 240 may include any dielectric material, such as silicon oxynitride, silicon nitride, SiBCN, SiOC, or any combination of these materials.

[0092] The inner spacers 240 may completely fill the spaces between the channel layers 212 where portions of the sacrificial layers 210 have been previously removed.

[0093] Vertical side surfaces of the inner spacer 240 may be aligned with vertical side surfaces of the channel layer 212 and vertical side surfaces of the dielectric spacer 232 surrounding the sacrificial gate 226 and the gate cap 228 .

[0094] Reference now Fig. 22 and Fig.23 , shows a structure 200 according to an exemplary embodiment. Fig. 22 and Fig.23 Each is a cross-sectional view of the structure 200 along the section lines XX and YY, respectively. Fig. 22 and Fig.23A liner 244 may be formed. A photolithography soft mask such as an organic planarization layer 246 (hereinafter referred to as “OPL”) that may be used for a patterning process may be formed. A backside contact trench 248 may be formed.

[0095] The liner 244 may be conformally formed on the structure 200. The liner 244 may cover the upper horizontal surface of the gate cap 228 and the dielectric spacer 232. The liner 244 may cover the dielectric spacer 232, the channel layer 212, the sacrificial layer 210, the thin silicon layer 206, the vertical side surface of the silicon germanium layer 204, a portion of the vertical side surface and the lower horizontal surface of the stacked sacrificial layer 206, and the vertical side surface and the upper horizontal surface of the silicon germanium layer 204. The liner 222 may be deposited using typical deposition techniques, such as atomic layer deposition (ALD), molecular layer deposition (MLD), chemical vapor deposition (CVD), physical vapor deposition (PVD), and spin coating techniques. In one embodiment, the liner 222 may include materials such as SiO2, SiN, SiOC, SiC, etc. In one embodiment, the liner 222 may have a thickness of about 3 nm to 20 nm, and varies therebetween, although thicknesses less than 3 nm and greater than 20 nm are also acceptable.

[0096] OPL 246 may be formed by blanket deposition using typical deposition techniques, such as spin coating. OPL 246 may be a self-planarizing organic material including carbon, hydrogen, oxygen, and optionally nitrogen, fluorine, and silicon. OPL 246 may be a standard C x H y Polymer. Non-limiting examples of materials include, but are not limited to, CHM701B (commercially available from Cheil Chemical Co., Ltd), HM8006 and HM8014 (commercially available from JSR Corporation), and ODL-102 or ODL-401 (commercially available from ShinEtsu Chemical, Co., Ltd).

[0097] A dry etching technique may be used to selectively remove vertically aligned portions of the OPL 246 to form the backside contact trench 248. A wet etching or dry ashing technique may be used to selectively remove the OPL 246 relative to the substrate 202, the thin silicon layer 206, the sacrificial layer 210, the channel layer 212, the sacrificial gate 226, the gate cap 228, the BDI 234, the inner spacer 240, and the dielectric spacer 232. The lower surface and vertical side surfaces of the sacrificial backside contact placeholder 136 may be the dielectric spacer 232.

[0098] Reference now Fig.24 and Fig.25 , shows a structure 200 according to an exemplary embodiment. Fig.24 and Fig.25 Each is a cross-sectional view of the structure 200 along the section lines XX and YY, respectively. Fig.24 and Fig.25 The back side contact trench 248 may be enlarged.

[0099] like Fig.24 As shown in cross-sectional line XX of FIG. 67 , a backside contact trench 248 may be formed above adjacent nanosheet stacks between an adjacent pair of sacrificial gates 226, gate caps 228, and dielectric spacers 232 surrounding each sacrificial gate 226. As shown in cross-sectional line YY of FIG. 67 , a backside contact trench 248 may be formed between a pair of dielectric spacers 232 at a location where a portion of the nanosheet stack between adjacent sacrificial gates 226 is removed.

[0100] The backside contact trench 248 may be formed by an anisotropic etching technique such as, for example, reactive ion etching (RIE), removing an aligned portion of the liner 244 and stopping when etching a portion of the thin silicon layer 206 .

[0101] The backside contact trench 248 can facilitate the formation of a self-aligned backside contact. The backside contact trench 248 can be formed in selected areas of the structure 200 where future bottom contacts can be formed to subsequently formed source drains. There can be one or more backside contact trenches 248 on the structure 100.

[0102] Reference now Fig.26 and Fig. 27 , shows a structure 200 according to an exemplary embodiment. Fig.26 and Fig. 27 Each is a cross-sectional view of the structure 200 along the section lines XX and YY, respectively. Fig.26 and Fig. 27 A sacrificial layer, such as sacrificial silicon germanium epitaxy 249 , may be formed in a portion of the backside contact trench 248 .

[0103] A sacrificial silicon germanium epitaxy 249 may be formed in the backside contact trench 248, filling a portion of the backside contact trench 248. A lower surface of the sacrificial silicon germanium epitaxy 249 may be adjacent to an upper surface of the thin silicon layer 206. A vertical side surface of the sacrificial silicon germanium epitaxy 249 may be adjacent to a vertical side surface of the thin silicon layer 206. A portion of the vertical side surface of the sacrificial silicon germanium epitaxy 249 may be adjacent to a portion of a vertical side surface of the dielectric spacer 232 surrounding the backside contact trench 248.

[0104] The sacrificial silicon germanium epitaxy 249 may be formed by epitaxial growth. In one embodiment, the sacrificial silicon germanium epitaxy 249 may be SiGe, a III-V semiconductor, or other materials that may be formed by deposition and recessing, such as AlOx, TiOx, SiC, etc.

[0105] Reference now Fig.28 and Fig.29 , shows a structure 200 according to an exemplary embodiment. Fig.28 and Fig.29 Each is a cross-sectional view of the structure 100 along the section lines XX and YY, respectively. Fig.28 and Fig.29 OPL 246 and liner 244 may be removed. Undoped silicon buffer epitaxy 250 may be formed. P-FET source drain epitaxy 252 may be formed. N-FET source drain epitaxy 254 may be formed.

[0106] OPL 246 and liner 244 may be selectively removed relative to substrate 202 , thin silicon layer 206 , STI liner 222 , STI 224 , dielectric spacer 232 , channel layer 212 , sacrificial layer 210 , inner spacer 240 , BDI 234 , and sacrificial silicon germanium epitaxy 249 using wet etching or dry ashing techniques.

[0107] The non-doped silicon buffer epitaxy 250 may be epitaxially grown around the vertical portion of the nanosheet stack on the opposite side of the sacrificial gate 226, filling a portion of the back contact trench 248. The lower surface of the non-doped silicon buffer epitaxy 250 may be adjacent to the upper surface of the thin silicon layer 206. The lower surface of the non-doped silicon buffer epitaxy 250 may be adjacent to the upper surface of the sacrificial silicon germanium epitaxy 249. The vertical side surfaces of the non-doped silicon buffer epitaxy 250 may be adjacent to the vertical side surfaces of the inner spacer 240, the vertical side surfaces of the BDI 234, and the vertical side surfaces of the channel layer 212. The non-doped silicon buffer epitaxy 250 may be non-doped. The upper surface of the non-doped silicon buffer epitaxy 250 may be at a greater distance from the upper surface of the thin silicon layer 206 than from the upper surface of the BDI 234.

[0108] The n-FET source drain epitaxy 254 may be epitaxially grown around the vertical portion of the nanosheet stack on the opposite side of the sacrificial gate 226, filling a portion of the opening 248 in the region 203. The lower surface of the n-FET source drain epitaxy 254 may be adjacent to the upper surface of the undoped silicon buffer epitaxy 250. The vertical side surfaces of the n-FET source drain epitaxy 254 may be adjacent to the vertical side surfaces of the inner spacer 240, the vertical side surfaces of the BDI 234, and the vertical side surfaces of the channel layer 212. The upper surface of the n-FET source drain epitaxy 254 may be at a greater distance from the thin silicon layer 206 than from the upper surface of the uppermost channel layer 212.

[0109] The p-FET source drain epitaxy 252 may be epitaxially grown around the vertical portion of the nanosheet stack on the opposite side of the sacrificial gate 226, filling a portion of the opening 248 in the region 201. The lower surface of the p-FET source drain epitaxy 252 may be adjacent to the upper surface of the undoped silicon buffer epitaxy 250. The vertical side surfaces of the p-FET source drain epitaxy 252 may be adjacent to the vertical side surfaces of the inner spacer 240, the vertical side surfaces of the BDI 234, and the vertical side surfaces of the channel layer 212. The upper surface of the p-FET source drain epitaxy 252 may be at a greater distance from the thin silicon layer 206 than from the upper surface of the uppermost channel layer 212.

[0110] An advantage of forming the undoped silicon buffer epitaxy 250 beneath both the p-FET source drain epitaxy 252 and the n-FET source drain epitaxy 254 is that it enables the sacrificial silicon germanium epitaxy 249 to be selectively removed from the back side of the wafer at a subsequent stage of manufacturing without damaging the p-FET source drain epitaxy 252 or the n-FET source drain epitaxy 254, especially the p-FET source drain epitaxy 252 which may include similar silicon germanium.

[0111] Reference now Fig.30 and Fig.31 , shows a structure 200 according to an exemplary embodiment. Fig.30 and Fig.31 Each is a cross-sectional view of the structure 100 along the section lines XX and YY, respectively. Fig.30 and Fig.31 perpendicular to each other. An interlayer dielectric (hereinafter referred to as "ILD") 260 may be formed. Gate cap 228 and sacrificial gate 226 may be removed. Sacrificial layer 210 may be removed. A high-k metal gate 264 may be formed.

[0112] ILD 260 can be formed by conformal deposition or growth of dielectric material. ILD 260 can be deposited using typical deposition techniques, such as atomic layer deposition (ALD), molecular layer deposition (MLD), chemical vapor deposition (CVD), physical vapor deposition (PVD), high density plasma (HDP) deposition and spin coating techniques, followed by a planarization process, such as CMP, or any suitable etching process. In one embodiment, ILD 260 may include one or more layers. In one embodiment, ILD 260 may include any dielectric material, such as silicon oxide, silicon oxynitride, silicon nitride, SiBCN, SiOC, low-k dielectrics, or any combination of these materials. The lower surface of ILD 260 may be adjacent to the upper surface of p-FET source drain epitaxy 252 and the upper surface of n-FET source drain epitaxy 254. The other lower surface of ILD 260 may be adjacent to the upper surface of STI 224. The vertical side surface of ILD 260 may be adjacent to the vertical side surface of dielectric spacer 232.

[0113] Chemical mechanical polishing (CMP) techniques may be used to remove excess material and polish the upper surface of structure 200, removing gate cap 228 and exposing the upper horizontal surface of sacrificial gate 226. The upper surface of structure 200 may also include the upper horizontal surface of ILD 260 and the upper horizontal surface of dielectric spacer 232.

[0114] The sacrificial gate 226 may be removed by methods known in the art. The sacrificial layer 210 is selectively removed relative to the channel layer 212, the inner spacer 240, the ILD 260, the dielectric spacer 232, the BDI 234, the sacrificial backside contact placeholder 249, the thin silicon layer 206, the silicon germanium layer 204, and the substrate 202. For example, a dry etching process may be used to selectively remove the sacrificial layer 210, such as dry etching using gaseous HCl. The upper and lower surfaces of the channel layer 212 may be exposed. The upper surface of the BDI 234 may be exposed.

[0115] According to an exemplary embodiment, a high-k metal gate 264 may be conformally formed on the structure 200. The high-k metal gate 264 is formed in each cavity of the nanosheet stack and surrounds the suspended portion of the channel layer 212. The high-k metal gate 264 forms a layer around the exposed portion of the nanosheet stack. The high-k metal gate 264 may cover the exposed vertical side surface of one side of the side spacer 240, the exposed vertical surface of one side of the dielectric spacer 232, and the exposed upper horizontal surface of the BDI 234. The high-k metal gate 264 may cover the vertical side surface, the upper horizontal surface, and the lower horizontal surface of the channel layer 210. The high-k metal gate 264 may fill the space between the dielectric spacers 232 above the nanosheet stack, where the sacrificial gate 226 is removed.

[0116] The high-k metal gate 264 may be deposited using typical deposition techniques, such as atomic layer deposition (ALD), molecular layer deposition (MLD), and chemical vapor deposition (CVD). In one embodiment, the high-k metal gate 264 may include more than one layer, for example, a conformal layer of a high-k dielectric material such as HfO2, ZrO2, La2O3, Al2O3, TiO2, SrTiO3, LaAlO3, Y2O3, HfO x N y 、ZrO x N y 、La2O x N y 、Al2O x N y 、TiO x N y 、SrTiO x N y 、LaAlO x N y 、Y2O x N y 、SiON、SiN x , silicates thereof, and alloys thereof. In one embodiment, the work function metal of the p-FET device in region 201 may include a metal nitride, such as titanium nitride or tantalum nitride, titanium carbide, titanium aluminum carbide, or other suitable materials known in the art. In one embodiment, the work function metal of the n-FET device in region 203 may include, for example, titanium aluminum carbide or other suitable materials known in the art. In one embodiment, the work function metal may include one or more layers to achieve desired device characteristics.

[0117] Chemical mechanical polishing (CMP) techniques may be used to remove excess material and polish the upper surface of structure 200. The upper surface of structure 200 may include an upper horizontal surface of ILD 260, an upper horizontal surface of dielectric spacer 232, and an upper horizontal surface of high-k metal gate 264.

[0118] Reference now Fig.32 and Fig.33 , shows a structure 200 according to an exemplary embodiment. Fig.32 and Fig.33 Each is a cross-sectional view of the structure 100 along the section lines XX and YY, respectively. Fig.32 and Fig.33 An upper contact 266 may be formed. A back end of line (BEOL) layer 268 (hereinafter “BEOL”) may be formed. A carrier wafer 270 may be bonded to the structure 200 .

[0119] Openings (not shown) may be made in structure 200 through ILD 260, exposing the upper horizontal surface of p-FET source drain epitaxy 252 or n-FET source drain epitaxy 254. Upper contacts 266 may be formed in the openings (not shown) to form contacts to p-FET source drain epitaxy 252 or n-FET source drain epitaxy 254. As shown in FIG76 , there are three upper contacts 266. There may be any number of upper contacts 266 on structure 200.

[0120] An upper contact 266 may be made to a p-FET source drain epitaxy 252 or an n-FET source drain epitaxy 254 that does not have a sacrificial backside contact placeholder 249 below the p-FET source drain epitaxy 252 or the n-FET source drain epitaxy 254. The p-FET source drain epitaxy 252 or the n-FET source drain epitaxy 254 with the sacrificial backside contact placeholder 249 may have a bottom contact formed in a subsequent process step. Each of the p-FET source drain 252 or the n-FET source drain 254 may have an upper contact 266 or a bottom contact.

[0121] Chemical mechanical polishing (CMP) techniques may be used to remove excess material and polish the upper surface of structure 200 , exposing the upper horizontal surface of ILD 260 and the upper horizontal surface of upper contacts 266 .

[0122] BEOL layers 268 may include wiring and via layers formed over existing structures, over upper contacts 266 and ILD 260. In one embodiment, BEOL layers 268 may include 12 or more layers of metal lines and vias. BEOL layers 268 may be formed using known techniques.

[0123] A carrier wafer 270 may be attached to the upper surface of structure 200 and mounted on the upper surface of BEOL layer 268. The carrier wafer may be attached using conventional wafer bonding processes such as dielectric-to-dielectric bonding or copper-to-copper bonding processes.

[0124] Reference now Fig.34 and Fig.35 , shows a structure 200 according to an exemplary embodiment. Fig.34 and Fig.35 Each is a cross-sectional view of the structure 200 along the section lines XX and YY, respectively. Fig.34 and Fig.35 The structure 200 may be flipped over and the substrate 202 may be removed.

[0125] The structure 200 may be rotated so that the carrier wafer 270 is now shown at Fig.34 and Fig.35, at the lowest point of the structure, and the (now) lower surface of substrate 202 is shown in the upper layers of the structure for further processing.

[0126] The substrate 202 may be selectively removed using a combination of process steps, such as wafer grinding, CMP, RIE, and wet etching processes. The final stage of the process may include selectively etching any remaining silicon of the substrate 202 to expose the surface of the STI liner 222. The continuous STI liner 222 protects the thin silicon layer 206 from being damaged during the substrate 202 removal process.

[0127] Reference now Fig.36 and Fig.37 , shows a structure 200 according to an exemplary embodiment. Fig.36 and Fig.37 Each is a cross-sectional view of the structure 200 along the section lines XX and YY, respectively. Fig.36 and Fig.37 An interlayer dielectric (hereinafter referred to as "ILD") 274 may be formed. An opening 276 may be formed.

[0128] ILD 274 may be formed as described for ILD 260. A lower surface of ILD 274 may be adjacent to an upper surface of STI liner 222. A vertical side surface of ILD 260 may be adjacent to a vertical side surface of STI liner 222. Chemical mechanical polishing (CMP) techniques may be used to remove excess material and polish the upper surface of structure 200.

[0129] Opening 276 may be formed using known techniques, such as, for example, conventional photolithography followed by an anisotropic etching technique, such as, for example, reactive ion etching (RIE). Opening 276 may be formed by removing an alignment portion of ILD 274, a portion of STI liner 222, a portion of STI 224, and a portion of thin silicon layer 206.

[0130] The opening 276 may expose the (now) upper surface of the sacrificial silicon germanium epitaxy 249. The sacrificial silicon germanium epitaxy 249 may be referred to as a sacrificial backside contact placeholder. There may be more than one sacrificial backside contact placeholder. Each sacrificial backside contact placeholder may be adjacent to an undoped silicon buffer epitaxy 250 adjacent to a p-FET source drain epitaxy 252 or an n-FET source drain epitaxy 254 without an upper contact 266.

[0131] The formation of the backside contacts may have a larger overlay error than the formation of the upper contacts. To compensate for the larger overlay error for aligning and exposing the sacrificial backside contact placeholders, larger openings must be made compared to the openings for the upper contacts.

[0132] Reference now Fig.38 and Fig.39 , shows a structure 200 according to an exemplary embodiment. Fig.38 and Fig.39 Each is a cross-sectional view of the structure 200 along the section lines XX and YY, respectively. Fig.38 and Fig.39 The sacrificial silicon germanium epitaxy 249 may be selectively removed to enlarge the opening 276 .

[0133] Reference now Fig.40 and Fig.41 , shows a structure 200 according to an exemplary embodiment. Fig.40 and Fig.41 Each is a cross-sectional view of the structure 200 along the section lines XX and YY, respectively. Fig.40 and Fig.41 The opening 276 can be further enlarged by selectively etching the surrounding thin silicon layer 206 and the undoped silicon buffer epitaxy 250 .

[0134] The material used in the etching process to enlarge the opening 276 may be selective to remove the exposed portion of the thin silicon layer 206 and a portion of the undoped silicon buffer epitaxy 250 relative to the ILD 274, the STI liner 222, the STI 224, the remaining portion of the thin silicon layer 206, the p-FET source drain epitaxy 252, and the n-FET source drain epitaxy 254. The remaining portion of the undoped silicon buffer epitaxy 250 may be present above the n-FET source drain epitaxy 254 (now).

[0135] Reference now Fig.42 and Fig.43 , shows a structure 200 according to an exemplary embodiment. Fig.42 and Fig.43 Each is a cross-sectional view of the structure 200 along the section lines XX and YY, respectively. Fig.42 and Fig.43 An inner spacer 280 may be formed perpendicular to each other.

[0136] The inner spacer 280 may be formed along the side surface of the opening 276. The inner spacer 280 may be formed as described with respect to the dielectric spacer 232.

[0137] Reference now Fig.44 and Fig.45 , shows a structure 200 according to an exemplary embodiment. Fig.44 and Fig.45 Each is a cross-sectional view of the structure 200 along the section lines XX and YY, respectively. Fig.44 and Fig.45The remaining portion of the undoped silicon buffer epitaxy 250 may be removed, enlarging the opening 276 and exposing the upper surface of the n-FET source drain epitaxy 254 .

[0138] The remaining portion of the undoped silicon buffer epitaxy 250 may be selectively removed. The material used for the etching process may be selective so that the ILD 274, STI liner 222, STI 224, thin silicon layer 206, p-FET source drain epitaxy 252, n-FET source drain epitaxy 254, and dielectric spacer 232 remain without being etched. The lower surface of the undoped silicon buffer epitaxy 250 above the n-FET source drain epitaxy 254 may be exposed.

[0139] Reference now Fig.46 and Fig.47 , shows a structure 200 according to an exemplary embodiment. Fig.46 and Fig.47 Each is a cross-sectional view of the structure 200 along the section lines XX and YY, respectively. Fig.46 and Fig.47 A bottom contact portion 282 may be formed.

[0140] Bottom contact 282 may be formed in opening 276 to form contact to n-FET source drain epitaxy 254. Fig.46 and Fig.47 As shown in FIG. 2 , there is one bottom contact 282 . There may be any number of bottom contacts 282 on the structure 200 .

[0141] Forming the bottom contact 282 includes filling the opening 276 with a highly conductive metal material. For clarity, the separate metal material in the bottom contact 282 is not shown. Although the body of the bottom contact 282 includes a base metal such as Co, Ru, or Mo to reduce its body resistivity, the metal compound directly adjacent to the semiconductor of the n-FET source drain epitaxy 254 (or the semiconductor of the p-FET source drain epitaxy 252) is selected to reduce the contact resistance between the bottom contact 282 and the semiconductor of the n-FET source drain epitaxy 254 (or the semiconductor of the p-FET source drain epitaxy 252). In one embodiment, the metal compound adjacent to the semiconductor of the n-FET source drain epitaxy 254 (or the semiconductor of the p-FET source drain epitaxy 252) is a metal silicide or a germanium silicide. The compound can be produced by reacting a base metal (such as titanium) with the semiconductor of the n-FET source drain epitaxy 254 (or the semiconductor of the p-FET source drain epitaxy 252). Although the metal silicide / germanium silicide is made thin, typically less than 3 nm, it sets the Schottky barrier at the semiconductor-metal interface and ultimately sets the contact resistivity of the interface. The metal silicide / germanium silicide can be separated from the base metal fill of the bottom contact 282 by a thin conductive metal liner (such as a titanium nitride liner). The high concentration of free carriers in the semiconductor of the n-FET source drain epitaxy 254 (or in the semiconductor of the p-FET source drain epitaxy 252) and the low Schottky barrier between the metal silicide / germanide and the semiconductor of the n-FET source drain epitaxy 254 (or in the semiconductor of the p-FET source drain epitaxy 252) enable the backside contact structure to the n-type and p-type semiconductors to have a resistance of about 10 -9 W cm 2 The presence of multiple metal compounds in the bottom contact 282 does not affect its series resistance because the additional interface compounds and liner are made thinner than the basic metal filler and each metal-metal interface resistance is at least one order of magnitude lower than the semiconductor-metal interface resistance.

[0142] The contact resistivity of the n-FET source drain epitaxy 254 (or the semiconductor of the p-FET source drain epitaxy 252) to the metal compound of the adjacent bottom contact 282 may be equal to or less than 1e-9 Ohm cm 2 The volume concentration of free electric carriers (electrons or holes) of the n-FET source-drain epitaxy 254 (or the semiconductor of the p-FET source-drain epitaxy 252) may be equal to or greater than 7e20 cm -3 .

[0143] In contrast, the contact resistivity of the n-FET source drain epitaxy 254 (or the semiconductor of the p-FET source drain epitaxy 252 ) to the contact 282 may be greater than or equal to 2e-9 Ohm cm 2 The volume concentration of free electric carriers (electrons or holes) in the n-FET source-drain epitaxy 254 (or the semiconductor of the p-FET source-drain epitaxy 252) may be less than or equal to 5e20 cm -3 .

[0144] Bottom contact 282 can be made to n-FET source drain epitaxy 254 or p-FET source drain epitaxy 252 without upper contact 266. n-FET source drain epitaxy 254 and p-FET source drain epitaxy 252 can have bottom contact 282 or upper contact 266. This provides more options for source drain contacts. In an example, n-FET source drain epitaxy 254 of an n-FET nanosheet stack can each have an upper contact 266, and p-FET source drain epitaxy 252 of a p-FET nanosheet stack can each have a bottom contact 282. This alternative is also an embodiment.

[0145] Chemical mechanical polishing (CMP) techniques may be used to remove excess material and polish the upper surface of structure 200 . The upper surface of structure 200 may include an upper horizontal surface of bottom contact 282 , an upper horizontal surface of inner spacer 280 , and an upper horizontal surface of ILD 274 .

[0146] Reference now Fig.48 and Fig.49 , shows a structure 200 according to an exemplary embodiment. Fig.48 and Fig.49 Each is a cross-sectional view of the structure 200 along the section lines XX and YY, respectively. Fig.48 and Fig.49 An interlayer dielectric (hereinafter referred to as "ILD") 286 may be formed. A backside power rail (hereinafter referred to as "BPR") including power rails Vss 290 and Vdd 288 and a backside power distribution network (hereinafter referred to as "BSPDN") 292 may be formed.

[0147] ILD 286 may be formed by conformally depositing or growing a dielectric material, as described for ILD 260. The lower surface of ILD 286 may be adjacent to the upper horizontal surface of ILD 274, the upper horizontal surface of inner spacer 280, and the upper horizontal surface of bottom contact 282. Chemical mechanical polishing (CMP) techniques may be used to remove excess material and polish the upper surface of structure 200.

[0148] Vss 290 and Vdd 288 may be formed in openings (not shown) in ILD 286 using known techniques. In one embodiment, Vss 290 and Vdd 288 may be parallel to cross-sectional line XX and perpendicular to cross-sectional line YY. The lower horizontal surface of Vdd 288 may be adjacent to the upper horizontal surface of bottom contact 282. As shown in FIG. 92 , there is one Vss 290 and one Vdd 288, however any number of Vss 290 and Vdd 288 may be present in structure 200.

[0149] BSPDN 292 may be formed over ILD 286 and BPR. BSPDN 292 may include additional wiring and via layers formed over existing structures, over ILD 286 and BPR. In one embodiment, BSPDN 292 may include 12 or more wiring and via layers. BSPDN 292 may be formed using known techniques.

[0150] The resulting structure 200 includes a FET nanosheet with self-aligned backside trench epitaxy that provides contacts with low contact resistivity, providing additional options for forming contacts to the FET nanosheet on the backside of the structure.

[0151] Advantages of structure 200 may include enlarging the backside contact area of ​​contact 282 by selectively etching thin silicon layer 206 laterally without shorting to the gate.

[0152] The description of various embodiments of the present invention has been given for the purpose of illustration, but it is not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope of the invention. The terms used herein are selected to best explain the principles of the embodiments, practical applications, or technical improvements existing in the market, or to enable other persons of ordinary skill in the art to understand the embodiments disclosed herein.

[0153] In a preferred embodiment of the present invention described herein, a semiconductor device is provided, comprising: a first source drain region; a second source drain region; an upper source drain contact, vertically aligned above the first source drain region and electrically connected to the first source drain region; and a bottom source drain contact, vertically aligned below the second source drain region and electrically connected to the second source drain region, wherein the bottom source drain contact and the upper source drain contact are located on opposite sides of the semiconductor device, wherein a dielectric spacer surrounds the relative vertical side surfaces of the bottom source drain contact, wherein the dielectric spacer overlaps the vertical side surfaces and the lower horizontal surface of the bottom isolation region, wherein the width of the bottom source drain contact is wider than the width of the second source drain. The bottom dielectric isolation region may be below the nanosheet stack of the semiconductor device. The dielectric spacer may be between the shallow trench isolation region and the bottom source drain contact. The device may also include a backside power rail below the bottom source drain contact, which is connected to the bottom source drain contact. The device may also include: a backside power distribution network below the backside power rail.

Claims

1. A semiconductor device, comprising: a first source-drain region; a second source drain region; an upper source-drain contact vertically aligned above the first source-drain region and electrically connected to the first source-drain region; as well as a bottom source drain contact vertically aligned below the second source drain region and electrically connected to the second source drain region, wherein the bottom source drain contact and the upper source drain contact are located on opposite sides of the semiconductor device, wherein a dielectric spacer surrounds opposing vertical side surfaces of the bottom source drain contact, The dielectric spacer overlaps the vertical side surfaces and the lower horizontal surface of the bottom isolation region.

2. The semiconductor device according to claim 1, wherein The bottom dielectric isolation region is located below the nanosheet stack of the semiconductor device.

3. The semiconductor device according to claim 1, wherein The dielectric spacer is located between the shallow trench isolation region and the bottom source drain contact.

4. The semiconductor device according to claim 1, further comprising: A backside power rail, located below the bottom source drain contact, is connected to the bottom source drain contact.

5. The semiconductor device according to claim 4, further comprising: A backside power distribution network is located below the backside power rail.

6. A method comprising: forming a double nanosheet stack on a substrate; Forming shallow trench isolation between adjacent double nanosheet stacks; dividing the double nanosheet stack into a first nanosheet stack and a second nanosheet stack; forming shallow trench isolation within the divided double nanosheet stack; forming an undoped silicon buffer epitaxy in the opening between and below the first nanosheet stack and the second nanosheet stack; forming a top source drain contact to an upper horizontal surface of a first source drain region adjacent to the first nanosheet stack; bonding a carrier wafer to an upper surface of the substrate above the first nanosheet stack and the second nanosheet stack; removing the non-doped silicon buffer epitaxy below the second source-drain region between the first nanosheet stack and the second nanosheet stack; as well as forming a bottom source drain contact to a lower horizontal surface of the second source drain region, the bottom source drain contact and the second source drain region being vertically aligned, The width of the bottom source-drain contact is wider than the width of the second source-drain region.

7. The method according to claim 6, wherein The bottom source drain contact includes a vertical side surface adjacent to a vertical side surface of a bottom dielectric isolation region below the second nanosheet stack.

8. The method according to claim 7, wherein The bottom source drain contact includes a vertical side surface adjacent to a vertical side surface of a pad of the second source drain, wherein the pad of the second source drain is located between the second source drain and a work function metal of a gate of the second nanosheet stack.

9. The method according to claim 6, further comprising: The epitaxial region is located between the bottom source-drain contact portion and the second source-drain region.

10. The method according to claim 9, wherein The lower horizontal surface of the epitaxial region is located below a lower horizontal surface of a bottom dielectric isolation region below the second nanosheet stack.

11. The method according to claim 6, further comprising: a buried power rail located above the bottom source drain contact and connected to the bottom source drain contact; as well as A backside power distribution network is located above the buried power rail.

12. The method according to claim 6, further comprising: A bottom dielectric isolation region is located below the first nanosheet stack and below the second nanosheet stack.

13. The method according to claim 6, wherein The first nanosheet stack comprises alternating layers of work function metal and semiconductor channel material vertically aligned and stacked on top of each other; and The second nanosheet stack includes alternating layers of work function metal and semiconductor channel material vertically aligned and stacked on top of each other.

14. The method according to claim 6, further comprising: The non-doped silicon buffer epitaxial region is located between the bottom source-drain contact portion and the first source-drain region.

15. The method according to claim 6, further comprising: Vertical spacers are located on opposite sides of the first source and drain regions.

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