Epitaxial wafer and growth method and device thereof

Abstract

The invention provides an epitaxial wafer and a growth method and device thereof. The growth method comprises the following steps: acquiring a mean value of ESFQD values of each polished wafer in a batch of polished wafers to be subjected to epitaxial growth; obtaining the optimal epitaxial growth parameter corresponding to each polished wafer according to the corresponding relationship between the average value of the ESFQD values of the polished wafers and the optimal epitaxial growth parameter; and determining epitaxial process parameters of the batch of polished wafers according to the optimal epitaxial growth parameters corresponding to all the polished wafers of the batch, so as to perform epitaxial growth on the batch of polished wafers according to the epitaxial process parameters.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor manufacturing technology, and in particular to an epitaxial wafer and a growth method and device thereof. Background Art

[0002] As substrates used in the manufacturing process of semiconductor devices, wafers made of semiconductors such as silicon wafers are widely used. It is known that there are polished wafers (PW) made by slicing single crystal ingots and performing grinding, polishing, cleaning and other processing processes, and epitaxial wafers with single crystal silicon epitaxial layers formed on the surface of polished wafers by chemical vapor deposition and other methods. The epitaxial wafers obtained by chemical vapor deposition have the characteristics of few surface defects, excellent crystallization performance and controllable resistivity.

[0003] The flatness of the epitaxial wafer surface is an important parameter affecting the performance of semiconductor devices. The better the flatness, the higher the device yield and performance. Therefore, improving flatness is an important part of epitaxial wafer research. Summary of the invention

[0004] The present disclosure provides an epitaxial wafer and a growth method and device thereof, which can improve the flatness of the grown epitaxial wafer.

[0005] The technical solution of the present disclosure is achieved as follows: In a first aspect, the present disclosure provides a method for growing an epitaxial wafer, the method comprising: Obtaining an average of the ESFQD values ​​of each polished wafer in a batch of polished wafers to be epitaxially grown; Obtaining the optimal epitaxial growth parameters corresponding to each polished wafer according to the corresponding relationship between the average value of the ESFQD value of the polished wafer and the optimal epitaxial growth parameters; The epitaxial process parameters of the batch of polished wafers are determined according to the optimal epitaxial growth parameters corresponding to all the polished wafers in the batch, so as to perform epitaxial growth on the batch of polished wafers according to the epitaxial process parameters.

[0006] In a second aspect, the present disclosure provides a growth device for an epitaxial wafer, the growth device comprising: a first acquisition unit, a second acquisition unit and a determination unit, wherein: The first acquisition unit is configured to acquire an average value of the ESFQD value of each polished wafer in a batch of polished wafers to be epitaxially grown; The second acquisition unit is configured to acquire the optimal epitaxial growth parameter corresponding to each polished wafer according to the correspondence between the average value of the ESFQD value of the polished wafer and the optimal epitaxial growth parameter; The determination unit is configured to determine the epitaxial process parameters of the batch of polished wafers according to the optimal epitaxial growth parameters corresponding to all the polished wafers, so as to perform epitaxial growth on the batch of polished wafers according to the epitaxial process parameters.

[0007] In a third aspect, the present disclosure provides an epitaxial wafer growth device, the epitaxial wafer growth device comprising: a processor and a memory; the processor is used to execute instructions stored in the memory to implement the epitaxial wafer growth method as described in the first aspect.

[0008] In a fourth aspect, the present disclosure provides an epitaxial wafer, which is manufactured by the epitaxial wafer growth method described in the first aspect, and the maximum local flatness SFQRmax of the epitaxial wafer is less than 30.26 nm.

[0009] The present disclosure provides an epitaxial wafer and a growth method and device thereof; the optimal epitaxial growth parameters corresponding to each wafer in a batch are obtained by utilizing the large correspondence between the mean value of the ESFQD values ​​of a batch of polished wafers and the optimal epitaxial growth parameters, and the epitaxial process parameters for epitaxial growth of the batch of polished wafers are obtained according to the optimal epitaxial growth parameters corresponding to all wafers in the batch; since the epitaxial process parameters are obtained based on the optimal epitaxial growth parameters of all polished wafers in the entire batch, the flatness of the epitaxial wafer can be improved by utilizing the influence of the mean value of the ESFQD values ​​of all polished wafers on the flatness of the epitaxial wafer, and the consistency of the flatness of the epitaxial wafer finally obtained from the entire batch of polished wafers is also improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 A schematic diagram of the structure of the epitaxial growth equipment provided in the present invention.

[0011] Figure 2 A schematic flow chart of a method for growing an epitaxial wafer provided in the present invention.

[0012] Figure 3 A schematic diagram showing how the susceptor height affects the growth rate of the epitaxial layer provided in the present disclosure.

[0013] Figure 4 A schematic diagram of the corresponding relationship between the average ESFQD value of the polished wafer provided in the present invention and the optimal epitaxial temperature.

[0014] Figure 5 SFQR of a batch of epitaxial wafers provided in the present disclosure max Schematic diagram of the curve.

[0015] Figure 6 SFQR before and after the process improvement provided by the present disclosure max Schematic diagram of mean comparison.

[0016] Figure 7 The average ESFQD value of the polished wafer provided by the present disclosure and the SFQR of the epitaxial wafer max Schematic diagram of the correlation between them.

[0017] Figure 8 A schematic diagram of the composition of an epitaxial wafer growth device provided in the present invention.

[0018] Fig. 9 A schematic diagram of another epitaxial wafer growth device provided in the present invention.

[0019] Fig.10 A schematic structural diagram of an epitaxial wafer growth device provided in the present invention. DETAILED DESCRIPTION

[0020] The technical solutions in the present disclosure will be described clearly and completely below in conjunction with the accompanying drawings in the present disclosure.

[0021] See also Figure 1 , which shows a schematic structural diagram of an exemplary epitaxial growth device 1 capable of implementing the technical solution of the present disclosure. The epitaxial growth device 1 comprises: The epitaxial base 10 is used to carry the polished wafer W; The support frame 20 is used to support the epitaxial pedestal 10 and drive the epitaxial pedestal 10 to rotate around the central axis X at a certain speed during the epitaxial growth process. During the rotation of the epitaxial pedestal 10, the polished wafer W rotates around the central axis X together with the epitaxial pedestal 10, that is, the polished wafer W remains stationary relative to the epitaxial pedestal 10. Therefore, a small gap G is required between the radial edge of the epitaxial pedestal 10 and the adjacent component 10A (usually a preheating ring).

[0022] The upper bell jar 30A and the lower bell jar 30B together enclose a reaction chamber RC containing the epitaxial base 10 and the support frame 20. The epitaxial base 10 divides the reaction chamber RC into an upper reaction chamber RC1 and a lower reaction chamber RC2, and the polished wafer W is placed in the upper reaction chamber RC1. Usually, the gas pressure in the upper reaction chamber RC1 is slightly greater than the gas pressure in the lower reaction chamber RC2, so that the gas in the upper reaction chamber RC1 can enter the lower reaction chamber RC2 through the gap G.

[0023] In some examples, the upper bell 30A and the lower bell 30B are made of quartz.

[0024] The gas inlet 40 is used to transport epitaxial reaction gas, such as silicon source gas such as SiHCl3, hydrogen, and dopant gas such as B2H6 or PH3, into the upper reaction chamber RC1, so that silicon atoms are generated by the reaction of the silicon source gas and hydrogen and deposited on the surface of the polished wafer W, thereby growing an epitaxial layer on the surface of the polished wafer W. In addition, the epitaxial layer is doped by the dopant gas to obtain a desired resistivity.

[0025] The exhaust port 50 is used to discharge the reaction tail gas out of the reaction chamber RC.

[0026] The heating bulb 60 is disposed at the periphery of the upper bell jar 30A and the lower bell jar 30B and is used to provide a high temperature environment for chemical vapor deposition in the reaction chamber RC through the upper bell jar 30A and the lower bell jar 30B.

[0027] A mounting member 70 for assembling the various elements of the epitaxial growth apparatus 1 .

[0028] For the epitaxial wafer produced by the epitaxial growth device 1 , as the semiconductor manufacturing process continues to develop, the index for evaluating its flatness may change accordingly.

[0029] In the present disclosure, exemplarily, the indicators for evaluating the flatness of a wafer (including a polished wafer or an epitaxial wafer) may include: an edge site front least squares deviation (ESFQD) for characterizing the flatness of the edge of a wafer (including a polished wafer or an epitaxial wafer). Specifically, ESFQD is an indicator of the local flatness (Site flatness) of the edge (also referred to as the periphery) of a wafer (including a polished wafer or an epitaxial wafer). ESFQD divides the edge of a wafer (including a polished wafer or an epitaxial wafer) into a plurality of (for example, 72) fan-shaped regions (local regions), and uses the least squares method to fit an imaginary plane as the reference plane within each fan-shaped region. ESFQD is the positive or negative distance deviation of each fan-shaped region relative to the reference plane within the region, expressed as a ± value. In some examples, each of the above-mentioned fan-shaped areas is a fan-shaped area that extends 15 mm from the outer peripheral reference end that is inner than the excluded area toward the center side of the wafer (including a polished wafer or an epitaxial wafer) after taking an area of ​​2 mm to 5 mm in diameter direction from the outermost periphery of the wafer (including a polished wafer or an epitaxial wafer) as an excluded area.

[0030] In the present disclosure, in addition to ESFQD, indicators for evaluating the flatness of wafers, especially epitaxial wafers, may also include: Site Front surface referenced least squares range (SFQR) for evaluating the local flatness of epitaxial wafers. For example, taking a 12-inch epitaxial wafer or a 300 mm diameter epitaxial wafer as an example, the surface of the entire epitaxial wafer is divided into local areas using squares of any size (e.g., 26 mm × 8 mm). In each local area (square), after calculating the reference plane based on the thickness value, the maximum difference between the thickness value of the point in the local area (square) and the reference plane is used as the SFQR value of the local area. In addition, the maximum value among the SFQR values ​​of all local areas (squares), that is, the SFQR max It can be used as an indicator to characterize the flatness of the entire surface of the epitaxial wafer.

[0031] For the epitaxial wafers produced by the above-mentioned epitaxial growth device 1, factors affecting their flatness include: the flatness of the polished wafer to be epitaxially grown and the uniformity of the epitaxial layer deposited by epitaxial growth. As for the flatness of the polished wafer, it is mainly affected by the processing technology such as slicing, grinding, polishing, and cleaning, which will cause the ESFQD values ​​of each polished wafer in the same batch (Lot) to vary greatly, and thus make the flatness of the epitaxial wafers obtained after epitaxial growth of each polished wafer in the batch less consistent. In order to avoid this situation, improve the flatness of the epitaxial wafer, see Figure 2 , which shows a method for growing an epitaxial wafer provided by the present disclosure, which method may include steps S201 to S203.

[0032] In step S201, the average ESFQD value of each polished wafer in a batch of polished wafers to be epitaxially grown is obtained.

[0033] In the present disclosure, in combination with the definition of the aforementioned ESFQD value, illustratively, the edge of each polished wafer is divided into 72 sector-shaped areas, and after fitting an imaginary plane as the reference plane within each sector-shaped area by the least squares method, the positive or negative distance deviation of each sector-shaped area relative to the reference plane within the area is the ESFQD value of the polished wafer. It can be understood that the ESFQD value of the polished wafer is usually illustratively represented by an array, the length of the array is consistent with the number of sector-shaped areas, for example, 72, and the value of each element in the array is the positive or negative distance deviation value of the corresponding sector-shaped area relative to the reference plane within the area, expressed as ± value.

[0034] In the present disclosure, illustratively, by obtaining the average of the ESFQD values ​​of these fan-shaped areas, and using the average as an indicator for evaluating the flatness of the polished wafer, the data dimension of the flatness indicator of each polished wafer is reduced to reduce the amount of data processing and calculation that may occur later. Exemplarily, for a batch (Lot) of polished wafers (for example, 25), each polished wafer can obtain its flatness indicator through the above example, that is, the average of the ESFQD value of each polished wafer.

[0035] In step S202, the optimal epitaxial growth parameters corresponding to each polished wafer are obtained according to the corresponding relationship between the average value of the ESFQD values ​​of the polished wafers and the optimal epitaxial growth parameters.

[0036] In the present disclosure, the inventors found that the average ESFQD value of the polished wafer is usually negative, that is, most of the fan-shaped areas of each polished wafer will show a negative distance deviation relative to the reference plane in the area, and "negative" is used to describe this situation in the present disclosure. When the negative distance deviation presented is large (that is, the degree of negative deviation is large), for example, when the distance deviation is greater than a set threshold, if it is desired to improve the flatness of the epitaxial wafer obtained by epitaxial growth of the polished wafer, then it is necessary to use epitaxial growth parameters that can increase the thickness of the edge epitaxial layer during the epitaxial growth process.

[0037] Regarding the epitaxial growth parameters that can increase the thickness of the edge epitaxial layer, the inventors found that these epitaxial growth parameters are related to the growth rate of the epitaxial layer. For example, taking the epitaxial temperature as an example, the higher the epitaxial temperature, the faster the growth rate of the edge area of ​​the polished wafer compared to the center part of the polished wafer. Such a difference in growth rate can make the thickness of the epitaxial layer grown in the edge area higher than that of the center part of the polished wafer. In this way, the degree of the above-mentioned "negative bias" can be reduced, thereby improving the flatness of the epitaxial wafer after epitaxial growth of the polished wafer.

[0038] In addition, in some other examples, the height of the pedestal supporting the wafer is also an exemplary epitaxial growth parameter related to the growth rate of the epitaxial layer. Figure 3 As shown, when the height of the base 10 supporting the wafer is increased, for example, with the adjacent component 10A as a reference, the height of the base supporting the wafer is increased by h. In this case, the epitaxial reaction gas deposited on the edge of the polished wafer will increase, thereby increasing the growth rate of the edge epitaxial layer, resulting in more single crystal silicon deposited on the edge of the polished wafer than on the center of the polished wafer. In this way, the degree of the above-mentioned "negative bias" can be reduced, thereby improving the flatness of the epitaxial wafer after epitaxial growth of the polished wafer.

[0039] It should be noted that, taking the above two exemplary epitaxial growth parameters as an example, corresponding to the value of the mean of each ESFQD value, there is a corresponding optimal epitaxial growth parameter corresponding thereto, and the inventors have found that the corresponding relationship mostly presents a linear relationship with the mean of the ESFQD value of the polished wafer. Based on this discovery, in some examples, for each possible mean value of the ESFQD value, the corresponding optimal epitaxial growth parameter is obtained, and the above linear relationship is fitted, so that the optimal epitaxial growth parameter corresponding to the mean of the ESFQD value of various values ​​is obtained according to the linear relationship.

[0040] In step S203, epitaxial process parameters of the batch of polished wafers are determined according to the optimal epitaxial growth parameters corresponding to all the polished wafers in the batch, so as to perform epitaxial growth on the batch of polished wafers according to the epitaxial process parameters.

[0041] In the present disclosure, for a batch of polished wafers, each polished wafer has a corresponding optimal epitaxial growth parameter. However, in the epitaxial production process, a unified epitaxial growth parameter is usually set for the entire batch (for example, 25 wafers) of polished wafers, and the epitaxial growth parameter is not set separately for each polished wafer. Based on this, in order to improve the flatness and consistency of the epitaxial wafers obtained by epitaxial growth of the entire batch of polished wafers, the present disclosure can obtain the epitaxial process parameters for epitaxial growth of the entire batch based on the optimal epitaxial growth parameters corresponding to each wafer in all the polished wafers in the entire batch. For example, the average of the optimal epitaxial growth parameters corresponding to each wafer in all the polished wafers in the entire batch can be used as the epitaxial process parameters for epitaxial growth of the entire batch.

[0042] It should be noted that the epitaxial process parameters are obtained based on the optimal epitaxial growth parameters of all polished wafers in the entire batch. The flatness of the epitaxial wafer can be improved by utilizing the influence of the average ESFQD value of all polished wafers on the flatness of the epitaxial wafer, and the consistency of the flatness of the epitaxial wafer finally obtained from the entire batch of polished wafers is also improved.

[0043] for Figure 2The technical scheme shown utilizes the large correspondence between the mean value of the ESFQD value of a batch of polished wafers and the optimal epitaxial growth parameters to obtain the optimal epitaxial growth parameters corresponding to each wafer in the batch, and obtains the epitaxial process parameters for epitaxial growth of the batch of polished wafers based on the optimal epitaxial growth parameters corresponding to all wafers in the batch. Since the epitaxial process parameters are obtained based on the optimal epitaxial growth parameters of all polished wafers in the entire batch, the flatness of the epitaxial wafer can be improved by utilizing the influence of the mean value of the ESFQD value of all polished wafers on the flatness of the epitaxial wafer, and the consistency of the flatness of the epitaxial wafer finally obtained from the entire batch of polished wafers is also improved.

[0044] for Figure 2 In the technical solution shown, in some possible implementations, the epitaxial temperature is used as an example of the epitaxial growth parameter, and the optimal epitaxial growth parameter corresponding to each polished wafer is obtained according to the corresponding relationship between the average value of the ESFQD value of the polished wafer and the optimal epitaxial growth parameter, including: The optimal epitaxial temperature corresponding to each polished wafer is obtained according to the corresponding relationship between the average ESFQD value of the polished wafer and the optimal epitaxial temperature.

[0045] For the above implementation, specifically, when the ESFQD value of the polished wafer is "negative" to a large extent, in order to improve the flatness of the epitaxial wafer, it is necessary to make the thickness of the epitaxial layer at the edge higher than the thickness of the epitaxial layer at the center of the polished wafer during the epitaxial growth process. The epitaxial temperature is an example of an epitaxial growth parameter that can increase the thickness of the epitaxial layer at the edge. max As an indicator of the flatness of the epitaxial wafer, the average ESFQD value of the polished wafer collected during the historical epitaxy process and the SFQR of the epitaxial wafer obtained by epitaxial growth are max The optimal epitaxial temperature is obtained by fitting the collected data. The inventors found that the corresponding relationship between the mean value of the ESFQD value of the polished wafer and the optimal epitaxial temperature is a linear negative correlation, such as Figure 4 As shown, this linear negative correlation can be expressed by the expression y = -1.0087x + 1099. In this expression, x represents the mean value of the ESFQD value of the polished wafer (ie, ESFQD (sub) in the figure), and y represents the optimal epitaxial growth temperature, that is, the optimal epitaxial temperature.

[0046] It should be noted that after obtaining the average ESFQD value of each polished wafer, the optimal epitaxial temperature corresponding to each polished wafer can be calculated according to the above corresponding relationship.

[0047] For the above implementation, in some examples, determining the epitaxial process parameters of the batch of polished wafers according to the optimal epitaxial growth parameters corresponding to all the polished wafers in the batch includes: The average value of the optimal epitaxial temperatures corresponding to all the polished wafers in the batch is determined as the epitaxial temperature value when the epitaxial growth is performed on the polished wafers in the batch.

[0048] For the above example, specifically, in the epitaxial production process, a unified epitaxial growth parameter is usually set for the entire batch (for example, 25) of polished wafers, and the epitaxial growth parameter is not set separately for each polished wafer. Based on this, in order to improve the flatness and consistency of the epitaxial wafers obtained by epitaxial growth of the entire batch of polished wafers, the average of the optimal epitaxial growth parameters corresponding to each wafer in all the polished wafers in the entire batch can be used as the epitaxial process parameter for epitaxial growth of the entire batch, that is, the epitaxial temperature value when performing epitaxial growth. When epitaxial growth is performed on the entire batch of polished wafers according to the epitaxial temperature value, not only the flatness of the epitaxial wafer obtained by epitaxial growth of each polished wafer is improved, but also the consistency of the flatness of the epitaxial wafers finally obtained from the entire batch of polished wafers is improved.

[0049] For example, SFQR max As an indicator of the flatness of epitaxial wafers, the number of polished wafers in the entire batch is 25. After the process improvement is carried out through the process described in the above implementation method and example, the SFQR of each epitaxial wafer in the batch is obtained. max like Figure 5 The middle grey curve is shown, and the black curve is the SFQR of the epitaxial wafer obtained by epitaxial growth equipment 1 for a batch of polished wafers according to the default epitaxial temperature (before process improvement) max Curve. Figure 5 It can be seen that the amplitude fluctuation of the black curve is greater than the amplitude fluctuation of the gray curve, and the amplitude mean of the black curve is greater than the amplitude mean of the gray curve. That is to say, after the process is improved by the technical solution of the present disclosure, the flatness and consistency of the flatness of the epitaxial wafer are improved. Figure 6 As shown, the SFQR of each epitaxial wafer after improvement max The average value is 26.36nm, which improves the SFQR of each epitaxial wafer before max The average value is 30.26nm.

[0050] for Figure 2 In the technical solution shown in the figure, in some other possible implementations, taking the height of the base supporting the wafer as an example, the optimal epitaxial growth parameters corresponding to each polished wafer are obtained according to the corresponding relationship between the mean value of the ESFQD value of the polished wafer and the optimal epitaxial growth parameter, including: The optimal height of the pedestal corresponding to each polished wafer is obtained according to the corresponding relationship between the average ESFQD value of the polished wafer and the optimal height of the pedestal supporting the wafer.

[0051] For the above implementation, similar to the above epitaxial temperature example, when the ESFQD value of the polished wafer is more "negative", in order to improve the flatness of the epitaxial wafer, it is necessary to make the thickness of the epitaxial layer at the edge higher than the thickness of the epitaxial layer at the center of the polished wafer during the epitaxial growth process. The height of the pedestal supporting the wafer is also an example of an epitaxial growth parameter that can increase the thickness of the epitaxial layer at the edge. max As an indicator of the flatness of the epitaxial wafer, the average ESFQD value of the polished wafer collected during the historical epitaxy process and the SFQR of the epitaxial wafer obtained by epitaxial growth are max The height of the pedestal at the optimum time is obtained, and the collected data is fitted to obtain the corresponding relationship between the mean value of the ESFQD value of the polished wafer and the optimal height of the pedestal. Specifically, it is obtained by least squares fitting, which is not described in detail in this disclosure.

[0052] It should be noted that after obtaining the average ESFQD value of each polished wafer, the optimal height of the base corresponding to each polished wafer can be calculated according to the above correspondence.

[0053] For the above implementation, in some examples, determining the epitaxial process parameters of the batch of polished wafers according to the optimal epitaxial growth parameters corresponding to all the polished wafers in the batch includes: The average value of the optimal heights of the susceptors corresponding to all the polished wafers in the batch is determined as the height value of the susceptors when the epitaxial growth is performed on the polished wafers in the batch.

[0054] For the above example, similar to the above epitaxial temperature example, the average of the optimal height of the pedestal corresponding to each wafer in all the polished wafers of the entire batch is used as the epitaxial process parameter for epitaxial growth of the entire batch, that is, the height value of the pedestal when performing epitaxial growth. When epitaxial growth is performed on the polished wafers of the entire batch according to the height value of the pedestal, not only the flatness of the epitaxial wafer obtained by epitaxial growth of each polished wafer is improved, but also the consistency of the flatness of the epitaxial wafer finally obtained from the polished wafers of the entire batch is improved.

[0055] Based on the above technical solution, in some possible implementations, the method further includes: The average ESFQD value of each polished wafer obtained by detection; Based on the average ESFQD value of each polished wafer obtained by processing, the average ESFQD value of the polished wafer and the maximum local flatness SFQR of the epitaxial wafer are used to calculate the average ESFQD value of the polished wafer. max According to the correlation relationship between the two, at least one batch of polished wafers to be epitaxially grown is selected from all the polished wafers obtained by processing according to the number of polished wafers included in a single batch.

[0056] For the above implementation, specifically, during the epitaxial growth process, the average ESFQD value of the polished wafer as the substrate and the SFQR of the epitaxial wafer obtained are max The inventor discovered that there is Figure 7 The correlation shown. Figure 7 In the figure, each point represents a polished wafer as a substrate, and the horizontal and vertical coordinate values ​​of each point represent the average ESFQD value of the polished wafer as a substrate (i.e., ESFQD (sub) in the figure) and the SFQR of the epitaxial wafer obtained by epitaxial growth of the polished wafer. max (Right now Figure 7 SFQR (EPI) in ). By observing Figure 7 It can be found that the average ESFQD value of the polished wafer as the substrate is similar to the SFQR of the epitaxial wafer obtained. max There is a correlation between Figure 7 The coordinate points in are characterized by the fitted straight line equation as shown by the dashed line. In some examples, Figure 7 The equation of the straight line shown by the dashed line can be used Figure 7 The coordinate points in are obtained by least square fitting, which will not be elaborated in this disclosure.

[0057] based on Figure 7 The exemplary correlation shown in FIG. 1 shows that in some examples, the present disclosure selects polished wafers to be epitaxially grown from polished wafers made by slicing, grinding, polishing, cleaning and other processing processes according to the number of single batches (for example, 25 wafers). Based on the average ESFQD value of each polished wafer obtained by processing, the average ESFQD value of the polished wafer is used to calculate the maximum local flatness SFQR of the epitaxial wafer. max According to the correlation between the two, at least one batch of polished wafers to be epitaxially grown is selected from all the processed polished wafers according to the number of polished wafers included in a single batch, including: From all the polished wafers obtained through processing, according to the correlation, the polished wafers having an average ESFQD value greater than or equal to -15 and less than or equal to -27 are selected to obtain at least one batch of polished wafers to be epitaxially grown according to the number of polished wafers included in a single batch.

[0058] For the above example, specifically, by continuing to observe Figure 7 It can also be found that when the mean ESFQD value of the polished wafer is in the range of [-15,-27], the SFQR of the epitaxial wafer obtained is max SFQR relative to other coordinate points as a whole max Based on this situation, the present disclosure selects polished wafers whose mean ESFQD value is in the range of [-15, -27] from all the polished wafers processed as polished wafers to be epitaxially grown, and divides these polished wafers to be epitaxially grown into at least one batch of polished wafers to be epitaxially grown according to the number of wafers included in a single batch (for example, 25).

[0059] It can be understood that, through the above implementation and the example thereof, the screening process of the polished wafer to be epitaxially grown can select the polished wafer that is more likely to improve the flatness of the epitaxial wafer, and the above Figure 2 The combination of the technical solutions shown can further improve the flatness of the epitaxial wafer.

[0060] Based on the same inventive concept as the above technical solution, see Figure 8 , which shows an epitaxial wafer growth device 80 provided by the present disclosure, the growth device 80 includes: a first acquisition unit 801, a second acquisition unit 802 and a determination unit 803, wherein, The first acquisition unit 801 is configured to acquire the average ESFQD value of each polished wafer in a batch of polished wafers to be epitaxially grown; The second acquisition unit 802 is configured to acquire the optimal epitaxial growth parameters corresponding to each polished wafer according to the correspondence between the average value of the ESFQD value of the polished wafer and the optimal epitaxial growth parameter; The determination unit 803 is configured to determine the epitaxial process parameters of the batch of polished wafers according to the optimal epitaxial growth parameters corresponding to all the polished wafers, so as to perform epitaxial growth on the batch of polished wafers according to the epitaxial process parameters.

[0061] for Figure 8 The epitaxial wafer growth device 80 shown in the figure, in a specific implementation process, Figure 1 The epitaxial growth device 1 shown performs epitaxial growth according to the epitaxial process parameters obtained by the determination unit 803 during the epitaxial growth process, which not only improves the flatness of the epitaxial wafer, but also improves the consistency of the flatness of the epitaxial wafers finally obtained by polishing the entire batch of wafers.

[0062] In some examples, the second acquisition unit 802 is configured to: The optimal epitaxial temperature corresponding to each polished wafer is obtained according to the corresponding relationship between the average ESFQD value of the polished wafer and the optimal epitaxial temperature.

[0063] In some examples, the determining unit 803 is configured to: The average value of the optimal epitaxial temperatures corresponding to all the polished wafers in the batch is determined as the epitaxial temperature value when the epitaxial growth is performed on the polished wafers in the batch.

[0064] In some examples, the correspondence between the mean ESFQD value of the polished wafer and the optimal epitaxial temperature is a linear negative correlation.

[0065] In some examples, the second acquisition unit 802 is configured to: The optimal height of the pedestal corresponding to each polished wafer is obtained according to the corresponding relationship between the average ESFQD value of the polished wafer and the optimal height of the pedestal supporting the wafer.

[0066] In some examples, the determining unit 803 is configured to: The average value of the optimal heights of the susceptors corresponding to all the polished wafers in the batch is determined as the height value of the susceptors when the epitaxial growth is performed on the polished wafers in the batch.

[0067] For some examples, see Fig. 9 The epitaxial wafer growth device 80 further includes a screening unit 804 configured to: The average ESFQD value of each polished wafer obtained by detection; Based on the average ESFQD value of each polished wafer obtained by processing, the average ESFQD value of the polished wafer and the maximum local flatness SFQR of the epitaxial wafer are used to calculate the average ESFQD value of the polished wafer. max According to the correlation relationship between the two, at least one batch of polished wafers to be epitaxially grown is selected from all the polished wafers obtained by processing according to the number of polished wafers included in a single batch.

[0068] In some examples, the screening unit 804 is configured to: From all the polished wafers obtained through processing, according to the correlation, the polished wafers having an average ESFQD value greater than or equal to -15 and less than or equal to -27 are selected to obtain at least one batch of polished wafers to be epitaxially grown according to the number of polished wafers included in a single batch.

[0069] Please refer to Fig.10, which shows a block diagram of the structure of an epitaxial wafer growth device 80 provided by an exemplary embodiment of the present disclosure. In some examples, the epitaxial wafer growth device 80 can be at least one of a smart phone, a smart watch, a desktop computer, a laptop, a virtual reality terminal, an augmented reality terminal, a wireless terminal, and a laptop portable computer. The epitaxial wafer growth device 80 has a communication function and can be connected to a wired network or a wireless network. The epitaxial wafer growth device 80 can generally refer to one of a plurality of terminals, and those skilled in the art can know that the number of the above terminals can be more or less. In some examples, the epitaxial wafer growth device 80 can receive data based on the wired network or wireless network to which it is connected. It can be understood that the epitaxial wafer growth device 80 undertakes the calculation and processing work of the technical solution of the present disclosure, and the present disclosure does not limit this.

[0070] like Fig.10 As shown, the epitaxial wafer growth device 80 in the present disclosure may include one or more of the following components: a processor 910 and a memory 920 .

[0071] Optionally, the processor 910 uses various interfaces and lines to connect various parts of the entire computing device, and executes various functions of the computing device and processes data by running or executing instructions, programs, code sets or instruction sets stored in the memory 920, and calling data stored in the memory 920. Optionally, the processor 910 can be implemented in at least one hardware form of digital signal processing (DSP), field-programmable gate array (FPGA), and programmable logic array (PLA). The processor 910 can integrate one or a combination of a central processing unit (CPU), a graphics processing unit (GPU), a neural network processor (NPU), and a baseband chip. Among them, the CPU mainly processes the operating system, user interface, and application programs; the GPU is responsible for rendering and drawing the content that needs to be displayed on the touch display; the NPU is used to implement artificial intelligence (AI) functions; and the baseband chip is used to process wireless communications. It is understandable that the above baseband chip may not be integrated into the processor 910, but may be implemented by a separate chip.

[0072] The memory 920 may include a random access memory (RAM) or a read-only memory (ROM). Optionally, the memory 920 includes a non-transitory computer-readable storage medium. The memory 920 may be used to store instructions, programs, codes, code sets, or instruction sets. The memory 920 may include a program storage area and a data storage area, wherein the program storage area may store instructions for implementing an operating system, instructions for at least one function (such as a touch function, a sound playback function, an image playback function, etc.), instructions for implementing the above various method embodiments, etc.; the data storage area may store data created according to the use of the computing device, etc.

[0073] In addition, those skilled in the art can understand that the structure of the computing device shown in the above drawings does not constitute a limitation on the computing device, and the computing device may include more or fewer components than shown in the figure, or combine certain components, or arrange the components differently. For example, the computing device also includes a display screen, a camera assembly, a microphone, a speaker, a radio frequency circuit, an input unit, a sensor (such as an acceleration sensor, an angular velocity sensor, a light sensor, etc.), an audio circuit, a WiFi module, a power supply, a Bluetooth module and other components, which will not be described in detail here.

[0074] The present disclosure also provides a computer-readable storage medium storing at least one instruction, wherein the at least one instruction is used to be executed by a processor to implement the epitaxial wafer growth method described in the above embodiments.

[0075] The present disclosure also provides a computer program product, which includes computer instructions stored in a computer-readable storage medium; a processor of a computing device reads the computer instructions from the computer-readable storage medium, and the processor executes the computer instructions, so that the computing device executes to implement the epitaxial wafer growth method described in the above-mentioned embodiments.

[0076] Based on the above technical solution, the present disclosure also provides an epitaxial wafer, the epitaxial wafer is manufactured by the epitaxial wafer growth method described in the above technical solution, and the maximum local flatness SFQR of the epitaxial wafer is max Less than 30.26nm.

[0077] Those skilled in the art should be aware that in one or more of the above examples, the functions described in the present disclosure can be implemented using hardware, software, firmware, or any combination thereof. When implemented using software, these functions can be stored in a computer-readable medium or transmitted as one or more instructions or codes on a computer-readable medium. Computer-readable media include computer storage media and communication media, wherein communication media include any media that facilitates the transmission of computer programs from one place to another. Storage media can be any available media that can be accessed by a general or special-purpose computer.

[0078] It should be noted that the technical solutions described in the present disclosure can be combined arbitrarily without conflict.

[0079] The above is only a specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any person skilled in the art can easily think of changes or substitutions within the technical scope disclosed by the present invention, which should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention should be based on the protection scope of the claims.

Claims

1. A method for growing an epitaxial wafer, characterized in that: The method comprises: Obtaining an average of the ESFQD values ​​of each polished wafer in a batch of polished wafers to be epitaxially grown; Obtaining the optimal epitaxial growth parameters corresponding to each polished wafer according to the corresponding relationship between the average value of the ESFQD value of the polished wafer and the optimal epitaxial growth parameters; The epitaxial process parameters of the batch of polished wafers are determined according to the optimal epitaxial growth parameters corresponding to all the polished wafers in the batch, so as to perform epitaxial growth on the batch of polished wafers according to the epitaxial process parameters.

2. The method according to claim 1, characterized in that: The step of obtaining the optimal epitaxial growth parameters corresponding to each polished wafer according to the correspondence between the average value of the ESFQD value of the polished wafer and the optimal epitaxial growth parameters includes: The optimal epitaxial temperature corresponding to each polished wafer is obtained according to the corresponding relationship between the average ESFQD value of the polished wafer and the optimal epitaxial temperature.

3. The method according to claim 2, characterized in that Determining the epitaxial process parameters of the batch of polished wafers according to the optimal epitaxial growth parameters corresponding to all the polished wafers in the batch includes: The average value of the optimal epitaxial temperatures corresponding to all the polished wafers in the batch is determined as the epitaxial temperature value when the polished wafers in the batch are subjected to epitaxial growth.

4. The method according to claim 2, characterized in that: The corresponding relationship between the mean value of the ESFQD value of the polished wafer and the optimal epitaxial temperature is a linear negative correlation.

5. The method according to claim 1, characterized in that The step of obtaining the optimal epitaxial growth parameters corresponding to each polished wafer according to the correspondence between the average value of the ESFQD value of the polished wafer and the optimal epitaxial growth parameters includes: The optimal height of the pedestal corresponding to each polished wafer is obtained according to the corresponding relationship between the average ESFQD value of the polished wafer and the optimal height of the pedestal supporting the wafer.

6. The method according to claim 5, characterized in that Determining the epitaxial process parameters of the batch of polished wafers according to the optimal epitaxial growth parameters corresponding to all the polished wafers in the batch includes: The average value of the optimal heights of the susceptors corresponding to all the polished wafers in the batch is determined as the height value of the susceptors when the epitaxial growth is performed on the polished wafers in the batch.

7. The method according to any one of claims 1 to 6, characterized in that: The method further comprises: The average ESFQD value of each polished wafer obtained by detection; Based on the average ESFQD value of each polished wafer obtained by processing, the average ESFQD value of the polished wafer and the maximum local flatness SFQR of the epitaxial wafer are used to calculate the average ESFQD value of the polished wafer. max According to the correlation relationship between the two, at least one batch of polished wafers to be epitaxially grown is selected from all the polished wafers obtained by processing according to the number of polished wafers included in a single batch.

8. The method according to claim 7, characterized in that The average ESFQD value of each polished wafer obtained by processing is calculated by using the average ESFQD value of the polished wafer and the maximum local flatness SFQR of the epitaxial wafer. max According to the correlation between the two, at least one batch of polished wafers to be epitaxially grown is selected from all the processed polished wafers according to the number of polished wafers included in a single batch, including: From all the polished wafers obtained through processing, according to the correlation, the polished wafers having an average ESFQD value greater than or equal to -15 and less than or equal to -27 are selected to obtain at least one batch of polished wafers to be epitaxially grown according to the number of polished wafers included in a single batch.

9. An epitaxial wafer growth device, characterized in that: The growth device comprises: a first acquisition unit, a second acquisition unit and a determination unit, wherein: The first acquisition unit is configured to acquire an average value of the ESFQD value of each polished wafer in a batch of polished wafers to be epitaxially grown; The second acquisition unit is configured to acquire the optimal epitaxial growth parameter corresponding to each polished wafer according to the correspondence between the average value of the ESFQD value of the polished wafer and the optimal epitaxial growth parameter; The determination unit is configured to determine the epitaxial process parameters of the batch of polished wafers according to the optimal epitaxial growth parameters corresponding to all the polished wafers, so as to perform epitaxial growth on the batch of polished wafers according to the epitaxial process parameters.

10. An epitaxial wafer growth device, characterized in that: The epitaxial wafer growth device comprises: a processor and a memory; the processor is used to execute instructions stored in the memory to implement the epitaxial wafer growth method according to any one of claims 1 to 8.

11. An epitaxial wafer, characterized in that: The epitaxial wafer is manufactured by the epitaxial wafer growth method according to any one of claims 1 to 8, and the maximum local flatness SFQR of the epitaxial wafer is max Less than 30.26nm.

Images