IP core for CV detection circuit of MEMS sensor

Abstract

The invention discloses an IP core for an MEMS sensor CV detection circuit, the IP core comprises a C / V conversion circuit, a low pass filter LPF, a programmable gain amplifier PGA, an analog-to-digital converter ADC, a digital top layer module, a reference module REF and a temperature sensor, the C / V conversion circuit is connected with the low pass filter LPF, the low pass filter LPF is connected with the programmable gain amplifier PGA, the analog-to-digital converter ADC is connected with the digital top layer module, the reference module REF is connected with the analog-to-digital converter ADC, the digital top layer module is connected with the digital top layer module, and the temperature sensor is connected with the analog-to-digital converter ADC. The programmable gain amplifier PGA is connected with the analog-to-digital converter ADC, the analog-to-digital converter ADC is connected with the digital top layer module, the reference module REF is connected with the temperature sensor, and the temperature sensor is connected with the digital top layer module. And a temperature sensor is arranged in the IP core to carry out heat monitoring and temperature compensation on the circuit, so that the temperature excursion during the period is inhibited.

Description

Technical Field

[0001] The invention belongs to the technical field of MEMS sensors, and in particular relates to an IP core for a CV detection circuit of a MEMS sensor. Background Art

[0002] In this era of the Internet of Everything, with the development of micro-nano technology, artificial intelligence technology and sensor technology, many electronic devices have the ability to perceive the world. The pursuit of more advanced, smarter and more integrated electronic devices has also promoted the development of reliable, high-performance and low-cost sensors.

[0003] Capacitive sensors are an important type of sensor in the sensor family. They use the principle of charge and discharge to convert the capacitance that changes with the measured variable into parameters such as voltage, current or frequency that are easy to measure and transmit. They are widely used in the measurement of humidity, temperature, displacement, pressure, etc. However, since the change in tiny capacitance is very small, generally in the order of pF, it is important to use a dedicated integrated interface circuit to detect and process tiny capacitance.

[0004] The existing MEMS sensor CV detection circuit has low integration and does not have the function of heat monitoring. Summary of the invention

[0005] In order to solve the above technical problems, the present invention provides an IP core for a MEMS sensor CV detection circuit.

[0006] The specific plan is as follows: An IP core for a CV detection circuit of a MEMS sensor, the IP core comprising a C / V conversion circuit, a low-pass filter LPF, a programmable gain amplifier PGA, an analog-to-digital converter ADC, a digital top-level module, a reference module REF and a temperature sensor, the C / V conversion circuit is connected to the low-pass filter LPF, the low-pass filter LPF is connected to the programmable gain amplifier PGA, the programmable gain amplifier PGA is connected to the analog-to-digital converter ADC, the analog-to-digital converter ADC is connected to the digital top-level module, the reference module REF is connected to the temperature sensor, and the temperature sensor is connected to the digital top-level module.

[0007] The C / V conversion circuit includes a capacitor to be measured Cin, a reference capacitor Cref, a feedback capacitor C2, an operational amplifier and a state switching switch, wherein two ends of the capacitor to be measured Cin are respectively provided with a positive input pin INA of the capacitor to be measured and a negative input pin INM of the capacitor to be measured, one end of the reference capacitor Cref is provided with a negative input pin INB of the reference capacitor, the other end of the reference capacitor Cref is connected to the negative input pin INM of the capacitor to be measured, the negative input pin INM of the capacitor to be measured is connected to the inverting input terminal VINN of the operational amplifier, the feedback capacitor C2 and the state switching switch are respectively connected between the inverting input terminal VINN of the operational amplifier and the output terminal VOUT of the operational amplifier, the state switching switch is connected in parallel with the feedback capacitor C2, and the positive input terminal VINP of the operational amplifier is connected to the reference module REF.

[0008] The state switching switch includes a P-channel MOS tube, an N-channel MOS tube and an inverter, the output end of the inverter is connected to the gate of the P-channel MOS tube, the source of the P-channel MOS tube is connected to the source of the N-channel MOS tube, the drain of the P-channel MOS tube is connected to the drain of the N-channel MOS tube, the drain of the P-channel MOS tube is connected to the inverting input end VINN of the operational amplifier, the source of the P-channel MOS tube is connected to the output end VOUT of the operational amplifier, the gate of the N-channel MOS tube is connected to the input end of the inverter, and the output end VOUT of the operational amplifier is connected to a low-pass filter LPF.

[0009] The low-pass filter LPF is a low-pass filter with adjustable bandwidth, which is used to filter out high-frequency noise of the C / V conversion circuit.

[0010] The programmable gain amplifier PGA includes a differential amplifier and a capacitor switch array, the capacitor switch array is connected between the input end of the differential amplifier and the output end of the differential amplifier, a pin control end is provided on the capacitor switch array, and the pin control end of the capacitor switch is electrically connected to the digital top-level module.

[0011] The analog-to-digital converter ADC is a single-slope architecture that uses correlated double sampling (CDS) to quantize the capacitance value. The analog-to-digital converter ADC includes a buffer CMP_buf, a comparator core adc_cmp, a comparator level converter cmp_and2, a comparator bias circuit cmp_bias, and a ramp signal generating circuit Rampdac. The ramp signal generating circuit Rampdac, the comparator bias circuit cmp_bias, and the buffer are all connected to the comparator core adc_cmp, and the output end of the comparator core adc_cmp is connected to the comparator level converter cmp_and2.

[0012] The temperature sensor is a PN junction temperature sensor.

[0013] The reference module REF includes a bandgap voltage reference and a current source reference, and is used to generate a voltage signal with a negative temperature coefficient for the temperature sensor and provide a reference voltage for the analog-to-digital converter ADC 4 .

[0014] The digital top-level module receives the capacitance quantization signal and the temperature sensor signal, and stores and processes the digital signal.

[0015] The digital top-level module also includes a PAD module, and the PAD module is an I2C module. The digital top-level module is connected to external communication via the PAD module.

[0016] The present invention discloses an IP core for a CV detection circuit of a MEMS sensor. A CV circuit IP core with higher integration is designed based on a CV conversion circuit. The IP core integrates a low-pass filter LPF with adjustable bandwidth, a programmable gain amplifier PGA, an analog-to-digital converter ADC, a digital circuit module Digital TOP, a reference module REF including a bandgap voltage reference and a current source reference, a temperature sensor Temperature Sensor, and a PAD module. The CV conversion circuit design of a MEMS capacitive sensor adopts a voltage-type capacitive digital sensor composed of a capacitor-to-voltage converter and an integral analog-to-digital converter as a basic structure. The data of multiple capacitors are read and outputted at the same time through the channel expansion capability of the integral analog-to-digital converter, reducing the influence of the long conversion time of the analog-to-digital converter on the overall sampling rate. The IP core is highly integrated and can more effectively collect tiny capacitance changes. A temperature sensor is equipped in the IP core to perform heat monitoring and temperature compensation on the circuit, thereby suppressing temperature drift during the period. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 It is a schematic diagram of the overall structure of the present invention.

[0018] Figure 2 It is the top-level circuit structure diagram of the present invention.

[0019] Figure 3 It is a structural diagram of a C / V conversion circuit.

[0020] Figure 4 This is an equivalent circuit diagram of one state of the C / V conversion circuit.

[0021] Figure 5 This is an equivalent circuit diagram of another state of the C / V conversion circuit.

[0022] Figure 6 It is a structural diagram of a low-pass filter LPF.

[0023] Figure 7It is a structural diagram of a programmable gain amplifier PGA.

[0024] Figure 8 It is a structural diagram of the analog-to-digital converter ADC.

[0025] Fig. 9 It is a schematic diagram of the structure of the internal buffer CMP_buf of the analog-to-digital converter ADC.

[0026] Fig.10 It is a structural diagram of the internal comparator core adc_cmp and comparator level conversion cmp_and2 of the analog-to-digital converter ADC.

[0027] Fig.11 It is a structural diagram of the comparator bias circuit cmp_bias inside the analog-to-digital converter ADC.

[0028] Fig.12 It is a schematic diagram of the structure of the temperature sensor.

[0029] Fig.13 It is a schematic diagram of the internal structure of the temperature sensor.

[0030] Fig.14 It is a structural diagram of the reference module REF.

[0031] Fig.15 It is a structural diagram of the digital top-level module and the PAD module.

[0032] Fig.16 It is the top-level design diagram of the IP core. DETAILED DESCRIPTION

[0033] The following will be combined with the accompanying drawings in the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the implementation of the present invention, not all of the implementations. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0034] like Figures 1 to 2As shown, an IP core for a CV detection circuit of a MEMS sensor includes a C / V conversion circuit 1, a low-pass filter LPF 2, a programmable gain amplifier PGA 3, an analog-to-digital converter ADC 4, a digital top-level module 5, a reference module REF 7 and a temperature sensor 6. The C / V conversion circuit 1 is connected to the low-pass filter LPF 2, the low-pass filter LPF 2 is connected to the programmable gain amplifier PGA 3, the programmable gain amplifier PGA 3 is connected to the analog-to-digital converter ADC4, the analog-to-digital converter ADC 4 is connected to the digital top-level module 5, the reference module REF 7 is connected to the temperature sensor 6, and the temperature sensor 6 is connected to the digital top-level module 5.

[0035] in, The C / V conversion circuit 1, namely C / V conversion:, is used to convert the input capacitance signal into a voltage signal to prepare for subsequent signal processing and quantization. The capacitance reading circuit has also produced many structures after years of development, such as frequency type, switched capacitor type, etc. This embodiment adopts a voltage-type capacitance-to-digital converter according to actual application requirements, and uses a capacitance-voltage converter and an analog-to-digital converter to combine into a capacitance-to-digital converter.

[0036] The low-pass filter LPF 2 is a low-pass filter with adjustable bandwidth, which is used to filter out high-frequency noise of the signal and C / V conversion circuit. The programmable gain amplifier PGA 3 is used to amplify the voltage signal passing through the low-pass filter LPF 2 to improve the signal-to-noise ratio; The analog-to-digital converter ADC 4 is used to complete the quantization process of the electrical signal In terms of implementation methods, there are many types of analog-to-digital converters ADC, such as successive approximation type, integral type, voltage-frequency conversion type, ∑-Δ type ADC, etc., and SS-ADC (single slope ADC) belongs to the successive approximation type. Due to its simple structure, small footprint, and low power consumption, it is widely used. Therefore, this embodiment adopts the SS-ADC (single slope ADC) method for analog-to-digital conversion.

[0037] In simple terms, successive approximation logic is a circuit implementation of binary division. It starts from the MSB of the circuit, that is, the most significant bit. Each time, the reference voltage REF is divided into half of the original through the digital-to-analog converter DAC, and then compared with the input voltage. The result is fed back to the DAC through digital logic to complete the conversion of one bit. Therefore, a simple N-bit SAR-ADC only needs N clock cycles to complete the entire conversion. In this embodiment, a 12-bit analog-to-digital converter ADC is used; The digital top-level module 5 is responsible for controlling each analog module, adjusting the working mode, receiving the signal of capacitance quantization and the signal of the temperature sensor, storing and processing the digital signal, and outputting it through the I2C pad.

[0038] The reference module REF 7 includes a bandgap voltage reference and a current source reference, generates a voltage signal with a negative temperature coefficient to the temperature sensor module, and provides a reference voltage for the ADC.

[0039] The temperature sensor 6 quantizes the voltage signal with a negative temperature coefficient into a digital signal through an ADC, and sends the digital top-level module 5 .

[0040] like Figures 3 to 5 As shown, the C / V conversion circuit 1 includes a capacitor to be measured Cin, a reference capacitor Cref, a feedback capacitor C2, an operational amplifier 9 and a state switching switch, wherein two ends of the capacitor to be measured Cin are respectively provided with a positive input pin INA of the capacitor to be measured and a negative input pin INM of the capacitor to be measured, one end of the reference capacitor Cref is provided with a negative input pin INB of the reference capacitor, the other end of the reference capacitor Cref is connected to the negative input pin INM of the capacitor to be measured, the negative input pin INM of the capacitor to be measured is connected to the inverting input terminal VINN of the operational amplifier 9, the feedback capacitor C2 and the state switching switch are respectively connected between the inverting input terminal VINN of the operational amplifier 9 and the output terminal VOUT of the operational amplifier 9, the state switching switch is connected in parallel with the feedback capacitor C2, and the positive input terminal VINP of the operational amplifier 9 is connected to the reference module REF7.

[0041] In this embodiment, Cin is the capacitor to be measured, and Cref is the external reference capacitor. INA / INM / INB are connected to both ends of Cin and Cref respectively. Square wave signals with opposite phases are input to INA and INB respectively. In this embodiment, the high level of the square wave signal is VDD, and the low level is the power ground.

[0042] like Figure 4 As shown, at this time, INA is connected to a low-level signal, while INB is connected to a high-level signal. At this time, RST is turned on to the state 1 of the C / V conversion circuit. At this time, Vout=V(INM)=VREF+Vos; Vos is the bias voltage of the transport amplifier. Figure 3 The network number is IP20U <2> To exercise control; like Figure 5As shown in the figure, when the C / V conversion circuit is in state 2, RST is turned off and the level on INA / INB is flipped, that is, a high-level signal is connected to INA and a low-level signal is connected to INB. Then the charge Q2 is added to both ends of C2, Vout-VREF-Vos=Q2 / C2=(Cref-Cin)*VDD / C2. Subtracting the Vout of the two states can eliminate the amplifier's offset voltage offset Vos. In this way, the capacitance signal of Cref is converted into a voltage signal. By continuously sampling and quantizing the voltage signal, the continuous change of Cref can be tracked.

[0043] In this embodiment, the P-channel MOS transistor 11, the N-channel MOS transistor 10 and the inverter 12 are used to control the switching of the state. Figure 3 As shown, the state switching switch includes a P-channel MOS transistor 11, an N-channel MOS transistor 10 and an inverter 12, the output end of the inverter 12 is connected to the gate of the P-channel MOS transistor 11, the source of the P-channel MOS transistor 11 is connected to the source of the N-channel MOS transistor 10, the drain of the P-channel MOS transistor 11 is connected to the drain of the N-channel MOS transistor 10, the drain of the P-channel MOS transistor 11 is connected to the inverting input end VINN of the operational amplifier 9, the source of the P-channel MOS transistor 11 is connected to the output end VOUT of the operational amplifier 9, the gate of the N-channel MOS transistor 10 is connected to the input end of the inverter 12, and the output end VOUT of the operational amplifier 9 is connected to the low-pass filter LPF2.

[0044] like Figure 6 As shown, the low-pass filter LPF2 is a low-pass filter with adjustable bandwidth, which is used to filter out high-frequency noise of the C / V conversion circuit 1.

[0045] like Figure 7 As shown, the programmable gain amplifier PGA3 includes a differential amplifier 13 and a capacitor switch array 14, the capacitor switch array 14 is connected between the input end of the differential amplifier 13 and the output end of the differential amplifier 13, and a pin control end 15 is provided on the capacitor switch array 14, and the pin control end 15 of the capacitor switch is electrically connected to the digital top-level module 5.

[0046] The programmable gain amplifier PGA 3 is used to amplify the voltage of the C / V conversion circuit. In this embodiment, 1X, 2X, 4X, 8X, and 16X gains can be selected through a digital register. The programmable gain amplifier can amplify the signal converted from the capacitor to the voltage. When the voltage signal is relatively weak, the voltage signal is amplified before quantization, which can improve the signal-to-noise ratio and obtain a more accurate quantization result.

[0047] like Figures 8 to 11As shown, the analog-to-digital converter ADC 4 is a single-slope architecture that uses correlated double sampling CDS to quantize the capacitance value. The analog-to-digital converter ADC 4 includes a buffer CMP_buf 16, a comparator core adc_cmp 17, a comparator level converter cmp_and2 18, a comparator bias circuit cmp_bias 19 and a ramp signal generating circuit Rampdac 20. The ramp signal generating circuit Rampdac 20, the comparator bias circuit cmp_bias 19 and the buffer are all connected to the comparator core adc_cmp 17, and the output end of the comparator core adc_cmp 17 is connected to the comparator level converter cmp_and2 18.

[0048] In this embodiment, a 12-bit single slope ADC is used. The CDS correlated double sampling method is used to quantize the Cap value. The ADC adopts a single slope architecture, which is easy to expand, has low power consumption and area, but the disadvantage is that the quantization speed increases exponentially with the improvement of accuracy. Because the capacitance changes slowly in this application, the quantization speed requirement is not high, which can fully meet the requirements.

[0049] like Figures 12 to 13 As shown, the temperature sensor 6 is a PN junction temperature sensor. The PN diode voltage from the band gap is negatively correlated with the temperature and is used to monitor temperature changes. The voltage is quantified by a 12-bit 1Ksps ADC. The digital temperature sensor uses the negative temperature coefficient voltage VBE (PN junction forward bias voltage) in the VREF module as an analog input and is quantized into a digital temperature signal by a 12-bit ADC. The VBE voltage can be calibrated by programming the current.

[0050] like Fig.14 As shown, the reference module REF7 includes a bandgap voltage reference and a current source reference, which are used to generate a voltage signal with a negative temperature coefficient to the temperature sensor 6 and provide a reference voltage for the analog-to-digital converter ADC 4 .

[0051] like Fig.15 As shown, the digital top-level module 5 receives the capacitance quantization signal and the temperature sensor 6 signal, and stores and processes the digital signal.

[0052] The digital top-level module 5 further includes a PAD module 8 , which is an I2C module. The digital top-level module 5 is connected to external communication via the PAD module 8 .

[0053] like Fig.16As shown in the figure, it is the Layout TOP View of the IP core, where the INA pin is the positive end of the capacitor to be measured, the INM pin is the negative end of the capacitor to be measured, the INB pin is the negative end of the reference capacitor, AVDD is the analog power supply, AGND is the analog ground, DVDD is the digital power supply, DGND is the digital ground, CKIN is the main clock input, SCL is the I2C clock input, SDA is the I2C data input and output pin, PD is the power-off input pin, and NA is an unused pin, which can be left floating during normal use.

[0054] In this embodiment, in the circuit diagram, pins with the same network number are electrically connected, such as Fig. 9 The network number of the buffer CMP_buf 16 pin is "EQC1B" and Fig.10 The network label of a pin in the comparator core adc_cmp 17 is the same as "EQC1B", indicating that the two pins are electrically connected.

[0055] The present invention discloses an IP core for a CV detection circuit of a MEMS sensor. A CV circuit IP core with higher integration is designed based on a CV conversion circuit. The IP core integrates a low-pass filter LPF with adjustable bandwidth, a programmable gain amplifier PGA, an analog-to-digital converter ADC, a digital circuit module Digital TOP, a reference module REF including a bandgap voltage reference and a current source reference, a temperature sensor Temperature Sensor, and a PAD module. The CV conversion circuit design of a MEMS capacitive sensor adopts a voltage-type capacitive digital sensor composed of a capacitor-to-voltage converter and an integral analog-to-digital converter as a basic structure. The data of multiple capacitors are read and outputted at the same time through the channel expansion capability of the integral analog-to-digital converter, reducing the influence of the long conversion time of the analog-to-digital converter on the overall sampling rate. The IP core is highly integrated and can more effectively collect tiny capacitance changes. A temperature sensor is equipped in the IP core to perform heat monitoring and temperature compensation on the circuit, thereby suppressing temperature drift during the period.

[0056] The technical means disclosed in the scheme of the present invention are not limited to the technical means disclosed in the above-mentioned implementation mode, but also include technical schemes composed of any combination of the above-mentioned technical features. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principle of the present invention, and these improvements and modifications are also regarded as the protection scope of the present invention.

Claims

1. An IP core for a MEMS sensor CV detection circuit, characterized in that: The IP core comprises a C / V conversion circuit (1), a low-pass filter LPF (2), a programmable gain amplifier PGA (3), an analog-to-digital converter ADC (4), a digital top-level module (5), a reference module REF (7) and a temperature sensor (6). The C / V conversion circuit (1) is connected to the low-pass filter LPF (2), the low-pass filter LPF (2) is connected to the programmable gain amplifier PGA (3), the programmable gain amplifier PGA (3) is connected to the analog-to-digital converter ADC (4), the analog-to-digital converter ADC (4) is connected to the digital top-level module (5), the reference module REF (7) is connected to the temperature sensor (6), and the temperature sensor (6) is connected to the digital top-level module (5).

2. The IP core for the MEMS sensor CV detection circuit according to claim 1, characterized in that: The C / V conversion circuit (1) comprises a capacitor to be measured (Cin), a reference capacitor (Cref), a feedback capacitor (C2), an operational amplifier (9) and a state switching switch. The two ends of the capacitor to be measured (Cin) are respectively provided with a positive input pin (INA) of the capacitor to be measured and a negative input pin (INM) of the capacitor to be measured. One end of the reference capacitor (Cref) is provided with a negative input pin (INB) of the reference capacitor. The other end of the reference capacitor (Cref) is connected to the negative input pin (INM) of the capacitor to be measured. The negative input pin (INM) of the capacitor to be measured is connected to an inverting input terminal (VINN) of the operational amplifier (9). The feedback capacitor (C2) and the state switching switch are respectively connected between the inverting input terminal (VINN) of the operational amplifier (9) and an output terminal (VOUT) of the operational amplifier (9). The state switching switch is connected in parallel with the feedback capacitor (C2). The positive input terminal (VINP) of the operational amplifier (9) is connected to a reference module REF (7).

3. The IP core for the MEMS sensor CV detection circuit according to claim 2, characterized in that: The state switching switch comprises a P-channel MOS tube (11), an N-channel MOS tube (10) and an inverter (12); the output end of the inverter (12) is connected to the gate of the P-channel MOS tube (11); the source of the P-channel MOS tube (11) is connected to the source of the N-channel MOS tube (10); the drain of the P-channel MOS tube (11) is connected to the drain of the N-channel MOS tube (10); the drain of the P-channel MOS tube (11) is connected to the inverting input end (VINN) of the operational amplifier (9); the source of the P-channel MOS tube (11) is connected to the output end (VOUT) of the operational amplifier (9); the gate of the N-channel MOS tube (10) is connected to the input end of the inverter (12); and the output end (VOUT) of the operational amplifier (9) is connected to a low-pass filter LPF (2).

4. The IP core for the MEMS sensor CV detection circuit according to claim 1, characterized in that: The low-pass filter LPF (2) is a low-pass filter with adjustable bandwidth, and is used to filter out high-frequency noise of the C / V conversion circuit (1).

5. The IP core for the MEMS sensor CV detection circuit according to claim 1, characterized in that: The programmable gain amplifier PGA (3) comprises a differential amplifier (13) and a capacitor switch array (14); the capacitor switch array (14) is connected between an input end of the differential amplifier (13) and an output end of the differential amplifier (13); a pin control end (15) is provided on the capacitor switch array (14); and the pin control end (15) of the capacitor switch is electrically connected to a digital top-level module (5).

6. The IP core for the MEMS sensor CV detection circuit according to claim 1, characterized in that: The analog-to-digital converter ADC (4) is a single-slope architecture and uses correlated double sampling (CDS) to quantize the capacitance value. The analog-to-digital converter ADC (4) comprises a buffer CMP_buf (16), a comparator core adc_cmp (17), a comparator level converter cmp_and2 (18), a comparator bias circuit cmp_bias (19) and a ramp signal generating circuit Rampdac (20). The ramp signal generating circuit Rampdac (20), the comparator bias circuit cmp_bias (19) and the buffer are all connected to the comparator core adc_cmp (17), and the output end of the comparator core adc_cmp (17) is connected to the comparator level converter cmp_and2 (18).

7. The IP core for the MEMS sensor CV detection circuit according to claim 1, characterized in that: The temperature sensor (6) is a PN junction temperature sensor.

8. The IP core for the CV detection circuit of a MEMS sensor according to claim 1, characterized in that: The reference module REF (7) comprises a bandgap voltage reference and a current source reference, and is used to generate a voltage signal with a negative temperature coefficient for the temperature sensor (6) and provide a reference voltage for the analog-to-digital converter ADC (4).

9. The IP core for the MEMS sensor CV detection circuit according to claim 1, characterized in that: The digital top module (5) receives the capacitance quantization signal and the temperature sensor (6) signal, and stores and processes the digital signal.

10. The IP core for the MEMS sensor CV detection circuit according to claim 9, characterized in that: The digital top-level module (5) further comprises a PAD module (8), wherein the PAD module (8) is an I2C module, and the digital top-level module (5) is connected to external communication via the PAD module (8).

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