Semiconductor structure and forming method thereof

Abstract

The invention provides a semiconductor structure and a forming method thereof, the semiconductor structure comprises an SOI substrate, the SOI substrate comprises a bottom silicon layer, an insulating layer and a top silicon layer, and the SOI substrate comprises a ridge-shaped waveguide region and a strip-shaped waveguide region; the plurality of ridge waveguides are positioned in the top silicon layer of the ridge waveguide region; the strip-shaped waveguides are located in the top silicon layer of the strip-shaped waveguide area, a first groove is formed between every two adjacent strip-shaped waveguides, the width of each first groove is smaller than or equal to 0.5 micrometer or larger than or equal to 1.5 micrometers, and no top silicon layer remains on the surfaces of the insulating layers on the two sides of each strip-shaped waveguide. According to the semiconductor structure and the forming method thereof, the etching process parameters in the transition process from the ridge waveguide to the strip waveguide are adjusted, silicon residues on the two sides of the strip waveguide can be avoided, the transmission loss is reduced, the transmission efficiency is improved, and the device reliability is improved.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a semiconductor structure and a method for forming the same. Background Art

[0002] Silicon photonics products based on silicon on insulator (SOI) substrates often use three types of waveguides, namely, ridge waveguides of two depths and strip waveguides obtained by three processes of shallow etching, deep etching, and full etching. These three types of waveguides need to be implemented with thin photoresist and anti-reflection layers. For fully etched strip waveguides, the thickness of the photoresist cannot protect the surface profile of the ridge waveguide, so a hard mask layer process needs to be introduced.

[0003] However, in some special processes, it is necessary to transition from ridge waveguide to strip waveguide. In the deep groove of the ridge waveguide with a certain etching width (i.e., the ridge waveguide cladding), a hard mask layer gap will be generated. The subsequent filling process of the anti-reflection layer will form the anti-reflection layer side wall. When the strip waveguide is etched, silicon residue will be generated, and defects will be generated next to the strip waveguide (i.e., in the strip waveguide cladding), resulting in increased transmission loss and greatly reduced transmission efficiency. The impact is particularly greater for high-power optical products, and the device will be burned due to overheating.

[0004] Therefore, it is necessary to provide more effective and reliable technical solutions. Summary of the invention

[0005] The present application provides a semiconductor structure and a method for forming the same, which can avoid silicon residues on both sides of a strip waveguide, reduce transmission loss, improve transmission efficiency, and improve device reliability.

[0006] One aspect of the present application provides a method for forming a semiconductor structure, comprising: providing an SOI substrate, the SOI substrate comprising a bottom silicon layer, an insulating layer and a top silicon layer, the SOI substrate comprising a ridge waveguide region and a strip waveguide region; forming a plurality of first grooves in the top silicon layer, so that a plurality of ridge waveguides are formed in the ridge waveguide region and the strip waveguide region, the width of the plurality of first grooves being less than or equal to 0.5 micrometers or greater than or equal to 1.5 micrometers; sequentially forming a hard mask layer and an anti-reflection layer in the first grooves and on the surface of the top silicon layer, the surface of the hard mask layer above the first grooves being flat; forming a photoresist layer on the surface of the anti-reflection layer, a plurality of first openings being formed in the photoresist layer and completely covering the first grooves in the strip waveguide region; etching the anti-reflection layer, the hard mask layer and the top silicon layer along the first openings to the surface of the insulating layer, so that the ridge waveguide in the strip waveguide region is converted into a strip waveguide, and no top silicon layer remains on the surfaces of the insulating layer on both sides of the strip waveguide.

[0007] In some embodiments of the present application, when the anti-reflection layer, the hard mask layer and the top silicon layer are etched along the first opening to the surface of the insulating layer, the first trench of the stripe waveguide region extends into the insulating layer.

[0008] In some embodiments of the present application, the method for forming the plurality of first grooves includes: forming a patterned photoresist layer on the surface of the top silicon layer, the patterned photoresist layer defining the positions of the first grooves; etching the top silicon layer using the patterned photoresist layer as a mask to form the plurality of first grooves; and removing the patterned photoresist layer.

[0009] In some embodiments of the present application, a minimum distance between a sidewall of the strip waveguide and a boundary of the first trench is 0 to 0.025 micrometers.

[0010] In some embodiments of the present application, a width of a portion of the plurality of first grooves is less than or equal to 0.5 micrometers, and a width of another portion of the plurality of first grooves is greater than or equal to 1.5 micrometers.

[0011] In some embodiments of the present application, the method for forming the semiconductor structure further includes: removing the hard mask layer, the anti-reflection layer and the photoresist layer.

[0012] Another aspect of the present application also provides a semiconductor structure, including: an SOI substrate, the SOI substrate including a bottom silicon layer, an insulating layer and a top silicon layer, the SOI substrate including a ridge waveguide region and a strip waveguide region; a plurality of ridge waveguides located in the top silicon layer of the ridge waveguide region; a plurality of strip waveguides located in the top silicon layer of the strip waveguide region, a first groove is included between adjacent strip waveguides, the width of the first groove is less than or equal to 0.5 microns or greater than or equal to 1.5 microns, and there is no top silicon layer residue on the surface of the insulating layer on both sides of the strip waveguide.

[0013] In some embodiments of the present application, the first trench of the strip waveguide region extends into the insulating layer.

[0014] In some embodiments of the present application, a minimum distance between a sidewall of the strip waveguide and a boundary of the first trench is 0 to 0.025 micrometers.

[0015] In some embodiments of the present application, a width of a portion of the first groove is less than or equal to 0.5 micrometers, and a width of another portion of the first groove is greater than or equal to 1.5 micrometers.

[0016] The present application provides a semiconductor structure and a method for forming the same, which adjusts the etching process parameters in the transition process from a ridge waveguide to a strip waveguide, thereby avoiding silicon residue on both sides of the strip waveguide, reducing transmission loss, improving transmission efficiency, and improving device reliability. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The following figures describe in detail the exemplary embodiments disclosed in this application. The same reference numerals represent similar structures in several views of the drawings. Those skilled in the art will understand that these embodiments are non-limiting, exemplary embodiments, and the drawings are only for the purpose of illustration and description, and are not intended to limit the scope of this application. Other embodiments may also accomplish the inventive intent in this application. It should be understood that the drawings are not drawn to scale.

[0018] in:

[0019] Figures 1 to 3 It is a schematic diagram of the structures of various steps in some methods for forming semiconductor structures;

[0020] Figures 4 to 15 It is a structural schematic diagram of each step in the method for forming a semiconductor structure described in an embodiment of the present application. DETAILED DESCRIPTION

[0021] The following description provides specific application scenarios and requirements of the present application, with the purpose of enabling those skilled in the art to make and use the content in the present application. It will be apparent to those skilled in the art that various local modifications to the disclosed embodiments are apparent, and the general principles defined herein may be applied to other embodiments and applications without departing from the spirit and scope of the present application. Therefore, the present application is not limited to the embodiments shown, but to the widest scope consistent with the claims.

[0022] The technical solution of the present invention is described in detail below in conjunction with the embodiments and drawings.

[0023] Figures 1 to 3 Schematic diagram of the structures of various steps in some methods for forming semiconductor structures.

[0024] refer to Figure 1 As shown, an SOI substrate 100 is provided, the SOI substrate 100 includes a bottom silicon layer 101, an insulating layer 102 and a top silicon layer 103, and a plurality of first grooves 110 and a ridge waveguide 120 are formed in the top silicon layer 103. The ridge waveguide 120 is represented by a dotted frame and is formed by etching a portion of the top silicon layer 103.

[0025] refer to Figure 2 As shown, a hard mask layer 130 and an anti-reflection layer 140 are sequentially formed in the first trench 110 and on the surface of the top silicon layer 103. Due to the existence of the first trench 110, a conical recess is formed above the first trench 110 when the hard mask layer 130 is deposited. The subsequent anti-reflection layer 140 will also fill the conical recess to form a conical sidewall 131 in the hard mask layer 130.

[0026] refer to Figure 3 As shown, the ridge waveguide 120 is etched using the hard mask layer 130 and the anti-reflection layer 140 as masks to transform the ridge waveguide 120 into a strip waveguide 150 .

[0027] However, since the etching speed of the tapered sidewall 131 is lower than that of the hard mask layer 130, the hard mask layer 130 below the tapered sidewall 131 is removed last, and then the top silicon layer 103 below the tapered sidewall 131 is etched last. When the top silicon layer 103 at the remaining position at the bottom of the first trench 110 is etched to the surface of the insulating layer 102, the top silicon layer 103 below the tapered sidewall 131 is not completely etched, resulting in silicon residue at the bottom of the first trench 110, defects next to the strip waveguide 150, and increased transmission loss. The transmission efficiency is greatly reduced, especially for high optical power products, which will burn the device due to overheating.

[0028] In view of the above problems, in some processes, the thickness of the tapered sidewalls and the size of the silicon residue are reduced by adjusting the thickness of the hard mask layer and improving the surface flatness of the hard mask layer. However, this method cannot completely solve the above problems, and adjusting the thickness of the hard mask layer and improving the surface flatness of the hard mask layer increase the complexity and difficulty of the process and reduce production efficiency.

[0029] Therefore, the present application provides a semiconductor structure and a method for forming the same, which adjusts the etching process parameters in the transition process from ridge waveguide to strip waveguide, thereby avoiding the generation of silicon residues on both sides of the strip waveguide, reducing transmission loss, improving transmission efficiency, and improving device reliability.

[0030] Figures 4 to 15 The following is a schematic diagram of the structure of each step in the method for forming a semiconductor structure according to an embodiment of the present application. The method for forming a semiconductor structure according to an embodiment of the present application is described in detail in conjunction with the accompanying drawings.

[0031] refer to Figure 4 As shown, an SOI substrate 200 is provided, the SOI substrate 200 includes a bottom silicon layer 201, an insulating layer 202 and a top silicon layer 203, and the SOI substrate 200 includes a ridge waveguide region 204 and a stripe waveguide region 205. Specifically, the SOI (silicon on insulator) substrate 200 includes a bottom silicon layer 201, an insulating layer 202 located on a surface of the bottom silicon layer 201, and a top silicon layer 203 located on a surface of the insulating layer 202.

[0032] In some embodiments of the present application, the material of the bottom silicon layer 201 is silicon, the material of the insulating layer 202 is silicon dioxide, and the material of the top silicon layer 203 is silicon. A silicon-on-insulator substrate (SOI substrate) is a common substrate structure in semiconductor structures, so the formation process and detailed structure of the silicon-on-insulator substrate 200 are not described here.

[0033] In some embodiments of the present application, the ridge waveguide region 204 is used to form a ridge waveguide. The strip waveguide region 205 is used to form a strip waveguide.

[0034] refer to Figure 5 , Figure 6 and Figure 7 As shown, Figure 5 is a top view of the semiconductor structure, Figure 6 For along Figure 5 The longitudinal section made by the dotted line XX, Figure 7 For along Figure 5 A plurality of first grooves 210 are formed in the top silicon layer 203, so that a plurality of ridge waveguides 220 are formed in the ridge waveguide region 204 and the strip waveguide region 205, and the width of the plurality of first grooves 210 is less than or equal to 0.5 microns or greater than or equal to 1.5 microns.

[0035] refer to Figure 5 As shown, due to Figure 5 This is a top view, and thus the first groove 210 cannot be directly shown. Instead, the first groove 210 is represented by a dotted line.

[0036] In some embodiments of the present application, the width of a portion of the plurality of first grooves 210 is less than or equal to 0.5 microns, such as 0.45 microns, 0.4 microns, 0.35 microns, 0.3 microns, 0.25, 0.2 microns, 0.15 microns, 0.1 microns, or less than or equal to 0.05 microns, etc.; the width of another portion of the plurality of first grooves 210 is greater than or equal to 1.5 microns, such as 1.55 microns, 1.6 microns, 1.65 microns, 1.7 microns, 1.75 microns, 1.8 microns, 1.85 microns, 1.9 microns, or greater than or equal to 1.95 microns, etc. Specifically, Figure 6 The first trench 210 is shown as having a width less than or equal to 0.5 micrometers. Figure 7 The portion of the first trench 210 having a width greater than or equal to 1.5 micrometers is shown.

[0037] In some embodiments of the present application, the method for forming the plurality of first grooves 210 includes: forming a patterned photoresist layer on the surface of the top silicon layer 203, the patterned photoresist layer defining the positions of the first grooves 210; etching the top silicon layer 203 using the patterned photoresist layer as a mask to form the plurality of first grooves 210; and removing the patterned photoresist layer. A mask layer may also be formed between the surface of the top silicon layer 203 and the patterned photoresist layer, and the mask layer may be retained after photolithography.

[0038] refer to Figure 8 and Fig. 9 As shown, Figure 8 For along Figure 5 The longitudinal section made by the dotted line XX, Fig. 9 For along Figure 5 The longitudinal section is made by the dotted line YY. A hard mask layer 230 and an anti-reflection layer 240 are formed in the first groove 210 and on the surface of the top silicon layer 203 in sequence, and the surface of the hard mask layer 230 above the first groove 210 is flat. It should be noted that the flatness mentioned here is not necessarily completely flat, but can be a range of relatively high flatness, for example, the surface thickness fluctuation range is below 1% to 3%. As long as the depression on the surface of the hard mask layer 230 does not affect the subsequent etching of the bottom silicon layer, no silicon residue will be generated on the surface of the insulating layer on both sides of the strip waveguide.

[0039] Specifically, refer to Figure 8 As shown, since the width of the first trench 210 is less than or equal to 0.5 microns, only a small conical depression is formed on the surface of the hard mask layer 230 above the first trench 210, and the conical sidewall 231 formed after the anti-reflection layer 240 fills the conical depression is also small in size. Under such a size, it can be ensured that the subsequent etching of the bottom silicon layer will not produce silicon residues on the surface of the insulating layer on both sides of the strip waveguide.

[0040] In some embodiments of the present application, the size of the tapered sidewall 231 is related to the width of the first trench 210. Reducing the width of the first trench 210 can reduce the size of the tapered sidewall 231 or even completely eliminate the tapered sidewall. In practice, the width of the first trench 210 can be set appropriately according to actual needs.

[0041] refer to Fig. 9 As shown, since the width of the first trench 210 is greater than or equal to 1.5 microns, only a small and smooth arc-shaped depression is formed on the surface of the hard mask layer 230 above the first trench 210, and the anti-reflection layer 240 fills the conical depression to form a small and smooth arc-shaped sidewall 232. Under such a size structure, it can be ensured that the subsequent etching of the bottom silicon layer will not produce silicon residues on the surface of the insulating layer on both sides of the strip waveguide.

[0042] In some embodiments of the present application, the size structure of the curved sidewall 232 is related to the width of the first groove 210. Increasing the width of the first groove 210 can reduce the size and curvature of the tapered sidewall 231 or even completely eliminate the curved sidewall. In practice, the width of the first groove 210 can be set appropriately according to actual needs.

[0043] In some embodiments of the present application, the width of the first groove 210 can also be set such that the width of some first grooves 210 is less than or equal to 0.5 microns, and the width of some first grooves 210 is greater than or equal to 1.5 microns. For example, the width of one first groove is less than or equal to 0.5 microns, and the width of another first groove is greater than or equal to 1.5 microns. The width of the first groove of the technical solution of the present application can be combined by a variety of different settings to meet different device requirements.

[0044] refer to Fig.10 and Fig.11 As shown, Fig.10 For along Figure 5 The longitudinal section made by the dotted line XX, Fig.11 For along Figure 5 A longitudinal cross-sectional view is made by the dotted line YY. A photoresist layer 250 is formed on the surface of the anti-reflection layer 240 , and a plurality of first openings 251 are formed in the photoresist layer 250 to completely cover the first grooves 210 in the strip waveguide region 205 .

[0045] In some embodiments of the present application, when the width of the plurality of first trenches 210 is greater than or equal to 1.5 microns, the width of the plurality of first openings 251 is 0 to 0.05 microns greater than the width of the plurality of first trenches 210. This is to prevent the top silicon layer 203 at the bottom of the first trenches 210 from not being completely etched, and to prevent silicon residues from being caused by line fluctuations in the process.

[0046] refer to Fig.12 and Fig.13 As shown, Fig.12 For along Figure 5 The longitudinal section made by the dotted line XX, Fig.13 For along Figure 5 The longitudinal cross-section is made by the dotted line YY. The anti-reflection layer 240, the hard mask layer 230 and the top silicon layer 203 are etched along the first opening 251 to the surface of the insulating layer 202, so that the ridge waveguide 220 in the strip waveguide area 205 is transformed into a strip waveguide 260, and no top silicon layer remains on the surface of the insulating layer 202 on both sides of the strip waveguide 260. Since the tapered sidewall 231 and the curved sidewall 232 are small in size or even have no tapered sidewall and curved sidewall, no silicon residue will be formed in the first trench 210 after etching.

[0047] In some embodiments of the present application, when etching the anti-reflection layer 240, the hard mask layer 230 and the top silicon layer 203 along the first opening 251 to the surface of the insulating layer 202, refer to Fig.12 and Fig.13 As shown, the first groove 210 of the strip waveguide region 205 extends into the insulating layer 202. It should be noted that the first groove 210 is represented by a dotted frame.

[0048] refer to Fig.14 and Fig.15 As shown, Fig.14 For along Figure 5 The longitudinal section made by the dotted line XX, Fig.15 For along Figure 5 The longitudinal cross-section is made by the dashed line YY. In some embodiments of the present application, the method for forming the semiconductor structure further includes: removing the hard mask layer 230 , the anti-reflection layer 240 and the photoresist layer 250 .

[0049] The present application provides a method for forming a semiconductor structure, which adjusts the etching process parameters in the transition process from a ridge waveguide to a strip waveguide, thereby avoiding silicon residues on both sides of the strip waveguide, reducing transmission losses, improving transmission efficiency, and improving device reliability.

[0050] The embodiment of the present application also provides a semiconductor structure, referring to Fig.14 and Fig.15 As shown, it includes: an SOI substrate 200, the SOI substrate 200 includes a bottom silicon layer 201, an insulating layer 202 and a top silicon layer 203, the SOI substrate 200 includes a ridge waveguide region 204 and a strip waveguide region 205; a plurality of ridge waveguides 220, located in the top silicon layer 203 of the ridge waveguide region 204; a plurality of strip waveguides 260, located in the top silicon layer 203 of the strip waveguide region 205, a first groove 210 is included between adjacent strip waveguides 260, the width of the first groove 210 is less than or equal to 0.5 microns or greater than or equal to 1.5 microns, and no top silicon layer remains on the surface of the insulating layer 202 on both sides of the strip waveguide 260.

[0051] refer to Fig.14 and Fig.15 As shown, the SOI (Silicon On Insulator) substrate 200 includes a bottom silicon layer 201 , an insulating layer 202 located on a surface of the bottom silicon layer 201 , and a top silicon layer 203 located on a surface of the insulating layer 202 .

[0052] In some embodiments of the present application, the material of the bottom silicon layer 201 is silicon, the material of the insulating layer 202 is silicon dioxide, and the material of the top silicon layer 203 is silicon. A silicon-on-insulator substrate (SOI substrate) is a common substrate structure in semiconductor structures, so the formation process and detailed structure of the silicon-on-insulator substrate 200 are not described here.

[0053] In some embodiments of the present application, a mask layer may also be formed on the surface of the top silicon layer 203 .

[0054] In some embodiments of the present application, the ridge waveguide region 204 is used to form a ridge waveguide. The strip waveguide region 205 is used to form a strip waveguide.

[0055] In some embodiments of the present application, the width of a portion of the plurality of first grooves 210 is less than or equal to 0.5 microns, such as 0.45 microns, 0.4 microns, 0.35 microns, 0.3 microns, 0.25, 0.2 microns, 0.15 microns, 0.1 microns, or less than or equal to 0.05 microns, etc.; the width of another portion of the plurality of first grooves 210 is greater than or equal to 1.5 microns, such as 1.55 microns, 1.6 microns, 1.65 microns, 1.7 microns, 1.75 microns, 1.8 microns, 1.85 microns, 1.9 microns, or greater than or equal to 1.95 microns, etc. Specifically, Fig.14 The first trench 210 is shown as having a width less than or equal to 0.5 micrometers. Fig.15 The portion of the first trench 210 having a width greater than or equal to 1.5 micrometers is shown.

[0056] In some embodiments of the present application, the width of the first groove 210 can also be set such that the width of some first grooves 210 is less than or equal to 0.5 microns, and the width of some first grooves 210 is greater than or equal to 1.5 microns. For example, the width of one first groove is less than or equal to 0.5 microns, and the width of another first groove is greater than or equal to 1.5 microns. The width of the first groove of the technical solution of the present application can be combined by a variety of different settings to meet different device requirements.

[0057] refer to Fig.12 and Fig.13 As shown, in some embodiments of the present application, the first groove 210 of the strip waveguide region 205 extends into the insulating layer 202. It should be noted that the first groove 210 is represented by a dotted frame.

[0058] In some embodiments of the present application, when the width of the plurality of first trenches 210 is greater than or equal to 1.5 micrometers, the minimum distance between the sidewall of the strip waveguide 260 and the boundary of the first trench is 0 to 0.025 micrometers.

[0059] The present application provides a semiconductor structure and a method for forming the same, which adjusts the etching process parameters in the transition process from a ridge waveguide to a strip waveguide, thereby avoiding silicon residue on both sides of the strip waveguide, reducing transmission loss, improving transmission efficiency, and improving device reliability.

[0060] In summary, after reading the contents of this application, those skilled in the art will appreciate that the aforementioned application contents may be presented only in an exemplary manner and may not be restrictive. Although not explicitly stated herein, those skilled in the art will appreciate that this application is intended to encompass various reasonable changes, improvements and modifications to the embodiments. These changes, improvements and modifications are within the spirit and scope of the exemplary embodiments of this application.

[0061] It should be understood that the term "and / or" used in this embodiment includes any or all combinations of one or more of the associated listed items. It should be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to another element, or there can also be intermediate elements.

[0062] Similarly, it should be understood that when an element such as a layer, region, or substrate is referred to as being "on" another element, it can be directly on the other element or there can be intervening elements. In contrast, the term "directly" means that there are no intervening elements. It should also be understood that the terms "comprising," "containing," "including," or "comprising," when used in this application document, indicate the presence of the recited features, wholes, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, components, and / or groups thereof.

[0063] It should also be understood that although the terms first, second, third, etc. can be used to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. Therefore, without departing from the teachings of the present application, the first element in some embodiments can be referred to as the second element in other embodiments. The same reference numerals or the same reference signs represent the same elements throughout the specification.

[0064] In addition, the present specification describes exemplary embodiments by reference to idealized exemplary cross-sectional views and / or plan views and / or stereograms. Therefore, differences from the illustrated shapes due to, for example, manufacturing techniques and / or tolerances are foreseeable. Therefore, the exemplary embodiments should not be interpreted as being limited to the shapes of the regions shown herein, but should include deviations in shapes caused by, for example, manufacturing. For example, an etched region shown as a rectangle will typically have circular or curved features. Therefore, the region shown in the figure is schematic in nature, and its shape is not intended to illustrate the actual shape of the region of the device nor to limit the scope of the exemplary embodiments.

Claims

1. A method for forming a semiconductor structure, characterized in that: include: Providing an SOI substrate, the SOI substrate comprising a bottom silicon layer, an insulating layer and a top silicon layer, the SOI substrate comprising a ridge waveguide region and a strip waveguide region; Forming a plurality of first grooves in the top silicon layer so that a plurality of ridge waveguides are formed in the ridge waveguide region and the strip waveguide region, wherein the width of the plurality of first grooves is less than or equal to 0.5 micrometers or greater than or equal to 1.5 micrometers; forming a hard mask layer and an anti-reflection layer in the first trench and on the surface of the top silicon layer in sequence, wherein the surface of the hard mask layer above the first trench is flat; forming a photoresist layer on the surface of the anti-reflection layer, wherein a plurality of first openings are formed in the photoresist layer and completely cover the first grooves in the strip waveguide region; The anti-reflection layer, the hard mask layer and the top silicon layer are etched along the first opening to the surface of the insulating layer, so that the ridge waveguide in the strip waveguide area is transformed into a strip waveguide, and no top silicon layer remains on the insulating layer surfaces on both sides of the strip waveguide.

2. The method for forming a semiconductor structure according to claim 1, wherein: When the anti-reflection layer, the hard mask layer and the top silicon layer are etched along the first opening to the surface of the insulating layer, the first trench of the stripe waveguide region extends into the insulating layer.

3. The method for forming a semiconductor structure according to claim 1, wherein: The method of forming the plurality of first grooves comprises: forming a patterned photoresist layer on the surface of the top silicon layer, wherein the patterned photoresist layer defines the position of the first groove; Using the patterned photoresist layer as a mask, etching the top silicon layer to form the plurality of first grooves; The patterned photoresist layer is removed.

4. The method for forming a semiconductor structure according to claim 1, wherein: The minimum distance between the sidewall of the stripe waveguide and the boundary of the first trench is 0 to 0.025 micrometers.

5. The method for forming a semiconductor structure according to claim 1, wherein: The width of a portion of the plurality of first grooves is less than or equal to 0.5 micrometers, and the width of another portion of the plurality of first grooves is greater than or equal to 1.5 micrometers.

6. The method for forming a semiconductor structure according to claim 1, wherein: Also includes: The hard mask layer, the anti-reflection layer and the photoresist layer are removed.

7. A semiconductor structure, characterized in that: include: An SOI substrate, the SOI substrate comprising a bottom silicon layer, an insulating layer and a top silicon layer, the SOI substrate comprising a ridge waveguide region and a strip waveguide region; A plurality of ridge waveguides located in the top silicon layer of the ridge waveguide region; A plurality of strip waveguides are located in the top silicon layer of the strip waveguide area, and a first groove is included between adjacent strip waveguides. The width of the first groove is less than or equal to 0.5 microns or greater than or equal to 1.5 microns, and no top silicon layer remains on the surface of the insulating layer on both sides of the strip waveguide.

8. The semiconductor structure according to claim 7, wherein: The first trench of the stripe waveguide region extends into the insulating layer.

9. The semiconductor structure according to claim 7, wherein: The minimum distance between the sidewall of the stripe waveguide and the boundary of the first trench is 0 to 0.025 micrometers.

10. The semiconductor structure according to claim 7, wherein: A width of a portion of the first trench is less than or equal to 0.5 micrometers, and a width of another portion of the first trench is greater than or equal to 1.5 micrometers.

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