Hard disk management system and method, electronic equipment and storage medium

Abstract

The invention provides a hard disk management system and method, electronic equipment and a storage medium, and relates to the field of hard disk management, the system comprises a CPU used for sending a VPP signal to an I2CSWITCH chip; the at least one I2CSWITCH chip is used for receiving the VPP signal output by the CPU and distributing the VPP signal into a plurality of shunt signals according to different PCIe ports, and the shunt signals are transmitted through respective corresponding I2CSWITCH channels; and the analysis module is connected with the I2CSWITCH chip through a plurality of I2CSWITCH channels, and is used for receiving the shunting signal from the I2CSWITCH chip, determining a target hard disk from the plurality of NVME hard disks according to the shunting signal, and sending a corresponding management instruction to the target hard disk. According to the method and the device, the number of available VPP addresses is effectively expanded, and the ever-increasing NVME hard disk management requirements are met.

Description

Technical Field

[0001] The present disclosure relates to the field of hard disk management, and in particular to a hard disk management system, method, electronic device and storage medium. Background Art

[0002] With the development of the Internet and data centers, the importance of data storage and management has become increasingly prominent. NVME (Non-Volatile Memory Express) hard drives are widely used in server platforms due to their high performance and low latency. In order to efficiently manage these NVME hard drives, servers usually use VPP (Virtual Pin Port) signals for control and monitoring.

[0003] In the traditional VPP topology, the CPU communicates with the backplane's parsing chip (such as CPLD) through a VPP signal to manage NVME hard disks connected to multiple PCIe ports. However, the number of preset VPP addresses is limited to only 8 addresses. When the CPU platform is upgraded and the number of PCIe ports increases, it is difficult to meet the growing management needs, resulting in insufficient addresses. Summary of the invention

[0004] The embodiments of the present disclosure provide a hard disk management system, method, electronic device and storage medium, aiming to solve the problems existing in the above-mentioned background technology.

[0005] In order to solve the above technical problems, the present disclosure is implemented as follows:

[0006] In a first aspect, an embodiment of the present disclosure provides a hard disk management system, the system comprising:

[0007] The CPU deployed on the mainboard is used to send a VPP signal to the I2CSWITCH chip, wherein the VPP signal includes a management instruction, and the management instruction is used to instruct management of the NVME hard disk;

[0008] At least one I2CSWITCH chip is deployed on the mainboard, the I2CSWITCH chip is used to receive the VPP signal output by the CPU, and distribute the VPP signal into a plurality of shunt signals according to different PCIe ports, the plurality of shunt signals are a plurality of independent signals output by the I2CSWITCH chip according to the input VPP signal, and the plurality of shunt signals are transmitted through the respective corresponding I2CSWITCH channels;

[0009] A parsing module deployed on the NVME hard disk backplane, the parsing module is connected to the I2CSWITCH chip through the multiple I2CSWITCH channels, the parsing module is used to receive a shunt signal from the I2CSWITCH chip, and, according to the shunt signal, determine a target hard disk from the multiple NVME hard disks and send a corresponding management instruction to the target hard disk.

[0010] Optionally, among the multiple shunt signals, the VPP address of each shunt signal is the same.

[0011] Optionally, for the different PCIe ports, the VPP signal line of each PCIe port is merged with the corresponding high-speed data transmission signal line, and the VPP signal of each PCIe port is bound to the corresponding high-speed data transmission signal.

[0012] Optionally, the system further includes an uplink device, which is connected to the analysis module by multiplexing the I2CSWITCH channel; the uplink device is used to send an I2C signal to the analysis module, and the I2C signal is used to instruct management of the NVME hard disk.

[0013] Optionally, the analysis module includes any one of the following: a complex programmable logic device CPLD, a microcontroller MCU, and a PCA9555 expander.

[0014] In a second aspect, an embodiment of the present disclosure provides a hard disk management method, which is applied to a hard disk management system. The method includes:

[0015] Receiving a VPP signal from a CPU, wherein the VPP signal includes a management instruction, and the management instruction is used to instruct management of an NVME hard disk;

[0016] The VPP signal is distributed into a plurality of shunt signals according to different PCIe ports through an I2CSWITCH chip, and the plurality of shunt signals are transmitted to a parsing module through one-to-one corresponding I2CSWITCH channels, wherein the plurality of shunt signals are a plurality of independent signals output by the I2CSWITCH chip according to the input VPP signal;

[0017] Through the analysis module, a target hard disk is determined from the multiple NVME hard disks according to the shunt signal, and a management instruction corresponding to the shunt signal is sent to the target hard disk.

[0018] Optionally, the determining, by the analysis module, a target hard disk from the multiple NVME hard disks according to the shunt signal, and sending a management instruction corresponding to the shunt signal to the target hard disk includes:

[0019] Receiving each shunt signal through the analysis module, wherein the VPP address of each shunt signal is the same, for the different PCIe ports, the VPP signal line of each PCIe port is merged with the corresponding high-speed data transmission signal line, and the VPP signal of each PCIe port is bound to the corresponding high-speed data transmission signal;

[0020] The shunt signal is matched with the high-speed data transmission signals of each of the multiple NVME hard disks, a target hard disk is determined, and a corresponding management instruction is sent to the target hard disk.

[0021] Optionally, after sending the management instruction corresponding to the diversion signal to the target hard disk, the method further includes:

[0022] Acquire, through a corresponding I2CSWITCH channel, management information returned by the parsing module, in which the target hard disk responds to the management instruction;

[0023] Integrate the management information according to different PCIe ports, and send the integrated management information to the CPU;

[0024] The management information is parsed by the CPU, and corresponding management operations are performed according to the management information.

[0025] In a third aspect, an embodiment of the present disclosure provides an electronic device, comprising: a processor, a memory, and a computer program stored in the memory and capable of running on the processor, wherein the computer program implements the steps of a hard disk management method when executed by the processor.

[0026] In a fourth aspect, an embodiment of the present application provides a computer-readable storage medium, on which a computer program is stored, and when the computer program is executed by a processor, the steps of a hard disk management method are implemented.

[0027] The technical solution provided by the embodiments of the present disclosure brings at least the following beneficial effects:

[0028] The present disclosure introduces the I2CSWITCH chip, which effectively expands the number of available VPP addresses by allocating the VPP signal into multiple shunt signals, meeting the growing demand for NVME hard disk management. This enables efficient management even when the number of PCIe ports increases. The parsing module can quickly identify the target NVME hard disk and send corresponding management instructions based on the shunt signal from the I2CSWITCH chip, thereby improving the system's response speed, reducing management delays, and enhancing user experience. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0030] Figure 1 It is a topological diagram of a hard disk management system in the related art;

[0031] Figure 2 This is a topological diagram of a hard disk management system provided by an embodiment of the present disclosure;

[0032] Figure 3 It is a topological diagram of a hard disk management system under different VPP uplink signal multiplexing conditions provided by an embodiment of the present disclosure;

[0033] Figure 4 It is a schematic diagram of the steps of a hard disk management method provided by an embodiment of the present disclosure. DETAILED DESCRIPTION

[0034] The following will be combined with the drawings in the embodiments of the present disclosure to clearly and completely describe the technical solutions in the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, rather than all of the embodiments. Based on the embodiments in the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0035] In today's data centers and high-performance computing environments, the management and monitoring of NVME hard drives are becoming increasingly important. As storage demand continues to grow, traditional hard drive management systems face many challenges such as insufficient VPP addresses, cable redundancy, and low resolution efficiency, which restrict the scalability and flexibility of the system. Figure 1 It is a topological diagram of a hard disk management system in the related art, such as Figure 1As shown, the CPU outputs a VPP signal, which is connected to the parsing module (VPP parsing IC) of the backplane through an independent VPP cable. In this process, the CPU manages multiple PCIe ports, each port corresponding to a different NVMe hard disk. The CPU passes the management information to the parsing module through this single VPP signal line, and the parsing module parses the VPP signal to identify and process the management instructions of each NVMe hard disk according to a specific VPP address. The parsing module on the backplane determines the NVMe disk to be operated according to the address information in the transmitted VPP signal, and performs corresponding operations, such as fault diagnosis, hard disk status indicator light (the embodiment of the present disclosure takes lighting as an example), etc. NVMe hard disks are distinguished by VPP addresses. Currently, there are only 8 available VPP addresses (0x40, 0x42, 0x44, 0x46, 0x48, 0x4A, 0x4C, 0x4E), so each CPU can only manage up to 4 PCIe ports (because each port corresponds to two NVMe disks, and each disk needs to occupy an address). Each backplane is connected to the CPU of the motherboard through a separate VPP cable. If the server configuration includes multiple backplanes, additional VPP cables are required to connect each backplane in series (using a daisy-chain topology) to ensure that all backplanes can receive the VPP signal from the CPU.

[0036] visible, Figure 1 The hard disk management system topology shown has the following obvious disadvantages. First, there are only 8 available VPP addresses, which limits the number of NVMe disks that can be managed by each CPU. With the upgrade of the CPU platform, the number of PCIe ports continues to increase, and 8 VPP addresses can no longer meet the demand. It is necessary to expand the chip for address multiplexing, which increases the complexity of system design. Secondly, each backplane requires an independent VPP cable, resulting in redundant cables. Especially in the multi-backplane configuration, the number of cables increases sharply, and the cable management is difficult, which increases the complexity of assembly and maintenance. The daisy chain topology is used to connect the backplane. Due to the cable length problem, the signal transmission may have the hidden danger of signal quality degradation, affecting the overall performance. Furthermore, the parsing module on the backplane needs to parse each NVMe disk according to the address information of the VPP signal. With the increase in the number of ports, the workload of the parsing module increases, occupying a large amount of parsing resources, increasing hardware costs and design difficulties. If it is necessary to support multiple different upstream controllers (such as motherboards and RAID cards), the parsing module also needs to parse the VPP signals of different buses at the same time, further exacerbating the complexity of parsing.

[0037] The present invention proposes an innovative hard disk management system, which aims to introduce the I2CSWITCH chip, and realize efficient NVME hard disk management by intelligently diverting the VPP signal and distributing it to each PCIe port as needed. This not only simplifies cable wiring and reduces hardware costs, but also significantly improves parsing efficiency and system response speed. Figure 2 is a topological diagram of a hard disk management system provided by an embodiment of the present disclosure, such as Figure 2 As shown, the system includes: a CPU deployed on a mainboard, used to send a VPP signal to an I2CSWITCH chip, wherein the VPP signal includes a management instruction, and the management instruction is used to instruct management of an NVME hard disk; at least one of the I2CSWITCH chips deployed on the mainboard, wherein the I2CSWITCH chip is used to receive the VPP signal output by the CPU, and the VPP signal is respectively distributed into a plurality of shunt signals according to different PCIe ports, wherein the plurality of shunt signals are a plurality of independent signals output by the I2CSWITCH chip according to the input VPP signal, and the plurality of shunt signals are transmitted through the respective corresponding I2CSWITCH channels; a parsing module deployed on an NVME hard disk backplane, wherein the parsing module is connected to the I2CSWITCH chip through the plurality of I2CSWITCH channels, and the parsing module is used to receive the shunt signal from the I2CSWITCH chip, and, according to the shunt signal, determine a target hard disk from the plurality of NVME hard disks, and send a corresponding management instruction to the target hard disk.

[0038] In the hard disk management system provided in the embodiment of the present disclosure, it is mainly composed of the following key parts. The first part is the CPU, which is deployed on the server motherboard and is responsible for generating and sending VPP signals. The VPP signal is a signal generated by the CPU, which contains management instructions. The management instructions are used to instruct the system to perform various management operations on the NVME hard disk, such as fault diagnosis, hard disk positioning, hot plug processing and other functions. The role of the VPP signal is to pass the management instructions from the CPU to the I2CSWITCH chip, and then pass the instructions to the corresponding NVME hard disk through the shunt mechanism. The CPU controls the management of the NVMe hard disk by transmitting the VPP signal to the I2CSWITCH chip. The second part is the I2CSWITCH chip, which is also deployed on the motherboard and is used to receive the VPP signal from the CPU and shunt it. Specifically, the I2CSWITCH chip can distribute the VPP signal into multiple shunt signals according to different PCIe ports. The multiple shunt signals are transmitted through different channels of the I2CSWITCH so as to be accurately transmitted to the corresponding NVMe hard disk backplanes. The shunt signal is a plurality of independent signals generated by the I2CSWITCH chip according to the input VPP signal. Each shunt signal corresponds to a specific PCIe port and a corresponding NVME hard disk. By allocating the VPP signal into multiple shunt signals, multiple NVME hard disks can be managed simultaneously, and each shunt signal is transmitted through the corresponding I2CSWITCH channel to ensure that each hard disk receives the correct management instruction. Multiple shunt signals enable the system to flexibly expand and manage multiple hard disks without the need to set up a complex signal path for each hard disk. The third part is a parsing module, which is deployed on the backplane of the NVMe hard disk and is responsible for receiving the VPP signal shunted through the I2CSWITCH chip. The parsing module can identify the location of the target hard disk based on the received shunt signal and execute the corresponding management instructions. In the disclosed embodiment, the target hard disk is the NVME hard disk that the VPP signal is intended to manage. It can be one hard disk or multiple hard disks, depending on the management instructions that the CPU is intended to issue. For example, the CPU needs to read the status information of hard disk A through port 1 and issues the corresponding VPP signal, then hard disk A is the target hard disk. The module is connected to each channel of the I2CSWITCH chip to ensure independent control and management of each NVMe hard disk.

[0039] In the present disclosure, the I2CSWITCH chip realizes efficient management of multiple NVMe hard disks through a shunt mechanism. Specifically, the I2CSWITCH chip is a multi-channel switch chip, which is usually used to manage signal transmission in the I2C bus. In the embodiment of the present disclosure, the I2CSWITCH chip is connected between the CPU of the motherboard and multiple NVMe hard disk backplanes, and is mainly used to shunt the VPP signal generated by the CPU to each hard disk according to different needs. When multiple NVMe hard disks need to be managed, the CPU generates one or more VPP signals and transmits these signals to the I2CSWITCH chip on the motherboard. After the I2CSWITCH chip receives the signal from the CPU, it distributes these signals to multiple channels according to predefined configurations or instructions. Each channel transmits the allocated signal to a specific hard disk backplane. Assume that the CPU sends a VPP signal, which indicates that an NVMe hard disk is to be operated and managed. In this process, the main task of the I2CSWITCH chip is to shunt the VPP signal into multiple independent signals, corresponding to different PCIe ports or hard disk backplanes. The I2CSWITCH chip splits a VPP signal into multiple sub-signals based on the internal channel configuration, and these sub-signals are transmitted to the subsequent NVMe hard drive backplane through multiple channels of the I2CSWITCH chip. The signal in each channel is associated with the corresponding PCIe port to ensure that each NVMe hard drive can receive an independent management signal. In this way, multiple hard drives can be managed in parallel without conflict or interference.

[0040] As mentioned above, one problem that may be encountered in VPP signal transmission is that the VPP address space is limited, making it difficult to manage a large number of NVMe hard drives. In the related art, only 8 VPP addresses are supported (for example: 0x40, 0x42, 0x44, 0x46, 0x48, 0x4A, 0x4C, 0x4E), that is, in a server, only 8 NVME hard drives can be managed at most. With the development of technology, the number of PCIe ports on modern server platforms continues to increase, and it may be necessary to manage 16, 32 or even more NVME hard drives at the same time. The present disclosure deploys one or more I2CSWITCH chips, and the VPP signal output by the CPU can be diverted into multiple independent signal channels. For example, assuming that an I2CSWITCH chip can divide the VPP signal into 4 independent channels, each channel can be connected to multiple NVME hard drives. In this way, assuming that each channel can manage 4 hard drives, then through an I2CSWITCH chip, the hard drive management system can manage up to 16 hard drives (4 channels × 4 hard drives). Furthermore, if more I2CSWITCH chips are added, or a higher specification I2CSWITCH is used, the number of managed hard disks can be further expanded. For example, two I2CSWITCH chips, each chip supports 4 channels, and each channel can manage 4 hard disks, then the number of hard disks that can be managed by the hard disk management system will reach 32 (2 chips × 4 channels × 4 hard disks), which not only solves the problem of insufficient VPP addresses, but also provides unlimited possibilities for future expansion, allowing users to easily manage a large number of NVME hard disks according to actual needs to meet the growing data storage needs.

[0041] The present disclosure introduces the I2CSWITCH chip, which effectively expands the number of available VPP addresses by allocating the VPP signal into multiple shunt signals to meet the growing NVME hard disk management needs. This enables efficient management even when the number of PCIe ports increases. The parsing module can quickly identify the target NVME hard disk and send corresponding management instructions based on the shunt signal from the I2CSWITCH chip, thereby improving the system's response speed, reducing management delays, and enhancing user experience.

[0042] Exemplarily, among the multiple shunt signals, the VPP address of each shunt signal is the same.

[0043] In the traditional I2C architecture, each NVMe hard drive backplane or device usually needs to be assigned a unique VPP address to distinguish management instructions and signals. As the number of hard drive devices in the system increases, the VPP address space can easily become insufficient. If a large number of devices need to be managed, the available address space may be exhausted, resulting in the inability to assign a unique address to each hard drive.

[0044] If multiple devices share the same I2C bus and use the same VPP address, address conflicts will occur and signals cannot be transmitted and parsed correctly. As the number of hard disk devices increases, assigning different VPP addresses also increases the complexity of configuration and management.

[0045] The present disclosure allows multiple shunt signals to share the same VPP address by using the I2CSWITCH chip, thereby solving the problem of insufficient address space and conflict in the traditional architecture. Specifically, the VPP signal is shunted by the I2CSWITCH chip, and each shunt signal carries the same VPP address, which can greatly simplify the management and expansion capabilities of the VPP signal. After the I2CSWITCH chip receives the VPP signal transmitted by the CPU, it can shunt the VPP signal to multiple channels through an internal multi-channel design, and the signal sent by each channel carries the same VPP address. That is, the VPP address is consistent in the signal actually received by all NVMe hard disk devices. Under the topological architecture of the present disclosure, no matter how many hard disk devices there are in the system, the I2CSWITCH chip allows these devices to share the same VPP address. The address space used for management and configuration in the system is greatly saved, so that the number of hard disks can be expanded on a large scale without changing the VPP address.

[0046] Assume that there are 8 NVMe hard disk backplanes in the system. In the traditional architecture, these hard disks require 8 different VPP addresses. If the number of available VPP addresses is limited, expansion to more hard disks may result in insufficient address space. In the embodiment of the present disclosure, through the diversion of the I2CSWITCH chip, the hard disk of each backplane can use the same VPP address, for example, all 8 hard disk backplanes use address 0x10. Even if it is increased to 16 or more hard disks, the same VPP address can still be used, solving the problem of insufficient address space. Since all hard disk devices use the same VPP address and independent channels are allocated to transmit signals through the I2CSWITCH chip, address conflicts in the traditional architecture will not occur. The signal of each channel can be accurately delivered to a specific hard disk device without worrying about signal confusion or conflict. In a system without an I2CSWITCH chip, if two NVMe hard disk devices share the same VPP address 0x20, the transmitted signals may conflict, resulting in operation failure. However, in the architecture of the present disclosure, even if multiple hard disks use the same VPP address 0x20, since the signals are transmitted through different channels, each hard disk can still receive the signal correctly without conflict.

[0047] In addition, each shunt signal uses the same VPP address, which provides great flexibility for system expansion. When adding hard disk devices, there is no need to configure a separate VPP address for each new device, just allocate it through the channels of the I2CSWITCH chip. This not only reduces management complexity, but also greatly improves the ability of system expansion. If the system expands from 8 hard disks to 16 hard disks, you only need to increase the number of channels of the I2CSWITCH chip, without having to configure a new VPP address for each new hard disk, which simplifies the process of system expansion.

[0048] In the topological architecture disclosed in the present invention, multiple shunt signals use the same VPP address, which is achieved through the multi-channel allocation mechanism of the I2CSWITCH chip. This solves the problems of VPP address conflicts and insufficient address space in traditional architectures, greatly improves the system scalability and signal management efficiency, and can significantly simplify configuration and improve system performance.

[0049] Exemplarily, for the different PCIe ports, the VPP signal line of each PCIe port is merged with the corresponding high-speed data transmission signal line, and the VPP signal of each PCIe port is bound to the corresponding high-speed data transmission signal.

[0050] In traditional server NVMe management systems, each PCIe port has two different signal lines, one for transmitting VPP signals and the other for high-speed data transmission (MCIO). VPP signals are used to manage NVMe hard disk status, fault diagnosis, hard disk positioning, hot swapping and other functions, while high-speed data transmission signals are used to handle the rapid transmission of large-scale data. Traditional designs require that each PCIe port be laid with two different signal lines, one for transmitting VPP signals and one for transmitting MCIO high-speed signals. However, as the number of NVMe hard disks in the server increases, the number of two signal lines corresponding to each port increases significantly, resulting in complex cables and difficult assembly and maintenance. Independently transmitted signal lines require precise cable management and layout, especially in multi-backplane configurations, where the redundancy of VPP cables further exacerbates the complexity of connections. In addition, longer cable connections can cause problems such as signal attenuation and interference, affecting the transmission quality of VPP signals.

[0051] Taking the above problems into consideration, the present disclosure proposes a solution to merge the VPP signal line with the high-speed data transmission signal line. Specifically, the VPP signal of each PCIe port is merged with its corresponding high-speed data transmission signal line (MCIO), and signal binding is implemented. The VPP signal is no longer transmitted through an independent cable, but shares the same cable with the high-speed data transmission signal (MCIO). The I2CSWITCH chip manages multiple PCIe ports through different channels, and each channel transmits the VPP signal and the high-speed data transmission signal at the same time. By binding these two signals for transmission, the system can simultaneously transmit management information (VPP) and data information (MCIO). In the traditional solution, assuming that a server has 4 backplanes, each backplane is connected to 8 NVMe hard drives, and VPP and MCIO cables need to be configured separately for each backplane. A total of 32 cables are required (4 backplanes × 8 ports × 2 cables). Through the merging solution disclosed in the present disclosure, the number of cables is reduced by half, and only 16 cables (4 backplanes × 8 ports × 1 cable) are required, which greatly simplifies the design. After binding the VPP signal with the MCIO signal, the VPP signal interference problem caused by excessively long cables is avoided. The signals are uniformly transmitted through MCIO high-speed cables, which have higher cable quality and transmission stability, effectively improving the transmission efficiency of VPP signals.

[0052] In addition, in the traditional solution, the parsing module needs to parse the source address of each VPP signal and perform operations and management according to different NVMe disk positions. With the improvement of the present disclosure, since the VPP signal is bound to the MCIO high-speed signal and the transmission path is unified, the parsing logic of the parsing module has been simplified, and there is no need to perform independent parsing for each VPP address, which reduces the occupancy of the parsing module resources and reduces the design complexity. In the merged solution of the present disclosure, the parsing module no longer needs to assign different VPP addresses to each NVMe hard drive for parsing, but can manage it through the unified VPP signal transmitted by MCIO, which greatly reduces resource occupancy and improves parsing efficiency.

[0053] In general, the present disclosure optimizes the existing VPP management solution by merging the VPP signal with the high-speed data transmission signal line, thereby significantly improving the design simplicity, performance, and scalability of the system.

[0054] Exemplarily, the system also includes an uplink device, which is connected to the analysis module by multiplexing the I2CSWITCH channel; the uplink device is used to send an I2C signal to the analysis module, and the I2C signal is used to instruct the management of the NVME hard disk.

[0055] In the traditional VPP solution, the motherboard and upstream devices (such as Tri-mode RAID cards) are each connected and communicated with the analysis module (such as CPLD) through independent channels. Each upstream device sends its own management signal (VPP signal or I2C signal) to manage the NVMe hard drive. Different from the signal sources of the two upstream devices, the analysis module of the backplane, such as the complex programmable logic device CPLD, needs to allocate different resources for each device, such as GPIO pins and signal channels. The CPLD needs to process the signals of the motherboard and RAID card separately, occupying more GPIO and logic resources. The inconsistent signals of the two upstream devices make the CPLD analysis logic complex and increase the cost of CPLD material selection.

[0056] Figure 3 FIG. 1 is a topological diagram of a hard disk management system under different VPP uplink signal multiplexing conditions provided by an embodiment of the present disclosure, such as Figure 3 As shown, the present disclosure is based on the I2CSWITCH technology to unify the signals of different upstream devices (such as the motherboard and Tri-modeRAID card), and connect them to the analysis module by multiplexing the same I2C channel. The I2CSWITCH chip acts as a multiplexer, which is used to transmit management signals (including VPP signals and I2C signals) to the analysis module through corresponding channels according to different PCIe ports and other upstream devices. I2CSWITCH is capable of processing I2C signals or VPP signals from multiple different upstream devices, and selects appropriate channels to send these signals to the CPLD for analysis. The VPP signal output by the motherboard is no longer transmitted through an independent VPP cable, but is multiplexed with the I2CSWITCH channel and transmitted to other upstream devices through the same I2CSWITCH channel. Figure 3 In the Tri-modeRAID card shown, the I2C signal is used to manage the NVMe hard disk. In the traditional design, it is transmitted through different paths. In the disclosed embodiment, the I2C signal of the Tri-modeRAID card and the VPP signal of the motherboard can share the same I2CSWITCH channel and be passed to the parsing module through the same path. The VPP signal of the motherboard and the I2C signal of the Tri-modeRAID card can share the same VPP address. Due to the use of I2CSWITCH, the parsing module no longer needs to allocate different address spaces for different devices, and only needs to parse the multiplexed channels, which greatly simplifies the parsing logic of the parsing module. Since the I2CSWITCH chip can uniformly manage the signals of different upstream devices, the parsing module, such as CPLD, no longer needs to independently allocate GPIO pins or complex logic resources for each device. It only needs to parse the signal sent from the I2CSWITCH channel and execute the management instructions of the NVMe hard disk (such as lighting, fault reporting, etc.).

[0057] Exemplarily, the analysis module includes any one of the following: a complex programmable logic device CPLD, a microcontroller MCU, and a PCA9555 expander.

[0058] CPLD (Complex Programmable Logic Device) is a digital logic integrated circuit that can define its logical behavior through programming and is used to implement various complex logic control and signal processing tasks. Its hardware logic can be customized and programmed according to needs. As mentioned above, CPLD can receive signals transmitted by upstream devices (such as motherboards and Tri-mode RAID cards) through I2C SWITCH in real time, parse its content and manage NVMe hard drives. CPLD can achieve compatible processing of different signal protocols through programming. Because CPLD is highly programmable, it can dynamically configure internal logic resources according to different hardware requirements to cope with different signal types (such as VPP signals and I2C signals). And CPLD has parallel processing capabilities and can manage the status of multiple NVMe hard drives at the same time, including hard drive fault monitoring, LED status indication, startup and deactivation operations. Therefore, the present disclosure prefers CPLD as a parsing module.

[0059] MCU (Microcontroller Unit) is a single-chip computer that integrates processor, memory, input / output (I / O) interface and other functions, and is usually used in embedded systems to perform specific control tasks. Compared with CPLD, MCU usually has richer software programming capabilities and stronger processor performance. Compared with CPLD, MCU has relatively low hardware cost and is suitable for simpler or medium-complexity systems. Therefore, MCU is suitable for scenarios that have certain requirements for signal processing and hard disk management but do not require overly complex logic control. It is suitable for scenarios where flexible control logic is implemented through software, especially systems where signal analysis is relatively simple but requires certain intelligent management.

[0060] PCA9555 is an I / O expander with I2C interface. It can provide additional I / O pins, communicate with the main controller through I2C bus, expand GPIO (general input / output) port, and is used to expand more signal pins through I2C bus to control or monitor peripheral devices when I / O pin resources are insufficient in the system. As an I / O expander, PCA9555 has a simple structure and low cost. It is suitable for systems that need to expand a large number of GPIO resources. When the I / O resources of CPLD or MCU are insufficient, additional pins can be expanded through PCA9555 to control and monitor the status of multiple NVMe hard drives.

[0061] Exemplarily, the system also includes a status monitoring module, which is connected to the analysis module and is used to monitor the operating status of the target hard disk in real time and feed back monitoring information to the CPU, wherein the monitoring information includes hard disk health status, temperature, data transmission rate and fault diagnosis information.

[0062] The status monitoring module is designed to comprehensively monitor the operating status of NVMe hard disks. By communicating with the parsing module, it can obtain the operating status of each target hard disk in real time. Optionally, it can read the SMART information of each NVMe hard disk regularly. And it feeds back the monitoring information such as hard disk health status, temperature, data transfer rate and fault diagnosis information to the CPU.

[0063] The status monitoring module can effectively identify potential failures or performance problems of the hard disk by real-time collection of key indicators of the hard disk. When the hard disk is abnormal, the module can issue a warning signal in time, prompting the CPU to issue corresponding management instructions (such as stopping the faulty hard disk or performing fault recovery operations). For example, if the SMART value of a hard disk shows that its working time is close to the limit of its service life, the status monitoring module will immediately send this information to the CPU. After receiving it, the CPU will issue a warning signal and instruct the administrator to replace the hard disk as soon as possible to avoid data loss. In addition, by monitoring parameters such as temperature and transmission rate, resource allocation is optimized accordingly to prevent the hard disk from affecting overall performance due to overload or overheating. Optionally, it can be checked by threshold comparison. If the temperature of a hard disk exceeds the safe range, the status monitoring module will immediately transmit the temperature data to the CPU. After receiving this information, the CPU can automatically take measures, such as adjusting the fan speed, reducing the hard disk workload, or even temporarily disabling the hard disk until the temperature returns to normal. For example, if the temperature of an NVMe hard disk rises to 75°C due to overheating, the status monitoring module will immediately feedback this information to the CPU, and the CPU will adjust the load of the hard disk to prevent the temperature from rising further and avoid damage to the hard disk. In scenarios where big data or high-concurrency requests are processed, the status monitoring module will track the data transfer rate of the NVMe hard drive in real time.

[0064] If the transmission rate of a hard disk fluctuates abnormally (for example, it is far below the normal value), the status monitoring module will feed back the abnormal information to the CPU. The CPU can use this information to evaluate the performance bottleneck of the hard disk and decide whether to optimize the data flow path or perform load balancing. For example, if the data transmission rate of a hard disk is continuously lower than the expected value, the status monitoring module will find this problem and feed back to the CPU. The CPU will then redistribute the data flow to reduce the pressure on the hard disk, thereby optimizing system performance.

[0065] The status monitoring module provided by the disclosed embodiment can comprehensively monitor the operating status of each NVMe hard disk, ensuring that the hard disk can be processed in time before problems occur, avoiding data loss, system crashes, etc., while also improving the service life of the hard disk and the overall stability of the system. Specific monitoring information provides strong support for system management decisions, especially for application scenarios with high intensity and high reliability requirements such as data centers and cloud computing platforms. Through automated monitoring and management, the need for human intervention is reduced, and the efficiency and security level of the system are improved.

[0066] Figure 4 FIG. 1 is a schematic diagram of the steps of a hard disk management method provided by an embodiment of the present disclosure, which is applied to the hard disk management system as described above. Figure 4 As shown, the method includes:

[0067] Step S101, receiving a VPP signal from a CPU, wherein the VPP signal includes a management instruction, and the management instruction is used to instruct management of an NVME hard disk;

[0068] Step S102, using an I2CSWITCH chip, respectively allocating the VPP signal into a plurality of shunt signals according to different PCIe ports, and transmitting the plurality of shunt signals to a parsing module through one-to-one corresponding I2CSWITCH channels, wherein the plurality of shunt signals are a plurality of independent signals output by the I2CSWITCH chip according to the input VPP signal;

[0069] Step S103: determining a target hard disk from the multiple NVME hard disks according to the shunt signal through the analysis module, and sending a management instruction corresponding to the shunt signal to the target hard disk.

[0070] Involving step S101, a VPP signal is received from the CPU through the I2CSWITCH chip, and the VPP signal is used to start the entire NVMe hard disk management process. In this step, the CPU, as the control center, first processes the overall needs of the system, and then sends the corresponding VPP signal to the I2CSWITCH chip through a specific PCIe interface. The VPP signal contains management instructions on which NVMe hard disks to operate, and indicates the management tasks that need to be performed. It is the starting point of the management operation so that the system can respond to and process the instructions issued by the CPU in a timely manner.

[0071] Involving step S102, when the I2CSWITCH chip receives the VPP signal from the CPU, it shunts the VPP signal into multiple management signals for different hard disks according to the different PCIe ports specified in the signal. A VPP signal sent by the CPU is disassembled into multiple sub-signals, and transmitted to the hard disk analysis module through one-to-one corresponding I2CSWITCH channels. At this stage, the I2CSWITCH chip effectively acts as a signal scheduler, matching the control information in the VPP signal to different PCIe ports, and ensuring that the signal can be accurately transmitted to the corresponding hard disk analysis module. The shunt signal transmitted by each channel contains specific management instructions, indicating which operation to perform on which hard disk.

[0072] Involving step S103, after receiving the shunt signal transmitted through the I2CSWITCH chip, the parsing module starts working. It determines the specific target hard disk based on the received shunt signal. The parsing module will analyze the shunt signal, extract the identification information of the target hard disk, and confirm which hard disk to manage next in combination with the management instructions. Once the parsing module determines the target hard disk, it will send the corresponding management instructions to the target hard disk according to the instructions carried in the shunt signal. After receiving these instructions, the target hard disk performs the corresponding management operations according to the instruction requirements, such as starting, stopping or performing data transmission. Throughout the process, the core task of the parsing module is to ensure that the management instructions are accurately transmitted to the target hard disk and prompt the hard disk to execute according to the predetermined requirements.

[0073] The present disclosure introduces the I2CSWITCH chip, which effectively expands the number of available VPP addresses by allocating the VPP signal into multiple shunt signals to meet the growing NVME hard disk management needs. This enables efficient management even when the number of PCIe ports increases. The parsing module can quickly identify the target NVME hard disk and send corresponding management instructions based on the shunt signal from the I2CSWITCH chip, thereby improving the system's response speed, reducing management delays, and enhancing user experience.

[0074] Exemplarily, the target hard disk is determined from the multiple NVME hard disks according to the shunt signal through the analysis module, and the management instruction corresponding to the shunt signal is sent to the target hard disk, including: receiving each shunt signal through the analysis module, wherein the VPP address of each shunt signal is the same, for the different PCIe ports, the VPP signal line of each PCIe port is merged with the corresponding high-speed data transmission signal line, and the VPP signal of each PCIe port is bound to the corresponding high-speed data transmission signal; matching the shunt signal with the high-speed data transmission signals of each of the multiple NVME hard disks, determining the target hard disk, and sending the corresponding management instruction to the target hard disk.

[0075] The parsing module first receives the shunt signal from I2CSWITCH. The shunt signal is the result of the VPP signal sent from the CPU being shunted by the I2CSWITCH chip. Although the VPP addresses of all shunt signals are the same, they have been allocated and transmitted, and each shunt signal is now associated with a different PCIe port. Assume that there are three NVMe hard drives in the system, connected to PCIe port 1, port 2, and port 3 respectively. The CPU sends a common VPP signal, which is shunted into three independent signals through I2CSWITCH and sent to the parsing module, each corresponding to a PCIe port. The VPP signal line of each PCIe port is merged with its corresponding high-speed data transmission signal line. In this way, the VPP signal is not only used to manage the start or stop of the hard drive, but it is also bound to the data transmission channel of the NVMe hard drive. For example, the NVMe hard drive connected to PCIe port 1 will have a bound VPP signal line and a corresponding data transmission signal line, and these two signal lines will be merged together during transmission. Therefore, whenever there is a VPP signal from this port, the parsing module can also access the high-speed data transmission status of the corresponding hard drive through this signal line.

[0076] After receiving these signals, the parsing module needs to perform a matching operation. It compares each shunt signal with the high-speed data transmission signals of multiple NVMe hard drives to find the signal corresponding to a specific hard drive. In other words, the parsing module will identify which specific hard drive is communicating through the port based on the signal of each PCIe port. For example, the parsing module receives a VPP signal from PCIe port 1 and simultaneously detects the corresponding high-speed data transmission signal on the port. Through this matching, the parsing module can confirm that this VPP signal is for the first NVMe hard drive connected to PCIe port 1.

[0077] When the parsing module completes the matching of the shunt signal and the high-speed data transmission signal, the specific target hard disk is determined. Then, the parsing module sends the management instructions contained in the shunt signal to the target hard disk, and the hard disk performs corresponding management operations such as starting, stopping or data processing according to these instructions. For example, after the parsing module confirms through matching that the NVMe hard disk on PCIe port 1 is the target hard disk, it will send management instructions (such as starting the hard disk or starting data transmission) to the hard disk. After receiving the management instructions, the target hard disk performs the task as required.

[0078] Exemplarily, after sending the management instruction corresponding to the diversion signal to the target hard disk, the method also includes: obtaining, through the corresponding I2CSWITCH channel, management information returned by the parsing module, in which the target hard disk responds to the management instruction; integrating the management information according to different PCIe ports, and sending the integrated management information to the CPU; parsing the management information by the CPU, and performing corresponding management operations based on the management information.

[0079] After sending management instructions to the target hard disk, the target hard disk will perform corresponding operations according to the instructions and generate management information. The management information is returned to the parsing module through the corresponding I2CSWITCH channel. The parsing module is responsible for collecting and processing this information. Assume that the target hard disk is an NVMe hard disk connected through PCIe port 1, and the CPU sends a startup instruction to the hard disk. After the hard disk is started, it will return status information through the I2CSWITCH channel, such as "startup successful" or "startup failed", and the status information is first received by the parsing module. When the parsing module receives management information from different hard disks from multiple PCIe ports, it integrates the management information according to the different PCIe ports. The purpose of integration is to organize the information of each hard disk and return it to the CPU in a unified format. For example, the parsing module receives the following management information from multiple PCIe ports:

[0080] PCIe port 1 returns information, and the hard disk is started successfully;

[0081] PCIe port 2 returns information: hard disk reads data normally;

[0082] PCIe port 3 returns information: the hard disk is faulty. Based on these returned information, the parsing module will mark them as received from different PCIe ports, and integrate all the information into a data packet, which is also sent to the CPU as a VPP signal. After receiving the integrated management information, the CPU will parse the information and take corresponding management actions based on the feedback from each hard disk. Depending on the status of different hard disks, the CPU can make adjustments or issue new instructions.

[0083] In this example, after receiving the management information, the CPU parses it and finds that: the hard disk on PCIe port 1 is successfully started and no further operation is required; the hard disk on PCIe port 2 is operating normally, and the CPU can continue to assign data tasks to it; the hard disk on PCIe port 3 fails, and the CPU will issue a new instruction, which may be to stop the operation of the hard disk, or to perform diagnostic and recovery operations.

[0084] The present disclosure realizes efficient management of multiple NVMe hard disks by introducing the I2CSWITCH chip. By shunting the VPP signal from the CPU and transmitting it to each NVMe hard disk, different hard disk devices can be accurately identified and managed. At the same time, the parsing module quickly determines the target hard disk and sends corresponding management instructions by matching the shunted signal with the high-speed data transmission signal, which not only improves the management accuracy of the system, but also optimizes the status monitoring and response speed of the hard disk by integrating the management information of the hard disk and sending it to the CPU, effectively reducing management delays, and improving the scalability and user experience of the system. When the number of PCIe ports increases, efficient and reliable management operations of NVMe hard disks can still be ensured.

[0085] An embodiment of the present disclosure also provides an electronic device, including a processor, a memory, and a computer program stored in the memory and capable of running on the processor. When the computer program is executed by the processor, the various processes in the above-mentioned embodiment of a hard disk management method are implemented, and the same technical effect can be achieved. To avoid repetition, it will not be repeated here.

[0086] The disclosed embodiment also provides a computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, each process in the above-mentioned embodiment of a hard disk management method is implemented, and the same technical effect can be achieved. To avoid repetition, it is not repeated here. Each embodiment in this specification is described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same and similar parts between the embodiments can be referred to each other.

[0087] Those skilled in the art will appreciate that the embodiments of the present disclosure may be provided as methods, systems, electronic devices, and computer-readable media. Therefore, the embodiments of the present disclosure may take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Moreover, the embodiments of the present disclosure may take the form of a computer program product implemented on one or more computer-readable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0088] The embodiments of the present disclosure are described with reference to the flowcharts and / or block diagrams of the methods, terminal devices (systems), and computer program products according to the embodiments of the present disclosure. It should be understood that each process and / or box in the flowchart and / or block diagram, as well as the combination of the processes and / or boxes in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing terminal device to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing terminal device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 These computer program instructions can also be stored in a computer-readable memory that can guide a computer or other programmable data processing terminal device to work in a specific way, so that the instructions stored in the computer-readable memory produce a product including an instruction device, which implements the functions specified in the process. Figure 1 A process or multiple processes and / or boxes Figure 1 These computer program instructions can also be loaded into a computer or other programmable data processing terminal device, so that a series of operation steps are executed on the computer or other programmable terminal device to produce a computer-implemented process, so that the instructions executed on the computer or other programmable terminal device provide for implementing the process in the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0089] Although the preferred embodiments of the present disclosure have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the present disclosure.

[0090] Finally, it should be noted that, in this article, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the term "include" or any other variant thereof is intended to cover non-exclusive inclusion, so that a process, method, article or terminal device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or terminal device. In the absence of further restrictions, the elements defined by the sentence "include..." do not exclude the existence of other identical elements in the process, method, article or terminal device including the elements. The above is a detailed introduction to a hard disk management system, method, electronic device and storage medium provided by the present disclosure. The principle and implementation method of the present disclosure are explained in this article using specific examples. The description of the above embodiments is only used to help understand the method and its core idea of ​​the present disclosure; at the same time, for those of ordinary skill in the art, according to the idea of ​​the present disclosure, there will be changes in the specific implementation method and application scope. In summary, the content of this specification should not be understood as a limitation on the present disclosure.

Claims

1. A hard disk management system, characterized in that: The system comprises: The CPU deployed on the mainboard is used to send a VPP signal to the I2C SWITCH chip, wherein the VPP signal includes a management instruction, and the management instruction is used to instruct management of the NVME hard disk; At least one I2C SWITCH chip is deployed on the mainboard, the I2C SWITCH chip is used to receive the VPP signal output by the CPU, and distribute the VPP signal into a plurality of shunt signals according to different PCIe ports, the plurality of shunt signals are a plurality of independent signals output by the I2C SWITCH chip according to the input VPP signal, and the plurality of shunt signals are transmitted through the respective corresponding I2C SWITCH channels; A parsing module deployed on the NVME hard disk backplane, the parsing module is connected to the I2C SWITCH chip through the multiple I2C SWITCH channels, the parsing module is used to receive a shunt signal from the I2C SWITCH chip, and, according to the shunt signal, determine a target hard disk from the multiple NVME hard disks and send a corresponding management instruction to the target hard disk.

2. The system according to claim 1, characterized in that Among the plurality of shunt signals, the VPP address of each shunt signal is the same.

3. The system according to claim 2, characterized in that For the different PCIe ports, the VPP signal line of each PCIe port is merged with the corresponding high-speed data transmission signal line, and the VPP signal of each PCIe port is bound with the corresponding high-speed data transmission signal.

4. The system according to claim 1, characterized in that The system also includes an uplink device, which is connected to the analysis module by multiplexing the I2C SWITCH channel; the uplink device is used to send an I2C signal to the analysis module, and the I2C signal is used to instruct the management of the NVME hard disk.

5. The system according to claim 1, characterized in that The analysis module includes any one of the following: a complex programmable logic device CPLD, a microcontroller MCU and a PCA9555 expander.

6. A hard disk management method, characterized in that: Applied to the system according to any one of claims 1 to 5, the method comprises: Receiving a VPP signal from a CPU, wherein the VPP signal includes a management instruction, and the management instruction is used to instruct management of an NVME hard disk; The VPP signal is respectively distributed into a plurality of shunt signals according to different PCIe ports through an I2C SWITCH chip, and the plurality of shunt signals are transmitted to a parsing module through one-to-one corresponding I2C SWITCH channels, wherein the plurality of shunt signals are a plurality of independent signals output by the I2C SWITCH chip according to the input VPP signal; Through the analysis module, a target hard disk is determined from the multiple NVME hard disks according to the shunt signal, and a management instruction corresponding to the shunt signal is sent to the target hard disk.

7. The method according to claim 6, characterized in that The step of determining a target hard disk from the plurality of NVME hard disks according to the shunt signal by the analysis module, and sending a management instruction corresponding to the shunt signal to the target hard disk includes: Receiving each shunt signal through the analysis module, wherein the VPP address of each shunt signal is the same, for the different PCIe ports, the VPP signal line of each PCIe port is merged with the corresponding high-speed data transmission signal line, and the VPP signal of each PCIe port is bound to the corresponding high-speed data transmission signal; The shunt signal is matched with the high-speed data transmission signals of each of the multiple NVME hard disks, a target hard disk is determined, and a corresponding management instruction is sent to the target hard disk.

8. The method according to claim 6, characterized in that After sending the management instruction corresponding to the diversion signal to the target hard disk, the method further includes: Acquire, through a corresponding I2C SWITCH channel, management information returned by the parsing module, in which the target hard disk responds to the management instruction; Integrate the management information according to different PCIe ports, and send the integrated management information to the CPU; The management information is parsed by the CPU, and corresponding management operations are performed according to the management information.

9. An electronic device, characterized in that: include: A processor, a memory, and a computer program stored in the memory and capable of running on the processor, wherein the computer program implements the steps of the method according to any one of claims 6 to 8 when executed by the processor.

10. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the steps of the method according to any one of claims 6 to 8 are implemented.

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