Liquid crystal screen

Abstract

The invention discloses a liquid crystal screen. The liquid crystal screen comprises a liquid crystal display; and a driving circuit. The driving circuit comprises a medium-voltage logic circuit and two voltage level converters, compared with a traditional driving circuit, the area of a high-voltage transistor is saved, power is saved, the number of the voltage level converters is minimized, and therefore output signals of an output stage circuit can be controlled to be in one of four states.

Description

[0001] This application is a divisional application of the invention patent application with application number 2024108255695. The filing date of the original application is June 25, 2024. Technical Field

[0002] The present application belongs to the field of driving circuits, and relates to a driving circuit that includes fewer voltage level converters and can output a floating state or a high impedance state. Background Art

[0003] When driving a liquid crystal display screen or an electronic paper display, a driving circuit needs to generate a scanning signal or a data signal with a relatively large voltage range so as to turn on a thin film transistor coupled to the electronic paper display or the liquid crystal display screen and control the color of the pixel.

[0004] Please refer to Figure 1 , which is a block diagram of a conventional liquid crystal display screen 100. In order to control the liquid crystal display 110, the liquid crystal display screen 100 includes a gate control circuit 120 and an output stage circuit 122 of a corresponding gate drive circuit. The liquid crystal display screen 100 also includes a source control circuit 130 and an output stage circuit 132 of a corresponding source drive circuit. In order to generate a switch control signal corresponding to the liquid crystal display screen, the output stage circuits 122 and 132 operate between a high voltage positive voltage VPOS and a high voltage negative voltage VNEG. The output stage circuits 122 and 132 include P-type transistors (hereinafter referred to as PMOS), N-type transistors (hereinafter referred to as NMOS) and / or complementary transistors (hereinafter referred to as CMOS).

[0005] The high-voltage components of the output stage circuits 122 and 132 occupy a large chip area and consume a large transition current when working. Furthermore, since the medium voltage output by the gate control circuit 120 and the source control circuit 130 or the working voltage of the logic circuit needs to be converted to a high voltage, more voltage level converters (LVSH or LS) are required. When multiple LVSHs are switched at the same time, the instantaneous current required is too large, exceeding the load, and there is a risk of voltage conversion failure.

[0006] Please refer to Figure 2 As shown, it is a timing diagram of various possible states of the output port of the output stage circuit 122 or 132. Figure 2 The upper part of contains the timing 210 of three possible states, Figure 2The lower half of the timing sequence 220 includes four possible states. In the timing sequence 210, when switching from the voltage VPOS to the ground potential GND or from the ground potential GND to a lower voltage VNEG, a short circuit may occur. In order to avoid instantaneous leakage current (leakage) caused by a short circuit, the potential of the output end can be set to a floating or high impedance (floating or HiZ) state before switching to avoid short circuit and leakage current. The aforementioned high impedance state is from the perspective of the output port. Those skilled in the art can understand that the floating or high impedance state is described from different perspectives and is essentially the same meaning.

[0007] In summary, there is an urgent need for a driving circuit that can use fewer high-voltage components, especially when reducing the use of voltage level converters and high-voltage components and switching to medium-voltage components, saving chip area and operating power consumption, and being able to first turn into a floating state when the output high voltage is switched to reduce leakage current and improve the reliability and life of the integrated circuit. Summary of the invention

[0008] The present application is a driving circuit proposed to solve the deficiencies in the prior art, and aims to save high voltage transistor area and power compared to conventional circuits. Furthermore, the present application can minimize the number of voltage level converters to control the output signal of the output stage circuit.

[0009] In order to achieve the above purpose, this application adopts the following technical solutions:

[0010] According to an embodiment of the present application, a driving circuit is provided, characterized in that it includes: an output port, which is in one of the following four states: a voltage VPOS, a ground voltage GND, a voltage VNEG and a floating state, wherein the voltage VPOS is greater than the ground voltage GND, and the ground voltage GND is greater than the voltage VNEG; an output switch circuit, which includes a first switch circuit, a second switch circuit and a third switch circuit, wherein the outputs of the first switch circuit, the second switch circuit and the third switch circuit are all coupled to the output port; a first voltage level converter for connecting the first switch circuit circuit; a second voltage level converter, used to connect the second switch circuit; a medium voltage logic circuit, receiving the first signal from the first voltage level converter, receiving the second signal from the second voltage level converter, and a group of HZ signals, used to connect the third switch circuit; and a control logic circuit, used to control the first switch circuit to be turned off, the second voltage level converter to control the second switch circuit to be turned off, and the medium voltage logic circuit to turn off the third switch circuit when the third group of input signals and the group of HZ signals are received in the second HZ state, so that the output port is in the floating state.

[0011] Preferably, in order to allow the output port to output a high-voltage driving signal, such as voltage VPOS, when the above-mentioned control logic circuit receives a first set of input signals and the set of HZ signals is in a first HZ state, the first voltage level converter controls the first switch circuit to be cut off, the second voltage level converter controls the second switch circuit to be turned on, and the medium voltage logic circuit turns off the third switch circuit, so that the output port is at the voltage VPOS, wherein the first HZ state and the second HZ state are inverted to each other.

[0012] Preferably, in order to allow the output port to output a driving signal at the ground potential, when the above-mentioned control logic circuit receives a second set of input signals and the set of HZ signals is in the first HZ state, the first voltage level converter controls the first switch circuit to be turned on, the second voltage level converter controls the second switch circuit to be turned off, and the medium voltage logic circuit turns off the third switch circuit, so that the output port is at the ground voltage GND, wherein the first HZ state and the second HZ state are inverted to each other.

[0013] Preferably, in order to allow the output port to output a high-voltage driving signal, such as voltage VNEG, when the above-mentioned control logic circuit receives a third group of input signals and the group of HZ signals is in the first HZ state, the first voltage level converter controls the first switch circuit to be cut off, the second voltage level converter controls the second switch circuit to be cut off, and the medium voltage logic circuit turns on the third switch circuit, so that the output port is at the voltage VNEG, wherein the first HZ state and the second HZ state are inverted to each other.

[0014] Preferably, in order to put the output port in a floating state, when the above-mentioned control logic circuit receives the fourth group of input signals and the group of HZ signals is in the second HZ state, the first voltage level converter controls the first switch circuit to be cut off, the second voltage level converter controls the second switch circuit to be cut off, and the medium voltage logic circuit cuts off the third switch circuit, so that the output port is in the floating state.

[0015] Preferably, in order to put the output port in a floating state, the HZ signal in the second HZ state is a voltage VCC, wherein the voltage VPOS is greater than the voltage VCC, and the voltage VCC is greater than the ground voltage GND.

[0016] Preferably, in order to prevent the output port from being in a floating state, the HZ signal in the first HZ state is a voltage of GND.

[0017] Preferably, in order to prevent the output port from being in a floating state, the driving circuit further comprises a third voltage level converter to provide the HZ signal of the first HZ state as a voltage VNEG.

[0018] Preferably, in order to reduce the chip area and operating power of the voltage level converter, the first voltage level converter includes two medium voltage transistors for correspondingly outputting the first signal to the medium voltage logic circuit.

[0019] Preferably, in order to reduce the chip area and operating power of the voltage level converter, the second voltage level converter includes two medium voltage transistors for correspondingly outputting the second signal to the medium voltage logic circuit.

[0020] Preferably, in order to reduce the chip area and operating power of the medium voltage logic circuit, the above-mentioned medium voltage logic circuit includes: two medium voltage transistors, used to respectively receive the above-mentioned group of HZ signals; two transistors, used to respectively receive the above-mentioned first signal and the above-mentioned second signal, wherein the voltage of the above-mentioned first signal is the voltage VCC or the voltage VNEG, and the voltage of the above-mentioned second signal is the voltage VCC or the voltage VNEG, wherein the voltage VPOS is greater than the voltage VCC, and the voltage VCC is greater than the ground voltage GND; and two high-voltage transistors, used to receive the voltage VNEG.

[0021] Preferably, in order to require fewer logic bits to control the driving circuit and reduce the operating power of the control logic circuit, the third set of input signals includes two logic bits, and the maximum operating voltage of the control logic circuit is lower than the voltage VPOS.

[0022] According to an embodiment of the present application, a liquid crystal screen is provided, characterized by comprising: a liquid crystal display; and a driving circuit as described above, used for controlling the output port to display pixels of the liquid crystal display.

[0023] According to an embodiment of the present application, an electronic paper is provided, comprising: an electronic paper display; and the aforementioned driving circuit, which is used to control the display of pixels of the electronic paper display through the output port.

[0024] Due to the adoption of the above-mentioned scheme, the beneficial effects of the present application are as follows: the present application provides a driving circuit that can use fewer high-voltage components, especially when reducing the use of voltage level converters and high-voltage components and switching to medium-voltage components, saving chip area and working power consumption, and can also be converted to a floating state when the output high voltage is switched, so as to reduce leakage current and improve the reliability and life of the integrated circuit.

[0025] Furthermore, the driving circuit provided in the present application reduces the number of voltage level converters through the use of a medium-voltage logic circuit and can also provide four output states; compared with the logic circuit operating at a high voltage VPOS and the traditional voltage level converter, the medium-voltage logic circuit operating at a lower voltage and the voltage level converter provided in the present application can save more operating power. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 It is a block diagram of a conventional liquid crystal display screen 100 .

[0027] Figure 2 FIG. 1 is a timing diagram of various possible states of the output port of the output stage circuit 122 or 132 .

[0028] Figure 3 FIG. 4 is a timing diagram of the operating voltage of the driving circuit according to an embodiment of the present application.

[0029] Figure 4 FIG. 4 is a block diagram of a driving circuit 400 according to an embodiment of the present application.

[0030] Figure 5 FIG. 4 is a block diagram of an output switch circuit 440 according to an embodiment of the present application.

[0031] Fig. 6A is a schematic diagram of a switch circuit 510 according to an embodiment of the present application.

[0032] Figure 6B FIG. 5 is a schematic diagram of a switch circuit 510 according to another embodiment of the present application.

[0033] Figure 6C FIG. 5 is a schematic diagram of a switch circuit 510 according to another embodiment of the present application.

[0034] Fig. 7A FIG. 4 is a block diagram of an output switch circuit 440 according to an embodiment of the present application.

[0035] Figure 7B FIG. 4 is a block diagram of an output switch circuit 440 according to another embodiment of the present application.

[0036] Figure 7C FIG. 4 is a block diagram of an output switch circuit 440 according to another embodiment of the present application.

[0037] Figure 8 , which is a block diagram of a level conversion logic circuit 430 according to an embodiment of the present application.

[0038] Fig. 9AFIG. 8 is a circuit diagram of a voltage level converter 810 according to an embodiment of the present application.

[0039] Fig. 9B FIG. 8 is a circuit diagram of a voltage level converter 810 according to another embodiment of the present application.

[0040] Fig. 10A FIG. 8 is a circuit diagram of a medium voltage logic circuit 820 according to an embodiment of the present application.

[0041] Fig. 10B FIG. 8 is a circuit diagram of a medium voltage logic circuit 820 according to another embodiment of the present application.

[0042] Fig. 10C FIG. 8 is a circuit diagram of a medium voltage logic circuit 820 according to another embodiment of the present application.

[0043] Fig.11 FIG. 4 is a schematic diagram of the medium voltage logic circuit 820 and the output switch circuit 440 outputting the potential VPOS according to an embodiment of the present application.

[0044] Fig.12 FIG. 4 is a schematic diagram of a medium voltage logic circuit 820 and an output switch circuit 440 outputting a ground potential GND according to an embodiment of the present application.

[0045] Fig.13 FIG. 4 is a schematic diagram of the medium voltage logic circuit 820 and the output switch circuit 440 outputting a potential VNEG according to an embodiment of the present application.

[0046] Fig.14 FIG. 4 is a schematic diagram of a medium voltage logic circuit 820 and an output switch circuit 440 according to an embodiment of the present application when the output port 450 is in a floating potential. DETAILED DESCRIPTION

[0047] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other implementation methods obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0048] The terms "first", "second", "third", etc. (if any) in the specification and claims of this application and the drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the objects described in these descriptions can be interchanged where appropriate. In the description of this application, "plurality" means two or more, unless otherwise clearly and specifically defined. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions. Some of the block diagrams shown in the drawings are functional entities and do not necessarily correspond to physically or logically independent entities. These functional entities can be implemented in software form, or in one or more hardware circuits or integrated circuits, or in different networks and / or processor devices and / or microcontroller devices.

[0049] In the description of the present application, it should be understood that the terms "center", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc., indicating directions or positional relationships, are based on the directions or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the device or component referred to must have a specific direction, be constructed and operated in a specific direction, and therefore should not be understood as a limitation on the present application.

[0050] In the description of this application, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, an electrical connection, or mutual communication; it can be a direct connection, or an indirect connection through an intermediate medium, it can be the internal connection of two components or the interaction relationship between two components. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0051] In order to make the purpose, features and advantages of the present application more obvious and easy to understand, the present application is further described in detail below in conjunction with drawings and specific implementation methods.

[0052] Please refer to Figure 3 As shown, it is a timing diagram of the working voltage of the driving circuit according to an embodiment of the present application. Figure 3It can be seen that the high voltage VPOS is greater than the voltage VCC, the voltage VCC is greater than the ground potential GND, and the ground potential GND is greater than the high voltage VNEG. Those of ordinary skill in the art can understand that if the components of the drive circuit can operate between the voltages VCC and GND, it is more power-saving and area-saving than the components operating between VPOS and GND. Similarly, if the components of the drive circuit can operate between the voltages VCC and VNEG, it is more power-saving and area-saving than the components operating between VPOS and VNEG. The logic circuit usually operates between the voltages VDD and GND. The voltage VDD is usually lower than the voltage VCC. In some embodiments, the logic circuit can also operate between the voltages VCC and GND. The above-mentioned voltages VCC and VDD can be called medium voltages.

[0053] To adjust the output signal of the control circuit, that is, the output voltage of the logic circuit, from a lower voltage VDD or VCC to a higher voltage VPOS or VNEG, LVSH is usually required. This process can also be called digital-to-analog conversion (DAC, Digital-to-Analog Conversion).

[0054] Please refer to Figure 4 , which is a block diagram of a driving circuit 400 according to an embodiment of the present application. The driving circuit 400 may be suitable for driving the drain or source of a liquid crystal display or an electronic paper display. The driving circuit 400 may include a control logic circuit 410, a digital-to-analog converter 420, and an output port 450. The control logic circuit 410 is used to output a control signal to the digital-to-analog converter 420. The control logic circuit 410 may operate between a voltage VDD and GND, or between a voltage VCC and GND.

[0055] Those skilled in the art can understand that the control logic circuit 410 can include any combination of the above-mentioned transistors and logic gates or any combination of equivalent circuits to achieve the purpose of controlling the digital-to-analog converter 420 .

[0056] The digital-to-analog converter 420 includes a level conversion logic circuit 430 and an output switch circuit 440. In other words, the control logic circuit 410 can be used to control the level conversion logic circuit 430 and the output switch circuit 440. In order to pull the voltage of the output port 450 from VDD or VCC to VPOS or VNEG, the level conversion logic circuit 430 can include two LVSH and medium voltage logic circuits. Figure 8 The level conversion logic circuit 430 will be further explained.

[0057] Please refer to Figure 5, which is a block diagram of an output switch circuit 440 according to an embodiment of the present application. The above-mentioned output switch circuit 440 is also called an output stage circuit. In order to make the output signal of the output port 450 be one of the aforementioned four states, the output switch circuit 440 can include three switch circuits, namely a first switch circuit 510A, a second switch circuit 510B, and a third switch circuit 510C. The designs of these three switch circuits can be the same as each other, or different from each other. The outputs of these three switches are coupled to the aforementioned output port 450. The input signals of the first switch circuit 510A, the second switch circuit 510B, and the third switch circuit 510C come from the aforementioned level conversion logic circuit 430, and are respectively called interface A, interface B, and interface C.

[0058] Depending on the design of each switch circuit, interface A, interface B or interface C may vary. Interface A, interface B or interface C may include one or more signals. The one or more signals may be Figure 3 One of the voltages shown is VPOS, VNEG, VCC, VDD or GND.

[0059] Please refer to Fig. 6A , which is a schematic diagram of a switch circuit 510 according to an embodiment of the present application. The switch circuit 510 includes a P-type transistor and an N-type transistor whose drains are connected to form an output port, which operates between voltages VPOS and VNEG and is a high-voltage component. The output port of the switch circuit is coupled to the aforementioned output port 450.

[0060] Please refer to Figure 6B , which is a schematic diagram of a switch circuit 510 according to another embodiment of the present application. The switch circuit 510 includes a P-type transistor, which is a high-voltage component. The drain of the switch circuit 510 is coupled to the aforementioned output port 450, and the source is connected to the voltage VPOS. .

[0061] Please refer to Figure 6C , which is a schematic diagram of a switch circuit 510 according to another embodiment of the present application. The switch circuit 510 includes an N-type transistor, which is a high-voltage component. The drain of the switch circuit 510 is coupled to the aforementioned output port 450, and the source is connected to the voltage VNEG.

[0062] Those skilled in the art can understand that FIG. 6A to FIG. 6C Any of the switch circuits 510 shown can be applied to Figure 5 One of the first switch circuit 510A, the second switch circuit 510B, and the third switch circuit 510C shown.

[0063] Please refer to Fig. 7A, which is a block diagram of an output switch circuit 440 according to an embodiment of the present application. FIG. 6A to FIG. 6C There are three embodiments of the switch circuit 510, Fig. 7A The first switching circuit 510A shown uses Fig. 6A The switch circuit 510 shown in FIG. 5 is a second switch circuit 510B. Figure 6B The switch circuit 510 shown in FIG. 5 is a third switch circuit 510C. Figure 6C The switching circuit 510 is shown.

[0064] Please refer to Figure 7B , which is a block diagram of an output switch circuit 440 according to another embodiment of the present application. Fig. 6A and Figure 6C There are two embodiments of the switch circuit 510, Figure 7B The first switching circuit 510A shown uses Fig. 6A The switch circuit 510 shown in FIG. 5 is a second switch circuit 510B. Fig. 6A The switch circuit 510 shown in FIG. 5 is a third switch circuit 510C. Figure 6C The switching circuit 510 is shown.

[0065] Please refer to Figure 7C , which is a block diagram of an output switch circuit 440 according to another embodiment of the present application. Fig. 6A An embodiment of the switching circuit 510, Figure 7C The first switch circuit 510A, the second switch circuit 510B and the third switch circuit 510C shown all use Fig. 6A The switching circuit 510 is shown.

[0066] By 7A to 7C The applicant believes that those skilled in the art can freely use any combination of various switch circuits 510 to implement the output switch circuit 440 described above.

[0067] Please refer to Figure 8As shown, it is a block diagram of a level conversion logic circuit 430 according to an embodiment of the present application. The level conversion logic circuit 430 includes a first voltage level converter 810A, a second voltage level converter 810B and a medium voltage logic circuit 820. The level conversion logic circuit 430 receives control from the control logic circuit 410 and is used to control the first signal XXI1_A output by the first voltage level converter 810A. Similarly, the level conversion logic circuit 430 receives control from the control logic circuit 410 and is used to control the second signal XXI1_B output by the second voltage level converter 810B. In one embodiment, the first signal XXI1_A and the second signal XXI1_B can each be a logic bit. The first state of the logic bit is the voltage VCC, and the second state of the logic bit is the voltage VNEG.

[0068] The first voltage level converter 810A is connected to the first switch circuit 510A of the output switch circuit 440 via the interface A. Similarly, the second voltage level converter 810B is connected to the second switch circuit 510B of the output switch circuit 440 via the interface B.

[0069] The medium voltage logic circuit 820 obtains a floating signal HZ or a pair of signals, namely the floating signal HZ and its inverted floating signal XHZ, from the control logic circuit 410, and obtains the first signal XXI1_A from the first voltage level converter 810A and the second signal XXI1_B from the second voltage level converter 810B. The medium voltage logic circuit 820 is connected to the third switch circuit 510C of the output switch circuit 440 through the interface C.

[0070] Please refer to Fig. 9A As shown, it is a circuit diagram of a voltage level converter 810 according to an embodiment of the present application. The voltage level converter 810 can be divided into a left and a right side. The left circuit includes two medium voltage P-type transistors MVP1 and MVP2. Unlike the other transistors of the voltage level converter 810, the drains of these two medium voltage P-type transistors MVP1 and MVP2 are connected to the medium voltage VCC, and their sources are respectively connected to four high voltage N-type transistors HVN1 to HVN4. The right circuit includes two high voltage P-type transistors HVP1 and HVP2 and two high voltage N-type transistors HVN5 and HVN6. The right circuit operates between the high voltage VPOS and VNEG.

[0071] exist Fig. 9A In the embodiment, the source of the medium voltage P-type transistor MVP2 is coupled to the drain of the high voltage N-type transistor HVN2 and the gates of the high voltage N-type transistors HVN2, HVN3 and HVN6, which is the signal XXI1.

[0072] Please refer to Fig. 9B , which is a circuit diagram of a voltage level converter 810 according to another embodiment of the present application. Fig. 9B The voltage level converter 810 shown only includes Fig. 9A The left circuit of the voltage level converter 810 shown in the figure omits the four high-voltage transistors HVP1 , HVP2 , HVN5 and HVN6 of the right circuit.

[0073] Similarly, in Fig. 9B In the embodiment of the present invention, the source of the medium voltage P-type transistor MVP2 is coupled to the drain of the high voltage N-type transistor HVN2 and the gates of the high voltage N-type transistors HVN2 and HVN3, which is the signal XXI1.

[0074] It can be understood by those skilled in the art that Fig. 9A or Fig. 9B The voltage level converter 810 shown can be applied to Figure 8 When it is applied to the first voltage level converter 810A, the aforementioned signal XXI1 is Figure 8 When it is applied to the second voltage level converter 810B, the aforementioned signal XXI1 is Figure 8 The second signal XXI1_B is shown.

[0075] Please refer to Fig. 10A As shown, it is a circuit diagram of a medium voltage logic circuit 820 according to an embodiment of the present application. The right side of the medium voltage logic circuit 820 is an interface C. The medium voltage logic circuit 820 includes two medium voltage P-type transistors MVP11 and MVP12. The right side of the medium voltage logic circuit 820 also includes two P-type transistors and two high voltage N-type transistors. The sources of the two high voltage N-type transistors are respectively connected to the voltage VNEG. The gates of the medium voltage P-type transistors MVP11 and MVP12 are respectively connected to the signal XHZ and its inverted signal HZ, which can come from Figure 4 The control logic circuit 410 is shown.

[0076] The above-mentioned signal XHZ and its inverted signal HZ are used to control the output switch circuit 440 to be in a floating state. In one embodiment, when the signal XHZ is at the potential GND, the inverted signal HZ is at the potential VCC. On the contrary, when the signal XHZ is at the potential VCC, the inverted signal HZ is at the potential GND. In another embodiment, when the signal XHZ is at the potential VNEG, the inverted signal HZ is at the potential VCC. On the contrary, when the signal XHZ is at the potential VCC, the inverted signal HZ is at the potential VNEG. In this embodiment, an additional voltage level converter needs to be connected to convert the ground potential GND into the high voltage potential VNEG.

[0077] Please refer to Fig. 10B , which is a circuit diagram of a medium voltage logic circuit 820 according to another embodiment of the present application. The right side of the medium voltage logic circuit 820 is an interface C. The medium voltage logic circuit 820 includes two medium voltage P-type transistors MVP17 and MVP18. The left side of the medium voltage logic circuit 820 also includes two P-type transistors and two high voltage N-type transistors. The gates of the medium voltage P-type transistors MVP17 and MVP18 are respectively connected to the signal XHZ and its inverted signal HZ, which comes from Figure 4 The control logic circuit 410 is shown.

[0078] Please refer to Fig. 10C , which is a circuit diagram of a medium voltage logic circuit 820 according to another embodiment of the present application. The right side of the medium voltage logic circuit 820 is an interface C. The medium voltage logic circuit 820 includes two medium voltage P-type transistors MVP21 and MVP22. The medium voltage logic circuit 820 includes two P-type transistors and two high voltage N-type transistors. The gates of the medium voltage P-type transistors MVP21 and MVP22 are respectively connected to the signal XHZ and its inverted signal HZ, which comes from Figure 4 The control logic circuit 410 is shown.

[0079] The medium voltage logic circuit 820 is connected to the third switch circuit 510C of the aforementioned output switch circuit through the interface C. FIG. 10A to FIG. 10C It can be seen from the embodiment that since the medium voltage logic circuit 820 is not connected to the high voltage potential VPOS, the potential of its output can be VCC, GND or VNEG.

[0080] Next, Fig. 10A The medium voltage logic circuit 820 and Figure 7C The output switch circuit 440 is shown as an embodiment, and the working states of the medium voltage logic circuit 820 and the output switch circuit 440 are explained with respect to the output port 450 being at voltages VPOS, GND, VNEG and a floating state HiZ, respectively.

[0081] Please refer to Fig.11, which is a schematic diagram of the medium voltage logic circuit 820 and the output switch circuit 440 outputting the potential VPOS according to an embodiment of the present application. In this embodiment, when the control logic circuit 410 connects the gate of the P-type transistor of the first switch circuit 510A to the voltage VPOS provided by the interface A, and connects the gate of the N-type transistor of the first switch circuit 510A to the voltage VNEG provided by the interface A, the first switch circuit 510A will be turned off.

[0082] When the control logic circuit 410 connects the gate of the P-type transistor of the second switch circuit 510B to the voltage VNEG provided by the interface B and connects the gate of the N-type transistor of the second switch circuit 510B to the voltage VPOS provided by the interface B, the second switch circuit 510B is turned on.

[0083] When the signal HZ is at the potential GND and its inverted signal XHZ is at the potential VCC, the medium voltage P-type transistor MVP11 is turned off and the other medium voltage P-type transistor MVP12 is turned on. Since the first signal XXI1_A output by the first voltage level converter 810A is at the voltage VNEG and the second signal XXI1_B output by the second voltage level converter 810B is at the voltage VCC, the N-type transistor on the right is turned on, so that the output signal of the interface C is the voltage VNEG, and the third switch circuit 510C is turned off.

[0084] Since among the three switch circuits of the output switch circuit 440 , the second switch circuit 510B is turned on, and the remaining two switch circuits 510A and 510C are turned off, the output port 450 is at the potential VPOS.

[0085] Please refer to Fig.12 , which is a schematic diagram of the medium voltage logic circuit 820 and the output switch circuit 440 outputting the ground potential GND according to an embodiment of the present application. In this embodiment, when the control logic circuit 410 connects the gate of the P-type transistor of the first switch circuit 510A to the voltage VNEG provided by the interface A, and connects the gate of the N-type transistor of the first switch circuit 510A to the voltage VPOS provided by the interface A, the first switch circuit 510A is turned on.

[0086] When the control logic circuit 410 connects the gate of the P-type transistor of the second switch circuit 510B to the voltage VPOS provided by the interface B and connects the gate of the N-type transistor of the second switch circuit 510B to the voltage VNEG provided by the interface B, the second switch circuit 510B will be turned off.

[0087] When the signal HZ is at the potential GND and its inverted signal XHZ is at the potential VCC, the medium voltage P-type transistor MVP11 is turned off and the other medium voltage P-type transistor MVP12 is turned on. Since the first signal XXI1_A output by the first voltage level converter 810A is at the potential VCC and the second signal XXI1_B output by the second voltage level converter 810B is at the voltage VNEG, the N-type transistor on the left is turned on, so that the signal of the interface C is at the voltage VNEG, and the third switch circuit 510C is turned off.

[0088] Since among the three switch circuits of the output switch circuit 440 , the first switch circuit 510A is turned on, and the other two switch circuits 510B and 510C are turned off, the output port 450 is at the voltage GND.

[0089] Please refer to Fig.13 , which is a schematic diagram of the medium voltage logic circuit 820 and the output switch circuit 440 outputting the potential VNEG according to an embodiment of the present application. In this embodiment, when the control logic circuit 410 connects the gate of the P-type transistor of the first switch circuit 510A to the voltage VPOS, and connects the gate of the N-type transistor of the first switch circuit 510A to the voltage VNEG, the first switch circuit 510A is turned off.

[0090] When the control logic circuit 410 connects the gate of the P-type transistor of the second switch circuit 510B to the voltage VPOS and connects the gate of the N-type transistor of the second switch circuit 510B to the voltage VNEG, the second switch circuit 510B will be turned off.

[0091] When the signal HZ is at the potential GND and its inverted signal XHZ is at the potential VCC, the medium voltage P-type transistor MVP11 is turned off and the other medium voltage P-type transistor MVP12 is turned on. Since the first signal XXI1_A output by the first voltage level converter 810A is at the potential VNEG, the second signal XXI1_B output by the second voltage level converter 810B is also at the potential VNEG, the P-type transistors MVP13 and MVP14 are turned on respectively, and the N-type transistors on the left and right sides are turned off. Accordingly, the potential of the signal C is VCC, and the third switch circuit 510C is turned on.

[0092] Since the third switch circuit 510C among the three switch circuits of the output switch circuit 440 is turned on and the remaining two switch circuits 510A and 510B are turned off, the output port 450 is at the potential VNEG.

[0093] Please refer to Fig.14, which is a schematic diagram of the medium voltage logic circuit 820 and the output switch circuit 440 according to an embodiment of the present application when the output port 450 is in a floating potential. In this embodiment, when the control logic circuit 410 connects the gate of the P-type transistor of the first switch circuit 510A to the voltage VPOS, and connects the gate of the N-type transistor of the first switch circuit 510A to the voltage VNEG, the first switch circuit 510A is turned off.

[0094] When the control logic circuit 410 connects the gate of the P-type transistor of the second switch circuit 510B to the voltage VPOS and connects the gate of the N-type transistor of the second switch circuit 510B to the voltage VNEG, the second switch circuit 510B will be turned off.

[0095] In order to turn off the medium voltage P-type transistor MVP12, the signal HZ is set to the VCC potential. Its inverted signal XHZ is set to the GND potential or the VNEG potential, so that the medium voltage P-type transistor MVP11 is turned on. Since the first signal XXI1_A output by the first voltage level converter 810A is at the potential VNEG, the second signal XXI1_B output by the second voltage level converter 810B is also at the potential VNEG, and accordingly, the signal C is at the potential VNEG, resulting in the third switch circuit 510C also not being turned on.

[0096] Since the three switch circuits 510A, 510B, and 510C of the output switch circuit 440 are not turned on, the potential of the output port 450 is floating.

[0097] Back to Figure 4 To control the output port 450 of the driving circuit 400 to output one of the above four voltages, the control logic circuit 410 only needs a set of N-bit input signals and HZ signals, where N can be 2. The level conversion logic circuit 430 includes N voltage level converters 810. The output voltage types of the output port 450 are 2 to the power of N, that is, 2 to the power of 2, 4 voltage outputs. According to the above embodiments, the following output signal and output signal table of the driving circuit 400 can be obtained.

[0098]

[0099]

[0100] As mentioned above, the present application provides a voltage level converter 810 with medium voltage components, which occupies a smaller chip area and has lower power consumption when operating than a conventional voltage level converter without medium voltage components. The first signal XXI1_A and the second signal XXI1_B outputted by the voltage level converter 810 can be used to assist the medium voltage logic circuit to control the output switch circuit 440, so that the latter can output a floating state, thereby reducing the instantaneous current or leakage current during voltage switching.

[0101] If three voltage level converters are used to control the three switch circuits 510 respectively, the additional voltage level converter will occupy a larger chip area. In addition to the transition current, the three voltage level converters converting voltage together will cause overall current instability.

[0102] The present application provides a driving circuit that can use fewer high-voltage components, especially when reducing the use of voltage level converters and high-voltage components and switching to medium-voltage components, saving chip area and operating power consumption, and can also be converted to a floating state when the output high voltage is switched to reduce leakage current, thereby improving the reliability and life of the integrated circuit.

[0103] According to an embodiment of the present application, a driving circuit is provided, characterized in that it includes: an output port, which is in one of the following four states: a voltage VPOS, a ground voltage GND, a voltage VNEG and a floating state, wherein the voltage VPOS is greater than the ground voltage GND, and the ground voltage GND is greater than the voltage VNEG; an output switch circuit, which includes a first switch circuit, a second switch circuit and a third switch circuit, wherein the outputs of the first switch circuit, the second switch circuit and the third switch circuit are all coupled to the output port; a first voltage level converter for connecting the first switch circuit circuit; a second voltage level converter, used to connect the second switch circuit; a medium voltage logic circuit, receiving the first signal from the first voltage level converter, receiving the second signal from the second voltage level converter, and a group of HZ signals, used to connect the third switch circuit; and a control logic circuit, used to control the first switch circuit to be turned off, the second voltage level converter to control the second switch circuit to be turned off, and the medium voltage logic circuit to turn off the third switch circuit when the third group of input signals and the group of HZ signals are received in the second HZ state, so that the output port is in the floating state.

[0104] Preferably, in order to allow the output port to output a high-voltage driving signal, such as voltage VPOS, when the above-mentioned control logic circuit receives a first set of input signals and the set of HZ signals is in a first HZ state, the first voltage level converter controls the first switch circuit to be cut off, the second voltage level converter controls the second switch circuit to be turned on, and the medium voltage logic circuit turns off the third switch circuit, so that the output port is at the voltage VPOS, wherein the first HZ state and the second HZ state are inverted to each other.

[0105] Preferably, in order to allow the output port to output a driving signal at the ground potential, when the above-mentioned control logic circuit receives a second set of input signals and the set of HZ signals is in the first HZ state, the first voltage level converter controls the first switch circuit to be turned on, the second voltage level converter controls the second switch circuit to be turned off, and the medium voltage logic circuit turns off the third switch circuit, so that the output port is at the ground voltage GND, wherein the first HZ state and the second HZ state are inverted to each other.

[0106] Preferably, in order to allow the output port to output a high-voltage driving signal, such as voltage VNEG, when the above-mentioned control logic circuit receives a third group of input signals and the group of HZ signals is in the first HZ state, the first voltage level converter controls the first switch circuit to be cut off, the second voltage level converter controls the second switch circuit to be cut off, and the medium voltage logic circuit turns on the third switch circuit, so that the output port is at the voltage VNEG, wherein the first HZ state and the second HZ state are inverted to each other.

[0107] Preferably, in order to put the output port in a floating state, when the above-mentioned control logic circuit receives the fourth group of input signals and the group of HZ signals is in the second HZ state, the first voltage level converter controls the first switch circuit to be cut off, the second voltage level converter controls the second switch circuit to be cut off, and the medium voltage logic circuit cuts off the third switch circuit, so that the output port is in the floating state.

[0108] Preferably, in order to put the output port in a floating state, the HZ signal in the second HZ state is a voltage VCC, wherein the voltage VPOS is greater than the voltage VCC, and the voltage VCC is greater than the ground voltage GND.

[0109] Preferably, in order to prevent the output port from being in a floating state, the HZ signal in the first HZ state is a voltage of GND.

[0110] Preferably, in order to prevent the output port from being in a floating state, the driving circuit further comprises a third voltage level converter to provide the HZ signal of the first HZ state as a voltage VNEG.

[0111] Preferably, in order to reduce the chip area and operating power of the voltage level converter, the first voltage level converter includes two medium voltage transistors for correspondingly outputting the first signal to the medium voltage logic circuit.

[0112] Preferably, in order to reduce the chip area and operating power of the voltage level converter, the second voltage level converter includes two medium voltage transistors for correspondingly outputting the second signal to the medium voltage logic circuit.

[0113] Preferably, in order to reduce the chip area and operating power of the medium voltage logic circuit, the above-mentioned medium voltage logic circuit includes: two medium voltage transistors, used to respectively receive the above-mentioned group of HZ signals; two transistors, used to respectively receive the above-mentioned first signal and the above-mentioned second signal, wherein the voltage of the above-mentioned first signal is the voltage VCC or the voltage VNEG, and the voltage of the above-mentioned second signal is the voltage VCC or the voltage VNEG, wherein the voltage VPOS is greater than the voltage VCC, and the voltage VCC is greater than the ground voltage GND; and two high-voltage transistors, used to receive the voltage VNEG.

[0114] Preferably, in order to require fewer logic bits to control the driving circuit and reduce the operating power of the control logic circuit, the third set of input signals includes two logic bits, and the maximum operating voltage of the control logic circuit is lower than the voltage VPOS.

[0115] According to an embodiment of the present application, a liquid crystal screen is provided, characterized by comprising: a liquid crystal display; and a driving circuit as described above, used for controlling the output port to display pixels of the liquid crystal display.

[0116] According to an embodiment of the present application, an electronic paper is provided, comprising: an electronic paper display; and the aforementioned driving circuit, which is used to control the display of pixels of the electronic paper display through the output port.

[0117] The above is only a preferred specific implementation manner of the present application, but the protection scope of the present application is not limited thereto. Any technician familiar with the technical field can make equivalent substitutions or changes within the technical scope disclosed in the present application according to the technical solution and application concept of the present application, which should be covered by the protection scope of the present application.

Claims

1. A liquid crystal screen, characterized in that: Include: Liquid crystal display; and The drive circuit includes: An output port, which is in one of the following four states: a voltage VPOS, a ground voltage GND, a voltage VNEG and a floating state, wherein the voltage VPOS is greater than the ground voltage GND, and the ground voltage GND is greater than the voltage VNEG; An output switch circuit, comprising a first switch circuit, a second switch circuit and a third switch circuit, wherein outputs of the first switch circuit, the second switch circuit and the third switch circuit are all coupled to the output port to control the display of pixels of the liquid crystal display; A first voltage level converter, used for connecting to the first switch circuit; A second voltage level converter, used for connecting to the second switch circuit; A medium voltage logic circuit receives a first signal from the first voltage level converter, a second signal from the second voltage level converter, and a set of HZ signals for connecting to the third switch circuit; as well as The control logic circuit is used to control the first switch circuit to be cut off by the first voltage level converter, control the second switch circuit to be cut off by the second voltage level converter, and control the third switch circuit to be cut off by the medium voltage logic circuit when a third group of input signals is received and the group of HZ signals is in the second HZ state, so that the output port is in the floating state, and the HZ signal of the second HZ state is a voltage VCC, wherein the voltage VPOS is greater than the voltage VCC, and the voltage VCC is greater than the ground voltage GND.

2. The liquid crystal screen according to claim 1, characterized in that: When the control logic circuit receives a first set of input signals and the set of HZ signals is in the first HZ state, the first voltage level converter controls the first switch circuit to be turned off, the second voltage level converter controls the second switch circuit to be turned on, and the medium voltage logic circuit turns off the third switch circuit, so that the output port is at the voltage VPOS, wherein the first HZ state and the second HZ state are inverse to each other.

3. The liquid crystal screen according to claim 1, characterized in that: When the control logic circuit receives the second set of input signals and the set of HZ signals is in the first HZ state, the first voltage level converter controls the first switch circuit to be turned on, the second voltage level converter controls the second switch circuit to be turned off, and the medium voltage logic circuit turns off the third switch circuit, so that the output port is at the ground voltage GND, wherein the first HZ state and the second HZ state are inverse to each other.

4. The liquid crystal screen according to claim 1, characterized in that: When the control logic circuit receives the third set of input signals and the set of HZ signals in the first HZ state, the first voltage level converter controls the first switch circuit to be cut off, the second voltage level converter controls the second switch circuit to be cut off, and the medium voltage logic circuit turns on the third switch circuit, so that the output port is at the voltage VNEG, wherein the first HZ state and the second HZ state are inverse to each other.

5. The liquid crystal screen according to claim 1, characterized in that: When the control logic circuit receives the fourth set of input signals and the set of HZ signals is in the second HZ state, the first voltage level converter controls the first switch circuit to be cut off, the second voltage level converter controls the second switch circuit to be cut off, and the medium voltage logic circuit controls the third switch circuit to be cut off, so that the output port is in the floating state.

6. The liquid crystal screen according to any one of claims 2 to 4, characterized in that: The HZ signal in the first HZ state is a voltage of GND.

7. The liquid crystal screen according to any one of claims 2 to 4, characterized in that: The driving circuit further includes a third voltage level converter to provide the HZ signal in the first HZ state as a voltage VNEG.

8. The liquid crystal screen according to claim 1, characterized in that: The first voltage level converter includes two medium voltage transistors for correspondingly outputting the first signal to the medium voltage logic circuit.

9. The liquid crystal screen according to claim 1, characterized in that: The second voltage level converter includes two medium voltage transistors for correspondingly outputting the second signal to the medium voltage logic circuit.

10. The liquid crystal screen according to claim 1, characterized in that: The above-mentioned medium voltage logic circuit comprises: Two medium voltage transistors, used for respectively receiving the above-mentioned group of HZ signals; Two transistors, for respectively receiving the first signal and the second signal, wherein the voltage of the first signal is the voltage VCC or the voltage VNEG, the voltage of the second signal is the voltage VCC or the voltage VNEG, wherein the voltage VPOS is greater than the voltage VCC, and the voltage VCC is greater than the ground voltage GND; and Two high-voltage transistors are used to receive the voltage VNEG.

11. The liquid crystal screen according to claim 1, characterized in that: The third set of input signals includes two logic bits, and the maximum operating voltage of the control logic circuit is lower than the voltage VPOS.

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