Sampled data processing method, interference signal transmitting method and related devices thereof

Abstract

The invention discloses a sampling data processing method, an interference signal transmitting method and related devices, which are applied to the technical field of wireless communication data transceiving, and comprise the following steps: acquiring sampling data output by a plurality of sampling channels; generating a target data block from the sampling data from the same sampling channel; and performing write-in operation on all the target data blocks in sequence according to a set write-in sequence. According to the method and the device, one target data block is generated by the sampling data from the same sampling channel, so that each target data block only contains the data of the own sampling channel, and therefore, the target data block read each time only contains the data of the required sampling channel instead of the data of other sampling channels, and the data reading efficiency is improved. Therefore, the required data can be quickly acquired, repeated reading of the data is avoided, a large amount of short-time sampling data can be efficiently processed, the data reading and writing fluency is increased, the sampling data processing efficiency is improved, and the cost can be reduced.

Description

Technical Field

[0001] The present invention relates to the technical field of wireless signal interference, and in particular to a sampling data processing method, an interference signal transmitting method and related devices thereof. Background Art

[0002] Wireless signal jamming or shielding technologies play a vital role in situations where wireless communication security and unauthorized wireless access need to be ensured. These technologies generally generate interference signals to shield or interfere with the wireless communication signals of illegal communication devices, thereby preventing these illegal communication devices from receiving or sending data. Although wireless signal jamming technologies are used in more and more application scenarios, traditional solutions have significant limitations in many aspects.

[0003] Among the traditional wireless signal interference methods, the commonly used technology is mainly to use co-frequency suppression on radio signals of known channels. The co-frequency suppression technology achieves interference effects on illegal communication devices by transmitting interference signals with the same frequency as the target base station signal. The main drawbacks of this method are its high energy consumption, low interference efficiency and short interference distance. In addition, co-frequency interference has extremely high requirements for frequency accuracy. Once the target frequency band deviates or the communication base station starts the backup frequency band, the interference effect will be greatly reduced. In practical applications, due to the diversity and complexity of wireless communication frequency bands, this method is often difficult to achieve full coverage and long-distance interference effects on multiple frequency band signals.

[0004] In addition, with the rapid development of communication technology, especially under high-speed communication standards such as 4G LTE and 5G NR, the frequency bands of wireless communication signals are becoming more and more complex. At present, domestic telecom operators, Wifi, Bluetooth and other wireless communications have allocated at least 10 frequency bands from 800MHz to 5GHz, and the bandwidth occupied by each frequency band also ranges from 10M to 100M. The more complex the frequency band of wireless communication signals, the more difficult it is to carry out wireless signal interference.

[0005] Therefore, how to improve the efficiency of wireless signal interference in the current wireless communication environment is a technical problem that technical personnel in this field urgently need to solve. Summary of the invention

[0006] In view of this, an object of the embodiments of the present invention is to provide a sampling data processing method, an interference signal transmitting method and related devices, which can improve the efficiency of wireless signal interference.

[0007] In order to solve the above technical problems, an embodiment of the present invention provides a sampling data processing method, comprising:

[0008] Get the sampling data output by multiple sampling channels;

[0009] Generate a target data block from the sampling data from the same sampling channel;

[0010] The write operation is performed sequentially on all the target data blocks according to the set write order.

[0011] Optionally, before the step of sequentially performing the writing operation on all the target data blocks according to the set writing order, the sampling data processing method further includes:

[0012] The plurality of target data blocks are sorted according to the set writing order.

[0013] Optionally, the step of sorting the plurality of target data blocks according to a set writing order includes:

[0014] Obtaining the serial number of the sampling channel to which each target data block belongs;

[0015] All the target data blocks are sorted according to the sequence numbers.

[0016] Optionally, the writing order is set such that the writing priority of the first target data block is higher than the writing priority of the second target data block;

[0017] The sequence number of the sampling channel to which the first target data block belongs is smaller than the sequence number of the sampling channel to which the second target data block belongs.

[0018] Optionally, the step of obtaining sampling data output by multiple sampling channels includes:

[0019] The sampling data output by all the sampling channels are acquired in parallel.

[0020] Optionally, the step of sequentially performing a write operation on all the target data blocks according to a set write order includes:

[0021] According to the set writing order, the plurality of target data blocks are sequentially written into the memory by direct memory access.

[0022] Optionally, the step of obtaining sampling data output by multiple sampling channels includes:

[0023] In a sampling period, sampling data output by a plurality of sampling channels are obtained in parallel, and sampling data of each sampling channel is obtained continuously;

[0024] The step of generating a target data block from the sampled data from the same sampling channel comprises:

[0025] After the acquisition times of each sampling channel reaches the set times, all the sampling data acquired by each sampling channel in the set times are used to generate a target data block in the order of sampling time; wherein the number of bits of the target data block is consistent with the number of bits of the storage capacity corresponding to the data block in the burst transmission of the direct memory access.

[0026] Optionally, after the acquisition times of each sampling channel reaches a set number of times, the step of generating a target data block according to the sampling time sequence of the sampling data acquired by each sampling channel in the set number of times includes:

[0027] For the same sampling channel, each time after acquiring new sampling data, the newly acquired sampling data is placed after the sampling data acquired last time;

[0028] Determine whether the number of times the sampling data is obtained reaches the set number. If so, generate a target data block corresponding to the sampling channel based on all the sampling data previously obtained from the same sampling channel. Otherwise, continue to obtain the sampling data until the number of times the sampling data is obtained reaches the set number.

[0029] Optionally, the step of generating a target data block according to the sampling time sequence of the sampling data acquired by each sampling channel within a set number of times includes:

[0030] Generate a sub-target data block according to the sampling time sequence based on all the sampling data acquired by each sampling channel within a set number of times;

[0031] The target data block is generated according to the sub-target data block and the check code; the check code is used to check whether the sampled data in the target data block is complete.

[0032] Optionally, the step of sequentially performing the write operation on all the target data blocks according to the set write order is specifically:

[0033] Writing all the target data blocks into the memory in sequence according to a set writing order;

[0034] After the step of sequentially performing the writing operation on all the target data blocks according to the set writing order, the sampling data processing method further includes:

[0035] The target data blocks corresponding to one or more sampling channels are read from all the target data blocks written into the memory.

[0036] Optionally, the step of reading the target data blocks corresponding to more than one sampling channels from all the target data blocks written into the memory includes:

[0037] From all the target data blocks written in the memory, the target data blocks corresponding to each of the N sampling channels are read in sequence according to the sequence number of the sampling channels; N is not less than 1 and not greater than the total number of sampling channels.

[0038] Optionally, the step of reading the target data block corresponding to each of the sampling channels includes:

[0039] Determine the burst address increment according to the total number of sampling channels;

[0040] Each target data block of each sampling channel is read out according to the burst address increment.

[0041] The embodiment of the present application also provides an interference signal transmission method, the interference signal transmission method comprising:

[0042] Acquire a target data block read by the above-mentioned sampling data processing method, and generate an interference signal according to the target data block;

[0043] The interference signal is transmitted.

[0044] Optionally, the step of obtaining a target data block read by the above-mentioned sampling data processing method, and generating an interference signal according to the target data block includes:

[0045] Step 01: After obtaining a target data block corresponding to a sampling channel, an interference code corresponding to the sampling channel is generated according to the read target data block;

[0046] Step 02: performing a write operation on the interference code of one of the sampling channels according to the address of the target data block corresponding to the sampling channel;

[0047] Step 03: For the remaining sampling channels, follow steps 01 and 02;

[0048] Step 04: Perform a read operation on the interference codes of all the sampling channels, and generate an interference signal according to the read interference codes.

[0049] Optionally, the sampling channel corresponds to multiple target data blocks;

[0050] The step 02 comprises:

[0051] Determine the burst address increment according to the total number of sampling channels;

[0052] According to the increment of the burst address, the interference code is segmented and written into the address of the memory where each of the corresponding target data blocks is located.

[0053] Optionally, the step of performing a read operation on the interference codes of all the sampling channels and generating an interference signal according to the read interference codes includes:

[0054] Executing a plurality of readout cycles in sequence, in each of the readout cycles, reading a corresponding data segment of the interference code of each of the N sampling channels in sequence according to the sequence number of the sampling channel; after all the readout cycles are executed, the set of all data segments of each sampling channel is consistent with the interference code; N is not less than 1 and not greater than the total number of sampling channels;

[0055] After each data segment corresponding to each sampling channel is read out, a corresponding interference signal is generated according to the read data segment.

[0056] Optionally, the total duration of all target data blocks of each sampling channel is the same as the duration of the interference code of each transmitting channel.

[0057] Optionally, after the step of transmitting the interference signal, the interference signal transmitting method further includes:

[0058] When the preset resampling time has passed, the steps of acquiring the target data block read by the sampling data processing method and subsequent steps are re-executed.

[0059] The present application also provides a sampling data processing device, the sampling data processing device comprising:

[0060] A sampling data acquisition module is used to acquire sampling data output by multiple sampling channels;

[0061] A target data block determination module, used for generating a target data block from the sampling data from the same sampling channel;

[0062] The writing module is used to perform writing operations on all the target data blocks in sequence according to a set writing order.

[0063] Optionally, the sampling data processing device is an FPGA.

[0064] The embodiment of the present application further provides an interference signal transmitting device, the interference signal transmitting device comprising:

[0065] A target data block acquisition module, used to acquire the target data block read by the above-mentioned sampling data processing method, and generate an interference signal according to the target data block;

[0066] The interference signal transmitting module is used to transmit the interference signal.

[0067] The present application also provides a sampling data processing system, the sampling data processing system comprising:

[0068] A plurality of sampling channels are used to sample data in parallel, and each of the sampling channels is used to sample a radio signal and output the sampled data;

[0069] The first signal processing unit is used to continuously acquire the sampling data of each sampling channel in a sampling period; after the acquisition times of each sampling channel reaches a set number of times, all the sampling data acquired by each sampling channel in the set number of times are used to generate a target data block in the sampling time sequence; wherein the number of bits of the target data block is consistent with the number of bits of the storage capacity corresponding to the data block in the burst transmission of the direct memory access; all the target data blocks are sequentially written in the set writing order; and the target data blocks corresponding to one or more sampling channels are read from all the target data blocks written to the memory;

[0070] A second signal processing unit, configured to obtain a target data block corresponding to each sampling channel, and generate an interference code according to the obtained target data block;

[0071] The first signal processing unit is further used to perform a write operation on the interference code of each sampling channel according to the address of the corresponding target data block, and perform a read operation on all the interference codes, wherein the interference codes are used to generate new interference signals.

[0072] An embodiment of the present application also provides a computer program product, including a computer program / instruction, which, when executed by a processor, implements the steps of the sampling data processing method as described above, or implements the steps of the interference signal transmission method as described above.

[0073] It can be seen that the embodiment of the present invention obtains the sampling data output by multiple sampling channels, generates a target data block with the sampling data from the same sampling channel, and performs write operations on all target data blocks in sequence according to the set write order. Compared with the scheme of directly generating a data block in parallel and including data of multiple channels, so that a large number of data blocks are repeatedly read, the beneficial effect of the embodiment of the present application is: the embodiment of the present application generates a target data block with the sampling data from the same sampling channel, so that each target data block contains only the data of its own sampling channel. In this way, if it is necessary to generate an interference signal based on the data of each sampling channel, when reading the data of each sampling channel, it can be ensured that the target data block read each time only includes the data of the required sampling channel, but not the data of other sampling channels, so that the required data can be obtained faster, avoiding repeated reading of data, making it possible to more efficiently process a large amount of short-term sampling data, increase the fluency of data reading and writing, improve the efficiency of sampling data processing, and avoid waste of resources, so as to reduce costs.

[0074] In addition, the embodiments of the present invention also provide a sampling data processing device, equipment and system, as well as an interference signal transmission method and device, and a computer program product, which also have the above-mentioned beneficial effects. BRIEF DESCRIPTION OF THE DRAWINGS

[0075] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without paying creative work.

[0076] Figure 1 A schematic diagram of a data link for parallelizing parallel sampled data into data blocks;

[0077] Figure 2 A flow chart of a sampling data processing method provided by an embodiment of the present invention;

[0078] Figure 3 A flow chart of a sampling data processing method provided by another embodiment of the present invention;

[0079] Figure 4 A flow chart of a sampling data processing method provided by another embodiment of the present invention;

[0080] Figure 5 A flow chart of a sampling data processing method provided by another embodiment of the present invention;

[0081] Figure 6 for Figure 5 One specific flow chart of step S210 in the illustrated embodiment;

[0082] Figure 7 An example diagram of a data link for processing a target data block provided by an embodiment of the present invention;

[0083] Figure 8 A schematic flow chart of a sampling data processing method provided by another embodiment of the present invention;

[0084] Fig. 9 A flowchart of an interference signal transmitting method provided by one embodiment of the present invention;

[0085] Fig.10 for Fig. 9 An example flow chart of step S500 in the illustrated embodiment;

[0086] Fig.11 A schematic diagram of an application environment of a sampling data processing method and an interference signal transmitting method provided in one embodiment of the present invention;

[0087] Fig.12 for Fig.11 An example flow chart of a sampling data processing method and an interference signal transmitting method in the application environment shown;

[0088] Fig.13 A timing diagram for reading and writing a target data block provided by an embodiment of the present invention;

[0089] Fig.14 A schematic diagram of a module of a sampling data processing device provided by an embodiment of the present invention;

[0090] Fig.15 A schematic diagram of a module of an interference signal transmitting device provided by an embodiment of the present invention;

[0091] Fig.16 A schematic diagram of modules of a sampling data processing system provided by an embodiment of the present invention.

[0092] Description of Figure Numbers:

[0093] 100: sampling data acquisition module;

[0094] 200: target data block determination module;

[0095] 300: write module;

[0096] 400: target data block acquisition module;

[0097] 500: interference signal transmitting module;

[0098] 600: multiple sampling channels;

[0099] 700: a first signal processing unit;

[0100] 800: second signal processing unit. DETAILED DESCRIPTION

[0101] In order to make the purpose, technical solution and advantages of the embodiments of the present invention clearer, the technical solution in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0102] In the field of wireless signal interference, it is also possible to quickly scan and collect signals at the predicted frequency points, and then determine whether there is a communication protocol signal based on the collected signal, and generate a confrontational and targeted interference signal based on the collected signal to transmit the interference signal on the same frequency band to shield the wireless communication equipment. This method has improved the interference efficiency compared to the same-frequency suppression technology, but requires a more complex parallel signal processing system solution and communication protocol analysis capabilities, thus increasing the difficulty of system design and increasing R&D and manufacturing costs.

[0103] One solution is that the FPGA directly parallelizes the signals of all channels sampled in parallel and forms a data block and writes it into the memory. Figure 1 As shown, for example, there are 8 sampling channels (i.e., sampling channels with analog-to-digital conversion functions), namely AD1 to AD8, and the digital bit width of each sampling channel is 16 bits. After the first sampling, the sampling data of the 8 sampling channels AD1-AD8 are parallelly composed of a 128-bit data block block1. After the second sampling, the data of the sampling channels AD1-AD8 also form a 128-bit data block block2, and so on. Then, the data blocks (block1, block2...) obtained by multiple samplings are sequentially written into the corresponding DDR addresses 1, 2, 3..., so that the host computer can read them when needed. Due to the limited performance of the host computer and the fact that the communication frame analysis algorithm will occupy more resources, the host computer only analyzes the data of one sampling channel each time, that is, each time the host computer reads a data block, it only needs to use the data of one sampling channel. For example, if the host computer first analyzes the data of sampling channel AD1, then in the first data block block1 read out at address 1, only the data of sampling channel AD1 is needed, and the data of sampling channels AD2-AD8 are not needed. When block2 is read out from address 2 of the memory, only the data of sampling channel AD1 is needed, and so on. Because the data block read out by the host computer is a complete block, but only the data of a sampling channel in the data block block is needed, it causes a waste of bandwidth and reading.

[0104] For example, for the above-mentioned 8 sampling channels, if 1 million data are sampled, the write address of the memory is continuously increased by 1 until 1 million, and vice versa, the read address is also continuously increased by 1 until 1 million. However, since the host computer can only analyze the data of a certain sampling channel at a time, all the data of the 8 sampling channels are read out 1 million times each time, and each read out 1 million times can only complete the communication frame analysis of the communication frequency band corresponding to one sampling channel, and when it is necessary to perform communication frame analysis on other sampling channels, it is necessary to read out all the data of the 8 sampling channels again, so the total number of reads required in the end is 8 million times. The embodiment of the present application is optimized here. In terms of the write-read scenario of 8 sampling channels, the data of the 8 sampling channels can be written 1 million times and read out 1 million times, thereby reducing the number of reads by 7 million times relative to the above scheme, greatly improving the reading efficiency and reducing the cost.

[0105] Please refer to Figure 2 , Figure 2 A flowchart of a sampling data processing method provided by an embodiment of the present invention. The method may include steps S100 to S300. The execution subject of this embodiment is, for example, an FPGA (Field Programmable Gate Array), which can optimize the processing of a large amount of short-term torrent data, and aims to solve how to achieve simultaneous acquisition and rapid transmission of signals covering multiple frequency bands and bandwidths at low cost and high efficiency, so as to further improve the effect of wireless signal interference. The sampling data processing method includes the following contents.

[0106] S100, acquiring sampling data output by multiple sampling channels.

[0107] Among them, different sampling channels can correspond to the collection of data in different frequency bands. Each sampling channel corresponds to an analog-to-digital conversion circuit, for example, and the front end of the sampling channel also includes a receiving antenna, a radio frequency signal processing circuit (such as filtering, amplification, etc.), which can refer to the wireless signal receiving circuit in the prior art and will not be repeated here. This embodiment does not limit the number of sampling channels. For example, the number of sampling channels in this embodiment is 8, 10 or other numbers. The frequency band of each sampling channel can be determined based on the actual wireless communication environment. For example, based on the current domestic telecommunications operators, Wifi and Bluetooth and other wireless communication allocation frequency bands, the frequency bands of each sampling channel are various frequency bands between 500MHz and 5GHz, and the occupied bandwidth of various frequency bands is between 10M and 100M.

[0108] It should be further explained that, in a specific embodiment, in order to improve the efficiency of acquiring sampled data, the above-mentioned step of acquiring sampled data output by multiple sampling channels may include: acquiring sampled data output by all sampling channels in parallel. This embodiment acquires sampled data output by all sampling channels in parallel, which means acquiring sampled data of all sampling channels at the same time. If the wireless signal is still collected by a single channel and received one by one in sequence, it will take a lot of time because of too many acquisition frequency bands and frequency switching, which may cause the wireless signal interference device to start too slowly and fail to periodically resample and update the interference code in time. Therefore, this embodiment adopts a parallel sampling method for each frequency band, which can avoid the waiting time caused by sequential acquisition when acquiring a single sampling channel, thereby greatly improving the overall acquisition efficiency of the sampled data. In addition, due to the use of parallel sampling, it is also convenient to achieve coverage of all wireless signals, so that wireless signals of all frequency bands can be interfered.

[0109] S200 , generating a target data block from sampling data from the same sampling channel.

[0110] In this embodiment, the sampled data from the same sampling channel are used to generate a target data block, which means that the data collected by the same sampling channel are integrated to form a data block, that is, compared with the traditional target data block including the sampled data of multiple sampling channels, each target data block in the embodiment of the present invention only includes the sampled data of a single sampling channel. In other words, different sampling channels correspond to different target data blocks. This embodiment does not limit the number of sampled data included in a target data block, which can be set according to the read and write performance of the memory or the length of the burst transmission. For example, the size of the target data block can be 128 bits. For each sampling channel, the size of the sampled data obtained by each sampling is 16 bits. After 8 consecutive samplings, the sampled data of these 8 times can form a target data block. Or in this embodiment, the size of the target data block can also be 256 bits. For each sampling channel, the size of the sampled data each time is 16 bits. After 16 consecutive samplings, the sampled data of these 16 times can form a target data block.

[0111] S300, performing write operations on all target data blocks in sequence according to a set write order.

[0112] This embodiment does not limit the specific set writing order. For example, all target data blocks can be written in order from small to large according to the serial numbers of the sampling channels to which they belong. Alternatively, all target data blocks can also be written in order from large to small according to the serial numbers of the sampling channels to which they belong. This embodiment does not limit the object to be written when performing the write operation, as long as the object can receive torrent data. For example, this embodiment can write all target data blocks in order according to the set write order and write them into DDR (Double Data Rate, double data rate synchronous dynamic random access memory).

[0113] For example, a specific write operation is described as follows: Assuming there are 8 sampling channels in total, and after a 128-bit target data block is generated based on the sampling data of each sampling channel, each target data block can be written into the memory in sequence. Of course, if the sampling channel continues to perform the next batch of sampling, the target data blocks generated in the second batch will be written into the memory in sequence in the above manner.

[0114] The target data blocks in this embodiment may be all target data blocks generated in the same batch, or the target data blocks generated in multiple batches.

[0115] Compared with the above-mentioned solution of directly and in parallel forming the data of all channels sampled in parallel into a data block, the sampling data processing method provided by the embodiment of the present invention optimizes the structure of the target data block so that each target data block contains only the data of its own sampling channel. In this way, if it is necessary to generate an interference signal based on the data of each sampling channel, when reading the data of each sampling channel, it can be ensured that the target data block read each time only includes the data of the required sampling channel, and does not include the data of other sampling channels, so that the required data can be obtained faster, avoiding repeated data reading, and can more efficiently process a large amount of short-time sampling data, increase data reading and writing fluency, improve the efficiency of sampling data processing, and avoid resource waste, thereby reducing costs.

[0116] In another optional embodiment, in order to improve the writing efficiency, as Figure 3 As shown, before the above step S300, the sampling data processing method may further include: step SA0: sorting multiple target data blocks according to a set writing order. In this embodiment, each target data block may be sorted according to a certain rule (such as according to the sequence number of the acquisition channel, according to the size of the frequency band), so that all the target data blocks form a queue, and then each target data block in the queue may be written in sequence. Therefore, in this embodiment, each sampling channel is sampled in parallel, but for the transmission of the sampling data backend, it is equivalent to first converting it into serial sorted data, and then writing the serial sorted data into the memory in sequence.

[0117] Specifically, take sorting according to the sequence number of the acquisition channel as an example. Figure 4 As shown, the above step SA0 may specifically include the following contents. Step SA1: Obtain the serial number of the sampling channel to which each target data block belongs. Step SA2: Sort all target data blocks according to the serial number. Meanwhile, the set writing order in the above step S300 is the order after all target data blocks are sorted in the above step SA2.

[0118] For ease of understanding, assume that the target data blocks corresponding to the acquisition channels AD1, AD2, AD3, AD4, AD5, AD6, AD7 and AD8 are block1, block2…block8 respectively. If the target data blocks are sorted from small to large according to the sampling channel numbers to which they belong, block1 is at the first position and block8 is at the eighth position in the queue formed after sorting. The queue is, for example, a FIFO (First Input First Output). In this way, when performing a write operation, the target data blocks in the queue are written in sequence, that is, block1, block2,…block8 are written into the memory in sequence.

[0119] In this embodiment, a plurality of target data blocks are first sorted according to a set writing order, so that when a write operation is performed on all target data blocks, writing can be performed directly according to the queue after sorting, thereby improving the writing efficiency. In addition, since each target data block is written into the memory according to a set writing order, the address calculation method of the target data block of each acquisition channel in the memory is relatively simple. For example, assuming that the storage address of the first target data block of AD1 is 1, the addresses of each target data block collected thereafter are 9, 17, 25, etc. In this way, when reading out the data of each acquisition channel, the addresses of all target data blocks of each acquisition channel can be calculated more quickly, thereby improving the speed of reading out data.

[0120] In addition, directly sorting the target data blocks according to the sequence number of the sampling channel also facilitates the data read operation, that is, when performing the read operation, all target data blocks of the relevant sampling channel can be directly read according to the sequence number of the sampling channel, further improving the efficiency of data transmission.

[0121] In another optional embodiment, the above-mentioned setting of the writing order is that the writing priority of the first target data block is higher than the writing priority of the second target data block. Among them, the sequence number of the sampling channel to which the first target data block belongs is less than the sequence number of the sampling channel to which the second target data block belongs. In other words, each target data block is sorted in order from small to large according to the sampling channel sequence number. For example, there are 8 sampling channels AD1, AD2... AD8, and the corresponding target data blocks are block1, block2... block8. At this time, if the smaller the sequence number, the higher the writing priority, the writing order is block1, block2... block8. It can be understood that the sorting method of each target data block is not limited to the above situation, as long as the target data blocks of all sampling channels are written in the same sorting method each time during the entire sampling period. For example, it is also possible to sort and perform the writing operation according to the sampling channel sequence number from large to small. Assuming that there are 8 sampling channels, the writing order can be block8, block7... block1, and each time the target data blocks of these 8 sampling channels are written, they are written in the order of block8, block7... block1. Alternatively, the data may be written in any other order, such as block3, block2, block1, block4, block5, block6, block8, block7, and the target data blocks of the eight sampling channels are written in this order each time.

[0122] It is understandable that in other embodiments, the sorting operation may not be performed on all target data blocks first, but the writing operation may be performed directly in a certain order while the writing operation is performed. For example, the sampling data of each sampling channel first generates a target data block in the corresponding cache, and different target data blocks have a one-to-one correspondence with the sequence number of the acquisition channel, and then each target data block is directly written into the memory in sequence according to the sequence number of the acquisition channel. These are all within the protection scope of the present application.

[0123] In another optional embodiment, in order to improve the efficiency of data transmission, the above step S300, i.e., the step of sequentially performing write operations on all target data blocks according to the set write order, may include: sequentially writing multiple target data blocks into the memory by direct memory access according to the set write order. The direct memory access (DMA) in this embodiment has the advantages of efficient data transmission, flexibility and scalability. DMA can perform data read and write operations with the DDR (Double Data Rate, double data rate synchronous dynamic random access memory) plug-in of the FPGA.

[0124] In one embodiment, please refer to Figure 5 The above step S100 is to obtain the sampling data output by multiple sampling channels, which specifically includes:

[0125] S110, in a sampling period, sampling data output by a plurality of sampling channels are obtained in parallel, and sampling data of each sampling channel is obtained continuously.

[0126] Among them, the time of the sampling period can be set according to the actual application environment. Since the interference signal is formulated based on the parsed communication protocol, the parsing result of the communication protocol directly affects the interference effect of the interference signal. If the wireless communication signal is to be subjected to protocol analysis, in order to achieve a more accurate analysis effect, it is necessary to collect multiple wireless frames for analysis. The length of each wireless frame is 10ms. Usually, at least 2 complete wireless frames of more than 20ms need to be collected. Data, that is, the above-mentioned sampling period can be greater than or equal to 20ms. Therefore, in one sampling period, each sampling channel can continuously collect data for 20ms or more, and finally multiple target data blocks can be obtained. Regarding the confirmation method of the sampling period, for example, if the sampling data processing method is executed by FPGA, a counter can be set, and FPGA can judge whether the duration of the sampling period is reached based on the counter.

[0127] It should be noted that after a sampling cycle ends, an interference signal can be generated and cyclically transmitted based on the data collected in the sampling cycle. However, after a period of time, the clock of the interference signal may deviate from the actual base station signal clock. Therefore, after a period of time (such as determining whether a preset resampling time has passed, such as 5s), resampling can be performed, that is, the above sampling cycle can be executed again (in other words, multiple sampling cycles can be executed) to adjust the timing of the interference signal based on the resampled data to ensure that the timing of the interference signal is always synchronized with the base station to achieve a better interference effect.

[0128] At the same time, the above step S200 generates a target data block from the sampled data from the same sampling channel, specifically including: step S210, after the acquisition times of each sampling channel reaches the set times, all the sampled data acquired by each sampling channel in the set times are generated into a target data block in the sampling time sequence. The number of bits of the target data block is consistent with the number of bits of the storage capacity corresponding to the data block in the burst transmission of the direct memory access.

[0129] This embodiment does not limit the specific number of settings. The number of settings in this embodiment can be 8 times, or the number of settings in this embodiment can be 7 times. The number of settings in this embodiment is determined by the amount of sampled data acquired in a single time and the total number of bits of the target data block. For example: if the length of the target data block is 128 bits, and the sampled data collected by the sampling channel each time is 16 bits, then the number of settings is 8, that is, after each sampling channel collects 8 sampling data, a target data block can be formed, and then data collection will continue until a sampling cycle lasts. Among them, for the same sampling channel, the sampled data collected in sequence should be sorted according to the sampling time order, so as to ensure that the continuity of the data is not destroyed and avoid errors caused by data misalignment. Among them, the sampling time order can be that the sampled data with an early sampling time is arranged in front, and the sampled data with a late sampling time is arranged in the back. In this embodiment, DMA can use burst transmission to transmit data, wherein the size of the data block in the burst transmission is related to the burst length and the data interface bit width. Assuming that the data interface bit width between the memory (such as DDR) and the FPGA is 16 bits, the size of the data block in the burst transmission is 128 bits, and the burst length is 8; or the size of the data block in the burst transmission is 256 bits, and the burst length is 16. The number of bits of the target data block is consistent with the number of bits of the storage capacity corresponding to the data block in the burst transmission of direct memory access. For example, when the data block in the burst transmission is 128 bits, the number of bits of the target data block can be 128. In this way, if a 128-bit target data block is written, given a destination address (i.e., burst address), DMA will automatically divide the target data block into 8 16-bit data blocks, and write each 16-bit data block into the memory for 8 consecutive times based on the destination address being incremented by 1.

[0130] In another alternative embodiment, if Figure 6 As shown, in order to improve the accuracy of target data block generation, the above step S210, that is, after the acquisition times of each sampling channel reaches the set times, the sampling data acquired by each sampling channel in the set times are used to generate a target data block in the order of sampling time, may include the following contents.

[0131] S211, for the same sampling channel, each time after acquiring new sampling data, the newly acquired sampling data is placed after the sampling data acquired last time.

[0132] This embodiment places the newly acquired sampled data after the sampled data acquired last time, so that the sampled data can be sorted in the order of sampling time to generate a target data block.

[0133] S212, determining whether the number of times of acquiring sampling data reaches the set number.

[0134] S213: If yes, then generate a target data block corresponding to a sampling channel according to all sampling data previously acquired from the same sampling channel.

[0135] S214: Otherwise, continue to obtain the sampled data until the number of times of obtaining the sampled data reaches the set number of times.

[0136] Next, combine Figure 7 The above scheme is illustrated with an example. Assume that there are 8 sampling channels AD1, AD2…AD8. In the first sampling cycle, all sampling channels perform parallel sampling for the first time, and all obtain 16-bit sampling data, which enter [15:0] of the target data blocks block1-block8 of AD1-AD8 respectively. After the second parallel sampling, the 16-bit sampling data collected again by AD1-AD8 enters [31:16] of the target data blocks block1-block 8 of AD1-AD8 respectively. Execute sequentially, and after the 8th parallel sampling, the 16-bit data collected by AD1-AD2 enters [127:112] of the target data blocks block1-block 8 of AD1-AD8 respectively. At this point, the target data block of each sampling channel is 128 bits. At this point, the construction of the first group of target data blocks block1-block8 is completed, and then the first group of target data blocks can be written into the memory in sequence. Then, the construction of the second group of target data blocks block9-block16 is continued until the end of the first sampling cycle. It is worth explaining that block 9-block 16 also store the data of sampling channels AD1-AD8 respectively.

[0137] In another optional embodiment, in order to ensure the accuracy of the target data block, the step of generating a target data block in the above step S210 according to the sampling time sequence of the sampling data obtained by each sampling channel in the set number of times may include: generating a sub-target data block according to the sampling time sequence of all the sampling data obtained by each sampling channel in the set number of times. Generate the target data block according to the sub-target data block and the check code. The check code is used to check whether the sampling data in the target data block is complete.

[0138] The embodiment of the present invention adds a check code, and the check code and the sub-target data block are combined to form a target data block with the same number of bits as the number of bits of the data block storage capacity in the burst transmission of DMA. The sub-target data block in this embodiment is composed of sampled data. For example, when 8 sampling channels collect data 7 times in parallel, for each sampling channel, the sampled data collected 7 times constitutes a sub-target data block, which is 112 bits. Then, the 16-bit check code is spliced ​​with the 112-bit sub-target data block to form a 128-bit target data block.

[0139] The check code enables the sampled data in the target data block to be checked for integrity according to the check code after the target data block is subsequently read out, thereby ensuring the integrity of the sampled data. Specifically, the relevant processing unit (such as the host computer) that subsequently reads out the target data block for analysis can check the check code in the target data block to determine whether the data in the target data block is wrong during the storage process and the reading process by determining whether the check code is correct. If the relevant processing unit determines that the check code is incorrect, it means that the probability that the sampled data in the target data block is also wrong is high, and the relevant processing unit can abandon the use of the target data block accordingly to avoid the erroneous sampled data affecting the analysis results. If the relevant processing unit determines that the check code is correct, it means that the probability that the sampled data in the target data block is wrong is low, and the relevant processing unit can continue to use the target data block to complete the generation of the interference signal.

[0140] This embodiment does not limit the subsequent process of using the check code for verification. For example, the check code in this embodiment can be checked by the FPGA after the DMA is read out. Or the check code in this embodiment can also be checked by the host computer. In the embodiment of the present invention, the check code can be implemented by using a CRC check code (Cyclic Redundancy Check, cyclic redundancy check code). Of course, in other optional embodiments, other types of check codes can also be used. The embodiment of the present application does not limit the type of the check code.

[0141] In another alternative embodiment, if Figure 8 As shown, the above step S300, i.e., the step of sequentially performing the writing operation on all target data blocks according to the set writing order, may specifically be: S310, sequentially writing all target data blocks into the memory according to the set writing order. Meanwhile, after the step of sequentially performing the writing operation on all target data blocks according to the set writing order, the sampling data processing method may further include: S4400, reading target data blocks corresponding to one or more sampling channels from all target data blocks written into the memory.

[0142] The memory in this embodiment is, for example, a DDR memory. At the same time, if the sampling data processing method is executed by FPGA, the writing (for example, the above steps S300 and S310) and reading (for example, the above step S400) operations can be performed by DMA. Before the interference signal is generated, it is necessary to be able to effectively parse the communication protocol. In order to effectively parse it, it is necessary to at least ensure that the data to be parsed contains a complete wireless frame. For example, for each sampling channel, at least one sampling cycle of data must be collected. Among them, before the entire collection process of a sampling cycle is completed, the collected data (that is, each target data block) needs to be temporarily stored in the memory. Once the sampling cycle is completed, the host computer can analyze the communication protocol based on all the data collected in the sampling cycle.

[0143] In this embodiment, the purpose of reading the target data block is to facilitate the analysis of the communication protocol so as to generate an interference signal based on the analysis result. Reading the target data block corresponding to one or more sampling channels means that when reading the data in the memory, the embodiment can read the target data blocks corresponding to all sampling channels or part of the sampling channels according to the actual interference requirements. Among them, when reading the data of each sampling channel, it is necessary to read all the target data blocks of each sampling channel within a sampling period. Assuming that the sampling period is 20ms, the total length of all the target data blocks read for each sampling channel is also 20ms, which is equivalent to the length of two wireless frames.

[0144] In another optional embodiment, the above step S400, i.e., the step of reading the target data blocks corresponding to more than one sampling channels from all the target data blocks written to the memory, may include: from all the target data blocks written to the memory, sequentially reading the target data blocks corresponding to each sampling channel in N sampling channels according to the sequence number of the sampling channels, where N is not less than 1 and not greater than the total number of sampling channels.

[0145] Among them, if N is equal to the total number of sampling channels, it means reading the data of all sampling channels. If N is less than the total number of sampling channels, it means reading the data of some sampling channels. Next, take reading the data of all sampling channels as an example: Assuming that there are 8 sampling channels (AD1-AD8), and a total of 8 data are collected in one sampling cycle, after completing the entire process of collecting data and storing, all target data blocks of each sampling channel are read from the memory in sequence according to the order of AD1-AD8: first read the data of sampling channel AD1, that is, read the target data blocks with burst addresses of 1, 9, 17, 25...57; then read the data of sampling channel AD2, that is, read the target data blocks with burst addresses of 2, 10, 18, 26...58. And so on, until the data of sampling channel AD8 is read.

[0146] It is understandable that, depending on the actual situation, interference signals corresponding to all sampling channel frequency bands may not be emitted during the interference process, that is, interference signals corresponding to frequency bands of some specified sampling channels may be emitted. In this case, only the target data blocks corresponding to some sampling channels need to be read.

[0147] In another optional embodiment, in order to improve the data transmission rate, the above step of reading the target data block corresponding to each sampling channel may include: determining a burst address increment according to the total number of sampling channels; and reading out each target data block of each sampling channel according to the burst address increment.

[0148] For example, if the number of sampling channels is 8, the burst address increment is 8. When reading all the target data blocks of sampling channel AD1, the read burst address will be incremented by 8, that is, the target data blocks with burst addresses of 1, 9, 17, 25, etc. are read in sequence. When reading the target data block of each burst address, it is also automatically read continuously based on the burst length. For example, assuming that the burst length is 8 and the data interface bit width is 16 bits, when reading the target data block with burst address 1 of sampling channel AD1, it is necessary to read 8 times of 16-bit data from the memory continuously; then read the target data block with burst address 9 of sampling channel AD1, it is necessary to read 8 times of 16-bit data from the memory continuously, and repeat this cycle until all the target data blocks of AD1 are read.

[0149] In this embodiment, each target data block of each sampling channel is read out in a burst address increment manner, which can improve the efficiency of data transmission and thus can be better applied to the collection and transmission of short-term torrent data.

[0150] To make the embodiments of the present invention easier to understand, please refer to Figure 7, specifically describe one of the specific implementation methods from data collection to data reading: FPGA executes the sampling data processing methods of the above embodiments, in a sampling cycle (such as 20ms), 8 (other numbers) sampling channels AD1-AD8 (sampling channel 1 to sampling channel 8) are sampled in parallel, and after sampling 8 times, the sampled data can be combined into a target data block block of only the sampling channel according to each channel through the delay unit, for example, block1 with only AD1 data, block2 with AD2 data to block8 with AD8 data, and written into the FIFO (first-in-first-out queue) in sequence, and DMA is used to write each target data block into the DDR according to the address wr_address (written burst address) incremented by 1. Then continue sampling, and after sampling 8 times again, the target data blocks block9, block10...block16 of the sampling channels AD1-AD8 will be generated through the delay unit. Cycle in sequence until the sampling of 20ms is completed. After that, data reading begins, and DMA uses burst address increment to read out the data of each sampling channel. Among them, when reading the data of each sampling channel, each read data is rd_address (the read burst address) plus 8 (because there are 8 channels). For example, for sampling channel AD1, block1, block9, ...block57 are read out in sequence. In this embodiment, when reading the data of each sampling channel, the read data only includes the data of the sampling channel to be read, and does not include the data of other sampling channels, so that the read efficiency can be improved. For example: if 1 million sampling data are sampled, they are written into DDR 1 million times, and the reading of 8 sampling channels is also 1 million times, so that the analysis of all data can be completed. In addition, after the preset resampling time, a new sampling cycle is started again, and the above-mentioned sampling data processing method is executed.

[0151] It should be noted that the DMA controller can be set to single transfer and burst transfer: in single transfer mode, each operation only reads or writes one data to the DDR memory. In burst transfer mode, the DMA controller can write continuous data into the storage unit with the continuously increasing target address in sequence until the entire burst sequence is completed. The above embodiment uses the burst transfer mode to write data into the memory and read it. In burst transfer mode, a reasonable burst length can reduce the number of times the DMA operation is initialized and started, improve the efficiency of data transmission, more effectively utilize the memory bandwidth, and improve the overall performance of the system. The burst length of DMA is usually set to 4, 8, 16, 32 or 64. For example, if a burst transfer of 256 bits (relative to the 32-bit data bit width, the burst length is 8) is set, only a destination address (i.e., the written burst address) and a 256-bit data block need to be written to the DMA, and then the DMA will automatically divide the 256-bit data into 8 data blocks, and write 8 times of 32-bit data to adjacent storage units on the basis of the storage address being incremented by 1 in sequence, completing a burst transfer process.

[0152] Please refer to Fig. 9 , Fig. 9 A flowchart of an interference signal transmission method provided by an embodiment of the present invention. The method may include steps S500 to S600.

[0153] S500, obtaining a target data block read by the above-mentioned sampling data processing method, and generating an interference signal according to the target data block.

[0154] The execution subject of this embodiment can be a host computer, FPGA, digital-to-analog conversion circuit (DA), and radio frequency circuit. The target data block read by the above-mentioned sampling data processing method in this embodiment is, for example, the above-mentioned step S400, that is, reading one or more target data blocks corresponding to the sampling channels from all the target data blocks written to the memory. The interference signal in this embodiment is generated based on the sampling data. For example, the communication protocol and time slot analysis can be performed on all the target data blocks of each sampling channel to generate an interference signal with the same frequency band as each sampling channel.

[0155] Specifically, the duration of the interference signal can be the same as the duration of the sampled data, which can be implemented specifically based on a counter. For example: if the duration of the sampling period is 20ms, the duration of the interference signal is also 20ms, that is, the duration of the interference signal in the frequency band corresponding to each sampling channel is 20ms. The advantage of this is that the reception and transmission periods are the same, so that the interference signal can imitate the timing of the base station signal as much as possible to enhance the interference effect. It should be noted that this embodiment does not make specific restrictions on the generation method of the interference signal, and it can be implemented using existing solutions, such as: directly using the collected data as the interference signal; or replacing part of the sampled data with a noise signal, etc., as long as it can affect the normal communication of the wireless communication device.

[0156] After the host computer generates the interference code, it can send the interference code to the FPGA. The FPGA can convert the interference code into a radio frequency signal through the DA and radio frequency circuit, which is the final interference signal.

[0157] S600: transmitting an interference signal.

[0158] The execution subject of this embodiment is, for example, a transmitting antenna. In this embodiment, the purpose of transmitting the interference signal is to interfere with the wireless communication device.

[0159] The above-mentioned scheme of directly and parallelizing all channel data sampled in parallel to form a data block, due to repeated reading of a large number of data blocks, not only wastes the read and write bandwidth, but also leads to low efficiency of data processing and transmission. The signal interference scenario has timeliness requirements. If the interference signal cannot be sent in time or the speed of sending the interference signal is slow, it will affect the interference effect. The interference signal transmission method provided by the embodiment of the present invention generates the interference signal based on the target data block of the sampling data processing method of each embodiment above, and the data reading and writing fluency of the target data block obtained by the sampling data processing method above is relatively high, and a large amount of short-time sampling data can be processed more efficiently, so that the speed of generating the interference signal by reading the target data block is also relatively fast, so that the interference signal can be quickly generated and transmitted, which can improve the effect of interference.

[0160] In another alternative embodiment, please refer to Fig.10 In order to improve the accuracy of interference signal generation, the above step S500, i.e., the step of obtaining the target data block read by the above sampling data processing method and generating the interference signal according to the target data block, may specifically include the following contents.

[0161] S01: After acquiring a target data block corresponding to a sampling channel, an interference code corresponding to the sampling channel is generated according to the read target data block.

[0162] The interference code refers to the baseband signal corresponding to the interference signal. Each interference code is generated based on all target data blocks in the corresponding frequency band within a sampling period. For example, if the total duration of all target data blocks collected by sampling channel AD1 within a sampling period is 20ms, then after the host computer obtains all target data blocks of the sampling channel, it will generate an interference code with the same duration of 20ms, and the frequency band of the interference code is the same as that of AD1.

[0163] S02: Perform a write operation on the interference code of a sampling channel according to the address of the target data block corresponding to the sampling channel.

[0164] In this embodiment, when performing a write operation, the interference code of each sampling channel is written one by one, and the writing of the interference code of all sampling channels is completed after waiting for the data of other sampling channels to be written. When writing, the address to which each interference code is written is the same as the address of the target data block of the sampling channel. For example, when performing a write operation, assuming that there are currently 8 sampling channels (AD1-AD8), since the burst address of the target data block of the sampling channel AD1 is 1, 9, 17, 25..., the burst address of the interference code corresponding to the sampling channel AD1 when performing a write operation is also 1, 9, 17, 25...

[0165] Specifically, the target data blocks corresponding to the above sampling channels are multiple. The above step 02 may specifically include: determining the burst address increment according to the total number of sampling channels; writing the interference code segments into the addresses of the corresponding target data blocks in the memory according to the burst address increment. Among them, the interference code segmentation means that the interference code is divided into several data segments, and each data segment corresponds to a burst address. For each sampling channel, the burst addresses of all data segments of the interference code cover the burst addresses of all target data blocks of the same sampling channel. For example, if DMA is used to perform data reading and writing, assuming that the total number of sampling channels in this embodiment is 8, the burst address increment is 8, and the burst addresses written into each data segment of the interference code of the sampling channel AD1 are: 1, 9, 17, 25..., and the data length of the data segment of the interference code is the same as the data length of the target data block (for example, both are 128 bits). Similarly, the burst addresses written into each data segment of the interference code of the sampling channel AD2 are 2, 10, 18, 26...

[0166] S03: For the remaining sampling channels, execute according to S01 and S02.

[0167] In this embodiment, for example, FPGA first uploads all target data blocks of sampling channel AD1 to the host computer for analysis. After the host computer completes the analysis, it will generate and send down the baseband signal of the interference signal with the same frequency band as AD1 (i.e., the interference code corresponding to sampling channel AD1). The baseband signal of the interference signal is sent down to FPGA and stored in the memory. Next, FPGA uploads all target data blocks of sampling channel AD2 to the host computer for analysis. The host computer then sends down and stores the generated baseband signal of the interference signal with the same frequency band as AD2 (i.e., the interference code corresponding to sampling channel AD2), and the cycle is repeated until the host computer analyzes the target data blocks of all sampling channels within a sampling cycle and sends down the interference codes of all sampling channels. S04: Perform a read operation on the interference codes of all sampling channels, and generate interference signals based on the read interference codes.

[0168] When performing a read operation on the interference code, this embodiment does not need to continuously read out all data segments of the same sampling channel, but can read and transmit at the same time, that is, the data segments of different sampling channels can be continuously read out, for example, the first data segment corresponding to each sampling channel with a burst address of 1, 2, 3, 4... is first read out, and the read data segment will be converted into a radio frequency signal and transmitted, and the second data segment of each sampling channel will continue to be read, and the cycle will continue. Interference code In another optional embodiment, the above step S04, that is, the step of performing a read operation on all interference codes and generating an interference signal based on the read interference code, can specifically include: executing multiple read cycles in sequence, in each read cycle, reading the corresponding data segment of the interference code of each sampling channel in N sampling channels in sequence according to the sequence number of the sampling channel; after all read cycles are completed, the set of all data segments of each sampling channel is consistent with the interference code. N is not less than 1 and not greater than the total number of sampling channels.

[0169] In this embodiment, after each read cycle is executed, the data read is the corresponding data segment of all sampling channels, so that the corresponding interference signal can be generated according to the read data segment. For example, assuming that there are 8 sampling channels (AD1-AD8) and the length of the target data block is 128 bits, then in the first read cycle, the first data segment of burst address 1 in the interference code corresponding to sampling channel AD1 and the first data segment of burst address 2 in the interference code corresponding to sampling channel AD2 are read out in sequence, until the first data segment of burst address 8 in the interference code corresponding to sampling channel AD8 is read out, the first read cycle is executed, and the above-mentioned first data segments are all 128 bits, at this time, the first data segments of the 8 sampling channels read out can be converted into radio frequency signals and sent out as corresponding interference signals. Next, the second read cycle is executed, that is, the second data segment corresponding to each sampling channel is read out in sequence. The cycle is repeated in sequence until all read cycles are executed, at which time all data segments are read out and converted into corresponding radio frequency signals and sent out as corresponding interference signals. So far, for each sampling channel, the set of all data segments read out is the corresponding interference code.

[0170] It should be noted that after the FPGA starts reading the data segments of each interference code from the memory, the transmission channel at the back end can start to continuously transmit the corresponding interference signal, that is, to start the uninterrupted interference. In order to ensure uninterrupted interference, the DDR readout speed needs to be greater than the data processing speed of the DA (digital-to-analog converter). The following is an example of formula (1).

[0171] (1);

[0172] in," The product of the data on the right side of the "" sign is the DDR transmission data rate. 800MHz is the operating frequency of DDR, 2 represents the double data rate mode, 32bit is the data bit width of DDR, and 0.8 takes into account the initialization time and response efficiency during DDR transmission. Therefore, the calculated DDR transmission data rate is about 40960bit per second. The product of the data on the left side of the "" sign is the data rate of the DA, because generally the DA is also in double data rate mode, such as a DA with a sampling rate of 122.88MSPS, a digital bit width of 12 bits, and a maximum rate of about (2950*N) per second when there are N parallel channels. If this formula is to be satisfied, the system can use up to 13 AD / DAs to sample and transmit data. If the number of parallel channels N needs to be increased, it is necessary to consider reducing the data bit width of each AD / DA or continue to increase the operating frequency of DDR to ensure that formula (1) can be satisfied.

[0173] The N channels in this embodiment are channels that need to be interfered. It is understandable that, according to the actual application scenario, it is not necessary to interfere with the corresponding frequency bands of all sampling channels, that is, only some frequency bands may need to be interfered. At this time, N is less than the total number of sampling channels. In this way, the host computer only needs to send the corresponding interference code to the sampling channels that need to be interfered. For example, only the frequency bands corresponding to 4 sampling channels out of 8 sampling channels are interfered, then N is equal to 4.

[0174] In another optional embodiment, the total duration of all target data blocks of each sampling channel is the same as the duration of the interference code of each sampling channel. For example: in a sampling period, the sampling channel AD1 collects 20ms of data in total, that is, the total duration of all target data blocks is 20ms, then the duration of the interference code corresponding to the sampling channel AD1 generated by the host computer is also 20ms, and the duration of the interference signal obtained after the interference code is finally converted into a radio frequency signal is also 20ms. In this embodiment, the total duration of all target data blocks is the same as the duration of the interference code of each transmission channel, in order to ensure that the generated interference signal is the same as the duration of the collected data, so as to better simulate the base station signal and enhance the effect of interference.

[0175] In another optional embodiment, in order to improve the interference effect, after the preset resampling time has passed, the target data block read by the above-mentioned sampling data processing method and subsequent steps are re-executed. In this embodiment, the preset resampling time is, for example, 5s. For example, a counter is set to generate a pulse valid signal every 5s. Each time a pulse valid signal is generated, it means that the preset resampling time has passed. At this time, a new sampling cycle needs to be started, and the sampling data processing methods of the above-mentioned embodiments are first executed, and then the interference signal transmission method of the above-mentioned embodiment is executed.

[0176] The timing offset value obtained by resampling can compensate the timing of the interference signal so that the timing of the corrected interference signal is consistent with the base station signal again, so that the interference signal sent subsequently can always maintain a good interference effect. It can be understood that because the interference signal will be repeatedly sent for a period of time after the end of a sampling cycle and the base station signal is stopped during this period of time, all relevant signals in the interference device need to rely on the local clock, for example, it is necessary to rely on the local clock in the signal interference device to repeatedly send the interference signal, but the local clock itself may have a certain accuracy error, even if the local clock is adjusted to a state aligned with the timing of the base station signal after receiving the base station signal at the beginning, after the repeated transmission process of the interference signal continues for a period of time, the accuracy error of the local clock will cause the timing of the transmitted interference signal to deviate from the timing of the base station signal, and this deviation will become larger and larger over time. When the deviation is so large that the timing of the generated interference signal differs greatly from the timing of the actual base station signal, the interference effect will be reduced. Since there may be frequency deviation between the base station clock and the interference signal transmission clock, the interference signal needs to be resampled and updated every once in a while to synchronize the timing of the base station and the interference device to achieve a better interference effect. For example, after resampling, the position offset between the synchronization signal (such as the PSS signal) corresponding to the new sampled data and the synchronization signal at the last sampling can be calculated, and then the position offset can be used to calibrate the transmission timing of the interference signal to ensure that the timing of the interference signal can reach the same state as the base station signal.

[0177] To make the embodiments of the present invention easier to understand, please refer to Fig.11 , Fig.11One of the specific application environments in which the sampling data processing method and the interference signal transmission method provided by the above-mentioned embodiments of the present invention can be applied. FPGA (Field Programmable Gate Array) is used as the control platform for data acquisition and transmission, and multiple AD / DA converters are used to be responsible for the parallel sampling of multi-band base station signals. At the same time, the FPGA is externally connected with a DDR (Double Data Rate, double data rate synchronous dynamic random access memory) for data caching and a PHY chip (Physical Layer Interface Chip physical layer interface chip, common USB3.0 data transmission technology or Ethernet PHY chip) for fast data transmission with the host computer. The host computer configures the AD / DA chip through the SPI (Serial Peripheral Interface-Serial Peripheral Interface) bus, configures the FPGA through the IIC (Inter-Integrated Circuit, Integrated Circuit Bus) bus, and the host computer transmits data with the FPGA through the PHY chip. Because higher-speed data transmission requires the support of a specially designed physical layer chip, sampling the PHY chip to transmit high-speed signals can implement specific data transmission protocols and reduce the difficulty of system design. The transmission interface between the AD / DA converter and the FPGA is LVDS, i.e., low voltage differential signal, which is an interface technology for high-speed data transmission. The transmission interface between the FPGA and the PHY is GPIO (General Purpose Input Output, a general digital input / output interface used in embedded systems and single-chip microcomputers). It should be further explained that in addition to using the PHY chip in this embodiment, FX3 (based on the USB3.0 protocol) or Ethernet EPHY (based on Ethernet) can also be used.

[0178] Please refer to Fig.12 , Fig.12 For Fig.11 A flowchart of one of the sampling data processing methods and interference signal transmission methods of the above-mentioned embodiments is executed under a specific application environment. It should be noted that: Fig.12 In the above, steps 5 and 6 in the sampling process and the analysis process are one specific embodiment of the sampling data processing method, and the remaining steps of the analysis process and the transmission process are one specific embodiment of the interference signal transmission method. In this embodiment, there are 8 groups of sampling channels, the sampling data is 16 bits, the sampling period is 20ms, and the resampling interval is 5s.

[0179] Step 1: The host computer uses the SPI bus to configure 8 groups of AD / DA and RF chips. The RF chip can receive 8 groups of data in different frequency bands and convert them into baseband signals. The 8 groups of baseband signals in different frequency bands enter 8 groups of AD for analog-to-digital conversion to obtain 8 groups of sampling data, and each group of sampling data includes IQ channels, a total of 16 bits. At the same time, the host computer uses IIC to initialize the FPGA.

[0180] Step 2: After confirming that the counter generates a valid signal of a 20ms periodic pulse, use 8 sampling channels to perform parallel sampling.

[0181] It is understandable that a 20ms counter can be set inside the FPGA to periodically send out a pulse signal every 20ms as a reference for the global start sampling signal and the start of transmitting the interference signal. The 20ms in this embodiment means that the sampling is currently performed according to the time of 2 frame lengths, where the frame length is 10ms. In addition to 20ms, it can also be 30ms, 40ms, 50ms, etc.

[0182] Step 3: 8 sets of sampled data enter the FPGA in parallel, and each of them forms a target data block. Figure 7 , the sampling data of 8 parallel sampling channels are converted into serial sorting through the delay unit. During the sorting process, the 8 sampling data continuously collected by each sampling channel are spliced ​​into a 128-bit target data block. Alternatively, a CRC check code can be added to the target data block, such as CRC-16. At this time, each sampling channel can splice 7 sampling data into a sub-target data block, and generate a 16-bit check code at the same time, and splice the check code and the sub-target data block into a 128-bit target data block, and store each target data block in the FIFO in sequence according to the order of the sampling channels. Finally, the target data blocks in the FIFO are block1 (the first target data block of AD1), block2 (the first target data block of AD2)...block8, block9 (the second target data block of AD1), block10...block16...

[0183] The step 3 is a specific implementation of the above steps S110, S210, SA1, and SA2.

[0184] Step 4: The DMA module in the FPGA reads the target data block and the corresponding burst address (burst length is 8) in the FIFO, and writes each target data block into the DDR in burst mode. The written burst address is incremented by 1 until all target data blocks are written. When the 20ms counter generates a new valid pulse, it is determined that 20ms of data have been sampled and written. At this time, the FPGA stops sampling and sends a valid sampling completion signal to the host computer through IIC.

[0185] This embodiment is a specific implementation of writing multiple target data blocks into the memory in sequence through direct memory access according to the set writing order described above. For ease of understanding, please refer to Fig.13 , Fig.13 A timing diagram for reading and writing a target data block provided by an embodiment of the present invention. Wherein, clk represents a clock signal. wr_addr is the burst address to be written, wr_dat is the data to be written, and wr_vld is write valid. rd_addr is the burst address to be read, rd_dat is the data to be read, and rd_vld is read valid. ad1 is the target data block of sampling channel 1, ad2 is the target data block of sampling channel 2, and ad3 is the target data block of sampling channel 3. Wherein, rd_addr is 1, 9, 17, 25..., respectively, and it can be seen that the burst address increment is 8.

[0186] Step 5: After the host computer receives the valid signal after the sampling is completed, it configures the FPGA to start uploading the target data block.

[0187] Step 6: FPGA reads out the target data block corresponding to each sampling channel through the DMA module.

[0188] In this embodiment, since there are 8 sampling channels, the burst address read by DMA is incremented by 8. If the host computer only needs the data of sampling channel AD1, the target data blocks read from burst addresses 1, 9, 17, 25, etc. are all sampling data of sampling channel AD1.

[0189] This step 6 is a specific implementation of the above step S400, determining the burst address increment according to the total number of sampling channels, and reading each target data block of each sampling channel by using the burst address increment.

[0190] Step 7: FPGA uploads the read target data block of the current sampling channel to the host computer through the PHY chip.

[0191] Step 8: The host computer generates an interference code of the corresponding frequency band based on the target data block corresponding to each sampling channel read out, and sends the interference code to the PHY chip and then back to the FPGA.

[0192] This step 8 is one of the specific implementations of generating an interference code corresponding to a sampling channel according to the read target data block after obtaining the target data block corresponding to a sampling channel above. In this embodiment, the host computer first receives all the target data blocks of the sampling channel AD1, and parses the communication protocol, time slot analysis, etc. according to the target data block, and then generates a targeted interference code and sends it to the FPGA. Next, all the target data blocks of the sampling channel AD2 are received and analyzed, and then the interference code with the same frequency band as AD2 is generated and sent to the FPGA. Until all the target data blocks of the last sampling channel, AD8, are read and analyzed to generate the corresponding interference code.

[0193] Step 9: FPGA writes the interference code returned by the host computer into DDR in segments through the DMA module according to the current configuration of the host computer. The burst mode is used for writing, and the burst address of the interference code is automatically increased by 8.

[0194] This step 9 is one of the specific implementations of the step of determining the burst address increment according to the total number of sampling channels, and using the burst address increment to write the scrambling code segment into the address of the corresponding target data block in the memory. Among them, the burst address written by the interference code corresponding to the sampling channel AD1 is 1, 9, 17, 25..., which just covers the burst address of each target data block of the sampling channel AD1. Therefore, the address of the interference code of the same sampling channel in the memory is the same as the address of the target data block. The same is true for other sampling channels, and the interference code covers the address of the target data block of the corresponding sampling channel.

[0195] Step 10: After all the interference codes of the 8 sampling channels are written into DDR, the FPGA will upload a completion signal, and the host computer can determine that the writing of the interference codes of all sampling channels is completed. After that, the host computer configures the FPGA to start synchronous transmission.

[0196] Step 11: The FPGA will wait for the counter to send out the next 20ms pulse valid signal, and then continuously read out the interference code in the DDR by incrementing the burst address by 1 (the read burst address is 1, 2, 3, 4...).

[0197] This step 11 is one of the specific implementation methods of the above step 04 to perform the read operation on the interference codes of all the sampling channels. In this embodiment, the DDR read speed is greater than the DA transmission speed to start uninterrupted interference. If the DDR read speed is too fast and the transmission channel has no time to process the currently received data, the DDR will pause to enter the waiting time. After the DA has processed all the current data, the DDR will continue to read the data. The FPGA will reset the DDR address after the next 20ms (it can be set according to needs, but at least greater than 10ms) period of valid signal. Then start to read the interference code in the DDR with the burst address incremented by 1.

[0198] Step 12: Distribute the interference code to the corresponding transmission channel and transmit the corresponding interference signal.

[0199] Step 13: Continue to read the interference code in each subsequent read cycle and synchronously transmit the interference signal.

[0200] Steps 11, 12, and 13 are one specific implementation of the above-mentioned step S04, i.e., performing a read operation on the interference codes of all sampling channels and generating interference signals according to the read interference codes. In this way, after a plurality of read cycles, all interference codes of 20ms in the frequency band corresponding to each sampling channel can be read out and transmitted in the form of interference signals.

[0201] Step 14: After every preset resampling interval, resampling is performed. The entire system can resample again from step 2 according to the host computer configuration, and then return to the host computer to complete the analysis. The host computer adjusts the interference signal according to the re-received sampling data to achieve a better interference effect.

[0202] Compared with the prior art, the embodiments of the present invention have the following advantages: 1. The sampling data processing flow is optimized for the application scenario of the wireless signal interference device, and the structure of the data block is adjusted, that is, the parallel data is converted into serial order. This design method can avoid repeated data reading, increase the fluency of data reading and writing, and enable the system to process a large amount of short-time sampling data more efficiently, thereby improving the response speed, processing capacity and interference effect of the overall system. 2. The use of reprogrammable FPGA as the core control platform, external DDR as data cache and PHY chip for data transmission with the host computer makes the whole system flexible and scalable, so that it can adapt to the development of future communication technology and changes in frequency bands, and can continue to expand more sampling channels, with better adaptability and long-term use value. 3. Realize periodic parallel acquisition and synchronous transmission, better generate interference signals in real time, and then cooperate with periodic resampling to achieve automatic adjustment of interference strategies and achieve better interference effects.

[0203] The following is an introduction to a sampling data processing device provided by an embodiment of the present invention. The sampling data processing device described below and the sampling data processing method described above can be referred to each other.

[0204] Please refer to Fig.14 , Fig.14 A schematic diagram of the structure of a sampling data processing device provided by an embodiment of the present invention may include:

[0205] The sampling data acquisition module 100 is used to acquire the sampling data output by multiple sampling channels.

[0206] The target data block determination module 200 is used to generate a target data block from the sampling data from the same sampling channel.

[0207] The writing module 300 is used to perform writing operations on all the target data blocks in sequence according to a set writing order.

[0208] Further, based on the above embodiment, the sampling data processing device is a FPGA.

[0209] It should be noted that the order of the modules and units in the above-mentioned sampling data processing device can be changed without affecting the logic.

[0210] Compared with a solution in which a data block directly generated in parallel contains data of multiple channels, so that the large data block is repeatedly read, the beneficial effect of the sampling data processing device provided by the embodiment of the present application is: the embodiment of the present application generates a target data block by using the sampling data from the same sampling channel, so that each target data block contains only the data of its own sampling channel. In this way, if it is necessary to generate an interference signal based on the data of each sampling channel, when reading the data of each sampling channel, it can be ensured that the target data block read each time only includes the data of the required sampling channel, but does not include the data of other sampling channels, so that the required data can be obtained faster, and repeated data reading can be avoided, so that a large amount of short-time sampling data can be processed more efficiently, the fluency of data reading and writing can be increased, the efficiency of sampling data processing can be improved, and resource waste can be avoided, thereby reducing costs.

[0211] The following is an introduction to an interference signal transmitting device provided in another embodiment of the present invention. The interference signal transmitting device described below and the interference signal transmitting method described above can be referenced to each other.

[0212] Please refer to Fig.15 , Fig.15 A structural diagram of an interference signal transmitting device provided for an embodiment of the present invention may include the following contents.

[0213] The target data block acquisition module 400 is used to acquire the target data block read by the above-mentioned sampling data processing method, and generate an interference signal according to the target data block.

[0214] The interference signal transmitting module 500 is used to transmit the interference signal.

[0215] It should be noted that the order of the modules and units in the above-mentioned interference signal transmitting device can be changed without affecting the logic.

[0216] The interference signal transmitting device provided by the embodiment of the present invention improves the speed of generating interference signals because the target data block is obtained by processing using the above-mentioned sampling data processing method during the whole process, and the data reading and writing fluency of the target data block obtained by the above-mentioned sampling data processing method is relatively high.

[0217] A sampling data processing system provided by another embodiment of the present invention is introduced below. The sampling data processing system described below and the sampling data processing method described above can be referred to each other.

[0218] Please refer to Fig.16 , Fig.16 A structural diagram of a sampling data processing system provided by an embodiment of the present invention may include the following contents.

[0219] The plurality of sampling channels 600 sample data in parallel, and each of the sampling channels is used to sample a radio signal and output sampled data.

[0220] The first signal processing unit 700 is used to continuously acquire the sampling data of each sampling channel in a sampling period. After the acquisition times of each sampling channel reach a set times, all the sampling data acquired by each sampling channel in the set times are used to generate a target data block in the order of sampling time. The number of bits of the target data block is consistent with the number of bits of the storage capacity corresponding to the data block in the burst transmission of the direct memory access. All the target data blocks are sequentially written in the set writing order. From all the target data blocks written to the memory, the target data blocks corresponding to one or more sampling channels are read.

[0221] The second signal processing unit 800 is used to obtain the target data block corresponding to each sampling channel, and generate an interference code according to the read target data block.

[0222] The first signal processing unit 700 is further configured to write the interference code of each sampling channel according to the address of the corresponding target data block, and read all the interference codes, wherein the interference codes are used to generate interference signals.

[0223] The sampling channel in the embodiment of the present invention may be AD. The first signal processing unit 700 in the embodiment may be FPGA. The second signal processing unit 800 in the embodiment may be a host computer. In the embodiment of the present invention, since each target data block only contains the sampling data of its own sampling channel, there is no need to repeatedly read the sampling data of other sampling channels, thus avoiding repeated data reading, thereby greatly increasing the data reading and writing fluency.

[0224] An embodiment of the present invention further provides a computer program product, including a computer program / instruction, which, when executed by a processor, implements the steps of the sampling data processing method as described above, or implements the steps of the interference signal transmission method as described above.

[0225] The computer-readable storage medium provided in an embodiment of the present invention is introduced below. The computer-readable storage medium described below and the steps of the sampling data processing method described above, or the above-mentioned interference signal transmitting method can correspond to each other.

[0226] Another embodiment of the present invention further provides a computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, the steps of the above-mentioned sampling data processing method are implemented, or the steps of the above-mentioned interference signal transmission method are implemented.

[0227] The computer-readable storage medium may include: a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk, and other media that can store program codes.

[0228] In this specification, each embodiment is described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the embodiments can be referred to each other. For the device disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, the description is relatively simple, and the relevant parts can be referred to the method part.

[0229] Professionals may further appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of the two. In order to clearly illustrate the interchangeability of hardware and software, the composition and steps of each example have been generally described in the above description according to function. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professionals and technicians may use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of the present invention.

[0230] Finally, it should be noted that, in this article, relationships such as first and second, etc. are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprises" or any other variations are intended to cover non-exclusive inclusion, so that a process, method, article or device that includes a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device.

[0231] The above is a detailed introduction to a sampling data processing method, an interference signal transmission method and related devices provided by the present invention. Specific examples are used in this article to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only used to help understand the method and core ideas of the present invention. At the same time, for those skilled in the art, according to the ideas of the present invention, there will be changes in the specific implementation methods and application scopes. In summary, the content of this specification should not be understood as limiting the present invention.

Claims

1. A sampling data processing method, characterized in that: The sampling data processing method comprises: Get the sampling data output by multiple sampling channels; Generate a target data block from the sampling data from the same sampling channel; The write operation is performed sequentially on all the target data blocks according to the set write order.

2. The sampling data processing method according to claim 1, characterized in that: Before the step of sequentially performing the writing operation on all the target data blocks according to the set writing order, the sampling data processing method further includes: The plurality of target data blocks are sorted according to the set writing order.

3. The sampling data processing method according to claim 2, characterized in that: The step of sorting the plurality of target data blocks according to a set writing order comprises: Obtaining the serial number of the sampling channel to which each target data block belongs; All the target data blocks are sorted according to the sequence numbers.

4. The sampling data processing method according to claim 2, characterized in that: The writing order is set such that the writing priority of the first target data block is higher than the writing priority of the second target data block; The sequence number of the sampling channel to which the first target data block belongs is smaller than the sequence number of the sampling channel to which the second target data block belongs.

5. The sampling data processing method according to claim 1, characterized in that: The steps of obtaining sampling data output by multiple sampling channels include: The sampling data output by all the sampling channels are acquired in parallel.

6. The sampling data processing method according to claim 1, characterized in that: The step of sequentially performing a write operation on all the target data blocks according to a set write order comprises: According to the set writing order, the plurality of target data blocks are sequentially written into the memory by direct memory access.

7. The sampling data processing method according to claim 6, characterized in that: The steps of obtaining sampling data output by multiple sampling channels include: In a sampling period, sampling data output by a plurality of sampling channels are obtained in parallel, and sampling data of each sampling channel is obtained continuously; The step of generating a target data block from the sampled data from the same sampling channel comprises: After the acquisition times of each sampling channel reaches the set times, all the sampling data acquired by each sampling channel in the set times are used to generate a target data block in the order of sampling time; wherein the number of bits of the target data block is consistent with the number of bits of the storage capacity corresponding to the data block in the burst transmission of the direct memory access.

8. The sampling data processing method according to claim 7, characterized in that: After the acquisition times of each sampling channel reaches a set number of times, the step of generating a target data block according to the sampling time sequence of the sampling data acquired by each sampling channel in the set number of times includes: For the same sampling channel, each time after acquiring new sampling data, the newly acquired sampling data is placed after the sampling data acquired last time; Determine whether the number of times the sampling data is obtained reaches the set number. If so, generate a target data block corresponding to the sampling channel based on all the sampling data previously obtained from the same sampling channel. Otherwise, continue to obtain the sampling data until the number of times the sampling data is obtained reaches the set number.

9. The sampling data processing method according to claim 7, characterized in that: The step of generating a target data block according to the sampling time sequence of the sampling data obtained by each sampling channel within a set number of times comprises: Generate a sub-target data block according to the sampling time sequence based on all the sampling data acquired by each sampling channel within a set number of times; The target data block is generated according to the sub-target data block and the check code; the check code is used to check whether the sampled data in the target data block is complete.

10. The sampling data processing method according to claim 7, characterized in that: The step of sequentially performing the write operation on all the target data blocks according to the set write order is specifically: Writing all the target data blocks into the memory in sequence according to a set writing order; After the step of sequentially performing the writing operation on all the target data blocks according to the set writing order, the sampling data processing method further includes: The target data blocks corresponding to one or more sampling channels are read from all the target data blocks written into the memory.

11. The sampling data processing method according to claim 10, characterized in that: The step of reading the target data blocks corresponding to more than one sampling channels from all the target data blocks written into the memory comprises: From all the target data blocks written in the memory, the target data blocks corresponding to each of the N sampling channels are read in sequence according to the sequence number of the sampling channels; N is not less than 1 and not greater than the total number of sampling channels.

12. The sampling data processing method according to claim 11, characterized in that: The step of reading the target data block corresponding to each of the sampling channels comprises: Determine the burst address increment according to the total number of sampling channels; Each target data block of each sampling channel is read out according to the burst address increment.

13. A method for transmitting an interference signal, characterized in that: The interference signal transmission method comprises: Acquire a target data block read by the sampling data processing method according to claim 10, and generate an interference signal according to the target data block; The interference signal is transmitted.

14. The interference signal transmitting method according to claim 13, characterized in that: The step of obtaining a target data block read by the sampling data processing method according to claim 10 and generating an interference signal according to the target data block comprises: Step 01: After obtaining a target data block corresponding to a sampling channel, an interference code corresponding to the sampling channel is generated according to the read target data block; Step 02: performing a write operation on the interference code of one of the sampling channels according to the address of the target data block corresponding to the sampling channel; Step 03: For the remaining sampling channels, follow steps 01 and 02; Step 04: Perform a read operation on the interference codes of all the sampling channels, and generate an interference signal according to the read interference codes.

15. The interference signal transmitting method according to claim 14, characterized in that: There are multiple target data blocks corresponding to the sampling channel; The step 02 comprises: Determine the burst address increment according to the total number of sampling channels; According to the increment of the burst address, the interference code is segmented and written into the address of the memory where each of the corresponding target data blocks is located.

16. The interference signal transmitting method according to claim 15, characterized in that: The step of performing a read operation on the interference codes of all the sampling channels and generating an interference signal according to the read interference codes comprises: Executing a plurality of readout cycles in sequence, in each of the readout cycles, reading a corresponding data segment of the interference code of each of the N sampling channels in sequence according to the sequence number of the sampling channel; after all the readout cycles are executed, the set of all data segments of each sampling channel is consistent with the interference code; N is not less than 1 and not greater than the total number of sampling channels; After each data segment corresponding to each sampling channel is read out, a corresponding interference signal is generated according to the read data segment.

17. The interference signal transmitting method according to claim 16, characterized in that: The total duration of all target data blocks of each sampling channel is the same as the duration of the interference code of each sampling channel.

18. The interference signal transmitting method according to claim 13, characterized in that: After the step of transmitting the interference signal, the interference signal transmitting method further includes: After the preset resampling time has passed, the target data block read by the sampling data processing method according to claim 10 and subsequent steps are re-executed.

19. A sampling data processing device, characterized in that: The sampling data processing device comprises: A sampling data acquisition module is used to acquire sampling data output by multiple sampling channels; A target data block determination module, used for generating a target data block from the sampling data from the same sampling channel; The writing module is used to perform writing operations on all the target data blocks in sequence according to a set writing order.

20. The sampling data processing device according to claim 19, characterized in that: The sampling data processing device is FPGA.

21. A jamming signal transmitting device, characterized in that: The interference signal transmitting device comprises: a target data block acquisition module, used to acquire the target data block read by the sampling data processing method according to claim 10, and generate an interference signal according to the target data block; The interference signal transmitting module is used to transmit the interference signal.

22. A sampling data processing system, characterized in that: The sampling data processing system comprises: A plurality of sampling channels are used to sample data in parallel, and each of the sampling channels is used to sample a radio signal and output the sampled data; The first signal processing unit is used to continuously acquire the sampling data of each sampling channel in a sampling period; after the acquisition times of each sampling channel reaches a set number of times, all the sampling data acquired by each sampling channel in the set number of times are used to generate a target data block in the sampling time sequence; wherein the number of bits of the target data block is consistent with the number of bits of the storage capacity corresponding to the data block in the burst transmission of the direct memory access; all the target data blocks are sequentially written in the set writing order; and the target data blocks corresponding to one or more sampling channels are read from all the target data blocks written to the memory; A second signal processing unit, configured to obtain a target data block corresponding to each sampling channel, and generate an interference code according to the obtained target data block; The first signal processing unit is further configured to write the interference code of each sampling channel according to the address of the corresponding target data block, and read all the interference codes, wherein the interference codes are used to generate interference signals.

23. A computer program product, characterized in that It includes a computer program / instruction, characterized in that when the computer program / instruction is executed by a processor, it implements the steps of the sampling data processing method as described in any one of claims 1 to 12, or implements the steps of the interference signal transmission method as described in any one of claims 13 to 18.

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