Self-aligned ion implantation MOSFET and manufacturing method

Abstract

The invention discloses a self-aligned ion implantation MOSFET and a manufacturing method thereof, and the method comprises the steps: forming a semiconductor layer with a drift region and a body region on a substrate, forming a plurality of first ion implantation regions in the body region, forming a pair of first side walls on the surface of the semiconductor layer on each first ion implantation region, and forming a pair of second side walls on the surface of the semiconductor layer on each first ion implantation region; a trench gate penetrating through the first ion implantation region is formed between each pair of first side walls, and a first ion implantation region contact trench and a second ion implantation region which are connected between two adjacent first ion implantation regions in a self-aligned manner are formed in the semiconductor layer between two adjacent pairs of first side walls; the width of the first ion implantation region can be adjusted through the distance between the outer side faces of the pair of first side walls and the width of the first ion implantation region contact groove, and the width of the second ion implantation region can be adjusted through the width of the first ion implantation region contact groove. According to the invention, photomasks can be reduced, overlay errors are eliminated, the device area is reduced, short-circuit resistance is reduced, and the device performance is improved.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor integrated circuit technology, and in particular to a self-aligned ion implantation MOSFET and a manufacturing method thereof. Background Art

[0002] Compared with planar MOSFET, trench MOSFET can provide a shorter current path between source and drain, thereby reducing on-resistance, allowing more current to flow through the switch, and significantly reducing power loss. Reducing the spacing between structures in MOSFET devices makes MOSFET devices have a smaller die area, which can further reduce the resistance per square area and increase the current density.

[0003] However, as the device area continues to shrink, the number of processing steps and the number of masks in the manufacturing process also increase, which undoubtedly increases the manufacturing cost. In addition, due to the existence of overlay error, the short-circuit resistance also increases.

[0004] On the other hand, there is often a need to adjust the size of the ion implantation area during the manufacturing process. However, due to the continuous reduction of device area and the existence of overlay errors, it will become very difficult to use a mask to adjust the size of the ion implantation area, thus affecting the reliability of the device. Summary of the invention

[0005] The purpose of the present invention is to overcome the above-mentioned defects in the prior art and provide a self-aligned ion implantation MOSFET and a manufacturing method thereof.

[0006] To achieve the above object, the technical solution of the present invention is as follows:

[0007] The present invention provides a self-aligned ion implantation MOSFET, comprising:

[0008] A semiconductor layer disposed on a substrate, wherein a body region and a drift region are sequentially disposed in the semiconductor layer from the surface toward the substrate, and a plurality of first ion implantation regions distributed along the surface of the semiconductor layer are disposed in the body region;

[0009] A pair of first sidewalls disposed on the surface of the semiconductor layer above each of the first ion implantation regions;

[0010] A trench gate disposed in the semiconductor layer between each pair of the first sidewalls and passing through a corresponding first ion implantation region;

[0011] A first ion implantation region contact groove disposed on the surface of the semiconductor layer between two adjacent pairs of the first sidewalls and self-aligned and connected to the first ion implantation region between two adjacent pairs of the first ion implantation regions;

[0012] A second ion implantation region disposed below the surface of the semiconductor layer between two adjacent pairs of the first sidewalls and self-aligned and connected between two adjacent first ion implantation regions;

[0013] Among them, along the surface direction of the semiconductor layer, the width of the first ion implantation zone is adjusted based on the distance between the outer side surfaces of a pair of the first side walls and the width of the contact groove of the first ion implantation zone, and the width of the second ion implantation zone is adjusted based on the width of the contact groove of the first ion implantation zone.

[0014] Furthermore, the first ion implantation region is used to form a source region of a first conductivity type, and the second ion implantation region is used to form a transition connection region of a second conductivity type.

[0015] Furthermore, the bottom of the trench gate also passes through the body region and is located in the drift region, and the second ion implantation region is located in the body region.

[0016] Furthermore, it also includes: a metal layer arranged on the surface of the semiconductor layer, the metal layer includes a gate metal separated between each pair of the first side walls and connected to a corresponding trench gate, and a first ion implantation area contact metal separated between two adjacent pairs of the first side walls and filled in the first ion implantation area contact groove, and an interlayer dielectric layer arranged on the surface of the metal layer.

[0017] Furthermore, the first ion implantation region contact groove is self-aligned on the surface of the semiconductor layer within adjacent side surfaces of two adjacent pairs of the first side walls, and the first ion implantation region contact metal is connected to the side surface of the first ion implantation region at least through the second ion implantation region.

[0018] The present invention also provides a method for manufacturing a self-aligned ion implantation MOSFET, comprising:

[0019] providing a substrate, and forming a semiconductor layer on a surface of the substrate;

[0020] forming a body region below the surface of the semiconductor layer, and forming a drift region in the semiconductor layer below the body region;

[0021] Forming a plurality of first hard mask layer patterns, second hard mask layer patterns contacting both sides of the first hard mask layer patterns, and a third hard mask layer pattern contacting between two of the second hard mask layer patterns on adjacent sides on the surface of the semiconductor layer;

[0022] removing the second hard mask layer pattern, and forming a first implantation window between the first hard mask layer pattern and the third hard mask layer pattern;

[0023] forming a first ion implantation region in the body region below the surface of the semiconductor layer below the first implantation window;

[0024] Forming first sidewall spacers on both sides of the first hard mask layer pattern and on both sides of the third hard mask layer pattern respectively, so as to form a pair of first sidewall spacers formed by two adjacent first sidewall spacers on the surface of the semiconductor layer above each first ion implantation region;

[0025] forming a trench gate passing through the corresponding first ion implantation region in the semiconductor layer between each pair of the first spacers;

[0026] forming a fourth hard mask layer pattern between each pair of the first sidewalls on the trench gate, and then removing the first hard mask layer pattern and the third hard mask layer pattern to form a second implantation window between two adjacent pairs of the first sidewalls;

[0027] A first ion implantation region contact groove is formed on the surface of the semiconductor layer below the second implantation window, the bottom of which is located in the body region and which is self-aligned and connected between two adjacent first ion implantation regions, and a second ion implantation region located in the body region is formed along the wall of the first ion implantation region contact groove, and then the fourth hard mask layer pattern is removed.

[0028] Further, forming the first hard mask layer pattern to the third hard mask layer pattern on the surface of the semiconductor layer specifically includes:

[0029] Using a patterning process to form a plurality of first hard mask layer patterns on the surface of the semiconductor layer;

[0030] Forming a second hard mask layer on the surface of the semiconductor layer to cover the first hard mask layer pattern, and performing back etching to form the second hard mask layer pattern that contacts the first hard mask layer pattern on both sides, and exposing the top of the first hard mask layer pattern and the surface of the semiconductor layer between the two second hard mask layer patterns on adjacent sides;

[0031] A third hard mask layer is formed on the surface of the semiconductor layer to cover the first hard mask layer pattern and the second hard mask layer pattern, and is back-etched to form the third hard mask layer pattern that contacts two second hard mask layer patterns located on adjacent sides and expose the tops of the first hard mask layer pattern and the second hard mask layer pattern.

[0032] Furthermore, by adjusting the formation thickness of the second hard mask layer and adjusting the width of the second hard mask layer pattern formed after back etching, the width of the first implantation window defined by the distance between the first hard mask layer pattern and the third hard mask layer pattern is adjusted, and by adopting a multi-directional ion implantation process, the width of the first ion implantation region is made larger than the width of the first implantation window, thereby pre-adjusting the width of the first ion implantation region formed through the first implantation window; and, by adjusting the formation width of the contact groove of the first ion implantation region, the distance between two adjacent first ion implantation regions is adjusted, thereby finally adjusting the width of the first ion implantation region serving as the source region, and adjusting the width of the second ion implantation region serving as the transition connection region formed along the wall of the contact groove of the first ion implantation region.

[0033] Further, forming the second implantation window, the first ion implantation region contact trench and the second ion implantation region specifically includes:

[0034] By back etching, the first hard mask layer pattern and the third hard mask layer pattern are removed to form the second implantation window between two adjacent pairs of the first sidewalls;

[0035] Using the fourth hard mask layer pattern and the first sidewalls on both sides thereof as a common mask, etching downward on the surface of the semiconductor layer exposed below the second implantation window to form a first ion implantation region contact groove, so that the sidewall of the first ion implantation region contact groove is connected to the side surfaces of two adjacent first ion implantation regions, and the bottom of the first ion implantation region contact groove is located in the body region;

[0036] Through the second implantation window, and by adopting a multi-directional ion implantation process, the second ion implantation region is formed along the first ion implantation region contacting the groove wall in the body region and self-aligned and connected between two adjacent first ion implantation regions;

[0037] Or include:

[0038] Removing the first hard mask layer pattern and the third hard mask layer pattern by etching back;

[0039] forming a second sidewall on the outer side of each pair of the first sidewalls, so as to form the second implantation window between two adjacent second sidewalls;

[0040] Using the fourth hard mask layer pattern and the first sidewalls and the second sidewalls on both sides thereof as a common mask, etching downwards on the surface of the semiconductor layer exposed below the second implantation window to form a first ion implantation region contact groove, so that the sidewalls of the first ion implantation region contact groove are connected to the side surfaces of two adjacent first ion implantation regions, and the bottom of the first ion implantation region contact groove is located in the body region;

[0041] Through the second implantation window and using a multi-directional ion implantation process, the second ion implantation region located in the body region and self-aligned and connected between two adjacent first ion implantation regions is formed along the first ion implantation region contacting the groove wall, and then the second sidewall is removed.

[0042] Furthermore, it also includes: filling metal layer material in the gap between the first side walls, and removing excess metal layer material on the top surface of the first side walls, forming a gate metal separated between each pair of the first side walls and connected to a corresponding trench gate, and a first ion implantation region contact metal separated between two adjacent pairs of the first side walls and filled in the first ion implantation region contact groove and connected to two adjacent first ion implantation regions through the second ion implantation region, thereby forming a metal layer located on the surface of the semiconductor layer; and forming an interlayer dielectric layer on the surface of the metal layer.

[0043] It can be seen from the above technical scheme that the present invention adopts multiple self-aligned patterning and sidewall processes (including forming the first hard mask layer pattern to the third hard mask layer pattern and the first sidewall and the second sidewall), and can reduce the mask while adjusting the width of the first implantation window and the second implantation window, so as to achieve accurate adjustment of the ion implantation range of the first ion implantation area and the second ion implantation area (i.e., the width of the first ion implantation area and the second ion implantation area), and can make the first ion implantation area contact groove self-aligned and located between two adjacent groove gates, and make the second ion implantation area self-aligned along the groove wall of the first ion implantation area contact groove and connected between two adjacent first ion implantation areas. The present invention can not only reduce the spacing between structures in the MOSFET device while reducing the mask, so that the MOSFET device has a smaller tube core area, and can further reduce the resistance per square area, and increase the current density, but also eliminate the overlay error, thereby effectively reducing the short-circuit resistance and improving the device performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] Figure 1 A schematic diagram of the structure of a self-aligned ion implantation MOSFET according to a preferred embodiment of the present invention;

[0045] Figure 2-Figure 8The present invention is a process flow chart of a method for manufacturing a self-aligned ion implantation MOSFET according to a preferred embodiment of the present invention. DETAILED DESCRIPTION

[0046] In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention. Unless otherwise defined, the technical terms or scientific terms used herein should be understood by people with general skills in the field to which the present invention belongs. "Including" and similar words used in this article mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects.

[0047] Unless otherwise specified below, the various parts of the MOSFET device can be made of materials known to those skilled in the art. Semiconductor materials may include, for example, III-V semiconductors, such as GaAs, InP, GaN, SiC, and IV semiconductors, such as Si, Ge, etc. The gate conductor may be formed of various materials that can conduct electricity, such as metal, doped polysilicon layer, or a stacked gate conductor including a metal and a doped polysilicon layer, or other conductive materials, such as TaC, TiN, TaSiN, HfSiN, TiSiN, TiCN, TaAlC, TiAlN, TaN, PtSi x , Ni3Si, Pt, Ru, W, and combinations of the above-mentioned various conductive materials. The gate dielectric (gate oxide layer) may be made of SiO2 or a material having a dielectric constant greater than SiO2, such as oxides, nitrides, oxynitrides, silicates, aluminates, titanates, etc. Furthermore, the gate dielectric may be formed not only of materials known to those skilled in the art, but also of materials to be developed in the future for use as gate dielectrics.

[0048] The first conductivity type may be one of N-type and P-type, and the second conductivity type may be the other of N-type and P-type. N-type may be formed by implanting N-type dopants (e.g., P, As, etc.) into a semiconductor material. P-type may be formed by implanting P-type dopants (e.g., B, etc.) into a semiconductor material. The above may be understood with reference to known techniques.

[0049] The specific implementation modes of the present invention will be further described in detail below in conjunction with the accompanying drawings.

[0050] refer to Figure 1A self-aligned ion implantation MOSFET of the present invention includes a substrate 10 and a semiconductor layer 18 disposed on the surface of the substrate 10 .

[0051] The semiconductor layer 18 is provided with a body region 12 and a drift region 11 (drift) in sequence from the surface of the semiconductor layer 18 to the substrate 10. That is, the body region 12 is located above the drift region 11 and below the surface of the semiconductor layer 18 away from the substrate 10. The body region 12 is provided with a plurality of independent first ion implantation regions 19 distributed along the surface of the semiconductor layer 18.

[0052] A pair of first sidewalls 15 are respectively disposed on the surface of the semiconductor layer 18 above each first ion implantation region 19. Each pair of first sidewalls 15 can be vertically disposed on the surface of the semiconductor layer 18 and spaced a certain distance apart, and the distance should ensure that the pair of first sidewalls 15 are located above the same first ion implantation region 19.

[0053] A trench gate 24 is correspondingly disposed in the semiconductor layer 18 between each pair of first spacers 15 ; the trench gate 24 passes through a first ion implantation region 19 at a corresponding position. The width of the trench gate 24 is determined by the distance between the pair of first spacers 15 .

[0054] A first ion implantation region contact groove 16 is provided on the surface of the semiconductor layer 18 between two adjacent pairs of first spacers 15 ; and the first ion implantation region contact groove 16 is connected between two adjacent first ion implantation regions 19 through self-alignment between two adjacent pairs of first spacers 15 .

[0055] A second ion implantation region 20 is also provided below the surface of the semiconductor layer 18 between two adjacent pairs of first sidewalls 15; and the second ion implantation region 20 is connected between two adjacent first ion implantation regions 19 through self-alignment between the two adjacent pairs of first sidewalls 15. That is, the second ion implantation region 20 is provided in the semiconductor layer 18 along the groove wall of the first ion implantation region contact groove 16; the first ion implantation region contact groove 16 is connected to the side surfaces of the two adjacent first ion implantation regions 19 on both sides through the side walls, and the second ion implantation region 20 is connected (intersected) to the side surfaces of the two adjacent first ion implantation regions 19 on both sides at the portion other than the side walls of the first ion implantation region contact groove 16.

[0056] Among them, along the surface direction of the semiconductor layer 18, the width of the first ion implantation region 19 is adjusted based on the distance between the outer side surfaces of a pair of first sidewalls 15 and the width of the first ion implantation region contacting the groove 16. The width of the second ion implantation region 20 is adjusted based on the width of the first ion implantation region contacting the groove 16. That is, the ion implantation range of the first ion implantation region 19 is associated with the distance between the outer side surfaces of the pair of first sidewalls 15, and the width of the first ion implantation region contacting the groove 16 is also associated with the distance between the outer side surfaces of the pair of first sidewalls 15. The width of the first ion implantation region 19 can be pre-adjusted by adjusting the distance between the outer side surfaces of the pair of first sidewalls 15, and the side of the first ion implantation region 19 can be further trimmed and fine-tuned by adjusting the width of the first ion implantation region contacting the groove 16, so that the width of the first ion implantation region 19 can be finally adjusted, thereby adjusting the width of the first ion implantation region contacting the groove 16 to adjust the width of the second ion implantation region 20 formed along the groove wall of the first ion implantation region contacting the groove 16.

[0057] In some embodiments, the first ion implantation region 19 may be used to form a source region 191 of a first conductivity type. The second ion implantation region 20 may be used to form a transition connection region 201 of a second conductivity type.

[0058] The following description is made by taking the case where the first conductivity type is N type and the second conductivity type is P type as an example.

[0059] refer to Figure 1 In some embodiments, the substrate 10 may be a heavily doped N+ type silicon substrate 10 (N+ substrate) of the first conductivity type.

[0060] The semiconductor layer 18 may be an epitaxial N-type silicon semiconductor layer 18 of the first conductivity type disposed on the surface of the substrate 10. The body region 12 may be a lightly doped P-type body region 12 (P-body) of the second conductivity type, and the drift region 11 may be an epitaxial N-type drift region 11 (N drift EPI) of the first conductivity type.

[0061] The first ion implantation region 19 is located below the surface of the semiconductor layer 18 and in the body region 12. The first ion implantation region 19 can be a heavily doped N+ type first ion implantation region 19 of the first conductivity type (a heavily doped N+ type source region 191 of the first conductivity type). The second ion implantation region 20 can be a heavily doped P+ type second ion implantation region 20 of the second conductivity type (a heavily doped P+ type transition connection region 201 of the second conductivity type).

[0062] In some embodiments, a trench gate 24 is formed in the gate trench 21. A heavily doped N+ type polysilicon gate 22 (poly 1) of the first conductivity type is disposed in the gate trench 21; a gate oxide layer 23 is disposed between the inner wall of the gate trench 21 and the polysilicon gate 22, thereby forming the trench gate 24. The polysilicon gate 22 is isolated from the first ion implantation region 19 by the gate oxide layer 23.

[0063] In some embodiments, the bottom of the trench gate 24 sequentially passes through the first ion implantation region 19 and the body region 12 and is located in the drift region 11 .

[0064] In some embodiments, the top of the trench gate 24 may protrude from the surface of the semiconductor layer 18 .

[0065] In some embodiments, the bottom of the first ion implantation region contacting the trench 16 is located in the body region 12. The second ion implantation region 20 is located in the body region 12.

[0066] In some embodiments, a metal layer is further provided on the surface of the semiconductor layer 18. The metal layer is provided with a gate metal 17 and a first ion implantation region contact metal 13, specifically including a gate metal 17 filled and separated between each pair of first sidewalls 15 and ohmically connected to a corresponding trench gate 24, and a first ion implantation region contact metal 13 filled and separated between two adjacent pairs of first sidewalls 15 and electrically connected to the second ion implantation region 20 and the first ion implantation region 19 by filling in the first ion implantation region contact groove 16. That is, the gate metal 17 in the metal layer and the first ion implantation region contact metal 13 are isolated by the first sidewall 15.

[0067] In some embodiments, the first ion implantation region contact groove 16 is self-aligned on the surface of the semiconductor layer 18 within the adjacent side surfaces of the two adjacent pairs of first spacers 15, and the first ion implantation region contact metal 13 is connected to the side surface of the first ion implantation region 19 at least through the second ion implantation region 20. Specifically, the sidewalls of the first ion implantation region contact groove 16 may correspond to the upper and lower positions of the adjacent side surfaces of the two adjacent pairs of first spacers 15, that is, the width of the first ion implantation region contact groove 16 corresponds to the distance between the adjacent side surfaces of the two adjacent pairs of first spacers 15; in this state, the first ion implantation region contact metal 13 will be connected to the side surface of the first ion implantation region 19 through the sidewalls of the first ion implantation region contact groove 16 and with the help of the second ion implantation region 20. Alternatively, the side wall of the first ion implantation region contact groove 16 can be located within the adjacent side surfaces of two adjacent pairs of first side walls 15, that is, the width of the first ion implantation region contact groove 16 is smaller than the distance between the adjacent side surfaces of two adjacent pairs of first side walls 15; in this state, the first ion implantation region contact metal 13 is further connected to the top of the first ion implantation region 19 exposed between the adjacent side surfaces of the two adjacent pairs of first side walls 15 to increase the contact area with the first ion implantation region 19.

[0068] By setting up the P+ type second ion implantation region 20 (transition connection region 201), the P type doping concentration of the body region 11 within a certain area below the bottom of the first ion implantation region contact metal 13 can be increased to improve the dynamic reliability of the formed device.

[0069] In some embodiments, an interlayer dielectric layer 14 is further provided on the surface of the metal layer. Furthermore, a metal interconnection layer (not shown) may be provided on the interlayer dielectric layer 14. The trench gate 24 may be interconnected with the metal interconnection layer through the gate metal 17 and the conductive contact hole (not shown) provided in the interlayer dielectric layer 14; the first ion implantation region 19 may be interconnected with the metal interconnection layer through the first ion implantation region contact metal 13 and the conductive contact hole provided in the interlayer dielectric layer 14. A dielectric passivation layer (not shown) may be further provided on the metal interconnection layer; a pad window connected to the metal interconnection layer may be provided on the surface of the passivation layer for forming a pad (not shown).

[0070] In some embodiments, the first spacer 15 may be formed of a dielectric material.

[0071] In some embodiments, the gate metal 17 and the first ion implantation region contact metal 13 material (metal layer material) include at least one of Au, Ag, Pt, Al, and W.

[0072] An adhesive layer (not shown) may be provided between the gate metal 17 and the top of the first spacer 15 and the trench gate 24, and between the first ion implantation region contact metal 13 and the first spacer 15 (including the portion of the top of the first ion implantation region 19 exposed between the adjacent side surfaces of two adjacent pairs of first spacers 15) and the groove wall of the first ion implantation region contact groove 16. The adhesive layer material includes at least one of Ti, TiN, and TaN.

[0073] refer to Figure 1 In some embodiments, the first ion implantation region 19 and the first ion implantation region contact groove 16 (the second ion implantation region 20) are alternately connected and arranged in a plurality along the surface of the semiconductor layer 18, and may form an array arrangement ( Figure 1 2 first ion implantation regions 19 and 3 first ion implantation region contact grooves 16 (second ion implantation regions 20) are exemplarily shown. A pair of first sidewalls 15 are provided on the surface of the semiconductor layer 18 above each first ion implantation region 19, and a gate metal 17 and a trench gate 24 are provided in the gap between each pair of first sidewalls 15; and a first ion implantation region contact metal 13 filled in the first ion implantation region contact grooves 16 is provided in the gap between any two adjacent pairs of first sidewalls 15.

[0074] It can be seen that each trench gate 24 is self-aligned and penetrates a corresponding first ion implantation region 19 through a pair of first sidewalls 15 formed above the first ion implantation region 19; the gate metal 17 is filled between the pair of first sidewalls 15 and self-aligned and connected to the trench gate 24 below to form a buried gate metal 17. The first ion implantation region contact trench 16 is self-aligned and located between two adjacent trench gates 24 through two adjacent pairs of first sidewalls 15, and each first ion implantation region contact trench 16 is self-aligned and connected to the side portions of the two first ion implantation regions 19 on both sides at the same time.

[0075] A method for manufacturing a self-aligned ion implantation MOSFET of the present invention is described in detail below through specific implementations and in conjunction with the accompanying drawings.

[0076] refer to Figure 2-Figure 8 The self-aligned ion implantation MOSFET manufacturing method of the present invention can be used to manufacture the above-mentioned Figure 1 A self-aligned ion implantation MOSFET of the present invention may include the following steps:

[0077] Step S1 : providing a substrate 10 , and forming a semiconductor layer 18 on a surface of the substrate 10 .

[0078] like Figure 2 As shown, a heavily doped N+ type silicon substrate 10 (N+ substrate) may be used, and an N-type epitaxial silicon semiconductor layer 18 may be formed on the silicon substrate 10 .

[0079] Step S2 : forming a body region 12 below the surface of the semiconductor layer 18 , and forming a drift region 11 in the semiconductor layer 18 below the body region 12 .

[0080] like Figure 2 As shown, after forming the N-type epitaxial silicon semiconductor layer 18, an ion implantation process can be used to form a lightly doped P-type body region 12 (P-body) below the surface of the semiconductor layer 18. In this way, an epitaxial N-type drift region 11 (N drift EPI) is formed in the N-type semiconductor layer 18 below the body region 12. In other words, the body region 12 is formed in the drift region 11 and is located below the surface of the semiconductor layer 18.

[0081] Step S3: forming a plurality of first hard mask layer patterns 25, second hard mask layer patterns 26 contacting both sides of the first hard mask layer patterns 25, and third hard mask layer patterns 27 contacting between two second hard mask layer patterns 26 on adjacent sides on the surface of the semiconductor layer 18.

[0082] like Figure 2 As shown, a first hard mask layer material may be deposited on the surface of the semiconductor layer 18. Then, a photoresist layer is formed on the first hard mask layer. Next, a plurality of first hard mask layer patterns 25 (HM1) are formed on the surface of the semiconductor layer 18 through photolithography and etching patterning processes. Figure 2 FIG. 2 exemplarily shows that two first hard mask layer patterns 25 are formed, but the present invention is not limited thereto. Afterwards, the photoresist remaining on the first hard mask layer patterns 25 is removed.

[0083] The first hard mask layer material may be a conventional hard mask layer material, for example, the first hard mask layer material may be one or more of silicon nitride, silicon carbide, silicon oxynitride, silicon carbonitride, and the like.

[0084] like Figure 3 As shown, a conformal CVD process can be used to form a second hard mask layer on the surface of the semiconductor layer 18 to cover the first hard mask layer pattern 25. Then, the second hard mask layer is etched back to form a second hard mask layer pattern 26 (HM2) on both sides of each first hard mask layer pattern 25, which is in contact with the side of the first hard mask layer pattern 25, and exposes the top of the first hard mask layer pattern 25 and the surface of the semiconductor layer 18 between the two second hard mask layer patterns 26 located on the adjacent sides (i.e., the two second hard mask layer patterns 26 located on the inner sides of the two adjacent first hard mask layer patterns 25).

[0085] When the second hard mask layer is deposited, the thickness during deposition can be controlled to reserve a width for subsequent deposition of the third hard mask layer.

[0086] The second hard mask layer material may be a conventional hard mask layer material, for example, one or more of silicon nitride, silicon carbide, silicon oxynitride, and silicon carbonitride.

[0087] like Figure 3 As shown, a deposition process can be used to form a third hard mask layer on the surface of the semiconductor layer 18, covering the first hard mask layer pattern 25 and the second hard mask layer pattern 26, and completely filling the gap between the two second hard mask layer patterns 26 on the adjacent sides. Then, the third hard mask layer material can be etched back to form a third hard mask layer pattern 27 (HM3) in contact with the side surface of the second hard mask layer pattern 26 between the two second hard mask layer patterns 26 on the adjacent sides, and expose the tops of the first hard mask layer pattern 25 and the second hard mask layer pattern 26.

[0088] By conformally forming a second hard mask layer on the first hard mask layer pattern 25 and back-etching to form a second hard mask layer pattern 26 on both sides of the first hard mask layer pattern 25, a third hard mask layer pattern 27 can be self-aligned between the second hard mask layer patterns 26, thereby achieving a reduction in pitch while saving one photomask.

[0089] The third hard mask layer material may be a conventional hard mask layer material, for example, the third hard mask layer material may be one or more of silicon nitride, silicon carbide, silicon oxynitride, silicon carbonitride, and the like.

[0090] Step S4 : removing the second hard mask layer pattern 26 , and forming a first implantation window 28 between the first hard mask layer pattern 25 and the third hard mask layer pattern 27 .

[0091] like Figure 4 As shown, then, the second hard mask layer pattern 26 can be removed by utilizing different etching selectivity ratios between the second hard mask layer material and the first hard mask layer material and the third hard mask layer material to expose the surface of the semiconductor layer 18 located between the first hard mask layer pattern 25 and the third hard mask layer pattern 27, thereby forming a first implantation window 28 between the first hard mask layer pattern 25 and the third hard mask layer pattern 27.

[0092] Step S5 : forming a first ion implantation region 19 in the body region 12 below the surface of the semiconductor layer 18 under the first implantation window 28 .

[0093] like Figure 4 As shown, then, through the first implantation window 28 , a multi-directional ion implantation process is adopted to form a heavily doped N+ type first ion implantation region 19 in the body region 12 below the surface of the semiconductor layer 18 below the first implantation window 28 .

[0094] For example, by adopting an inclined implantation angle in the directions around the first implantation window 28, a heavily doped N+ type first ion implantation region 19 with a width greater than the width of the first implantation window 28 can be formed in the body region 12 below the surface of the semiconductor layer 18 below the first implantation window 28 and serve as the source region 191. Figure 4 FIG. 4 exemplarily shows that two first ion implantation regions 19 (source regions 191 ) are formed, but the present invention is not limited thereto.

[0095] Step S6: First sidewall spacers 15 are formed on both sides of the first hard mask layer pattern 25 and on both sides of the third hard mask layer pattern 27 to form a pair of first sidewall spacers 15 formed by two first sidewall spacers 15 on adjacent sides on the surface of the semiconductor layer 18 above each first ion implantation region 19.

[0096] like Figure 4 As shown, next, a spacer material is deposited on the surface of the semiconductor layer 18 exposed between the first hard mask layer pattern 25 and the third hard mask layer pattern 27, and the first hard mask layer pattern 25 and the third hard mask layer pattern 27 are covered. Then, a spacer process is adopted and back-etching is performed to form a first spacer 15 (Spacer) structure on both sides of each first hard mask layer pattern 25 and each third hard mask layer pattern 27. Among them, the first spacers 15 located on two adjacent sides between the first hard mask layer pattern 25 and the third hard mask layer pattern 27 are simultaneously located on the surface of the semiconductor layer 18 above the same first ion implantation region 19, forming a pair of first spacers 15.

[0097] It can be seen that by adjusting the thickness of the second hard mask layer, the width of the second hard mask layer pattern 26 formed after back etching is adjusted to adjust the width of the first implantation window 28 defined by the distance between the first hard mask layer pattern 25 and the third hard mask layer pattern 27, and by adopting a multi-directional ion implantation process, the width of the first ion implantation region 19 is made greater than the width of the first implantation window 28, thereby achieving pre-adjustment of the width of the first ion implantation region 19 formed through the first implantation window 28. In other words, the width of the first ion implantation region 19 (the range of ion implantation) is pre-adjusted based on the distance between the outer side surfaces of a pair of first sidewalls 15.

[0098] The material of the first spacer 15 can be a conventional spacer material having different etching selectivities with the material of the first hard mask layer and the material of the third hard mask layer.

[0099] Step S7 : forming a trench gate 24 penetrating the corresponding first ion implantation region 19 in the semiconductor layer 18 between each pair of first spacers 15 .

[0100] like Figure 5As shown, then, using the first hard mask layer pattern 25 and the combined pattern of the first side walls 15 on both sides thereof and the combined pattern of the third hard mask layer pattern 27 and the first side walls 15 on both sides thereof as a common mask, etching is performed downward on the surface of the semiconductor layer 18 between a pair of first side walls 15 to form a gate trench 21 in the semiconductor layer 18 that passes through the first ion implantation region 19. Figure 5 2 shows two parallel gate trenches 21 formed through the first ion implantation region 19 , and through etching, the bottom of the gate trench 21 further passes through the body region 12 and is located in the drift region 11 below.

[0101] Then, the gate oxide layer 23 material is fully deposited on the inner wall surface of the gate trench 21 and the exposed surfaces of the first side wall 15, the first hard mask layer pattern 25, and the third hard mask layer pattern 27, and the gate electrode 22 material is further filled in the gate trench 21 within the gate oxide layer 23 material, and the gap between a pair of first side walls 15 can be filled up, so that the gate electrode 22 material covers the gate oxide layer 23 material.

[0102] Next, the gate 22 material and the gate oxide layer 23 material may be etched back to form a gate oxide layer 23 on the inner wall of the gate trench 21, and a gate 22 may be formed in the gate trench 21 within the gate oxide layer 23, thereby forming a trench gate 24. The formed gate 22 may be an N+ type polysilicon gate 22 (poly 1).

[0103] When etching back the gate 22 material and the gate oxide layer 23 material, the etching back time can be controlled so that the tops of the formed gate 22 and the gate oxide layer 23 protrude above the surface of the semiconductor layer 18 and are lower than the top of the first spacer 15 .

[0104] It can be seen that when forming the first sidewall 15, the horizontal width of the first sidewall 15 formed by back etching can be adjusted by controlling the deposition thickness of the first sidewall 15 material, so as to adjust the spacing between a pair of first sidewalls 15, that is, adjust the width of the surface of the semiconductor layer 18 exposed between a pair of first sidewalls 15, thereby achieving the adjustment of the horizontal width of the gate trench 21 formed by etching later and the horizontal width of the corresponding trench gate 24.

[0105] Step S8: forming a fourth hard mask layer pattern 29 between each pair of first spacers 15 on the trench gate 24 , then removing the first hard mask layer pattern 25 and the third hard mask layer pattern 27 to form a second implantation window 34 between two adjacent pairs of first spacers 15 .

[0106] like Figure 6As shown, then, a fourth hard mask layer can be filled between each pair of first spacers 15 on the trench gate 24 through a deposition process to cover the first spacers 15, the first hard mask layer pattern 25 and the third hard mask layer pattern 27. Then, the fourth hard mask layer is etched back to remove the redundant fourth hard mask layer on the top surface of the first spacers 15, the first hard mask layer pattern 25 and the third hard mask layer pattern 27, thereby forming a fourth hard mask layer pattern 29 (HM4) located between a pair of first spacers 15 and covering the trench gate 24.

[0107] The fourth hard mask layer material includes tetraethyl orthosilicate oxide (ie, CVD oxide using tetraethyl orthosilicate TEOS precursor, TEOS OX for short), but is not limited thereto.

[0108] like Figure 7 As shown, then, the first hard mask layer pattern 25 and the third hard mask layer pattern 27 are removed by etching back to expose the surface of the semiconductor layer 18 between the two first spacers 15 on the adjacent sides.

[0109] Then, a spacer process may be used to further form a second spacer 30 outside each pair of first spacers 15 , thereby forming a second implantation window 31 between two second spacers 30 on adjacent sides.

[0110] The second spacer 30 needs to be made of another spacer material having a different etching selectivity ratio from the first spacer 15 material.

[0111] Step S9: A first ion implantation region contact groove 16 is formed on the surface of the semiconductor layer 18 below the second implantation window 31, the bottom of which is located in the body region 12 and is self-aligned and connected between two adjacent first ion implantation regions 19, and a second ion implantation region 20 located in the body region 12 is formed along the wall of the first ion implantation region contact groove 16, and then the fourth hard mask layer pattern 29 is removed.

[0112] like Figure 7 As shown, then, using the fourth hard mask layer pattern 29 and the first side walls 15 and the second side walls 30 on both sides thereof as a common mask, a first ion implantation region contact groove 16 is etched downward on the surface of the semiconductor layer 18 exposed below the second implantation window 31 between the two second side walls 30 on the adjacent sides, so that the side walls of the formed first ion implantation region contact groove 16 are respectively connected to the side surfaces of the two adjacent first ion implantation regions 19, and the bottom of the first ion implantation region contact groove 16 is located in the body region 12 between the two adjacent first ion implantation regions 19, so that the formed first ion implantation region contact groove 16 is self-aligned with the trench gate 24 and the first ion implantation region 19 on both sides.

[0113] When forming the second sidewall 30, the deposition thickness of the material of the second sidewall 30 can be controlled to adjust the horizontal width of the second sidewall 30 formed by etching back, so as to adjust the spacing between the two second sidewalls 30 on the adjacent sides, that is, to adjust the width of the second implantation window 31, so as to adjust the width of the surface of the semiconductor layer 18 exposed between the two second sidewalls 30 on the adjacent sides, so as to achieve the adjustment of the horizontal width of the first ion implantation region contact groove 16 formed by etching later. In addition, by adjusting the horizontal width of the formed first ion implantation region contact groove 16, the distance between the two adjacent first ion implantation regions 19 can also be adjusted, so as to finally adjust the width of the first ion implantation region 19 as the source region 191. In other words, the width of the first ion implantation region 19 is determined based on the distance between the outer side surfaces of a pair of first sidewalls 15 (that is, the distance between the first hard mask pattern 29 and the third hard mask pattern 31) and the width adjustment of the first ion implantation region contact groove 16.

[0114] Then, the second ion implantation region 20 as the transition connection region 201 can be formed in the semiconductor layer 18 along the groove wall of the first ion implantation region contacting the groove 16 by multi-directional ion implantation and with the gap between the two second sidewalls 30 on the adjacent sides as the second implantation window 31. The first ion implantation region contacting the groove 16 region can be implanted with a heavily doped P+ type second ion implantation region 20 (P+imp) in a certain area of ​​the semiconductor layer 18 along the groove wall of the first ion implantation region contacting the groove 16 by adopting an inclined implantation angle in the surrounding directions of the second implantation window 31 and adopting P-type ion implantation, for example, by adopting ion implantation of boron and boron difluoride (BF2), and performing rapid thermal annealing (RTA), thereby forming a heavily doped P+ type second ion implantation region 20 (P+imp) in the body region 12 within a certain area of ​​the semiconductor layer 18 contacting the groove wall of the groove 16 along the first ion implantation region.

[0115] By forming the second sidewalls 30 on both sides of the first sidewall 15, the second ion implantation region 20 formed between the two second sidewalls 30 on the adjacent sides can be self-aligned and connected between the two adjacent first ion implantation regions 19. Thus, while adjusting the horizontal width of the second sidewalls 30 to adjust the formation width of the first ion implantation region contact groove 16, the horizontal width of the second implantation window 31 is also adjusted, thereby achieving accurate adjustment of the width of the second ion implantation region 20 as the transition connection region 201 formed along the groove wall of the first ion implantation region contact groove 16.

[0116] like Figure 8As shown, the fourth hard mask layer pattern 29 can then be removed by back-etching to expose the top of the trench gate 24. The second sidewall 30 can also be removed by back-etching to expose the first sidewall 15 and the top of the first ion implantation region 19 below the second sidewall 30. That is, the width of the first ion implantation region contact groove 16 is smaller than the distance between the inner side surfaces of the two adjacent pairs of first sidewalls 15. In this way, after removing the second sidewall 30, the first ion implantation region contact metal 13 filled subsequently can be connected to the first ion implantation region 19 through the exposed top and side of the first ion implantation region 19, increasing the contact area, thereby meeting the requirements of good source region ohmic contact and current carrying capacity, thereby further improving the device performance.

[0117] In other embodiments, the second sidewall 30 may not be formed. Instead, after the first hard mask layer pattern 25 and the third hard mask layer pattern 27 are removed by back etching, the first ion implantation region contact groove 16 is formed by etching downward on the surface of the semiconductor layer 18 exposed between two adjacent pairs of first sidewalls 15, using the fourth hard mask layer pattern 29 and the first sidewalls 15 on both sides thereof as a common mask, so that the sidewalls of the first ion implantation region contact groove 16 are in contact with the side surfaces of the two adjacent first ion implantation regions 19, and the bottom of the first ion implantation region contact groove 16 is located in the body region 12. The second implantation window 31 formed between the two adjacent pairs of first sidewalls 15 is used to form a heavily doped P+ type second ion implantation region 20 by the aforementioned method, and the fourth hard mask layer pattern 29 is removed. At this time, the width of the first ion implantation region contact groove 16 will correspond to the distance between the inner side surfaces of the two adjacent pairs of first sidewalls 15, and defines the minimum width of the first ion implantation region 19 finally formed. When this method is used, the sizes of the first hard mask layer pattern 25 and the third hard mask layer pattern 27 need to be controlled respectively, so the process requirements are relatively strict.

[0118] Afterwards, the following steps may be further included:

[0119] Step S10: forming a metal layer on the surface of the semiconductor layer 18; and forming an interlayer dielectric layer on the surface of the metal layer.

[0120] like Figure 8As shown, an adhesive layer (not shown) can be deposited on the surface of each first sidewall 15 and the top surface of the exposed trench gate 24, and the surface of the semiconductor layer 18 exposed between two adjacent pairs of first sidewalls 15 through a deposition process, and a metal layer material is filled in the gaps between the first sidewalls on the adhesive layer to fill the gaps between the first sidewalls 15. Then, by etching back or chemical mechanical polishing (CMP) the metal layer material and the adhesive layer, the excess metal layer material on the top surface of the first sidewall 15 is removed to form a gate metal 17 separated between each pair of first sidewalls 15 and connected to a corresponding trench gate 24, and a first ion implantation region contact metal 13 separated between two adjacent pairs of first sidewalls 15 and filled in the first ion implantation region contact trench 16 and connected to two adjacent first ion implantation regions 19 through the second ion implantation region 20, thereby forming a metal layer on the surface of the semiconductor layer 18.

[0121] Finally, an interlayer dielectric layer 14 (ILD) can be formed on the top surface of the first spacer 15, the gate metal 17 and the first ion implantation region contact metal 13 (ie, the top surface of the metal layer) by a deposition process. The interlayer dielectric layer 14 can be made of conventional interlayer dielectric materials.

[0122] In addition, a conductive contact hole whose bottom is respectively connected to the gate metal 17 and the first ion implantation region contact metal 13 may be further formed in the interlayer dielectric layer 14, a metal interconnection layer connected to the top of the conductive contact hole may be formed on the interlayer dielectric layer 14, a dielectric passivation layer may be formed on the metal interconnection layer, and a pad connected to the metal interconnection layer may be formed on the surface of the passivation layer, which will not be described in detail. It should be noted that by forming a gate metal 17 connected to the trench gate 24 on the trench gate 24, the polysilicon gate 22 in the trench gate 24 can be connected to the conductive contact hole (for example, a tungsten contact hole) through the gate metal 17, so that the voltage conducted from the conductive contact hole can be reliably conducted to the trench gate 24 through the gate metal 17, thereby effectively reducing the contact resistance between the polysilicon gate 22 and the conductive contact hole, and improving the reliability of voltage conduction between the conductive contact hole and the trench gate 24, thereby accelerating the conduction speed, that is, increasing the switching frequency.

[0123] In summary, the present invention adopts multiple self-aligned patterning and sidewall processes including forming the first hard mask layer pattern 25 to the fourth hard mask layer pattern 29 and the first sidewall 15 and the second sidewall 30, and can reduce the mask while adjusting the width of the formed first implantation window 28 and the second implantation window 31, so as to achieve accurate adjustment of the ion implantation range of the first ion implantation area 19 and the second ion implantation area 20 (i.e., the width of the first ion implantation area 19 and the second ion implantation area 20), and can make the first ion implantation area contact groove 16 self-aligned and located between two adjacent trench gates 24, and make the second ion implantation area 20 self-aligned and connected to the adjacent two first ion implantation areas 19 along the groove wall of the first ion implantation area contact groove 16. The present invention can not only reduce the spacing between structures in the MOSFET device while reducing the mask, so that the MOSFET device has a smaller tube core area, can further reduce the resistance per square area, and increase the current density, but also eliminate the overlay error, thereby effectively reducing the short-circuit resistance and improving the device performance.

[0124] Although the embodiments of the present invention are described in detail above, it is obvious to those skilled in the art that various modifications and variations can be made to these embodiments. However, it should be understood that such modifications and variations are within the scope and spirit of the present invention as described in the claims. Moreover, the present invention described herein may have other embodiments and may be implemented or realized in a variety of ways.

Claims

1. A self-aligned ion implantation MOSFET, characterized in that: include: A semiconductor layer disposed on a substrate, wherein a body region and a drift region are sequentially disposed in the semiconductor layer from the surface toward the substrate, and a plurality of first ion implantation regions distributed along the surface of the semiconductor layer are disposed in the body region; A pair of first sidewalls disposed on the surface of the semiconductor layer above each of the first ion implantation regions; A trench gate disposed in the semiconductor layer between each pair of the first sidewalls and passing through a corresponding first ion implantation region; A first ion implantation region contact groove disposed on the surface of the semiconductor layer between two adjacent pairs of the first sidewalls and self-aligned and connected to the first ion implantation region between two adjacent pairs of the first ion implantation regions; A second ion implantation region disposed below the surface of the semiconductor layer between two adjacent pairs of the first sidewalls and self-aligned and connected between two adjacent first ion implantation regions; Among them, along the surface direction of the semiconductor layer, the width of the first ion implantation zone is adjusted based on the distance between the outer side surfaces of a pair of the first side walls and the width of the contact groove of the first ion implantation zone, and the width of the second ion implantation zone is adjusted based on the width of the contact groove of the first ion implantation zone.

2. The self-aligned ion implantation MOSFET according to claim 1, characterized in that: The first ion implantation region is used to form a source region of a first conductivity type, and the second ion implantation region is used to form a transition connection region of a second conductivity type.

3. The self-aligned ion implantation MOSFET according to claim 1, characterized in that: The bottom of the trench gate also passes through the body region and is located in the drift region, and the second ion implantation region is located in the body region.

4. The self-aligned ion implantation MOSFET according to claim 1, characterized in that: Also includes: A metal layer is arranged on the surface of the semiconductor layer, and the metal layer includes a gate metal separated between each pair of the first side walls and connected to a corresponding trench gate, a first ion implantation area contact metal separated between two adjacent pairs of the first side walls and filled in the first ion implantation area contact groove, and an interlayer dielectric layer is arranged on the surface of the metal layer.

5. The self-aligned ion implantation MOSFET according to claim 4, characterized in that: The first ion implantation region contact groove is self-aligned and located on the surface of the semiconductor layer within adjacent side surfaces of two adjacent pairs of the first sidewalls, and the first ion implantation region contact metal is connected to the side surface of the first ion implantation region at least through the second ion implantation region.

6. A method for manufacturing a self-aligned ion implantation MOSFET, characterized in that: include: providing a substrate, and forming a semiconductor layer on a surface of the substrate; forming a body region below the surface of the semiconductor layer, and forming a drift region in the semiconductor layer below the body region; Forming a plurality of first hard mask layer patterns, second hard mask layer patterns contacting both sides of the first hard mask layer patterns, and a third hard mask layer pattern contacting between two of the second hard mask layer patterns on adjacent sides on the surface of the semiconductor layer; removing the second hard mask layer pattern, and forming a first implantation window between the first hard mask layer pattern and the third hard mask layer pattern; forming a first ion implantation region in the body region below the surface of the semiconductor layer below the first implantation window; Forming first sidewall spacers on both sides of the first hard mask layer pattern and on both sides of the third hard mask layer pattern respectively, so as to form a pair of first sidewall spacers formed by two adjacent first sidewall spacers on the surface of the semiconductor layer above each first ion implantation region; forming a trench gate passing through the corresponding first ion implantation region in the semiconductor layer between each pair of the first spacers; forming a fourth hard mask layer pattern between each pair of the first sidewalls on the trench gate, and then removing the first hard mask layer pattern and the third hard mask layer pattern to form a second implantation window between two adjacent pairs of the first sidewalls; A first ion implantation region contact groove is formed on the surface of the semiconductor layer below the second implantation window, the bottom of which is located in the body region and which is self-aligned and connected between two adjacent first ion implantation regions, and a second ion implantation region located in the body region is formed along the wall of the first ion implantation region contact groove, and then the fourth hard mask layer pattern is removed.

7. The method for manufacturing a self-aligned ion implantation MOSFET according to claim 6, characterized in that: Forming the first hard mask layer pattern to the third hard mask layer pattern on the surface of the semiconductor layer specifically includes: Using a patterning process to form a plurality of first hard mask layer patterns on the surface of the semiconductor layer; Forming a second hard mask layer on the surface of the semiconductor layer to cover the first hard mask layer pattern, and performing back etching to form the second hard mask layer pattern that contacts the first hard mask layer pattern on both sides, and exposing the top of the first hard mask layer pattern and the surface of the semiconductor layer between the two second hard mask layer patterns on adjacent sides; A third hard mask layer is formed on the surface of the semiconductor layer to cover the first hard mask layer pattern and the second hard mask layer pattern, and is back-etched to form the third hard mask layer pattern that contacts two second hard mask layer patterns located on adjacent sides and expose the tops of the first hard mask layer pattern and the second hard mask layer pattern.

8. The method for manufacturing a self-aligned ion implantation MOSFET according to claim 7, characterized in that: By adjusting the formation thickness of the second hard mask layer and adjusting the width of the second hard mask layer pattern formed after back etching, the width of the first implantation window defined by the distance between the first hard mask layer pattern and the third hard mask layer pattern is adjusted, and by adopting a multi-directional ion implantation process, the width of the first ion implantation region is made larger than the width of the first implantation window, thereby pre-adjusting the width of the first ion implantation region formed through the first implantation window; and, by adjusting the formation width of the contact groove of the first ion implantation region, the distance between two adjacent first ion implantation regions is adjusted, thereby finally adjusting the width of the first ion implantation region serving as the source region, and adjusting the width of the second ion implantation region serving as the transition connection region formed along the groove wall of the contact groove of the first ion implantation region.

9. The method for manufacturing a self-aligned ion implantation MOSFET according to claim 6, characterized in that: Forming the second implantation window, the first ion implantation region contact trench and the second ion implantation region specifically includes: By back etching, the first hard mask layer pattern and the third hard mask layer pattern are removed to form the second implantation window between two adjacent pairs of the first sidewalls; Using the fourth hard mask layer pattern and the first sidewalls on both sides thereof as a common mask, etching downward on the surface of the semiconductor layer exposed below the second implantation window to form a first ion implantation region contact groove, so that the sidewall of the first ion implantation region contact groove is connected to the side surfaces of two adjacent first ion implantation regions, and the bottom of the first ion implantation region contact groove is located in the body region; Through the second implantation window, and by adopting a multi-directional ion implantation process, the second ion implantation region is formed along the first ion implantation region contacting the groove wall in the body region and self-aligned and connected between two adjacent first ion implantation regions; Or include: Removing the first hard mask layer pattern and the third hard mask layer pattern by etching back; forming a second sidewall on the outer side of each pair of the first sidewalls, so as to form the second implantation window between two adjacent second sidewalls; Using the fourth hard mask layer pattern and the first sidewalls and the second sidewalls on both sides thereof as a common mask, etching downwards on the surface of the semiconductor layer exposed below the second implantation window to form a first ion implantation region contact groove, so that the sidewalls of the first ion implantation region contact groove are connected to the side surfaces of two adjacent first ion implantation regions, and the bottom of the first ion implantation region contact groove is located in the body region; Through the second implantation window and using a multi-directional ion implantation process, the second ion implantation region located in the body region and self-aligned and connected between two adjacent first ion implantation regions is formed along the first ion implantation region contacting the groove wall, and then the second sidewall is removed.

10. The method for manufacturing a self-aligned ion implantation MOSFET according to claim 6, characterized in that: Also includes: Metal layer material is filled in the gap between the first side walls, and excess metal layer material on the top surface of the first side walls is removed to form a gate metal separated between each pair of the first side walls and connected to a corresponding trench gate, and a first ion implantation region contact metal separated between two adjacent pairs of the first side walls and filled in the first ion implantation region contact groove and connected to two adjacent first ion implantation regions through the second ion implantation region, thereby forming a metal layer located on the surface of the semiconductor layer; and an interlayer dielectric layer is formed on the surface of the metal layer.

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