Capacitor structure manufacturing method, capacitor structure, chip and circuit

Abstract

The invention provides a capacitor structure manufacturing method, a capacitor structure, a chip and a circuit, and relates to the technical field of semiconductors. The manufacturing method comprises the steps that a substrate is provided, and a first electrode layer, an initial dielectric layer and an etching displacement layer with an alignment window are sequentially formed on the upper surface of the substrate; the width of the alignment window is equal to that of the capacitor structure; taking the etching displacement layer as a barrier layer, and forming a second electrode layer by using the self-alignment effect of the alignment window; forming an intermediate dielectric layer using the initial dielectric layer; the middle dielectric layer is of a convex structure with an upper step and a lower step, and the width of the upper step is equal to that of the capacitor structure; and forming a dielectric layer, and forming a first conductive structure and a second conductive structure. According to the invention, the local loss of the dielectric layer can be reduced, and the performance and stability of the capacitor structure are ensured.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a capacitor structure manufacturing method, a capacitor structure, a chip and a circuit. Background Art

[0002] With the rapid development of integrated circuit technology, traditional capacitor devices can no longer meet the requirements of some circuits such as radio frequency circuits. Metal-insulator-metal (MIM) capacitors are a new type of capacitors that have replaced traditional capacitors. With the trend of shrinking device feature sizes and increasing device integration, MIM capacitors have been increasingly widely used due to their higher capacitance density, smaller capacitance voltage coefficient and lower leakage current.

[0003] A capacitor is a device that uses a layer of insulating medium to separate two adjacent conductors. When pressure is applied to the two plates, the capacitor will store charge. There are many types of capacitors, and the parasitic resistance requirements of metal capacitors are different for different application needs. When metal capacitors are used to store charge in charge pumps, the capacitors need to have a higher breakdown voltage, and at the same time, the time-dependent dielectric breakdown (TDDB) voltage of the metal capacitors is required to be higher. However, the performance of existing capacitors still needs to be improved. Summary of the invention

[0004] In view of the technical problem that the performance of capacitors in the prior art needs to be improved, the present invention provides a capacitor structure manufacturing method, a capacitor structure, a chip and a circuit. The capacitor structure manufacturing method can reduce damage to the dielectric layer, thereby avoiding the problem of dielectric layer depression, ensuring that the thickness of the dielectric layer between the first electrode layer and the second electrode layer is consistent with the thickness of the dielectric layer edge, thereby improving the breakdown voltage of the capacitor structure, expanding the application range, reducing the local loss of the dielectric layer, improving the energy storage efficiency and life of the capacitor structure, and ensuring the performance and stability of the capacitor structure.

[0005] To achieve the above-mentioned purpose, the first aspect of the present invention provides a method for manufacturing a capacitor structure, which comprises: providing a substrate, and sequentially forming a first electrode layer, an initial dielectric layer and an etched replacement layer with an alignment window on the upper surface of the substrate; wherein the width of the alignment window is equal to the width of the capacitor structure; using the etched replacement layer as a barrier layer, and utilizing the self-alignment effect of the alignment window to form a second electrode layer; utilizing the initial dielectric layer to form an intermediate dielectric layer; wherein the intermediate dielectric layer is a convex-shaped configuration with an upper step and a lower step, and the width of the upper step is equal to the width of the capacitor structure; forming a dielectric layer, and forming a first conductive structure and a second conductive structure; wherein the first conductive structure extends downward from the upper surface of the dielectric layer and contacts the first electrode layer, and the second conductive structure extends downward from the upper surface of the dielectric layer and contacts the second electrode layer.

[0006] Furthermore, an etching substitute layer with an alignment window is formed by the following method: forming an initial etching substitute layer and a photoresist layer on the upper surface of the initial dielectric layer; forming an etching window on the photoresist layer using an exposure and development process; and etching the initial etching substitute layer through the etching window to form an etching substitute layer with an alignment window.

[0007] Furthermore, the etching replacement layer is used as a barrier layer, and the self-alignment effect of the alignment window is utilized to form a second electrode layer, comprising: forming a replacement dielectric layer in the alignment window; forming the second electrode layer on the upper surface of the replacement dielectric layer; wherein the width of the second electrode layer is equal to the width of the alignment window.

[0008] Furthermore, the forming of the replacement dielectric layer in the alignment window includes: depositing dielectric material on the upper surface of the etched replacement layer and filling the alignment window with the dielectric material to form a dielectric material layer; removing the dielectric material on the upper surface of the etched replacement layer and retaining the dielectric material in the alignment window to form the replacement dielectric layer.

[0009] Furthermore, forming the second electrode layer on the upper surface of the replacement dielectric layer includes: forming an initial electrode layer on the upper surface of the etched replacement layer and the replacement dielectric layer; removing the initial electrode layer on the upper surface of the etched replacement layer, and retaining the initial electrode layer on the upper surface of the replacement dielectric layer as the second electrode layer.

[0010] Furthermore, the forming of the intermediate dielectric layer by using the initial dielectric layer includes: using the initial dielectric layer and the supplementary dielectric layer in the alignment window as the intermediate dielectric layer.

[0011] Furthermore, under the same etching conditions, the etching rate of the substitution layer is greater than the etching rate of the supplementary dielectric layer.

[0012] Furthermore, the etching replacement layer is used as a barrier layer and the self-alignment effect of the alignment window is utilized to form a second electrode layer, including: depositing electrode material on the surface of the etching replacement layer and filling the alignment window with the electrode material to form an initial electrode layer; and removing the electrode material on the upper surface of the etching replacement layer to form the second electrode layer.

[0013] Furthermore, the forming of the intermediate dielectric layer using the initial dielectric layer includes: using a dry etching process to remove the etching replacement layer to expose the initial dielectric layer not covered by the second electrode layer; using the second electrode layer as a mask to remove the portion of the initial dielectric layer not covered by the second electrode layer to form the intermediate dielectric layer.

[0014] Furthermore, under the same etching conditions, the etching rate of the replacement layer is greater than the etching rate of the initial dielectric layer.

[0015] Furthermore, under the same etching conditions, the etching rate of the second electrode layer is greater than the etching rate of the etching replacement layer.

[0016] Furthermore, the etching replacement layer is made of silicon nitride or silicon carbonitride material.

[0017] Furthermore, the initial dielectric layer is made of silicon oxide or silicon oxynitride.

[0018] A second aspect of the present invention provides a capacitor structure, wherein the capacitor structure is formed by the capacitor structure manufacturing method described above.

[0019] A third aspect of the present invention provides a chip, which includes the capacitor structure described above.

[0020] A fourth aspect of the present invention provides a circuit, which includes the capacitor structure described above.

[0021] Through the technical solution provided by the present invention, the present invention has at least the following technical effects:

[0022] The capacitor structure manufacturing method of the present invention first forms a first electrode layer, an initial dielectric layer and an etched replacement layer with an alignment window on the upper surface of the substrate, and the width of the alignment window is equal to the width of the capacitor structure. The etched replacement layer is used as a barrier layer, and the second electrode layer is formed by the self-alignment effect of the alignment window. The initial dielectric layer is used to form an intermediate dielectric layer, and the intermediate dielectric layer is a convex-shaped configuration with an upper step and a lower step, and the width of the upper step is equal to the width of the capacitor structure. Finally, a dielectric layer is formed, and a first conductive structure and a second conductive structure are formed on the protective dielectric layer. Through the present invention, it is possible to avoid damage to the dielectric layer, thereby avoiding the problem of dielectric layer depression, ensuring that the thickness of the dielectric layer between the first electrode layer and the second electrode layer is consistent with the thickness of the edge of the dielectric layer, thereby improving the breakdown voltage of the capacitor structure, expanding the scope of application, reducing the local loss of the dielectric layer, improving the energy storage efficiency and life of the capacitor structure, and ensuring the performance and stability of the capacitor structure.

[0023] Other features and advantages of the present invention will be described in detail in the following detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] The accompanying drawings are used to provide a further understanding of the embodiments of the present invention and constitute a part of the specification. Together with the following specific embodiments, they are used to explain the embodiments of the present invention, but do not constitute a limitation on the embodiments of the present invention. In the accompanying drawings:

[0025] Figure 1 A schematic diagram of the structure of an initial second electrode layer formed in a capacitor structure manufacturing method in the prior art;

[0026] Figure 2 A schematic diagram of the structure of a second electrode layer formed in a capacitor structure manufacturing method in the prior art;

[0027] Figure 3 A schematic diagram of the structure of a dielectric layer formed in a capacitor structure manufacturing method in the prior art;

[0028] Figure 4 A schematic diagram of a capacitor structure formed in a capacitor structure manufacturing method in the prior art;

[0029] Figure 5 A schematic structural diagram of a substrate formed in an embodiment of a method for manufacturing a capacitor structure provided in an embodiment of the present invention;

[0030] Figure 6 A schematic diagram of the structure of a first electrode layer, an initial dielectric layer, an etched replacement layer and an alignment window formed in an embodiment of a method for manufacturing a capacitor structure provided in an embodiment of the present invention;

[0031] Figure 7A schematic structural diagram of a dielectric material layer formed in an embodiment of a method for manufacturing a capacitor structure provided in an embodiment of the present invention;

[0032] Figure 8 A schematic diagram of the structure of a supplementary dielectric layer formed in an embodiment of a method for manufacturing a capacitor structure provided in an embodiment of the present invention;

[0033] Fig. 9 A schematic diagram of the structure of an initial electrode layer formed in an embodiment of a method for manufacturing a capacitor structure provided in an embodiment of the present invention;

[0034] Fig.10 A schematic diagram of a second electrode layer formed in an embodiment of a method for manufacturing a capacitor structure provided in an embodiment of the present invention;

[0035] Fig.11 A schematic diagram of a capacitor structure formed in an embodiment of a capacitor structure manufacturing method provided in an embodiment of the present invention;

[0036] Fig.12 A schematic diagram of a substrate, a first electrode layer and an initial dielectric layer formed in another embodiment of the method for manufacturing a capacitor structure provided in an embodiment of the present invention;

[0037] Fig.13 A schematic diagram of an initial etching replacement layer formed in another embodiment of the method for manufacturing a capacitor structure provided in an embodiment of the present invention;

[0038] Fig.14 A schematic diagram of an alignment window formed in another embodiment of the method for manufacturing a capacitor structure provided in an embodiment of the present invention;

[0039] Fig.15 A schematic diagram of an initial electrode layer formed in another embodiment of the method for manufacturing a capacitor structure provided in an embodiment of the present invention;

[0040] Fig.16 A schematic diagram of a second electrode formed in another embodiment of the method for manufacturing a capacitor structure provided in an embodiment of the present invention;

[0041] Fig.17 A schematic diagram of another embodiment of the capacitor structure manufacturing method provided by the embodiment of the present invention after removing the etching replacement layer;

[0042] Fig.18 A schematic diagram of an intermediate dielectric layer formed in another embodiment of the method for manufacturing a capacitor structure provided in an embodiment of the present invention;

[0043] Fig.19 A schematic diagram of a capacitor structure formed in another embodiment of the capacitor structure manufacturing method provided in an embodiment of the present invention;

[0044] Fig. 20A flowchart of a method for manufacturing a capacitor structure provided by an embodiment of the present invention.

[0045] Description of Reference Numerals

[0046] 100-substrate; 101-first electrode layer; 102-dielectric layer; 103-initial second electrode layer; 104-second electrode layer; 105-dielectric layer; 106-first conductive structure; 107-second conductive structure; 200-substrate; 201-first electrode layer; 202-initial dielectric layer; 203-etching replacement layer; 204-alignment window; 205-dielectric material layer; 206-replacement dielectric layer; 207-initial electrode layer; 20 8-second electrode layer; 209-dielectric layer; 210-first conductive structure; 211-second conductive structure; 300-substrate; 301-first electrode layer; 302-initial dielectric layer; 303-initial etching substitute layer; 304-etching substitute layer; 305-alignment window; 306-initial electrode layer; 307-second electrode layer; 308-intermediate dielectric layer; 309-dielectric layer; 310-first conductive structure; 311-second conductive structure. DETAILED DESCRIPTION

[0047] The specific implementation of the embodiment of the present invention is described in detail below in conjunction with the accompanying drawings. It should be understood that the specific implementation described here is only used to illustrate and explain the embodiment of the present invention, and is not used to limit the embodiment of the present invention.

[0048] It should be noted that, in the absence of conflict, the embodiments of the present invention and the features in the embodiments may be combined with each other.

[0049] In the present invention, unless otherwise specified, directional words such as "up, down, top, bottom" are usually used with reference to the directions shown in the drawings or are used to describe the relative positional relationships of components in the vertical, perpendicular or gravity direction.

[0050] As the background technology, the performance of the existing capacitor structure is poor.

[0051] Please refer to Figure 1 , providing a substrate 100; forming an oxide layer 101 on the surface of the substrate 100; forming a patterned layer 103 on the surface of the oxide layer 101; using the patterned layer 103 as a mask, etching the oxide layer 101 and a partial thickness of the substrate 100 to form a capacitor structure 102 in the substrate 100.

[0052] However, during the formation of the above capacitor structure, the capacitor structure 102 is usually etched by plasma dry etching. Due to the directionality of plasma etching, the etching ability of the groove sidewall is weak, and the groove sidewall is tilted. Since the capacitor structure 102 is deep, as the etching depth and etching time increase, the gap between the bottom dimension d2 (Bottom CD) and the top dimension d1 (Top CD) of the capacitor structure 102 becomes larger and larger, thereby reducing the quality of the capacitor structure finally formed.

[0053] On this basis, the present invention provides a method for manufacturing a capacitor structure, providing a substrate, a first electrode layer, an initial dielectric layer and an etching replacement layer with an alignment window, wherein the width of the alignment window is equal to the width of the capacitor structure. The etching replacement layer is used as a barrier layer, and the second electrode layer is formed by the self-alignment effect of the alignment window, the etching replacement layer is removed, and the initial dielectric layer is used to form an intermediate dielectric layer, wherein the intermediate dielectric layer is a convex-shaped configuration having an upper step and a lower step, and the width of the upper step is equal to the width of the capacitor structure. When etching the second electrode, the dielectric layer is replaced by the etching replacement layer, and the dielectric layer will not be directly etched, so that damage to the dielectric layer can be avoided, thereby avoiding the problem of dielectric layer depression, and ensuring that the thickness of the dielectric layer between the first electrode layer and the second electrode layer is consistent with the thickness of the edge of the dielectric layer, thereby improving the breakdown voltage of the capacitor structure, expanding the scope of application, reducing the local loss of the dielectric layer, improving the energy storage efficiency and life of the capacitor structure, and ensuring the performance and stability of the capacitor structure.

[0054] The present invention will be described in detail below with reference to the accompanying drawings and in conjunction with embodiments.

[0055] Embodiment 1

[0056] Please refer to Fig. 20 According to a first aspect of an embodiment of the present invention, there is provided a method for manufacturing a capacitor structure, the method comprising:

[0057] Step S101: providing a substrate 200, and sequentially forming a first electrode layer 201, an initial dielectric layer 202, and an etched replacement layer 203 having an alignment window 204 on the upper surface of the substrate 200; wherein the width of the alignment window 204 is equal to the width of the capacitor structure;

[0058] Step S102: using the etching replacement layer 203 as a barrier layer and utilizing the self-alignment effect of the alignment window 204 to form a second electrode layer 208;

[0059] Step S103: forming an intermediate dielectric layer using the initial dielectric layer 202; wherein the intermediate dielectric layer is in a convex shape with an upper step and a lower step, and the width of the upper step is equal to the width of the capacitor structure;

[0060] Step S104: forming a dielectric layer 209 and forming a first conductive structure 210 and a second conductive structure 211; wherein the first conductive structure 210 extends downward from the upper surface of the dielectric layer 209 and contacts the first electrode layer 201, and the second conductive structure 211 extends downward from the upper surface of the dielectric layer 209 and contacts the second electrode layer 208.

[0061] Specifically, step S101 is first performed: providing a substrate 200, and sequentially forming a first electrode layer 201, an initial dielectric layer 202, and an etched replacement layer 203 having an alignment window 204 on the upper surface of the substrate 200; wherein the width of the alignment window 204 is equal to the width of the capacitor structure.

[0062] Furthermore, the etching replacement layer 203 having the alignment window 204 is formed by the following method: forming an initial etching replacement layer 203 and a photoresist layer on the upper surface of the initial dielectric layer 202; forming an etching window on the photoresist layer by using exposure and development processes; and etching the initial etching replacement layer 203 through the etching window to form the etching replacement layer 203 having the alignment window 204.

[0063] Furthermore, the etching replacement layer 203 is made of silicon nitride or silicon carbonitride material.

[0064] Furthermore, the initial dielectric layer 202 is made of silicon oxide or silicon oxynitride.

[0065] Specifically, in the embodiment of the present invention, the following is provided: Figure 5 The substrate 200 shown in the figure is made of silicon. In other embodiments, the substrate 200 may be made of germanium, silicon germanium, silicon carbide, gallium arsenide or indium gallium. In other embodiments, the substrate may be a silicon-on-insulator substrate or a germanium-on-insulator substrate. Figure 6 The first electrode layer 201, the initial dielectric layer 202, the initial etching replacement layer 203 and the photoresist layer are shown.

[0066] In this embodiment, the material of the first electrode layer 201 is a copper-aluminum alloy with a thickness between 1000 angstroms and 100,000 angstroms. In other embodiments, the material of the first electrode layer 201 also includes one or more of TiN, TaN, copper, tungsten, nickel, chromium and titanium. In this embodiment, the formation process of the first electrode layer 201 includes a physical vapor deposition process. In other embodiments, the formation process of the first electrode layer 201 may also include one or more of a chemical vapor deposition process, chemical plating and an atomic layer deposition process.

[0067] In this embodiment, the material of the initial dielectric layer 202 is silicon oxide or silicon oxynitride, and the formation process of the initial dielectric layer 202 includes an atomic layer deposition process, in which an organic gas containing Si and O is used, the temperature is between 80° C. and 300° C., the pressure is between 5 mtorr and 20 torr, and the number of processes is between 5 and 100. In other embodiments, the formation process of the initial dielectric layer 202 may also include physical vapor deposition or chemical vapor deposition.

[0068] Then, the photoresist layer is exposed and developed to form an etching window, and the initial etching replacement layer 203 is etched through the etching window to form an etching replacement layer 203 with an alignment window 204. The thickness of the etching replacement layer 203 is between 300 angstroms and 800 angstroms. The material of the etching replacement layer 203 is different from that of the initial dielectric layer 202, and the material of the etching replacement layer 203 includes silicon nitride or silicon carbonitride.

[0069] Then, step S102 is performed: the etching replacement layer 203 is used as a barrier layer, and the self-alignment effect of the alignment window 204 is utilized to form a second electrode layer 208 .

[0070] Furthermore, the etching replacement layer 203 is used as a blocking layer, and the self-alignment effect of the alignment window 204 is utilized to form the second electrode layer 208, including: forming a replacement dielectric layer 206 in the alignment window 204; forming the second electrode layer 208 on the upper surface of the replacement dielectric layer 206; wherein the width of the second electrode layer 208 is equal to the width of the alignment window 204.

[0071] Furthermore, the formation of the replacement dielectric layer 206 in the alignment window 204 includes: depositing a dielectric material on the upper surface of the etched replacement layer 203, and filling the alignment window 204 with the dielectric material to form a dielectric material layer 205; removing the dielectric material on the upper surface of the etched replacement layer 203, retaining the dielectric material in the alignment window 204, and forming the replacement dielectric layer 206.

[0072] Furthermore, the forming of the second electrode layer 208 on the upper surface of the replacement dielectric layer 206 includes: forming an initial electrode layer 207 on the upper surfaces of the etched replacement layer 203 and the replacement dielectric layer 206; removing the initial electrode layer 207 on the upper surface of the etched replacement layer 203, and retaining the initial electrode layer 207 on the upper surface of the replacement dielectric layer 206 as the second electrode layer 208.

[0073] Furthermore, under the same etching conditions, the etching rate of the second electrode layer 208 is greater than the etching rate of the substitution layer 203 .

[0074] Specifically, in the embodiment of the present invention, a dielectric material is deposited on the upper surface of the etched replacement layer 203, and the dielectric material is filled into the alignment window 204 to form a dielectric material. Figure 7 The dielectric material layer 205 is shown in FIG. In this embodiment, the dielectric material layer 205 is formed by an atomic layer deposition process. In other embodiments, the dielectric material layer 205 may be formed by a chemical vapor deposition process or a physical vapor deposition process. The dielectric material layer 205 is planarized, and the dielectric material on the upper surface of the etched replacement layer 203 is removed, and the dielectric material in the alignment window 204 is retained to form a dielectric layer 205 as shown in FIG. Figure 8 The replacement dielectric layer 206 is shown. The material of the replacement dielectric layer 206 is the same as or different from the material of the initial dielectric layer 202 , and the material of the replacement dielectric layer 206 is different from the material of the etched replacement layer 203 .

[0075] The method for planarizing the dielectric material layer 205 is a chemical mechanical polishing method. Since the chemical corrosion efficiency of the dielectric material layer 205 is different from the chemical corrosion efficiency of the etching substitute layer 203, in the process of planarizing and removing excess dielectric material layer 205 to expose the etching substitute layer 203, the surface of the etching substitute layer 203 can be ensured to be undamaged, thereby ensuring the quality of the etching substitute layer 203, thereby preparing for the formation of a high-quality capacitor structure.

[0076] Next, electrode materials are chemically vapor deposited on the upper surfaces of the etched replacement layer 203 and the supplementary dielectric layer 206 to form Fig. 9 The initial electrode layer 207 is shown in FIG. In this embodiment, the material of the initial electrode layer 207 is a copper-aluminum alloy. In other embodiments, the material of the initial electrode layer 207 may also be one or more of TiN, TaN, copper, tungsten, nickel, chromium and titanium. Fig.10 As shown, the initial electrode layer 207 on the upper surface of the etched replacement layer 203 is then removed by an etching process, and the initial electrode layer 207 retained on the upper surface of the supplementary dielectric layer 206 is used as the second electrode layer 208. In this embodiment, a dry etching process is adopted, and the etching gas for dry etching includes chlorine, boron chloride, argon, nitrogen, trifluoromethane and methane. The power of dry etching is between 200W-400W, the pressure of the etching chamber is between 30mTorr-200mTorr, and the etching temperature is between 40℃-60℃.

[0077] The alignment window 204 for etching the replacement layer 203 defines the position and width of the capacitor structure, as well as the thickness of the complementary dielectric layer 206. Due to the existence of the etching replacement layer 203, during the etching process of the initial electrode layer 207, the etching ions on the side of the second electrode layer 208 are gathered, and the etching replacement layer 203 forms a depression in the bottom area on both sides of the second electrode layer 208 instead of the dielectric layer of the prior art, so the complementary dielectric layer 206 is not damaged, thereby ensuring the thickness of the intermediate dielectric layer (i.e., the initial dielectric layer 202 and the complementary dielectric layer 206) between the second electrode layer 208 and the first electrode layer 201, thereby improving the breakdown voltage of the capacitor structure and expanding the scope of application.

[0078] Under dry etching conditions, the etching rate of the second electrode layer 208 is greater than the etching rate of the replacement layer 203. Since the upper surface of the replacement layer 203 will not be absolutely horizontal, when the second electrode layer 208 on the upper surface of the replacement layer 203 is not completely etched, the etching of the replacement layer 203 exposed by the second electrode layer 208 that has been completely etched will be weakened, which can reduce the damage to the surface of the replacement layer 203 and ensure the quality of the replacement layer 203, thereby preparing for the formation of a high-quality capacitor structure. Under the same etching conditions, the etching rate of the replacement layer 203 is greater than the etching rate of the supplementary dielectric layer 206. Damage to the supplementary dielectric layer 206 can be avoided.

[0079] Then, step S103 is performed: forming an intermediate dielectric layer using the initial dielectric layer 202; wherein the intermediate dielectric layer is in a convex shape with an upper step and a lower step, and the width of the upper step is equal to the width of the capacitor structure.

[0080] Furthermore, the forming of the intermediate dielectric layer by using the initial dielectric layer 202 includes: removing the etching replacement layer 203 by a wet etching process, and using the initial dielectric layer 202 and the replacement dielectric layer 206 in the alignment window 204 as the intermediate dielectric layer.

[0081] Furthermore, under the same etching conditions, the etching rate of the replacement layer 203 is greater than the etching rate of the supplementary dielectric layer 206 .

[0082] Specifically, in the embodiment of the present invention, the initial dielectric layer 202 and the supplementary dielectric layer 206 in the alignment window 204 are used as the intermediate dielectric layer of the capacitor structure. The thickness of the intermediate dielectric layer is between 150 angstroms and 800 angstroms. If the thickness of the intermediate dielectric layer is less than 150 angstroms, it is more likely to break down in a small voltage range, the leakage current is relatively large, and the capacitance value is also relatively large; if the thickness of the intermediate dielectric layer is greater than 800 angstroms, the capacitance value is relatively small.

[0083] In another possible implementation, after forming the second electrode 208, the replacement layer 203 is removed by wet etching to expose the initial dielectric layer 202 under the replacement layer 203. Then, the dielectric layer 209 is formed, and the first conductive structure 210 and the second conductive structure 211 are formed.

[0084] During the wet etching process, the wet etching solution only reacts with the replacement layer 203, and does not react with the initial dielectric layer 202 and the supplementary dielectric layer 206 (that is, the etching rate of the replacement layer 203 is much greater than the etching rate of the supplementary dielectric layer 206 and the initial dielectric layer 202), which can ensure the integrity of the initial dielectric layer 202 and the supplementary dielectric layer 206, and will not cause damage to the initial dielectric layer 202 and the supplementary dielectric layer 206.

[0085] Furthermore, dry etching can be used to remove the replacement layer 203. The dry etching parameters include: the gas used includes CF 4 Gas and CHF 3 Gas, CF 4 The gas flow rate is between 8sccm-500sccm, CHF 3 The gas flow rate is between 30sccm-200sccm, the chamber pressure is between 10mtorr-2000mtorr, the source RF power is between 100W-1300W, the bias voltage is between 80V-500V, and the time is between 4 seconds-500 seconds. The ratio of the etching rate of the replacement layer 203 to the etching rate of the supplementary dielectric layer 206 is greater than 5, and the ratio of the etching rate of the replacement layer 203 to the etching rate of the initial dielectric layer 202 is greater than 5, so that the initial dielectric layer 202 and the supplementary dielectric layer 206 can be avoided from being damaged in the process of removing the replacement layer 203, thereby ensuring the quality of the initial dielectric layer 202 and the supplementary dielectric layer 206.

[0086] Finally, step S104 is performed: forming a dielectric layer 209, and forming a first conductive structure 210 and a second conductive structure 211; wherein the first conductive structure 210 extends downward from the upper surface of the dielectric layer 209 and contacts the first electrode layer 201, and the second conductive structure 211 extends downward from the upper surface of the dielectric layer 209 and contacts the second electrode layer 208.

[0087] Specifically, in the embodiment of the present invention, Fig.11As shown, a dielectric material is deposited on the upper surface of the etched replacement layer 203 and the second electrode layer 208 to form a dielectric layer 209. A first conductive structure 210 and a second conductive structure 211 are formed, the first conductive structure 210 extends downward from the upper surface of the dielectric layer 209 and contacts the first electrode layer 201, and the second conductive structure 211 extends downward from the upper surface of the dielectric layer 209 and contacts the second electrode layer 208. The material of the first conductive structure 210 is copper, aluminum, titanium or tungsten, and the material of the second conductive structure 211 is copper, aluminum, titanium or tungsten.

[0088] Embodiment 2

[0089] Please refer to Fig. 20 According to a first aspect of an embodiment of the present invention, there is provided a method for manufacturing a capacitor structure, the method comprising:

[0090] Step S101: providing a substrate 300, and sequentially forming a first electrode layer 301, an initial dielectric layer 302, and an etched replacement layer 304 having an alignment window 305 on the upper surface of the substrate 300; wherein the width of the alignment window 305 is equal to the width of the capacitor structure;

[0091] Step S102: using the etching replacement layer 304 as a barrier layer and utilizing the self-alignment effect of the alignment window 305 to form a second electrode layer 307;

[0092] Step S103: forming an intermediate dielectric layer 308 using the initial dielectric layer 302; wherein the intermediate dielectric layer 308 is a convex-shaped configuration having an upper step and a lower step, and the width of the upper step is equal to the width of the capacitor structure;

[0093] Step S104: forming a dielectric layer 309 and forming a first conductive structure 310 and a second conductive structure 311; wherein the first conductive structure 310 extends downward from the upper surface of the dielectric layer 309 and contacts the first electrode layer 301, and the second conductive structure 311 extends downward from the upper surface of the dielectric layer 309 and contacts the second electrode layer 307.

[0094] Specifically, firstly perform step S101: provide a substrate 300, and sequentially form a first electrode layer 301, an initial dielectric layer 302 and an etched replacement layer 304 having an alignment window 305 on the upper surface of the substrate 300; wherein the width of the alignment window 305 is equal to the width of the capacitor structure.

[0095] Furthermore, an etching replacement layer 304 having an alignment window 305 is formed by the following method: an initial etching replacement layer 303 and a photoresist layer are formed on the upper surface of the initial dielectric layer 302; an etching window is formed on the photoresist layer by using an exposure and development process; and the initial etching replacement layer 303 is etched through the etching window to form an etching replacement layer 304 having an alignment window 305.

[0096] Furthermore, the etched replacement layer 304 is made of silicon nitride or silicon carbonitride material.

[0097] Furthermore, the initial dielectric layer 302 is made of silicon oxide or silicon oxynitride.

[0098] Then, step S102 is performed: the etching replacement layer 304 is used as a barrier layer, and the self-alignment effect of the alignment window 305 is utilized to form a second electrode layer 307 .

[0099] Furthermore, the etching replacement layer 304 is used as a barrier layer, and the self-alignment effect of the alignment window 305 is utilized to form the second electrode layer 307, including: depositing electrode material on the surface of the etching replacement layer 304, and filling the alignment window 305 with the electrode material to form an initial electrode layer 306; removing the electrode material on the upper surface of the etching replacement layer 304 to form the second electrode layer 307.

[0100] Furthermore, under the same etching conditions, the etching rate of the second electrode layer 307 is greater than the etching rate of the substitution layer 304 .

[0101] Specifically, in the embodiment of the present invention, Figure 12-14 As shown, a substrate 300 is provided, and a first electrode layer 301, an initial dielectric layer 302, and an etched replacement layer 304 having an alignment window 305 are sequentially formed on the upper surface of the substrate 300. The specific forming method is the same as that of the first embodiment, and will not be repeated in this embodiment. Fig.15 As shown, after forming the etching replacement layer 304 with the alignment window 305, the electrode material is deposited on the upper surface of the etching replacement layer 304, and the electrode material fills the alignment window 305 to form the initial electrode layer 306. Fig.16 As shown, the initial electrode layer 306 is planarized based on the designed height of the second electrode layer 307 , and then the planarized initial electrode layer 306 is etched to remove the electrode materials on both sides of the second electrode layer 307 forming area to form the second electrode layer 307 .

[0102] The alignment window 305 of the etching substitute layer 304 defines the position and width of the capacitor structure, and due to the existence of the etching substitute layer 304, during the etching process of the initial electrode layer 306, the etching ions on the side of the second electrode layer 307 are gathered, and the etching substitute layer 304 replaces the dielectric layer of the prior art to form a depression in the bottom area on both sides of the second electrode layer 307, so that the thickness of the initial dielectric layer 302 is not damaged, thereby ensuring the thickness of the intermediate dielectric layer between the second electrode layer 307 and the first electrode layer 301, thereby improving the breakdown voltage of the capacitor structure and expanding the scope of application.

[0103] Under dry etching conditions, the etching rate of the initial electrode layer 306 is greater than the etching rate of the replacement layer 304. Since the upper surface of the etched replacement layer 304 will not be absolutely horizontal, when the initial electrode layer 306 on the upper surface of the etched replacement layer 304 is partially not completely etched, the etching of the etched replacement layer 304 exposed by the partially etched initial electrode layer 306 will be weakened, which can reduce the damage to the surface of the etched replacement layer 304 and ensure the quality of the etched replacement layer 304, thereby preparing for the formation of a high-quality capacitor structure.

[0104] Then, step S103 is performed: forming an intermediate dielectric layer 308 using the initial dielectric layer 302; wherein the intermediate dielectric layer 308 is a convex-shaped configuration with an upper step and a lower step, and the width of the upper step is equal to the width of the capacitor structure.

[0105] Furthermore, the formation of the intermediate dielectric layer 308 using the initial dielectric layer 302 includes: using a dry etching process to remove the etching replacement layer 304 to expose the initial dielectric layer 302 not covered by the second electrode layer 307; using the second electrode layer 307 as a mask to remove the portion of the initial dielectric layer 302 not covered by the second electrode layer 307 to form the intermediate dielectric layer 308.

[0106] Furthermore, under the same etching conditions, the etching rate of the replacement layer 304 is greater than the etching rate of the initial dielectric layer 302 .

[0107] like Fig.17 As shown, specifically, in the embodiment of the present invention, after the second electrode layer 307 is formed, the replacement layer 304 is removed by a dry etching process until the initial dielectric layer 302 not covered by the second electrode layer 307 is exposed. The etching rate of the replacement layer 304 is greater than the etching rate of the initial dielectric layer 302, so that when the replacement layer 304 is removed, the damage to the initial dielectric layer 302 can be reduced, and the problem of dielectric layer depression can be further avoided.

[0108] like Fig.18As shown, the second electrode layer 307 is used as a mask to remove the portion of the initial dielectric layer 302 not covered by the second electrode layer 307, so that the slight damage to the initial dielectric layer 302 when removing the etching replacement layer 304 can be removed, and the intermediate dielectric layer 308 with a smooth surface is formed. In this way, the problem of dielectric layer depression is avoided, and the thickness of the dielectric layer between the first electrode layer and the second electrode layer is ensured to be consistent with the thickness of the dielectric layer edge, thereby improving the breakdown voltage of the capacitor structure, expanding the application range, reducing the local loss of the dielectric layer, improving the energy storage efficiency and life of the capacitor structure, and ensuring the performance and stability of the capacitor structure.

[0109] Finally, step S104 is performed: forming a dielectric layer 309, and forming a first conductive structure 310 and a second conductive structure 311; wherein the first conductive structure 310 extends downward from the upper surface of the dielectric layer 309 and contacts the first electrode layer 301, and the second conductive structure 311 extends downward from the upper surface of the dielectric layer 309 and contacts the second electrode layer 307.

[0110] like Fig.19 As shown, specifically, in the embodiment of the present invention, a dielectric layer 309 is formed on the surface of the intermediate dielectric layer 308 and the second electrode layer 307, and then a first conductive structure 310 and a second conductive structure 311 are formed. The method for forming the dielectric layer 309, the first conductive structure 310 and the second conductive structure 311 is the same as that in the first embodiment, and will not be repeated in this embodiment.

[0111] A second aspect of the present invention provides a capacitor structure, wherein the capacitor structure is formed by the capacitor structure manufacturing method described above.

[0112] A third aspect of the present invention provides a chip, which includes the capacitor structure described above.

[0113] A fourth aspect of the present invention provides a circuit, which includes the capacitor structure described above.

[0114] The preferred embodiments of the present invention are described in detail above in conjunction with the accompanying drawings. However, the present invention is not limited to the specific details in the above embodiments. Within the technical concept of the present invention, a variety of simple modifications can be made to the technical solution of the present invention, and these simple modifications all belong to the protection scope of the present invention.

[0115] It should also be noted that the various specific technical features described in the above specific embodiments can be combined in any suitable manner without contradiction. In order to avoid unnecessary repetition, the present invention will not further describe various possible combinations.

[0116] In addition, various embodiments of the present invention may be arbitrarily combined, and as long as they do not violate the concept of the present invention, they should also be regarded as the contents disclosed by the present invention.

Claims

1. A method for manufacturing a capacitor structure, characterized in that: The capacitor structure manufacturing method comprises: Providing a substrate, and sequentially forming a first electrode layer, an initial dielectric layer, and an etched replacement layer having an alignment window on the upper surface of the substrate; wherein the width of the alignment window is equal to the width of the capacitor structure; The etching replacement layer is used as a barrier layer, and a second electrode layer is formed by utilizing the self-alignment effect of the alignment window; Using the initial dielectric layer to form an intermediate dielectric layer; wherein the intermediate dielectric layer is in a convex shape with an upper step and a lower step, and the width of the upper step is equal to the width of the capacitor structure; A dielectric layer is formed, and a first conductive structure and a second conductive structure are formed; wherein the first conductive structure extends downward from the upper surface of the dielectric layer and contacts the first electrode layer, and the second conductive structure extends downward from the upper surface of the dielectric layer and contacts the second electrode layer.

2. The method for manufacturing a capacitor structure according to claim 1, characterized in that: The etched replacement layer with the alignment window is formed by the following method: forming an initial etching replacement layer and a photoresist layer on the upper surface of the initial dielectric layer; forming an etching window on the photoresist layer by using exposure and development processes; The initial etching replacement layer is etched through the etching window to form an etching replacement layer with an alignment window.

3. The method for manufacturing a capacitor structure according to claim 1, characterized in that: The method of using the etching replacement layer as a barrier layer and utilizing the self-alignment effect of the alignment window to form a second electrode layer comprises: forming a supplementary dielectric layer in the alignment window; The second electrode layer is formed on the upper surface of the supplementary dielectric layer; wherein the width of the second electrode layer is equal to the width of the alignment window.

4. The method for manufacturing a capacitor structure according to claim 3, characterized in that: The forming of a supplementary dielectric layer in the alignment window comprises: Depositing a dielectric material on the upper surface of the etching replacement layer, and filling the alignment window with the dielectric material to form a dielectric material layer; The dielectric material on the upper surface of the etched replacement layer is removed, and the dielectric material in the alignment window is retained to form the supplementary dielectric layer.

5. The method for manufacturing a capacitor structure according to claim 3, characterized in that: The forming of the second electrode layer on the upper surface of the supplementary dielectric layer comprises: Forming an initial electrode layer on the upper surfaces of the etched replacement layer and the supplementary dielectric layer; The initial electrode layer on the upper surface of the etched replacement layer is removed, and the initial electrode layer retained on the upper surface of the supplementary dielectric layer is used as the second electrode layer.

6. The method for manufacturing a capacitor structure according to claim 3, characterized in that: The forming of the intermediate dielectric layer by using the initial dielectric layer comprises: The initial dielectric layer and the supplementary dielectric layer in the alignment window are used as the intermediate dielectric layer.

7. The method for manufacturing a capacitor structure according to claim 3, characterized in that: Under the same etching conditions, the etching rate of the substitution layer is greater than the etching rate of the supplementary dielectric layer.

8. The method for manufacturing a capacitor structure according to claim 1, characterized in that: The method of using the etching replacement layer as a barrier layer and utilizing the self-alignment effect of the alignment window to form a second electrode layer comprises: Depositing electrode material on the surface of the etched replacement layer, and filling the alignment window with the electrode material to form an initial electrode layer; The electrode material on the upper surface of the etching replacement layer is removed to form the second electrode layer.

9. The method for manufacturing a capacitor structure according to claim 8, characterized in that: The forming of the intermediate dielectric layer by using the initial dielectric layer comprises: Removing the etching replacement layer by dry etching process to expose the initial dielectric layer not covered by the second electrode layer; The second electrode layer is used as a mask to remove a portion of the initial dielectric layer not covered by the second electrode layer to form the intermediate dielectric layer.

10. The method for manufacturing a capacitor structure according to claim 1, characterized in that: Under the same etching conditions, the etching rate of the substitutional layer is greater than the etching rate of the initial dielectric layer.

11. The method for manufacturing a capacitor structure according to claim 1, characterized in that: Under the same etching conditions, the etching rate of the second electrode layer is greater than the etching rate of the etching replacement layer.

12. The method for manufacturing a capacitor structure according to claim 1, characterized in that: The etching replacement layer is made of silicon nitride or silicon carbonitride material.

13. The method for manufacturing a capacitor structure according to claim 1, characterized in that: The initial dielectric layer is made of silicon oxide or silicon oxynitride.

14. A capacitor structure, characterized in that: The capacitor structure is formed by the capacitor structure manufacturing method according to any one of claims 1 to 13.

15. A chip, characterized in that: The chip comprises the capacitor structure as claimed in claim 14.

16. A circuit, characterized in that: The circuit comprises the capacitor structure of claim 14.

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