Test structure and test method for nominal value and mismatch characteristic of element to be tested

Abstract

The invention relates to a test structure and a test method for a nominal value and a mismatch characteristic of a to-be-tested element, and the test structure for the nominal value of the to-be-tested element comprises an inverting circuit and a first to-be-tested element, the inverting circuit comprises a first PMOS (P-channel Metal Oxide Semiconductor) tube, a first NMOS (N-channel Metal Oxide Semiconductor) tube, a second PMOS tube, a second NMOS tube, a first output end and a second output end, the grid electrode of the first PMOS tube is connected with the grid electrode of the second PMOS tube, the drain electrode of the first PMOS tube is connected with the first output end and the drain electrode of the first NMOS tube, and the drain electrode of the second PMOS tube is connected with the second output end and the drain electrode of the second NMOS tube; the grid electrode of the first NMOS tube is connected with the grid electrode of the second NMOS tube, and the source electrode of the first NMOS tube and the source electrode of the second NMOS tube are both grounded; the first end of the first to-be-tested element is connected with the first output end.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a test structure and a test method for a nominal value and mismatch characteristic of a component to be tested. Background Art

[0002] With the continuous development of semiconductor process technology, accurate measurement of the nominal value and mismatch characteristics of the DUT is very important for evaluating process stability. Existing test structures for measuring the nominal value and mismatch characteristics of the DUT include charge-based capacitance measurement structures and charge injection induced error-free structures.

[0003] In the charge-based capacitance measurement structure, the mirror-symmetric structure of PMOS and NMOS devices is adopted. The mismatch characteristics of the capacitance are measured by measuring the current values ​​of the left and right circuits of the mirror-symmetric structure. However, the capacitance value measured by the above scheme also includes other capacitances of the PMOS and NMOS devices, resulting in inaccurate capacitance value measurement and cannot be used for small capacitance mismatch measurement.

[0004] In the charge injection induced error-free structure, other parasitic capacitances can be excluded through testing to improve the test accuracy, but this test structure and method cannot be used for capacitance mismatch testing. Summary of the invention

[0005] The technical problem solved by the present invention is that the existing measurement structure cannot guarantee the measurement accuracy of the nominal value of the component to be measured.

[0006] To solve the above technical problems, an embodiment of the present invention provides a test structure for the nominal value of a component under test, comprising: an inverting circuit, a first component under test; the inverting circuit comprises: a first PMOS tube, a first NMOS tube, a second PMOS tube, a second NMOS tube, a first output end and a second output end; a gate of the first PMOS tube is connected to a gate of the second PMOS tube, a drain of the first PMOS tube is connected to the first output end and the drain of the first NMOS tube, and a drain of the second PMOS tube is connected to the second output end and the drain of the second NMOS tube; a gate of the first NMOS tube is connected to a gate of the second NMOS tube, and a source of the first NMOS tube and a source of the second NMOS tube are both grounded; and a first end of the first component under test is connected to the first output end.

[0007] Optionally, the first element to be measured includes a first resistor to be measured, a first inductor to be measured, or a first capacitor to be measured.

[0008] Optionally, the test structure also includes a first measurement module; the first measurement module is suitable for, in a charging stage, applying a first voltage to the gate of the first PMOS tube, the gate of the second PMOS tube, the gate of the first NMOS tube and the gate of the second NMOS tube, so that the first PMOS tube and the second PMOS tube are turned on in a first turn-on time period, and the first NMOS tube and the second NMOS tube are turned off in a first turn-off time period, controlling the first turn-off time period to include the first turn-on time period, applying a first voltage to the second end of the first element under test, measuring and comparing the current value flowing through the first PMOS tube and the current value flowing through the second PMOS tube to obtain a current difference; and obtaining the nominal value of the first element under test according to the current difference.

[0009] Optionally, the first measurement module is also suitable for applying a second voltage to the gate of the first PMOS tube, the gate of the second PMOS tube, the gate of the first NMOS tube and the gate of the second NMOS tube in a discharge phase, so that the first PMOS tube and the second PMOS tube are cut off in a second cut-off time period, and the first NMOS tube and the second NMOS tube are turned on in a second turn-on time period, and the second cut-off time period is controlled to include the second turn-on time period, and a second voltage is applied to the second end of the first element to be measured, and a current value flowing through the first PMOS tube and a current value flowing through the second PMOS tube are measured and compared to obtain a current difference, and a nominal value of the first element to be measured is obtained according to the current difference; wherein the first voltage is an inverted signal of the second voltage.

[0010] An embodiment of the present invention further provides a test structure for a mismatch characteristic of a DUT, comprising a second DUT, a second measuring module, a second output terminal and the test structure for the nominal value of the DUT described above; when the first DUT is a first resistor to be measured, the second DUT comprises a second resistor to be measured, and a first terminal of the second resistor to be measured is connected to the second output terminal and a drain of a second NMOS tube; the second measuring module is adapted to, in a first measuring phase, apply a first voltage to a gate of a first PMOS tube, a gate of a second PMOS tube, a gate of a first NMOS tube and a gate of a second NMOS tube, so that the first PMOS tube and the second PMOS tube are turned on in a first on-time period, and the first NMOS tube and the second NMOS tube are turned off in a first off-time period, control the first off-time period to include the first on-time period, apply a first voltage to a second terminal of the first resistor to be measured and a second terminal of the second resistor to be measured, and measure a first current value flowing through the first PMOS tube and a first current value flowing through the second PMOS tube. a second current value of the first PMOS tube; in a second measurement phase, applying a second voltage to the gate of the first PMOS tube, the gate of the second PMOS tube, the gate of the first NMOS tube, and the gate of the second NMOS tube, so that the first PMOS tube and the second PMOS tube are turned off in a second cut-off time period, and the first NMOS tube and the second NMOS tube are turned on in a second on time period, controlling the second cut-off time period to include the second on time period, applying a first voltage to the second end of the first resistor to be measured and the second end of the second resistor to be measured, measuring a third current value flowing through the first PMOS tube and a fourth current value flowing through the second PMOS tube; wherein the first voltage is an inverted signal of the second voltage; comparing the difference between the first current value and the third current value to obtain a first difference, and comparing the difference between the second current value and the fourth current value to obtain a second difference; obtaining a mismatch characteristic between the first resistor to be measured and the second resistor to be measured according to the first difference and the second difference.

[0011] Optionally, when the first element to be measured is a first inductor to be measured, the second element to be measured also includes a second inductor to be measured, and the first end of the second inductor to be measured is connected to the second output end; the second measurement module is suitable for, in a first measurement phase, applying a first voltage to the gate of the first PMOS tube, the gate of the second PMOS tube, the gate of the first NMOS tube, and the gate of the second NMOS tube, so that the first PMOS tube and the second PMOS tube are turned on in a first turn-on time period, and the first NMOS tube and the second NMOS tube are turned off in a first turn-off time period, controlling the first turn-off time period to include the first turn-on time period, applying a first voltage to the second end of the first inductor to be measured and the second end of the second inductor to be measured, and measuring a first current value flowing through the first PMOS tube and a second current value flowing through the second PMOS tube; wherein the first voltage is an inverted signal of the second voltage; and in the first In the second measurement stage, a second voltage is applied to the gate of the first PMOS tube, the gate of the second PMOS tube, the gate of the first NMOS tube, and the gate of the second NMOS tube, so that the first PMOS tube and the second PMOS tube are turned off in a second cut-off time period, and the first NMOS tube and the second NMOS tube are turned on in a second on time period, and the second cut-off time period is controlled to include the second on time period, a first voltage is applied to the second end of the first inductor to be measured and the second end of the second resistor to be measured, and a third current value flowing through the first PMOS tube and a fourth current value flowing through the second PMOS tube are measured; a difference between the first current value and the third current value is compared to obtain a first difference, and a difference between the second current value and the fourth current value is compared to obtain a second difference; and a mismatch characteristic between the first inductor to be measured and the second inductor to be measured is obtained according to the first difference and the second difference.

[0012] An embodiment of the present invention also provides a method for testing a test structure of a nominal value of a component under test, comprising: in a charging stage, applying a first voltage to a gate of a first PMOS tube, a gate of a second PMOS tube, a gate of a first NMOS tube, and a gate of a second NMOS tube, so that the first PMOS tube and the second PMOS tube are turned on in a first turn-on time period, and the first NMOS tube and the second NMOS tube are turned off in a first turn-off time period, controlling the first turn-off time period to include the first turn-on time period, applying a first voltage to a second end of the first component under test, measuring and comparing a current value flowing through the first PMOS tube and a current value flowing through the second PMOS tube to obtain a current difference, and obtaining the nominal value of the first component under test according to the current difference.

[0013] Optionally, in the discharge stage, a second voltage is applied to the gate of the first PMOS tube, the gate of the second PMOS tube, the gate of the first NMOS tube and the gate of the second NMOS tube, so that the first PMOS tube and the second PMOS tube are cut off in a second cut-off time period, and the first NMOS tube and the second NMOS tube are turned on in a second turn-on time period, and the second cut-off time period is controlled to include the second turn-on time period, and a second voltage is applied to the second end of the first element to be measured, and the current value flowing through the first PMOS tube and the current value flowing through the second PMOS tube are measured and compared to obtain a current difference, and the nominal value of the first element to be measured is obtained according to the current difference, wherein the first voltage is an inverted signal of the second voltage.

[0014] The embodiment of the present invention also provides a test method for a test structure of a mismatch characteristic of a component to be tested, comprising: in a first measurement phase, applying a first voltage to a gate of a first PMOS tube, a gate of a second PMOS tube, a gate of a first NMOS tube, and a gate of a second NMOS tube, so that the first PMOS tube and the second PMOS tube are turned on in a first on-time period, and the first NMOS tube and the second NMOS tube are turned off in a first off-time period, controlling the first off-time period to include the first on-time period, applying a first voltage to a second end of a first resistor to be tested and a second end of a second resistor to be tested, and measuring a first current value flowing through the first PMOS tube and a second current value flowing through the second PMOS tube; in a second measurement phase, applying a second voltage to the gate of the first PMOS tube, the gate of the second PMOS tube, the gate of the first NMOS tube, and the gate of the second PMOS tube. The gate of the first PMOS tube and the gate of the second NMOS tube make the first PMOS tube and the second PMOS tube cut off in the second cut-off time period and turn on the first NMOS tube and the second NMOS tube in the second turn-on time period, control the second cut-off time period to include the second turn-on time period, apply a first voltage to the second end of the first resistor to be measured and the second end of the second resistor to be measured, measure the third current value flowing through the first PMOS tube and the fourth current value flowing through the second PMOS tube; wherein the first voltage is an inverted signal of the second voltage; compare the difference between the first current value and the third current value to obtain a first difference, compare the difference between the second current value and the fourth current value to obtain a second difference; obtain the mismatch characteristic between the first resistor to be measured and the second resistor to be measured according to the first difference and the second difference.

[0015] Optionally, in a first measurement phase, a first voltage is applied to the gate of the first PMOS tube, the gate of the second PMOS tube, the gate of the first NMOS tube, and the gate of the second NMOS tube, so that the first PMOS tube and the second PMOS tube are turned on in a first turn-on time period, and the first NMOS tube and the second NMOS tube are turned off in a first turn-off time period, the first turn-off time period is controlled to include the first turn-on time period, a first voltage is applied to the second end of the first inductor to be measured and the second end of the second inductor to be measured, and a first current value flowing through the first PMOS tube and a second current value flowing through the second PMOS tube are measured; in a second measurement phase, a second voltage is applied to the gate of the first PMOS tube, the gate of the second PMOS tube, the gate of the first NMOS tube, and the gate of the second NMOS tube The invention relates to a method for controlling a first inductor to be measured and a second inductor to be tested, wherein the first PMOS transistor and the second PMOS transistor are turned off in a second off time period and the first NMOS transistor and the second NMOS transistor are turned on in a second on time period, and the second off time period is controlled to include the second on time period, and a first voltage is applied to the second end of the first inductor to be measured and the second end of the second inductor to be measured, and a third current value flowing through the first PMOS transistor and a fourth current value flowing through the second PMOS transistor are measured; wherein the first voltage is an inverted signal of the second voltage; a difference between the first current value and the third current value is compared to obtain a first difference, and a difference between the second current value and the fourth current value is compared to obtain a second difference; and a mismatch characteristic between the first inductor to be measured and the second inductor to be measured is obtained according to the first difference and the second difference.

[0016] Compared with the prior art, the technical solution of the embodiment of the present invention has the following beneficial effects:

[0017] The test structure for the nominal value of the component to be tested provided by the technical solution of the present invention comprises a first component to be tested. When measuring the nominal value of the component to be tested, the first resistor to be tested is connected to the first output terminal in the inverting circuit. By measuring and comparing the current flowing through the first PMOS tube and the current flowing through the second PMOS tube, the current of the first component to be tested in a charging state is obtained, and the influence of the current generated by the parasitic element is eliminated. Then, the nominal value of the first component to be tested is calculated, so that the nominal value of the first component to be tested can be accurately measured, and the performance of the circuit can be further measured.

[0018] Furthermore, the first DUT in the technical solution of the present invention includes a resistor, a capacitor or an inductor, so that the test structure can measure different types of DUTs, thus avoiding the single application of the test structure.

[0019] Furthermore, the test structure for the mismatch characteristics of the element to be tested provided by the technical solution of the present invention comprises a first element to be tested and a second element to be tested, and the first element to be tested comprises a resistor or an inductor. When testing the mismatch characteristics of the element to be tested, the first resistor to be tested is connected to the first output end in the inverting circuit, and the second resistor to be tested is connected to the second output end in the inverting circuit. By measuring and comparing the current flowing through the first PMOS tube in the charging stage and the current flowing through the second PMOS tube in the discharging stage, as well as the current flowing through the first PMOS tube in the charging stage and the current flowing through the second PMOS tube in the discharging stage, the mismatch characteristics between the first resistor to be tested and the second resistor to be tested are obtained, thereby realizing the testing of the mismatch characteristics of different types of elements to be tested. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 It is a schematic diagram of a charge-based capacitance test structure;

[0021] Figure 2 It is a schematic diagram of the structure of a charge injection induced error-free structure;

[0022] Figure 3 The structure of a test structure for the nominal value of a component under test provided by an embodiment of the present invention is shown in FIG. Figure 1 ;

[0023] Figure 4 The structure of a test structure for the nominal value of a component under test provided by an embodiment of the present invention is shown in FIG. Figure 2 ;

[0024] Figure 5 The structure of a test structure for the nominal value of a component under test provided by an embodiment of the present invention is shown in FIG. Figure 3 ;

[0025] Figure 6 The structure of a test structure for the nominal value of a component under test provided by an embodiment of the present invention is shown in FIG. Figure 4 ;

[0026] Figure 7 It is a working timing diagram of a test method of a test structure of a nominal value of a component under test provided by an embodiment of the present invention;

[0027] Figure 8 The structure of a test structure for measuring the mismatch characteristics of a component under test provided by an embodiment of the present invention is shown in FIG. Figure 1 ;

[0028] Fig. 9 The structure of a test structure for measuring the mismatch characteristics of a component under test provided by an embodiment of the present invention is shown in FIG. Figure 2 ;

[0029] Fig.10 The structure of a test structure for measuring the mismatch characteristics of a component under test provided by an embodiment of the present invention is shown in FIG. Figure 3 ;

[0030] Fig.11 It is a working timing diagram of a testing method of a testing structure for mismatch characteristics of a component under test provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0031] From the background technology, we can understand that the existing test structure has the problem of not being able to take into account both the accuracy of measurement and the single measurement object. Now we analyze the reasons in combination with the existing test structure:

[0032] Figure 1 It is a structural schematic diagram of a charge-based capacitance test structure.

[0033] Please refer to Figure 1 The test structure includes: a first PMOS tube PM1, a second PMOS tube PM2, a first NMOS tube NM1, a second NMOS tube NM2, a first ammeter I', a second ammeter I, a first metal interconnection line Metal1 and a second metal interconnection line Metal2, wherein the first PMOS tube PM1 and the first NMOS tube NM1 constitute a first inverter, and the second PMOS tube PM2 and the second NMOS tube NM2 constitute a second inverter.

[0034] Below Figure 1 The working principle of the charge-based capacitance test structure (Charge-Based Capacitance Measurement) is explained.

[0035] Figure 1 The first inverter side is connected to the capacitor calibration structure, and the second inverter side is connected to the grounded capacitor structure to be measured. The first ammeter I' and the second ammeter I respectively measure the current flowing through the first inverter and the second inverter, and the input signals of the first PMOS tube PM1, the second PMOS tube PM2, the first NMOS tube NM1 and the second NMOS tube NM2 are respectively controlled by two non-overlapping clock signals V1 and V2. The frequencies of the clock signals V1 and V2 are the same, but the duty cycles in the signal cycles are different, that is, the low-level duration of V1 completely includes the low-level duration of V2, and the high-level duration of V2 completely includes the high-level duration of V1, ensuring that at any time when the capacitance value is measured, in one inverter, only one device of the NMOS and PMOS tubes can be turned on.

[0036] When the PMOS tube is turned on and the NMOS tube is turned off, the capacitor structure to be tested in the right test structure is charged; when the NMOS tube is turned on and the PMOS tube is turned off, these charges are released to the ground terminal. The PMOS tube and the NMOS tube can respectively realize the charging and discharging of the capacitor structure to be tested, and the current caused by the charge change can be measured by the ammeter, so the capacitor CDUT to be tested can be calculated by the following formula:

[0037] II′=CDUT·Vdd·f, wherein f is the signal frequency of the clock signals V1 and V2, and Vdd is the power supply voltage.

[0038] In the above scheme, the capacitance to be measured is measured by adding capacitors on the left and right sides. However, the addition of two metal interconnects Metal1 and Metal2 will bring parasitic capacitance to the measurement structure, thereby affecting the measurement accuracy of the capacitance to be measured, and the above scheme cannot measure the mismatch characteristics of the capacitor.

[0039] Figure 2 It is a structural schematic diagram of a charge injection induced error-free structure.

[0040] Please refer to Figure 2 The charge injection induced error-free structure (Charge-Injection Induced-Error-Free) includes: a PMOS tube V p 、NMOS tube V N , an ammeter A, a capacitor to be measured C, and a PAD control circuit, wherein the charge injection induced error-free structure also includes a parasitic capacitor C P .

[0041] In the above scheme, only the single-sided MOS tube test is used to exclude other parasitic capacitances to improve the test accuracy of the capacitor C to be tested. However, the addition of additional circuits will also bring the influence of parasitic capacitance to the measurement structure, and this test structure cannot be used for capacitance mismatch testing.

[0042] also, Figure 1 and Figure 2 The solutions provided only mention the measurement of the capacitance value to be measured, but do not mention how to measure the values ​​or mismatch characteristics of different types of components to be measured.

[0043] To solve the above problems, the technical solution of the present invention provides a test structure for the nominal value of a component to be tested, wherein the test structure has a first component to be tested. When measuring the nominal value of the component to be tested, the first resistor to be tested is connected to the first output end in the inverting circuit, and the current flowing through the first PMOS tube and the current flowing through the second PMOS tube are measured and compared to obtain the current of the first component to be tested in a charging state, eliminating the influence of the current generated by the parasitic elements, and then calculating the nominal value of the first component to be tested, so that the nominal value of the first component to be tested can be accurately measured, and further the performance of the circuit can be measured.

[0044] In order to make the above-mentioned objects, features and beneficial effects of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0045] Figure 3 The structure of a test structure for the nominal value of a component under test provided by an embodiment of the present invention is shown in FIG. Figure 1 .

[0046] The test structure for the nominal value of the DUT includes: an inverting circuit and a first DUT 101 .

[0047] The inverting circuit includes: a first PMOS transistor PM1, a first NMOS transistor NM1, a second PMOS transistor PM2, a second NMOS transistor NM2, a first output end, and a second output end.

[0048] The gate of the first PMOS transistor PM1 is connected to the gate of the second PMOS transistor PM2, the drain of the first PMOS transistor PM1 is connected to the first output end and the drain of the first NMOS transistor NM1, and the drain of the second PMOS transistor PM2 is connected to the second output end and the drain of the second NMOS transistor NM2.

[0049] The gate of the first NMOS transistor NM1 is connected to the gate of the second NMOS transistor NM2 , and the source of the first NMOS transistor NM1 and the source of the second NMOS transistor NM2 are both grounded.

[0050] The first end of the first DUT 101 is connected to the first output end.

[0051] In other embodiments, the source of the first PMOS tube and the source of the second PMOS tube are connected to the same power supply voltage terminal.

[0052] The test structure for the nominal value of the component to be tested provided by the technical solution of the present invention comprises a first component to be tested. When measuring the nominal value of the component to be tested, the first resistor to be tested is connected to the first output terminal in the inverting circuit. By measuring and comparing the current flowing through the first PMOS tube and the current flowing through the second PMOS tube, the current of the first component to be tested in a charging state is obtained, and the influence of the current generated by the parasitic element is eliminated. Then, the nominal value of the first component to be tested is calculated, so that the nominal value of the first component to be tested can be accurately measured, and the performance of the circuit can be further measured.

[0053] In this embodiment, please refer to Figure 4 , Figure 5 as well as Figure 6 , the first device under test includes a first resistor under test Ra, a first inductor under test La or a first capacitor under test Ca.

[0054] Among them, when the first measured element is the first measured resistor Ra, the first end of the first measured resistor Ra is connected to the first output end; when the first measured element is the first measured inductor La, the first end of the first measured inductor La is connected to the first output end; when the first measured element is the first measured capacitor Ca, the first end of the first measured capacitor Ca is connected to the first output end.

[0055] In this embodiment, the test structure of the nominal value of the element to be measured further includes a first parasitic element 102 and a second parasitic element 202. The types of the first parasitic element 102 and the second parasitic element 202 are consistent with the type of the first element to be measured. For example, when the first element to be measured is the first resistor to be measured Ra, the first parasitic element 102 is the first parasitic resistor Rp1, and the second parasitic element 202 is the second parasitic resistor Rp2; when the first element to be measured is the first inductor to be measured La, the first parasitic element 102 is the first parasitic inductor Lp1, and the second parasitic element 202 is the second parasitic inductor Lp2; when the first element to be measured is the first capacitor to be measured Ca, the first parasitic element 102 is the first parasitic capacitor Cp1, and the second parasitic element 202 is the second parasitic capacitor Cp2.

[0056] The first end of the first parasitic element 102 is connected to the first output end, the second end of the first parasitic element 102 is connected to the source of the first NMOS transistor NM1, the first end of the second parasitic element 202 is connected to the second output end, and the second end of the first parasitic element 102 is connected to the source of the second NMOS transistor NM2.

[0057] Since the first DUT in the technical solution of the present invention includes a resistor, a capacitor or an inductor, the test structure can measure different types of DUTs, thus avoiding the single application of the test structure.

[0058] In a specific embodiment, the device under test of the present invention includes MIS (metal insulator silicon), MIM (metal insulator metal), or MOM (metal oxide metal) capacitors.

[0059] In other embodiments, the first PMOS transistor PM1 and the second PMOS transistor PM2 are mirror-symmetrical structures, and the first NMOS transistor NM1 and the second NMOS transistor NM2 are mirror-symmetrical structures, wherein the PMOS transistor is used to charge the device under test, and the NMOS transistor is used to discharge the device under test.

[0060] In an embodiment of the present invention, the test structure further includes a first measurement module (not shown); the first measurement module is suitable for, in a charging stage, applying a first voltage to a gate Vp of the first PMOS tube PM1, a gate Vp of the second PMOS tube PM2, a gate Vn of the first NMOS tube NM1, and a gate Vn of the second NMOS tube NM2, so that the first PMOS tube PM1 and the second PMOS tube PM2 are turned on in a first turn-on time period, and the first NMOS tube NM1 and the second NMOS tube NM2 are turned off in a first turn-off time period, the first turn-off time period is controlled to include the first turn-on time period, a first voltage is applied to the second end Vapp of the first element under test, and a current value flowing through the first PMOS tube PM1 and a current value flowing through the second PMOS tube PM2 are measured and compared to obtain a current difference; and a nominal value of the first element under test is obtained according to the current difference.

[0061] Correspondingly, the first measurement module is also suitable for, in the discharge stage, applying a second voltage to the gate Vp of the first PMOS tube PM1, the gate Vp of the second PMOS tube PM2, the gate Vn of the first NMOS tube NM1 and the gate Vn of the second NMOS tube NM2, so that the first PMOS tube PM1 and the second PMOS tube PM2 are cut off in the second cut-off time period, and the first NMOS tube NM1 and the second NMOS tube NM2 are turned on in the second turn-on time period, controlling the second cut-off time period to include the second turn-on time period, applying a second voltage to the second end Vapp of the first element under test, measuring and comparing the current value flowing through the first PMOS tube PM1 and the current value flowing through the second PMOS tube PM2 to obtain a current difference, and obtaining the nominal value of the first element under test according to the current difference.

[0062] Wherein, the first voltage is an inverted signal of the second voltage.

[0063] Specifically, the first voltage and the second voltage applied by the signal generator to the gate of the first PMOS transistor PM1 , the gate of the first NMOS transistor NM1 , and the second end of the first DUT are non-overlapping clock signals.

[0064] In one embodiment, the first voltage is a value of a ground voltage Vcc, and the second voltage is a value of a power supply voltage Vdd.

[0065] In other embodiments, the first end of the first element under test is connected to the second output end. At this time, the nominal value of the first element under test represents the circuit design performance of the second PMOS tube side. The testing method is the same as the testing method when the first end of the first element under test is connected to the second output end, and will not be repeated here.

[0066] Combination Figure 3 The working principle of the test structure of the nominal value of the DUT of this embodiment is described as follows:

[0067] In the charging stage, a first voltage is applied to the gate Vp of the first PMOS transistor PM1, the gate Vp of the second PMOS transistor PM2, the gate Vn of the first NMOS transistor NM1, and the gate Vn of the second NMOS transistor NM2, so that the first PMOS transistor PM1 and the second PMOS transistor PM2 are turned on, that is, the drain of the first PMOS transistor PM1 and the drain of the second PMOS transistor PM2 are both in a high level state, and a first voltage is applied to the second end Vapp of the first DUT 101, so that the second end of the first DUT 101 is in a low level state, thereby generating a potential difference between the two ends of the first DUT 101, and a current flows from the first end of the first DUT 101 to the second end, so that the first DUT 101 is in a state of being charged. Charging state; the first NMOS tube NM1 and the second NMOS tube NM2 are turned off, that is, the sources of the first NMOS and the second NMOS tube NM2 are in a low level state, so that the second end of the first parasitic element 102 and the second end of the second parasitic element 202 are both in a low level state, and in this embodiment, the first end of the first parasitic element 102 and the first end of the second parasitic element 202 are both in a high level state, thereby generating a potential difference between the two ends of the first parasitic element 102 and the two ends of the second parasitic element 202, and the current flows from the first end to the second end of the first parasitic element 102, and from the first end to the second end of the second parasitic element 202, so that the first parasitic element 102 and the second parasitic element 202 are both in a charged state.

[0068] In the above scheme, the current flowing through the first PMOS tube PM1 is the sum I1 of the charging current of the first DUT 101 and the charging current of the first parasitic element 102, and the current flowing through the second PMOS tube PM2 is the charging current I2 of the second parasitic element 202. No DUT is added to the second PMOS tube PM2 side, so the current I2 of the second parasitic element 202 is the current of the parasitic element generated in the circuit. It can be seen that the current difference between I1 and I2 is the charging current value of the first DUT 101 on the first PMOS tube PM1 side, and then according to the charging current value of the first DUT 101, the nominal value of the first DUT 101 can be calculated.

[0069] Similarly, in the discharge stage, a second voltage is applied to the gate Vp of the first PMOS transistor PM1, the gate Vp of the second PMOS transistor PM2, the gate Vn of the first NMOS transistor NM1, and the gate Vn of the second NMOS transistor NM2, so that the first PMOS transistor PM1 and the second PMOS transistor PM2 are turned off, that is, the drain of the first PMOS transistor PM1 and the drain of the second PMOS transistor PM2 are both in a low level state, and a second voltage is applied to the second end Vapp of the first device under test 101, so that the second end of the first device under test 101 is in a high level state, thereby generating a potential difference between the two ends of the first device under test 101, and a current flows from the second end to the first end of the first device under test 101, so that the first device under test 101 is at a low level state. The first NMOS tube NM1 and the second NMOS tube NM2 are in a discharged state; the first NMOS tube NM1 and the second NMOS tube NM2 are turned on, that is, the sources of the first NMOS tube and the second NMOS tube NM2 are in a high level state, so that the second end of the first parasitic element 102 and the second end of the second parasitic element 202 are both in a high level state, and in this embodiment, the first end of the first parasitic element 102 and the first end of the second parasitic element 202 are both in a low level state, thereby generating a potential difference between the two ends of the first parasitic element 102 and the two ends of the second parasitic element 202, and the current flows from the second end of the first parasitic element 102 to the first end, and from the second end of the second parasitic element 202 to the first end, so that the first parasitic element 102 and the second parasitic element 202 are both in a discharged state.

[0070] In the above scheme, the current flowing through the first PMOS tube PM1 is the sum I1 of the discharge current of the first DUT 101 and the discharge current of the first parasitic element 102, and the current flowing through the second PMOS tube PM2 is the discharge current I2 of the second parasitic element 202. No DUT is added to the second PMOS tube PM2 side, so the current I2 of the second parasitic element 202 is the current of the parasitic element generated in the circuit. It can be seen that the current difference between I1 and I2 is the discharge current value of the first DUT 101 on the first PMOS tube PM1 side, and then according to the discharge current value of the first DUT 101, the nominal value of the first DUT 101 can be calculated.

[0071] In a specific embodiment, when the first measured element is the first measured capacitor Ca, the calculation formula for the first measured capacitance value is as follows: Ca=d(I1-I2) / dV*f, wherein V is the power supply voltage, and f is the signal frequency of the clock signal composed of the first voltage and the second voltage.

[0072] In a specific embodiment, when the first component to be measured is a first resistor to be measured Ra, a calculation formula for the first resistor to be measured is as follows: Ra=dV / d(I1-I2), wherein V is a power supply voltage.

[0073] In a specific embodiment, when the first measured element is the first measured inductor La, the calculation formula of the first measured inductor value is as follows: La=dV / [d(I1-I2)*f], wherein V is the power supply voltage, and f is the signal frequency of the clock signal composed of the first voltage and the second voltage.

[0074] The technical solution of the present invention also provides a testing method for a test structure of a nominal value of a component to be tested, including: in a charging stage, applying a first voltage to a gate of a first PMOS tube, a gate of a second PMOS tube, a gate of a first NMOS tube, and a gate of a second NMOS tube, so that the first PMOS tube and the second PMOS tube are turned on in a first on-time period, and the first NMOS tube and the second NMOS tube are turned off in a first off-time period, controlling the first off-time period to include the first on-time period, applying a first voltage to the second end of the first component to be tested, measuring and comparing a current value flowing through the first PMOS tube and a current value flowing through the second PMOS tube to obtain a current difference, and obtaining the nominal value of the first component to be tested according to the current difference.

[0075] Correspondingly, in the discharge stage, a second voltage is applied to the gate of the first PMOS tube, the gate of the second PMOS tube, the gate of the first NMOS tube, and the gate of the second NMOS tube, so that the first PMOS tube and the second PMOS tube are cut off in a second cut-off time period, and the first NMOS tube and the second NMOS tube are turned on in a second turn-on time period, and the second cut-off time period is controlled to include the second turn-on time period, and a second voltage is applied to the second end of the first element under test, and the current value flowing through the first PMOS tube and the current value flowing through the second PMOS tube are measured and compared to obtain a current difference, and the nominal value of the first element under test is obtained according to the current difference, wherein the first voltage is an inverted signal of the second voltage.

[0076] The following example takes the first voltage value of 0V and the second voltage value of 1.8V as an example, and combines Figure 7 , the working process of the test structure of the nominal value of the DUT of this embodiment is specifically described:

[0077] In the discharge stage, by applying a second voltage (i.e., 1.8V) to the gate of the first PMOS transistor PM1, the gate of the second PMOS transistor PM2, the gate of the first NMOS transistor NM1, and the gate of the second NMOS transistor NM2, the first PMOS transistor PM1 and the second PMOS transistor PM2 are turned off in the second cut-off time period T1, and the first NMOS transistor NM1 and the second NMOS transistor NM2 are turned on in the second turn-on time period T2, wherein the second cut-off time period T1 includes the second turn-on time period T2, so as to ensure that the first NMOS transistor NM1 is turned on when the first PMOS transistor PM1 is completely cut off, and the second NMOS transistor NM2 is turned on when the second PMOS transistor PM2 is completely cut off, thereby making the first parasitic element 102 and the second parasitic element 202 in the discharge state in the second turn-on time period T2; applying a second voltage (i.e., 1.8V) to the second end of the first device under test 101, so that the first device under test 101 is in the discharge state in the T2 time period.

[0078] It can be seen that in the second conduction time period T2, the first parasitic element 102, the second parasitic element 202 and the first DUT 101 are all in a discharge state. At this time, the current difference between the current value flowing through the first PMOS transistor PM1 and the current value flowing through the second PMOS transistor PM2 is the discharge current of the DUT.

[0079] In the charging stage, by applying a first voltage (i.e., 0V) to the gate of the first PMOS transistor PM1, the gate of the second PMOS transistor PM2, the gate of the first NMOS transistor NM1, and the gate of the second NMOS transistor NM2, the first PMOS transistor PM1 and the second PMOS transistor PM2 are turned on in a first on-time period T4, and the first NMOS transistor NM1 and the second NMOS transistor NM2 are turned off in a first off-time period T5, wherein the first off-time period T5 includes the first on-time period T4, so as to ensure that the first PMOS transistor PM1 is turned on when the first NMOS transistor NM1 is completely turned off, and the second PMOS transistor PM2 is turned on when the second NMOS transistor NM2 is completely turned off, thereby making the first parasitic element 102 and the second parasitic element 202 in a charging state in the first on-time period T4; applying a first voltage (i.e., 0V) to the second end of the first device under test 101, so that the first device under test 101 is in a charging state in the T4 time period.

[0080] It can be seen that in the first conduction time period T4, the first parasitic element 102, the second parasitic element 202 and the first DUT 101 are all in a charging state. At this time, the current difference between the current value flowing through the first PMOS transistor PM1 and the current value flowing through the second PMOS transistor PM2 is the charging current of the DUT.

[0081] In one embodiment, please continue to refer to Figure 7 , Figure 7 The sum of the time in the first on-time period T4 and the second off-time period T1 is the length of a measurement cycle, but the present invention is not limited thereto, and other divisions of measurement cycles are within the protection scope of the present invention.

[0082] Please refer to Figure 8 and Fig. 9 , Figure 8 The structure of a test structure for measuring the mismatch characteristics of a component under test provided by an embodiment of the present invention is shown in FIG. Figure 1 , Fig. 9 The structure of a test structure for measuring the mismatch characteristics of a component under test provided by an embodiment of the present invention is shown in FIG. Figure 2 In an embodiment of the present invention, the test structure for the mismatch characteristic of the DUT includes a second DUT 202, a second measuring module (not shown), a second output terminal and the test structure for the nominal value of the DUT mentioned above.

[0083] When the first DUT 101 is a first DUT resistor Ra, the second DUT 202 includes a second DUT resistor Rb, and a first end of the second DUT resistor Rb is connected to the second output end and the drain of the second NMOS transistor NM2.

[0084] The second measurement module is suitable for, in a first measurement phase, applying a first voltage to the gate of the first PMOS tube PM1, the gate of the second PMOS tube PM2, the gate of the first NMOS tube NM1 and the gate of the second NMOS tube NM2, so that the first PMOS tube PM1 and the second PMOS tube PM2 are turned on in a first turn-on time period, and the first NMOS tube NM1 and the second NMOS tube NM2 are turned off in a first turn-off time period, controlling the first turn-off time period to include the first turn-on time period, applying a first voltage to the second end of the first resistor to be measured Ra and the second end of the second resistor to be measured Rb, and measuring a first current value flowing through the first PMOS tube PM1 and a second current value flowing through the second PMOS tube PM2.

[0085] In the second measurement phase, a second voltage is applied to the gate of the first PMOS tube PM1, the gate of the second PMOS tube PM2, the gate of the first NMOS tube NM1, and the gate of the second NMOS tube NM2, so that the first PMOS tube PM1 and the second PMOS tube PM2 are cut off in the second cut-off time period, and the first NMOS tube NM1 and the second NMOS tube NM2 are turned on in the second turn-on time period, and the second cut-off time period is controlled to include the second turn-on time period, and a first voltage is applied to the second end of the first resistor to be measured Ra and the second end of the second resistor to be measured Rb, and a third current value flowing through the first PMOS tube PM1 and a fourth current value flowing through the second PMOS tube PM2 are measured; wherein the first voltage is an inverted signal of the second voltage.

[0086] The difference between the first current value and the third current value is compared to obtain a first difference, and the difference between the second current value and the fourth current value is compared to obtain a second difference.

[0087] A mismatch characteristic between the first resistor to be measured Ra and the second resistor to be measured Rb is obtained according to the first difference and the second difference.

[0088] Accordingly, please refer to Fig.10 When the first DUT 101 is a first DUT inductor La, the second DUT 202 further includes a second DUT inductor Lb, and a first end of the second DUT inductor Lb is connected to the second output end.

[0089] The second measurement module is suitable for, in a first measurement phase, applying a first voltage to the gate of the first PMOS tube PM1, the gate of the second PMOS tube PM2, the gate of the first NMOS tube NM1 and the gate of the second NMOS tube NM2, so that the first PMOS tube PM1 and the second PMOS tube PM2 are turned on in a first turn-on time period, and the first NMOS tube NM1 and the second NMOS tube NM2 are turned off in a first turn-off time period, controlling the first turn-off time period to include the first turn-on time period, applying a first voltage to the second end of the first inductor La to be measured and the second end of the second inductor Lb to be measured, and measuring a first current value flowing through the first PMOS tube PM1 and a second current value flowing through the second PMOS tube PM2; wherein the first voltage is an inverted signal of the second voltage.

[0090] In the second measurement phase, a second voltage is applied to the gate of the first PMOS transistor PM1, the gate of the second PMOS transistor PM2, the gate of the first NMOS transistor NM1, and the gate of the second NMOS transistor NM2, so that the first PMOS transistor PM1 and the second PMOS transistor PM2 are turned off in a second cut-off time period, and the first NMOS transistor NM1 and the second NMOS transistor NM2 are turned on in a second turn-on time period, the second cut-off time period is controlled to include the second turn-on time period, a first voltage is applied to the second end of the first inductor La to be measured and the second end of the second resistor Rb to be measured, and a third current value flowing through the first PMOS transistor PM1 and a fourth current value flowing through the second PMOS transistor PM2 are measured.

[0091] The difference between the first current value and the third current value is compared to obtain a first difference, and the difference between the second current value and the fourth current value is compared to obtain a second difference.

[0092] A mismatch characteristic between the first inductor La to be measured and the second inductor Lb to be measured is obtained according to the first difference and the second difference.

[0093] In one embodiment, the same voltage signal is applied to the second end of the first DUT and the second end of the second DUT.

[0094] In another embodiment, different voltage signals are applied to the second end of the first DUT and the second end of the second DUT.

[0095] The working principle of the test structure for the mismatch characteristic of the DUT of this embodiment is described below:

[0096] In the first measurement phase, a first voltage is applied to the gate of the first PMOS transistor PM1, the gate of the second PMOS transistor PM2, the gate of the first NMOS transistor NM1, and the gate of the second NMOS transistor NM2, so that the first PMOS transistor PM1 and the second PMOS transistor PM2 are turned on, that is, the drain of the first PMOS transistor PM1 and the drain of the second PMOS transistor PM2 are both in a high level state, and a first voltage is applied to the second end of the first component under test 101 and the second end of the second component under test 202, so that the second end of the first component under test 101 and the second end of the second component under test 202 are both in a low level state, thereby generating a potential difference between the two ends of the first component under test 101 and the second end of the second component under test 202, and a current flows from the first end of the first component under test 101 to the second end, so that the first component under test 101 is in a charged state; a current flows from the first end of the second component under test 202 to the second end, so that the second component under test 202 is in a charged state.

[0097] The first NMOS transistor NM1 and the second NMOS transistor NM2 are turned off, that is, the sources of the first NMOS and the second NMOS transistor NM2 are in a low level state, so that the second end of the first parasitic element 102 and the second end of the second parasitic element 202 are both in a low level state, and in this embodiment, the first end of the first parasitic element 102 and the first end of the second parasitic element 202 are both in a high level state, thereby generating a potential difference between the two ends of the first parasitic element 102 and the two ends of the second parasitic element 202, and the current flows from the first end to the second end of the first parasitic element 102, and from the first end to the second end of the second parasitic element 202, so that the first parasitic element 102 and the second parasitic element 202 are both in a charged state.

[0098] In the first measurement phase, the current flowing through the first PMOS transistor PM1 is the sum I3 of the charging current of the first DUT 101 and the charging current of the first parasitic element 102 , and the current flowing through the second PMOS transistor PM2 is the sum I4 of the charging current of the second DUT 202 and the charging current of the second parasitic element 202 .

[0099] In the second measurement phase, a second voltage is applied to the gate of the first PMOS transistor PM1, the gate of the second PMOS transistor PM2, the gate of the first NMOS transistor NM1, and the gate of the second NMOS transistor NM2, so that the first PMOS transistor PM1 and the second PMOS transistor PM2 are turned off in the second turn-off time period, that is, the drain of the first PMOS transistor PM1 and the drain of the second PMOS transistor PM2 are both in a low level state, and a first voltage is applied to the second end of the first component under test 101 and the second end of the second component under test 202, so that the second end of the first component under test 101 and the second end of the second component under test 202 are both in a low level state, thereby causing no potential difference to be generated at both ends of the first component under test 101 and the second end of the second component under test 202, that is, no current flows from the first end to the second end of the first component under test 101, and no current flows from the first end to the second end of the second component under test 202.

[0100] The first NMOS transistor NM1 and the second NMOS transistor NM2 are turned on, that is, the sources of the first NMOS and the second NMOS transistor NM2 are in a high level state, so that the second end of the first parasitic element 102 and the second end of the second parasitic element 202 are both in a high level state, and in this embodiment, the first end of the first parasitic element 102 and the first end of the second parasitic element 202 are both in a low level state, thereby generating a potential difference between the two ends of the first parasitic element 102 and the two ends of the second parasitic element 202, and the current flows from the second end of the first parasitic element 102 to the first end, and from the second end of the second parasitic element 202 to the first end, so that the first parasitic element 102 and the second parasitic element 202 are both in a discharged state.

[0101] It can be seen that in the second measurement phase, the current flowing through the first PMOS transistor PM1 is only the discharge current I3 ′ of the first parasitic element 102 , and the current flowing through the second PMOS transistor PM2 is only the discharge current I4 ′ of the second parasitic element 202 .

[0102] Therefore, the difference between I3 and I3′ is the charging current value of the first device under test 101 on the side of the first PMOS transistor PM1, and the difference between I4 and I4′ is the charging current value of the second device under test 202 on the side of the second PMOS transistor PM2. Further, according to the charging current value of the first device under test 101 and the charging current value of the second device under test 202, the nominal value of the first device under test 101 and the nominal value of the second device under test 202 can be calculated. Further, according to the difference between the nominal value of the first device under test 101 and the nominal value of the second device under test 202, the mismatch characteristic of the device under test can be calculated.

[0103] In a specific embodiment, when the first DUT 101 is a first resistor Ra, and the second DUT 202 is a second resistor Rb,

[0104] The resistance value of the first measured resistor Ra is: Ra=dV / d(I3-I3'), and the resistance value of the second measured resistor Rb is: Rb=dV / d(I4-I4'), wherein V is the power supply voltage, f is the signal frequency of the clock signal composed of the first voltage and the second voltage, and the mismatch characteristic between the first measured resistor Ra and the second measured resistor Rb is characterized by ΔR=2*(Ra-Rb) / (Ra+Rb).

[0105] In a specific embodiment, when the first DUT 101 is the first DUT inductor La, and the second DUT 202 is the second DUT inductor Lb,

[0106] The inductance value of the first inductor La to be measured is: La=dV / [d(I3-I3')*f], and the inductance value of the second inductor Lb to be measured is: Lb=dV / [d(I4-I4')*f], wherein V is the power supply voltage, f is the signal frequency of the clock signal composed of the first voltage and the second voltage, and the mismatch characteristic between the first inductor La to be measured and the second inductor Lb to be measured is characterized by: ΔL=2*(La-Lb) / (La+Lb).

[0107] In the above scheme, in the first measurement phase, the sum of the charging currents flowing through the first DUT 101 and the first parasitic element 102 is measured, and the difference is made between the sum of the charging currents flowing through the first DUT 101 and the first parasitic element 102 measured in the second measurement phase, so as to obtain the nominal value of the first DUT 101. Similarly, the nominal value of the second DUT 202 is obtained through the above process, and finally the mismatch characteristic of the DUT is calculated.

[0108] In other embodiments, the nominal value of the first device under test 101 is obtained by measuring the sum of the charging currents flowing through the first device under test 101 and the first parasitic element 102 in the first measurement phase and subtracting the sum from the charging current of the first parasitic element 102 measured in the second measurement phase. Similarly, the nominal value of the second device under test 202 is obtained through the above process, and finally the mismatch characteristic of the device under test is calculated.

[0109] In other embodiments, the nominal value of the first device under test 101 is obtained by measuring the sum of the discharge currents flowing through the first device under test 101 and the first parasitic element 102 in the first measurement phase and subtracting the sum from the charge current of the first parasitic element 102 measured in the second measurement phase. Similarly, the nominal value of the second device under test 202 is obtained through the above process, and finally the mismatch characteristic of the device under test is calculated.

[0110] In other embodiments, the nominal value of the first device under test 101 is obtained by measuring the sum of the discharge currents flowing through the first device under test 101 and the first parasitic element 102 in the first measurement phase and subtracting the sum from the discharge current of the first parasitic element 102 measured in the second measurement phase. Similarly, the nominal value of the second device under test 202 is obtained through the above process, and finally the mismatch characteristic of the device under test is calculated.

[0111] In the above scheme, since the charging current and the discharging current of the same DUT or parasitic element are the same, different current types can be selected for measurement in the first measurement phase and the second measurement phase, and the mismatch characteristics can be obtained by combining the differences.

[0112] In addition, in the present embodiment, a measurement process of the charging current of the first DUT and the second DUT in the first measurement phase, and a measurement process of the discharging current of the first parasitic element 102 and the second parasitic element 202 in the second measurement phase are provided, and the difference between the measurement of the charging current and the measurement of the discharging current lies in that the level states at both ends of the DUT or the level states at both ends of the parasitic element are controlled differently, so the measurement process of the discharging current of the first DUT and the second DUT in the first measurement phase, and the measurement process of the charging current of the first parasitic element 102 and the second parasitic element 202 in the second measurement phase are not described in detail here.

[0113] The test structure for the mismatch characteristic of the element to be tested provided by the technical solution of the present invention comprises a first element to be tested and a second element to be tested, and the first element to be tested comprises a resistor or an inductor. When testing the mismatch characteristic of the element to be tested, the first resistor to be tested is connected to the first output end of the inverting circuit, and the second resistor to be tested is connected to the second output end of the inverting circuit. By measuring and comparing the current flowing through the first PMOS tube in the charging stage and the current flowing through the second PMOS tube in the discharging stage, as well as the current flowing through the first PMOS tube in the charging stage and the current flowing through the second PMOS tube in the discharging stage, the mismatch characteristic between the first resistor to be tested and the second resistor to be tested is obtained, thereby realizing the testing of the mismatch characteristics of different types of elements to be tested.

[0114] An embodiment of the present invention also provides a testing method for a test structure of a mismatch characteristic of a component to be tested, comprising: in a first measurement phase, applying a first voltage to a gate of a first PMOS tube, a gate of a second PMOS tube, a gate of a first NMOS tube, and a gate of a second NMOS tube, so that the first PMOS tube and the second PMOS tube are turned on in a first on-time period, and the first NMOS tube and the second NMOS tube are turned off in a first off-time period, controlling the first off-time period to include the first on-time period, applying a first voltage to a second end of a first resistor to be tested and a second end of a second resistor to be tested, and measuring a first current value flowing through the first PMOS tube and a second current value flowing through the second PMOS tube.

[0115] In the second measurement phase, a second voltage is applied to the gate of the first PMOS tube, the gate of the second PMOS tube, the gate of the first NMOS tube, and the gate of the second NMOS tube, so that the first PMOS tube and the second PMOS tube are cut off in a second cut-off time period, and the first NMOS tube and the second NMOS tube are turned on in a second turn-on time period, and the second cut-off time period is controlled to include the second turn-on time period, and a first voltage is applied to the second end of the first resistor to be measured and the second end of the second resistor to be measured, and a third current value flowing through the first PMOS tube and a fourth current value flowing through the second PMOS tube are measured; wherein the first voltage is an inverted signal of the second voltage.

[0116] The difference between the first current value and the third current value is compared to obtain a first difference, and the difference between the second current value and the fourth current value is compared to obtain a second difference.

[0117] A mismatch characteristic between the first resistor to be measured and the second resistor to be measured is obtained according to the first difference and the second difference.

[0118] In one embodiment, in a first measurement phase, a first voltage is applied to a gate of a first PMOS tube, a gate of a second PMOS tube, a gate of a first NMOS tube, and a gate of a second NMOS tube, so that the first PMOS tube and the second PMOS tube are turned on in a first turn-on time period, and the first NMOS tube and the second NMOS tube are turned off in a first turn-off time period, the first turn-off time period is controlled to include the first turn-on time period, a first voltage is applied to a second end of the first inductor to be measured and a second end of the second inductor to be measured, and a first current value flowing through the first PMOS tube and a second current value flowing through the second PMOS tube are measured.

[0119] In the second measurement phase, a second voltage is applied to the gate of the first PMOS tube, the gate of the second PMOS tube, the gate of the first NMOS tube, and the gate of the second NMOS tube, so that the first PMOS tube and the second PMOS tube are turned off in a second cut-off time period, and the first NMOS tube and the second NMOS tube are turned on in a second turn-on time period, the second cut-off time period is controlled to include the second turn-on time period, a first voltage is applied to the second end of the first inductor to be measured and the second end of the second inductor to be measured, and a third current value flowing through the first PMOS tube and a fourth current value flowing through the second PMOS tube are measured; wherein the first voltage is an inverted signal of the second voltage.

[0120] The difference between the first current value and the third current value is compared to obtain a first difference, and the difference between the second current value and the fourth current value is compared to obtain a second difference.

[0121] A mismatch characteristic between the first inductor to be measured and the second inductor to be measured is obtained according to the first difference and the second difference.

[0122] The following example takes the first voltage value of 0V and the second voltage value of 1.8V as an example, and combines Figure 7 and Fig.11 , the working process of the test structure of the mismatch characteristic of the DUT of this embodiment is specifically described:

[0123] refer to Figure 7 , in a first measurement phase, by applying a first voltage (i.e., 0V) to the gate of the first PMOS tube, the gate of the second PMOS tube, the gate of the first NMOS tube, and the gate of the second NMOS tube, the first PMOS tube and the second PMOS tube are turned on in a first on time period T4, and the first NMOS tube and the second NMOS tube are turned off in a first off time period T5, wherein the first off time period T5 includes the first on time period T4, ensuring that the first PMOS tube is turned on when the first NMOS tube is completely turned off, and the second PMOS tube is turned on when the second NMOS tube is completely turned off, thereby making the first parasitic element and the second parasitic element in a charging state in the first on time period T4; applying a first voltage (i.e., 0V) to the second end of the first DUT and the second end of the second DUT in a T6 time period, making the first DUT and the second DUT in a charging state in a T4 time period, and measuring the charging current on the first parasitic element and the first DUT in the T4 time period, and the charging current on the second parasitic element and the second DUT.

[0124] refer to Fig.11In the second measurement phase, by applying a second voltage (i.e., 1.8V) to the gate of the first PMOS tube, the gate of the second PMOS tube, the gate of the first NMOS tube, and the gate of the second NMOS tube, the first PMOS tube and the second PMOS tube are turned off in the second cut-off time period T1, and the first NMOS tube and the second NMOS tube are turned on in the second turn-on time period T2, wherein the second cut-off time period T1 includes the second turn-on time period T2, so as to ensure that the first NMOS tube is turned on when the first PMOS tube is completely cut off, and the second NMOS tube is turned on when the second PMOS tube is completely cut off, so that the first parasitic element and the second parasitic element are in a discharge state in the second turn-on time period T2; in the time period T7, applying a first voltage (i.e., 0V) to the second end of the first element under test and the second end of the second element under test, so that the first element under test and the first element under test do not generate current in the time period T2, and measuring the discharge current on the first parasitic element and the second parasitic element in the time period T2.

[0125] For other embodiments, please continue to refer to Fig.11 In the second measurement phase, by applying a first voltage (i.e., 0V) to the gate of the first PMOS tube, the gate of the second PMOS tube, the gate of the first NMOS tube, and the gate of the second NMOS tube, the first PMOS tube and the second PMOS tube are turned on in a first on time period T4, and the first NMOS tube and the second NMOS tube are turned off in a first off time period T5, wherein the first off time period T5 includes the first on time period T4, so as to ensure that the first PMOS tube is turned on when the first NMOS tube is completely turned off, and the second PMOS tube is turned on when the second NMOS tube is completely turned off, so that the first parasitic element and the second parasitic element are in a charging state in the first on time period T4; applying a first voltage (i.e., 0V) to the second end of the first element under test and the second end of the second element under test in the T8 time period, so that the first element under test and the second element under test do not generate current in the T4 time period; and measuring the charging current on the first parasitic element and the second parasitic element in the T4 time period.

[0126] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A test structure for the nominal value of a component under test, characterized in that: include: An inverting circuit and a first device under test; The inverting circuit comprises: a first PMOS tube, a first NMOS tube, a second PMOS tube, a second NMOS tube, a first output end and a second output end; The gate of the first PMOS tube is connected to the gate of the second PMOS tube, the drain of the first PMOS tube is connected to the first output terminal and the drain of the first NMOS tube, and the drain of the second PMOS tube is connected to the second output terminal and the drain of the second NMOS tube; The gate of the first NMOS tube is connected to the gate of the second NMOS tube, and the source of the first NMOS tube and the source of the second NMOS tube are both grounded; The first end of the first DUT is connected to the first output end.

2. The test structure for the nominal value of the device under test as claimed in claim 1, characterized in that: include: The first device under test includes a first resistor under test, a first inductor under test, or a first capacitor under test.

3. The test structure for the nominal value of the device under test according to claim 1 or 2, characterized in that: The test structure also includes a first measurement module; The first measurement module is adapted to, in a charging phase, apply a first voltage to the gate of the first PMOS tube, the gate of the second PMOS tube, the gate of the first NMOS tube, and the gate of the second NMOS tube, so that the first PMOS tube and the second PMOS tube are turned on in a first on time period, and the first NMOS tube and the second NMOS tube are turned off in a first off time period, control the first off time period to include the first on time period, apply a first voltage to the second end of the first DUT, measure and compare a current value flowing through the first PMOS tube and a current value flowing through the second PMOS tube, so as to obtain a current difference; A nominal value of the first DUT is obtained according to the current difference.

4. The test structure for the nominal value of the device under test as claimed in claim 3, characterized in that: include: The first measurement module is further adapted to, in a discharge phase, apply a second voltage to the gate of the first PMOS tube, the gate of the second PMOS tube, the gate of the first NMOS tube, and the gate of the second NMOS tube, so that the first PMOS tube and the second PMOS tube are turned off in a second cut-off time period, and the first NMOS tube and the second NMOS tube are turned on in a second on time period, control the second cut-off time period to include the second on time period, apply a second voltage to the second end of the first DUT, measure and compare a current value flowing through the first PMOS tube and a current value flowing through the second PMOS tube to obtain a current difference, and obtain a nominal value of the first DUT according to the current difference; Wherein, the first voltage is an inverted signal of the second voltage.

5. A test structure for measuring the mismatch characteristics of a component under test, characterized in that: A test structure comprising a second DUT, a second measuring module, a second output terminal and a nominal value of the DUT according to claim 1 or 2; When the first element to be measured is a first resistor to be measured, the second element to be measured includes a second resistor to be measured, and a first end of the second resistor to be measured is connected to the second output end and the drain of the second NMOS tube; The second measurement module is adapted to, in a first measurement phase, apply a first voltage to the gate of the first PMOS tube, the gate of the second PMOS tube, the gate of the first NMOS tube, and the gate of the second NMOS tube, so that the first PMOS tube and the second PMOS tube are turned on in a first turn-on time period, and the first NMOS tube and the second NMOS tube are turned off in a first turn-off time period, control the first turn-off time period to include the first turn-on time period, apply a first voltage to the second end of the first resistor to be measured and the second end of the second resistor to be measured, and measure a first current value flowing through the first PMOS tube and a second current value flowing through the second PMOS tube; In the second measurement phase, a second voltage is applied to the gate of the first PMOS tube, the gate of the second PMOS tube, the gate of the first NMOS tube, and the gate of the second NMOS tube, so that the first PMOS tube and the second PMOS tube are turned off in a second cut-off time period, and the first NMOS tube and the second NMOS tube are turned on in a second turn-on time period, the second cut-off time period is controlled to include the second turn-on time period, a first voltage is applied to the second end of the first resistor to be measured and the second end of the second resistor to be measured, and a third current value flowing through the first PMOS tube and a fourth current value flowing through the second PMOS tube are measured; wherein the first voltage is an inverted signal of the second voltage; Comparing the difference between the first current value and the third current value to obtain a first difference, and comparing the difference between the second current value and the fourth current value to obtain a second difference; A mismatch characteristic between the first resistor to be measured and the second resistor to be measured is obtained according to the first difference and the second difference.

6. The test structure for measuring mismatch characteristics of a DUT as claimed in claim 5, characterized in that: include: When the first component under test is a first inductor under test, the second component under test further includes a second inductor under test, and a first end of the second inductor under test is connected to the second output end; The second measurement module is adapted to, in a first measurement phase, apply a first voltage to the gate of the first PMOS tube, the gate of the second PMOS tube, the gate of the first NMOS tube, and the gate of the second NMOS tube, so that the first PMOS tube and the second PMOS tube are turned on in a first on time period, and the first NMOS tube and the second NMOS tube are turned off in a first off time period, control the first off time period to include the first on time period, apply a first voltage to the second end of the first inductor to be measured and the second end of the second inductor to be measured, and measure a first current value flowing through the first PMOS tube and a second current value flowing through the second PMOS tube; wherein the first voltage is an inverted signal of the second voltage; In the second measurement phase, a second voltage is applied to the gate of the first PMOS transistor, the gate of the second PMOS transistor, the gate of the first NMOS transistor, and the gate of the second NMOS transistor, so that the first PMOS transistor and the second PMOS transistor are turned off in a second off-time period, and the first NMOS transistor and the second NMOS transistor are turned on in a second on-time period, the second off-time period is controlled to include the second on-time period, a first voltage is applied to the second end of the first inductor to be measured and the second end of the second resistor to be measured, and a third current value flowing through the first PMOS transistor and a fourth current value flowing through the second PMOS transistor are measured; Comparing the difference between the first current value and the third current value to obtain a first difference, and comparing the difference between the second current value and the fourth current value to obtain a second difference; A mismatch characteristic between the first inductor to be measured and the second inductor to be measured is obtained according to the first difference and the second difference.

7. A method for testing a test structure of a nominal value of a component under test, characterized in that: include: In the charging stage, a first voltage is applied to the gate of the first PMOS tube, the gate of the second PMOS tube, the gate of the first NMOS tube, and the gate of the second NMOS tube, so that the first PMOS tube and the second PMOS tube are turned on in a first turn-on time period, and the first NMOS tube and the second NMOS tube are turned off in a first turn-off time period, the first turn-off time period is controlled to include the first turn-on time period, a first voltage is applied to the second end of the first element to be measured, a current value flowing through the first PMOS tube and a current value flowing through the second PMOS tube are measured and compared to obtain a current difference, and a nominal value of the first element to be measured is obtained according to the current difference.

8. The testing method according to claim 7, characterized in that: include: In the discharge stage, a second voltage is applied to the gate of the first PMOS tube, the gate of the second PMOS tube, the gate of the first NMOS tube, and the gate of the second NMOS tube, so that the first PMOS tube and the second PMOS tube are cut off in a second cut-off time period, and the first NMOS tube and the second NMOS tube are turned on in a second turn-on time period, and the second cut-off time period is controlled to include the second turn-on time period, and a second voltage is applied to the second end of the first element under test, and a current value flowing through the first PMOS tube and a current value flowing through the second PMOS tube are measured and compared to obtain a current difference, and a nominal value of the first element under test is obtained according to the current difference, wherein the first voltage is an inverted signal of the second voltage.

9. A method for testing a test structure for measuring mismatch characteristics of a device under test, characterized in that: include: In a first measurement phase, a first voltage is applied to the gate of the first PMOS tube, the gate of the second PMOS tube, the gate of the first NMOS tube, and the gate of the second NMOS tube, so that the first PMOS tube and the second PMOS tube are turned on in a first on-time period, and the first NMOS tube and the second NMOS tube are turned off in a first off-time period, the first off-time period is controlled to include the first on-time period, a first voltage is applied to the second end of the first resistor to be measured and the second end of the second resistor to be measured, and a first current value flowing through the first PMOS tube and a second current value flowing through the second PMOS tube are measured; In the second measurement phase, a second voltage is applied to the gate of the first PMOS tube, the gate of the second PMOS tube, the gate of the first NMOS tube, and the gate of the second NMOS tube, so that the first PMOS tube and the second PMOS tube are turned off in a second cut-off time period, and the first NMOS tube and the second NMOS tube are turned on in a second turn-on time period, the second cut-off time period is controlled to include the second turn-on time period, a first voltage is applied to the second end of the first resistor to be measured and the second end of the second resistor to be measured, and a third current value flowing through the first PMOS tube and a fourth current value flowing through the second PMOS tube are measured; wherein the first voltage is an inverted signal of the second voltage; Comparing the difference between the first current value and the third current value to obtain a first difference, and comparing the difference between the second current value and the fourth current value to obtain a second difference; A mismatch characteristic between the first resistor to be measured and the second resistor to be measured is obtained according to the first difference and the second difference.

10. The method for testing the structure for testing the mismatch characteristics of a DUT as claimed in claim 9, characterized in that: Also includes: In a first measurement phase, a first voltage is applied to a gate of a first PMOS transistor, a gate of a second PMOS transistor, a gate of a first NMOS transistor, and a gate of a second NMOS transistor, so that the first PMOS transistor and the second PMOS transistor are turned on in a first turn-on time period, and the first NMOS transistor and the second NMOS transistor are turned off in a first turn-off time period, the first turn-off time period is controlled to include the first turn-on time period, a first voltage is applied to a second end of the first inductor to be measured and a second end of the second inductor to be measured, and a first current value flowing through the first PMOS transistor and a second current value flowing through the second PMOS transistor are measured; In the second measurement phase, a second voltage is applied to the gate of the first PMOS tube, the gate of the second PMOS tube, the gate of the first NMOS tube, and the gate of the second NMOS tube, so that the first PMOS tube and the second PMOS tube are turned off in a second cut-off time period, and the first NMOS tube and the second NMOS tube are turned on in a second turn-on time period, the second cut-off time period is controlled to include the second turn-on time period, a first voltage is applied to the second end of the first inductor to be measured and the second end of the second inductor to be measured, and a third current value flowing through the first PMOS tube and a fourth current value flowing through the second PMOS tube are measured; wherein the first voltage is an inverted signal of the second voltage; Comparing the difference between the first current value and the third current value to obtain a first difference, and comparing the difference between the second current value and the fourth current value to obtain a second difference; A mismatch characteristic between the first inductor to be measured and the second inductor to be measured is obtained according to the first difference and the second difference.

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