Electronic lock circuit of automobile charging equipment

Abstract

The invention relates to the technical field of electronics, and discloses an electronic lock circuit of automobile charging equipment, which comprises a driving circuit, a feedback circuit, a level conversion circuit, a logic control circuit, an isolating circuit, a buck-boost capacitor charging and discharging circuit and a power-off unlocking circuit. The controller is connected to the level conversion circuit; the level conversion circuit is connected with the logic control circuit; the logic control circuit is connected with the isolation circuit; the isolating circuit is connected with the driving circuit; the driving circuit is connected with the driving port; the feedback port is connected to the feedback circuit; the feedback circuit is connected with the controller; the capacitor charging and discharging circuit is connected with the power-off unlocking circuit; the de-energizing unlocking circuit is connected with the isolating circuit; the driving circuit is connected with the driving port. According to the invention, PWM signals are used for driving and controlling, interference is resisted, and false operation is not caused; during program debugging, breakpoints are broken when locking / unlocking logic is driven, PWM has no output, and damage cannot be caused; when the charging pile auxiliary source is abnormally powered down, the capacitor charging and discharging circuit is used for unlocking; the number of the control feedback signal line is one, resource occupation is small, and design is simplified.

Description

Technical Field

[0001] The present invention relates to the field of electronic technology, and in particular to an electronic lock circuit for a vehicle charging device. Background Art

[0002] Traditional electronic lock circuits are usually implemented by connecting aluminum electrolytic capacitors in series and parallel with relays. However, since aluminum electrolytic capacitors are easily affected by temperature, electrolytic capacitors have charging and discharging time limits, and differences in driving time for different electronic locks result in uncertain capacitance values, the hardware and structural design cannot be unified. The use of signal relays is limited by the electrical life of the relays. Although the use of transistor switches can solve the power-on charging current problem, the voltage resistance parameters of the transistors cannot meet the back-electromotive force voltage requirements of the electronic locks, and the working stability is poor.

[0003] The prior art mostly adopts the technical solution disclosed in "A control system and control method for an electronic lock of an electric vehicle charging gun" (publication number CN110745021A), which adopts an H-bridge drive control solution, which outputs a low level when the control signal is at a low level, and outputs a high level when the control signal is at a high level. When the control signal is at a low level, the main circuit inside the logic non-locking module is turned on to lock the electronic lock; when the control signal is at a high level, the main circuit inside the unlocking switch module is turned on to unlock the electronic lock; the power switch module is used to provide power to subsequent modules. In general, the control reliability of this solution is higher. Although this solution can meet the basic needs, there are still problems: (1) Refer to the specification attached to CN110745021A. Figure 5 , its driving end is a high or low level signal. When there is a disturbance in the control signal, it is easy to cause the electronic lock to malfunction; (2) when debugging the electronic lock driver in the control chip, the program breakpoint is set in the lock / unlock logic. At this time, the control pin logic is not controlled, and the electronic lock will be damaged due to excessive working time; (3) when the switching power supply is abnormally powered off, because there is no energy storage device in the circuit, the electronic lock cannot complete the unlocking action; (4) the instruction manual of CN110745021A is attached Figure 5 There are more control feedback signal lines in the system, which occupies more controller resources and increases control costs. Summary of the invention

[0004] In view of the shortcomings and defects of the prior art, the present invention provides an electronic lock circuit for a car charging device. The drive control signal adopts a PWM signal, which has strong anti-interference ability and will not cause malfunction of the electronic lock. When debugging the program, a program breakpoint is set when the electronic lock drives the locking / unlocking logic, and the PWM can have no output, which will not cause damage to the electronic lock. When the auxiliary source of the charging device loses power abnormally, the electronic lock is unlocked through a buck-boost capacitor charging and discharging circuit. There is only one control feedback signal line, which occupies less resources.

[0005] The purpose of the present invention can be achieved by the following technical solutions:

[0006] An electronic lock circuit for a car charging device, comprising a drive circuit, a feedback circuit, a level conversion circuit, a logic control circuit, an isolation circuit, a buck-boost capacitor charging and discharging circuit, and a power-off unlocking circuit;

[0007] The connection relationship is: the controller is connected to the level conversion circuit; the level conversion circuit is connected to the logic control circuit; the logic control circuit is connected to the isolation circuit; the isolation circuit is connected to the drive circuit; the drive circuit is connected to the electronic lock drive port; the electronic lock feedback port is connected to the feedback circuit; the feedback circuit is connected to the controller; the buck-boost capacitor charging and discharging circuit is connected to the power-off unlocking circuit; the power-off unlocking circuit is connected to the isolation circuit; and the drive circuit is connected to the electronic lock drive port.

[0008] Preferably, the level conversion circuit includes a resistor R4, a capacitor C2, a switching diode VD1, a capacitor C3, and a resistor R6;

[0009] The connection relationship is: R4 is connected in series with C2, C2 is connected in series with pin 3 of VD1, pins 1 and 2 of VD1 are connected in series with both ends of C3 respectively, and R6 is connected in parallel with both ends of C3;

[0010] The PWM signal output by the controller is converted into an absolute AC signal output through the capacitor C2 that isolates the DC. The energy storage capacitor C3 and the discharge resistor R6 effectively maintain a voltage level without dropping, thereby achieving frequency / voltage conversion.

[0011] Preferably, the logic control circuit includes resistors R1, R2, R3, R5, R7, R8, a capacitor C1, and a comparator D1;

[0012] The connection relationship is as follows: R2 and R7 are connected in series, the midpoint of the two is connected to the No. 2 pin of D1, the other end of R2 is connected to the +3.3V power supply, and the other end of R7 is grounded; R3 and R8 are connected in series, the midpoint of the two is connected to the No. 6 pin of D1, the other end of R3 is connected to the +3.3V power supply, and the other end of R8 is grounded; the No. 2 pin of the switching diode VD1 of the level conversion circuit is connected to the No. 3 and No. 5 pins of D1; R1 is connected to the No. 1 pin of D1, and R5 is connected to the No. 7 pin of D1; C1 is connected to the No. 8 pin of D1;

[0013] The logic control circuit uses two comparators to ensure different output logics under different voltage amplitudes.

[0014] Preferably, the isolation circuit includes a first isolation circuit and a second isolation circuit;

[0015] The connection relationship is as follows: the output end of the logic control circuit is connected in series to the input end of the first isolation circuit and the second isolation circuit; the output end of the first isolation circuit and the second isolation circuit is connected in series to the input end of the drive circuit;

[0016] The first isolation circuit includes a resistor R9, a resistor R10, a resistor R13, a resistor R15, a resistor R17, a resistor R18, a capacitor C4, a capacitor C6, a MOS tube VT1, a MOS tube VT2, and an isolation photoelectric coupler chip O1;

[0017] The connection relationship is: C6 and R17 are connected in parallel; the gate of VT2 is connected in series with one end of C6 and R18 respectively; the drain of VT2 is connected in series with R15 and the gate of VT1; R9 is connected in series with pin 1 of O1; pin 2 of O1 is connected in series with the drain of VT1; R10 is connected in series with pin 4 of O1; R13 and C4 are connected in parallel, and pin 3 of O1 is connected with R13 and C4;

[0018] The second isolation circuit includes a resistor R11, a resistor R12, a resistor R14, a resistor R16, a capacitor C5, a MOS tube VT3, and an isolation photocoupler chip O2.

[0019] The connection relationship is: the gate of VT3 is connected in series to R16; R11 is connected in series to pin 1 of O2; pin 2 of O2 is connected in series to the drain of VT3; R12 is connected in series to pin 4 of O2; R14 is connected in parallel to C5; pin 3 of O2 is connected to R14 and C5;

[0020] When pin 1 of comparator D1 outputs a high level and pin 7 of comparator D1 outputs a high level, the second isolation circuit outputs a high level and the first isolation circuit outputs a low level; when pin 1 of comparator D1 outputs a low level and pin 7 of comparator D1 outputs a high level, the second isolation circuit outputs a low level and the first isolation circuit outputs a high level; when pin 1 of comparator D1 outputs a low level and pin 7 of comparator D1 outputs a low level, the second isolation circuit outputs a low level and the first isolation circuit outputs a low level.

[0021] Preferably, the buck-boost capacitor charging and discharging circuit includes a boost circuit, a capacitor charging current limiting circuit, and a buck circuit;

[0022] The boost circuit includes a DC blocking capacitor C9, a capacitor C12, a capacitor C13, a capacitor C15, a capacitor C16, a resistor R26, a resistor R29, a resistor R33, a resistor R35, a resistor R36, a resistor R37, an inductor L1, an inductor L3, and a switching power supply chip D2;

[0023] The connection relationship is as follows: R35 is connected in parallel with C16 and then in series with R29, and as a whole is connected in parallel with capacitor C12; the midpoint of R35 and C16 connected in parallel and in series with R29 is connected to pin 2 of D2; one end of L1 is connected to R29, and the other end is connected to pin 3 of D2 and one end of C9; the other end of C9 is connected to one end of L3 and VD3; the other end of VD3 is connected to one end of R26 and C13; the other end of L3 is connected to one end of R37, one end of R36, and the other end of C13; one end of C15 is connected to the other end of R37, and the other end of C15 is connected to pin 5 of D2; R26 is connected in series with R33, and the other end of R33 is respectively connected to pin 6 of D2 and the other end of R36;

[0024] The capacitor charging current limiting circuit includes a resistor R23, a resistor R27 (used for current limiting, voltage stabilization, and anti-oscillation), a resistor R30, a resistor R34, a capacitor C10, a capacitor E2, a MOS tube VT5, and a MOS tube VT6;

[0025] The connection relationship is: one end of C10 and R27 connected in parallel is connected to one end of R23 and the source of VT5, and the other end is connected to the drain of VT6 and the gate of VT5; R30 is connected to R34 and the gate of VT6; the drain of VT5 is connected to the other end of R23 and E2;

[0026] When the voltage of the aluminum electrolytic capacitor E2 is lower than the threshold voltage, the switch VT5 is disconnected, and the current charges E2 through the current limiting resistor R23; when the voltage of the aluminum electrolytic capacitor E2 reaches the threshold voltage, the switch VT5 is closed, the current limiting resistor R23 is bypassed by the switch, and the current charges E2 through VT5;

[0027] The buck circuit supplies power to the driving circuit, the feedback circuit, and the power-off unlocking circuit, and includes resistor R24, resistor R25, resistor R28, resistor R31, resistor R32, capacitor C8, capacitor C11, capacitor C14, inductor L2, and switching power supply chip N1;

[0028] The connection relationship is: R25 and R31 are connected in series; R31 and C14 are connected in parallel; the midpoint of R25 and R31 in series is connected to pin 5 of N1, and the other end of R25 is connected to pin 3 of N1; C8 and R24 are connected in series, the other end of C8 is connected to pin 6 of N1, and the other end of R24 is connected to L2; the midpoint of R28 and R32 in series is connected to pin 4 of N1; L2 is connected to the other end of R28 and one end of C11, and the other end of C11 is connected to the other end of R32, C14, and the other end of R31.

[0029] Preferably, the feedback circuit is a circuit built based on an isolation optocoupler, the isolation front end is connected to the electronic lock dry contact signal end, and the isolation back end is connected in parallel to the drive signal end. The basic working logic is as follows:

[0030] When the electronic lock is unlocked, the dry contact is open. At this time, the level amplitude of the drive signal end is high. The controller configures the drive signal end as input, and confirms the state of the electronic lock by detecting the drive signal level; when the electronic lock is locked, the dry contact is short-circuited. At this time, the level amplitude of the drive signal end is low. The controller configures the drive signal end as input, and confirms the state of the electronic lock by detecting the drive signal level.

[0031] Preferably, the power-off unlocking circuit includes a resistor R22 and a MOS tube VT4;

[0032] The connection relationship is: R22 is connected to the gate of VT4;

[0033] When an abnormal power failure of the external power supply is detected, the output voltage of the second isolation circuit changes from a low level to a high level, and the electronic lock is automatically unlocked.

[0034] Preferably, the driving circuit is implemented by an H-bridge motor driving chip or an H-bridge circuit constructed by a MOS tube.

[0035] Beneficial technical effects of the present invention:

[0036] (1) The drive control signal adopts PWM signal, which has strong anti-interference ability and will not cause malfunction of the electronic lock;

[0037] (2) When debugging the program, set a program breakpoint when the electronic lock drives the locking / unlocking logic. The PWM can have no output and will not cause damage to the electronic lock.

[0038] (3) When the auxiliary power source of the charging device loses power abnormally, the electronic lock is unlocked through the buck-boost capacitor charging and discharging circuit;

[0039] (4) There is only one control feedback signal line, which occupies less resources and simplifies the external design. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] Figure 1 This is a schematic diagram of the level conversion circuit of the present invention.

[0041] Figure 2 This is a schematic diagram of the logic control circuit of the present invention.

[0042] Figure 3 This is a schematic diagram of the isolation circuit of the present invention.

[0043] Figure 4 The figure is a general schematic diagram of the buck-boost capacitor charging and discharging circuit of the present invention.

[0044] Figure 5 This is a schematic diagram of the boost circuit of the present invention.

[0045] Figure 6This is a schematic diagram of the capacitor charging current limiting circuit of the present invention.

[0046] Figure 7 This is a schematic diagram of the buck circuit described in the present invention.

[0047] Figure 8 This is a schematic diagram of the feedback circuit of the present invention.

[0048] Fig. 9 This is a schematic diagram of the power-off unlocking circuit of the present invention.

[0049] Fig.10 This is a schematic diagram of the driving circuit of the present invention.

[0050] Fig.11 It is a general schematic diagram of the present invention. DETAILED DESCRIPTION

[0051] In order to make the purpose, technical solution and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and do not limit the present invention.

[0052] Example: Fig.11 As shown, an electronic lock circuit for a car charging device includes a level conversion circuit, a logic control circuit, an isolation circuit, a buck-boost capacitor charging and discharging circuit, a power-off unlocking circuit, a feedback circuit, and a driving circuit.

[0053] like Figure 1 As shown in the figure, the principle of the level conversion circuit is: when LOCK_A inputs a PWM signal, it passes through the current limiting resistor R4 and is transmitted to the front end of the capacitor C2 that isolates the DC and conducts the AC; the AC signal passes through C2 and is connected to the anti-reverse diode VD1. At this time, VD1 has two working processes according to the signal state:

[0054] (1) When the current PWM signal is at a high level, the level of C2 is left + (3.3V) and right -, the capacitor is charged, and the high-level signal passes through C2 and the VD1 forward diode to charge C3;

[0055] (2) When the current PWM signal is at a low level, the level of C2 is left + (0V) and right -, the capacitor is discharged, and the low level signal passes through C2 and the VD1 reverse diode to discharge C3.

[0056] In this process, because C3 is not completely discharged within a unit cycle, the remaining voltage will keep C3 within a stable level amplitude range; R6 is used to balance the voltage on C3; when PWM stops, the charge of C3 capacitor can be discharged through R6.

[0057] Figure 2For the logic control circuit, R2 and R7 are connected in series to +3.3V, and the midpoint can output +2.5V through voltage division; similarly, R3 and R8 are connected in series to +3.3V, and the midpoint can output +1.2V through voltage division; when Figure 1 When LOCK_A inputs a PWM signal, COMP_A outputs a voltage value; at this time, the COMP_A signal is connected to the 3 and 5 PIN pins of D1. According to the working logic of the comparator (when the +INX level is higher than -INX, OUTX outputs a high level, otherwise it outputs a low level; the resistors R1 and R5 in the figure are pull-up resistors, which can improve the driving capability; C1 is the decoupling capacitor of the chip D1 circuit), the output logic of LOCK_A1 and LOCK_A2 is shown in the following table:

[0058] Table 1 LOCK_A, COMP_A, LOCK_A1, LOCK_A2 logic comparison table

[0059] Serial number LOCK_A / Frequency value COMP_A / voltage value LOCK_A1 / Logical value LOCK_A2 / Logical value 1 0 0 0 0 2 5kHz +1.5V±0.1V 0 1 3 10kHz +3.0V±0.1V 1 1

[0060] 5kHz and 10kHz are a set of test data, which can be adjusted according to different working conditions.

[0061] like Figure 3 As shown, the isolation circuit outputs the logic state in Table 1 to the isolation backend through the conversion circuit and its optocoupler. The working logic of O1 is as follows:

[0062] (1) When LOCK_A2 input is low level and LOCK_A1 input is low level, the gate of PMOS VT2 is low level, and PMOSV GS The voltage is 0V, PMOSDS is cut off, the gate voltage of VT1 is low and cut off, the light-emitting diode at the source end of the O1 optocoupler loses power, the collector and emitter at the secondary end of the O1 optocoupler are cut off, and LOCK_A_2 outputs a low level; drop_ctrl outputs a high level through the pull-up resistor R10;

[0063] (2) When LOCK_A2 input is high level and LOCK_A1 input is low level, the gate of PMOS VT2 is low level, and PMOSV GS , the voltage of the voltage-stabilizing resistor R15 is +3.3V, PMOSDS is turned on, the gate voltage of VT1 is high and DS is turned on, +3.3V is supplied to the light-emitting diode at the source end of the O1 optocoupler through the current-limiting resistor R9, the collector and emitter of the secondary end of the O1 optocoupler are turned on, and +12V passes through the voltage-dividing resistors R10 and R13 (the parallel capacitor C4 plays a role in stabilizing the output), so that LOCK_A_2 outputs a high level; drop_ctrl outputs a high level;

[0064] (3) When LOCK_A2 input is high level and LOCK_A1 input is high level, after R17 (parallel capacitor C6 plays the role of voltage stabilization output) and R18 resistor series voltage division, the gate of PMOS VT2 is high level, and PMOSV GS The voltage is 0V, PMOSDS is cut off, the gate voltage of VT1 is low and DS is cut off, the light-emitting diode at the source end of the O1 optocoupler loses power, the collector and emitter at the secondary end of the O1 optocoupler are cut off, LOCK_A_2 outputs a low level; drop_ctrl outputs a high level through the pull-up resistor R10.

[0065] To summarize the above working logic, the logic comparison table of LOCK_A1, LOCK_A2, LOCK_A_2, and drop_ctrl is as follows:

[0066] Table 2 LOCK_A1, LOCK_A2, LOCK_A_2, drop_ctrl logic comparison table

[0067]

[0068]

[0069] The working logic of O2 is as follows:

[0070] (1) When LOCK_A1 inputs a high level, the voltage of the VT3 gate and the voltage regulator resistor R16 is high and DS is turned on. +3.3V is supplied to the light-emitting diode at the source end of the O2 optocoupler through the current limiting resistor R11, and the collector and emitter of the secondary end of the O2 optocoupler are turned on. +12V passes through the voltage divider resistors R12 and R14 (the parallel capacitor C5 plays a role in voltage regulation output), so that LOCK_A_1 outputs a high level;

[0071] (2) When LOCK_A1 inputs a low level, the gate voltage of VT3 is low and DS is cut off, the light-emitting diode at the source end of the O2 optocoupler loses power, the collector and emitter at the secondary end of the O2 optocoupler are cut off, and LOCK_A_1 outputs a low level.

[0072] To summarize the above working logic, the LOCK_A1 and LOCK_A_1 logic comparison table is as follows:

[0073] Table 3 LOCK_A1, LOCK_A_1 logic comparison table

[0074] Serial number LOCK_A1 / Logical value LOCK_A_1 / Logical value 1 0 0 2 1 1

[0075] Summary Tables 1 to 3, LOCK_A1, LOCK_A_1, LOCK_A_2 logic comparison table is as follows:

[0076] Table 4 LOCK A1, LOCK A 1, LOCK A 2 logic comparison table

[0077] Serial number LOCK_A / Frequency value LOCK_A_1 / Logical value LOCK_A_2 / Logical value 1 0 0 0 2 5kHz 0 1 3 10kHz 1 0

[0078] 5kHz and 10kHz are a set of test data, and this parameter can be adjusted according to different application conditions;

[0079] According to the above logic comparison table, different logic outputs of LOCK_A_1 and LOCK_A_2 can be achieved at different frequencies. When debugging the program, it can be achieved that after the interruption, PWM has no output, which will not cause damage to the electronic lock.

[0080] Figures 4 to 7 It is a buck-boost capacitor charging and discharging circuit, including a boost circuit built around D2, a capacitor current-limiting charging circuit built around VT5, VT6, and E2, and a buck circuit built around N1;

[0081] Boost circuit principle:

[0082] After the power supply DCP12V+ is stabilized by C12, it is divided in series by R29 and R35, and then stabilized by C16 before being given to the EN enable pin of the boost chip; DCP12V+ is connected to the SW end of the boost chip through the energy storage inductor L1, and is also connected to the boot capacitor. The boot capacitor can be current-limited by the L3 inductor, and can also output voltage when the boost drive output; C15 and R37 are connected in series for boost frequency regulation; after R26, R33, and R36 are divided in series, the midpoint of the voltage division between R33 and R36 is connected to D2 FB, which mainly plays a role in voltage feedback regulation; VD3 is a voltage anti-reverse function, and a stable voltage output can be achieved through the voltage stabilizing filter capacitor C13;

[0083] Capacitor current limiting charging circuit principle:

[0084] S1, when DCP12V+ is first powered on, the current voltage of E2 is 0V, the gate voltage of NMOS VT6 is 0V, the DS channel of VT6 is cut off, and the gate voltage of VT5 PMOS is DCP12V+ and cut off due to the voltage stabilizing capacitor C10 and the parallel resistor R27. At this time, the current charges the capacitor E2 through the current limiting resistor R23;

[0085] S2, when the E2 capacitor voltage rises to the threshold point, that is, the voltage divider value VCAP of the series resistors R30 and R34 exceeds the VT6 NMOS gate turn-on voltage, VT6 is turned on, at this time the VT5 gate is pulled to a low level, VT5 is turned on, and the current passes through VT5 to charge the capacitor.

[0086] Buck circuit principle:

[0087] The VCAP voltage is divided by R25 and R31, and the midpoint of the voltage division is stabilized by C14 and then given to the EN pin of N1; VCAP is connected to the input pin VIN of N1; C8 is the boost startup capacitor, R24 is the current limiting resistor; L2 is the buck energy storage inductor; after R28 and R32 are connected in series, the midpoint of the voltage division is connected to the feedback pin FB of N1, which mainly plays a role in voltage feedback regulation; the voltage is stabilized and filtered by C11, and the output is +12V;

[0088] Combined with the principle of capacitor current limiting charging circuit, the working process of buck-boost capacitor charging and discharging circuit is as follows:

[0089] S1, when powered on for the first time, the boost circuit starts softly, and charges the capacitor E2 through the current limiting resistor R23; when the voltage of E2 meets the threshold voltage, VT5 is turned on, and E2 is quickly charged; during this process, when the voltage of the EN terminal of N1 reaches the turn-on voltage, the N1buck circuit starts softly, and outputs a 12V power supply;

[0090] S2, when the electronic lock is activated, E1( Figure 8 ) discharges first, and E2 serves as the main energy storage end to power the buck circuit. At the same time, the boost circuit will also share part of the current to charge E2. When the voltage amplitude of E2 drops below the threshold, VT5 is cut off, and the boost circuit continues to charge capacitor E2 through R23.

[0091] S3, when the electronic lock action ends, E2 continues to charge until it is fully charged.

[0092] Note: The E2 capacitance value needs to be calculated based on the electronic lock drive power consumption. To reduce the ESR loss of a single E2, multiple groups of capacitors can be connected in parallel.

[0093] Figure 8 It is a feedback circuit, the principle is as follows:

[0094] (1) When the XS1 resistor lock dry contact is open, the O5 source end light emitting diode is open, the secondary end collector emitter is cut off, and the +3.3V voltage is given to LOCK_A1 through R20 and VD2. At this time, the controller sets the current pin as the input detection pin and can detect that LOCK_A1 is a high level signal;

[0095] (2) When the XS1 resistor lock dry contact is short-circuited, +12VD passes through the current limiting resistor R21, causing the O5 source end light emitting diode to turn on, and the secondary end collector emitter to turn on. +3.3VD passes through the pull-up resistor R20, causing the right end of VD2 to be at a low level, and the anti-reverse diode VD2 to be cut off; LOCK_A1 pulls the pin level to a low level through R39. At this time, when the controller sets the current pin to an input pin, it can detect that LOCK_A1 is a low level signal.

[0096] Among them, the resistance values ​​of R20 and R39 need to be more than ten kilo-ohms, and the ratio of R20:R39 needs to be configured in a ratio of 1:20 to 40.

[0097] Fig. 9 It is a power-off unlocking circuit. When DCP12V+ experiences an abnormal power failure, the communication between the charging device and the vehicle-side BMS CAN is interrupted, and the car stops charging. At this time, the electronic lock is unlocked, and the user can pull out the gun. The specific principle is: when the device is in normal charging / standby state, DCP12V+ gives a high level to the VT4 gate through the current limiting resistor R22, and VT4 is cut off and does not act; when DCP12V+ experiences an abnormal power failure, the VT4 gate is at a low level, the PMOS is turned on, LOCK_A_1 is at a high level, and LOCK_A_2 is at a low level. According to the working logic of the isolation circuit, the current electronic lock is unlocked; because this unlocking process is a complete discharge of E2, the stored energy can maintain the unlocking of the electronic lock and is consumed, and will not cause overheating and damage to the electronic lock.

[0098] Fig.10 It is an H-bridge driving circuit. This circuit can use a chip or NMOS to build an H-bridge circuit.

[0099] The above embodiments are descriptions of specific implementation methods of the present invention rather than limitations of the present invention. Technical personnel in the relevant technical field may make various changes and modifications to obtain corresponding equivalent technical solutions without departing from the spirit and scope of the present invention. Therefore, all equivalent technical solutions should be included in the patent protection scope of the present invention.

Claims

1. An electronic lock circuit for a car charging device, comprising a drive circuit and a feedback circuit, characterized in that: It also includes a level conversion circuit, a logic control circuit, an isolation circuit, a buck-boost capacitor charging and discharging circuit, and a power-off unlocking circuit; The connection relationship is: the controller is connected to the level conversion circuit; the level conversion circuit is connected to the logic control circuit; the logic control circuit is connected to the isolation circuit; the isolation circuit is connected to the drive circuit; the drive circuit is connected to the electronic lock drive port; the electronic lock feedback port is connected to the feedback circuit; the feedback circuit is connected to the controller; the buck-boost capacitor charging and discharging circuit is connected to the power-off unlocking circuit; the power-off unlocking circuit is connected to the isolation circuit; and the drive circuit is connected to the electronic lock drive port.

2. The electronic lock circuit of a vehicle charging device according to claim 1, characterized in that: The level conversion circuit includes a resistor R4, a capacitor C2, a switching diode VD1, a capacitor C3, and a resistor R6; The connection relationship is: R4 is connected in series with C2, C2 is connected in series with pin 3 of VD1, pins 1 and 2 of VD1 are connected in series with both ends of C3 respectively, and R6 is connected in parallel with both ends of C3; The PWM signal output by the controller is converted into an absolute AC signal output through the capacitor C2 that isolates the DC. The energy storage capacitor C3 and the discharge resistor R6 effectively maintain a voltage level without dropping, thereby achieving frequency / voltage conversion.

3. The electronic lock circuit of a car charging device according to claim 1, characterized in that: The logic control circuit includes resistors R1, R2, R3, R5, R7, R8, capacitor C1, and comparator D1; The connection relationship is as follows: R2 and R7 are connected in series, the midpoint of the two is connected to the No. 2 pin of D1, the other end of R2 is connected to the +3.3V power supply, and the other end of R7 is grounded; R3 and R8 are connected in series, the midpoint of the two is connected to the No. 6 pin of D1, the other end of R3 is connected to the +3.3V power supply, and the other end of R8 is grounded; the No. 2 pin of the switching diode VD1 of the level conversion circuit is connected to the No. 3 and No. 5 pins of D1; R1 is connected to the No. 1 pin of D1, and R5 is connected to the No. 7 pin of D1; C1 is connected to the No. 8 pin of D1; The logic control circuit uses two comparators to ensure different output logics under different voltage amplitudes.

4. The electronic lock circuit of a car charging device according to claim 1, characterized in that: The isolation circuit includes a first isolation circuit and a second isolation circuit; The connection relationship is as follows: the output end of the logic control circuit is connected in series to the input end of the first isolation circuit and the second isolation circuit; the output end of the first isolation circuit and the second isolation circuit is connected in series to the input end of the drive circuit; The first isolation circuit includes a resistor R9, a resistor R10, a resistor R13, a resistor R15, a resistor R17, a resistor R18, a capacitor C4, a capacitor C6, a MOS tube VT1, a MOS tube VT2, and an isolation photoelectric coupler chip O1; The connection relationship is: C6 and R17 are connected in parallel; the gate of VT2 is connected in series with one end of C6 and R18 respectively; the drain of VT2 is connected in series with R15 and the gate of VT1; R9 is connected in series with pin 1 of O1; pin 2 of O1 is connected in series with the drain of VT1; R10 is connected in series with pin 4 of O1; R13 and C4 are connected in parallel, and pin 3 of O1 is connected with R13 and C4; The second isolation circuit includes a resistor R11, a resistor R12, a resistor R14, a resistor R16, a capacitor C5, a MOS tube VT3, and an isolation photocoupler chip O2. The connection relationship is: the gate of VT3 is connected in series to R16; R11 is connected in series to pin 1 of O2; pin 2 of O2 is connected in series to the drain of VT3; R12 is connected in series to pin 4 of O2; R14 is connected in parallel to C5; pin 3 of O2 is connected to R14 and C5; When pin 1 of comparator D1 outputs a high level and pin 7 of comparator D1 outputs a high level, the second isolation circuit outputs a high level and the first isolation circuit outputs a low level; when pin 1 of comparator D1 outputs a low level and pin 7 of comparator D1 outputs a high level, the second isolation circuit outputs a low level and the first isolation circuit outputs a high level; when pin 1 of comparator D1 outputs a low level and pin 7 of comparator D1 outputs a low level, the second isolation circuit outputs a low level and the first isolation circuit outputs a low level.

5. The electronic lock circuit of a car charging device according to claim 1, characterized in that: The buck-boost capacitor charging and discharging circuit includes a boost circuit, a capacitor charging current limiting circuit, and a buck circuit; The boost circuit includes capacitor C9, capacitor C12, capacitor C13, capacitor C15, capacitor C16, resistor R26, resistor R29, resistor R33, resistor R35, resistor R36, resistor R37, inductor L1, inductor L3, and switching power supply chip D2; The connection relationship is as follows: R35 is connected in parallel with C16 and then in series with R29, and as a whole is connected in parallel with capacitor C12; the midpoint of R35 and C16 connected in parallel and in series with R29 is connected to pin 2 of D2; one end of L1 is connected to R29, and the other end is connected to pin 3 of D2 and one end of C9; the other end of C9 is connected to one end of L3 and VD3; the other end of VD3 is connected to one end of R26 and C13; the other end of L3 is connected to one end of R37, one end of R36, and the other end of C13; one end of C15 is connected to the other end of R37, and the other end of C15 is connected to pin 5 of D2; R26 is connected in series with R33, and the other end of R33 is respectively connected to pin 6 of D2 and the other end of R36; The capacitor charging current limiting circuit includes a resistor R23, a resistor R27, a resistor R30, a resistor R34, a capacitor C10, a capacitor E2, a MOS tube VT5, and a MOS tube VT6; The connection relationship is: one end of C10 and R27 connected in parallel is connected to one end of R23 and the source of VT5, and the other end is connected to the drain of VT6 and the gate of VT5; R30 is connected to R34 and the gate of VT6; the drain of VT5 is connected to the other end of R23 and E2; When the voltage of the aluminum electrolytic capacitor E2 is lower than the threshold voltage, the switch VT5 is disconnected, and the current charges E2 through the current limiting resistor R23; when the voltage of the aluminum electrolytic capacitor E2 reaches the threshold voltage, the switch VT5 is closed, the current limiting resistor R23 is bypassed by the switch, and the current charges E2 through VT5; The buck circuit supplies power to the driving circuit, the feedback circuit, and the power-off unlocking circuit, and includes resistor R24, resistor R25, resistor R28, resistor R31, resistor R32, capacitor C8, capacitor C11, capacitor C14, inductor L2, and switching power supply chip N1; The connection relationship is: R25 and R31 are connected in series; R31 and C14 are connected in parallel; the midpoint of R25 and R31 in series is connected to pin 5 of N1, and the other end of R25 is connected to pin 3 of N1; C8 and R24 are connected in series, the other end of C8 is connected to pin 6 of N1, and the other end of R24 is connected to L2; the midpoint of R28 and R32 in series is connected to pin 4 of N1; L2 is connected to the other end of R28 and one end of C11, and the other end of C11 is connected to the other end of R32, C14, and the other end of R31.

6. The electronic lock circuit of a car charging device according to claim 1, characterized in that: The feedback circuit is a circuit built based on an isolated optocoupler. The isolation front end is connected to the electronic lock dry contact signal end, and the isolation back end is connected in parallel to the drive signal end. The basic working logic is as follows: When the electronic lock is unlocked, the dry contact is open. At this time, the level amplitude of the drive signal end is high. The controller configures the drive signal end as input, and confirms the state of the electronic lock by detecting the drive signal level; when the electronic lock is locked, the dry contact is short-circuited. At this time, the level amplitude of the drive signal end is low. The controller configures the drive signal end as input, and confirms the state of the electronic lock by detecting the drive signal level.

7. The electronic lock circuit of a vehicle charging device according to claim 1, characterized in that: The power-off unlocking circuit includes a resistor R22 and a MOS tube VT4; The connection relationship is: R22 is connected to the gate of VT4; When an abnormal power failure of the external power supply is detected, the output voltage of the second isolation circuit changes from a low level to a high level, and the electronic lock is automatically unlocked.

8. The electronic lock circuit of a car charging device according to claim 1, characterized in that: The driving circuit is implemented by an H-bridge motor driving chip or an H-bridge circuit built with a MOS tube.

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