Ultra-wideband high-efficiency distributed power amplifier with reconfigurable frequency band

Abstract

The invention discloses an ultra-wideband high-efficiency distributed power amplifier with a reconfigurable frequency band, and belongs to the technical field of wireless communication. The device comprises a plurality of power units, a drain traveling wave line, a gate traveling wave line, a drain bias circuit and a gate bias circuit, wherein reconfigurable terminal loads are loaded in the drain traveling wave line and the gate traveling wave line. According to the distributed power amplifier, the reconfigurable terminal loads are loaded on the grid traveling wave line and the drain traveling wave line, so that the power amplifier is reconfigured to a high-frequency band, and the high-frequency efficiency of the distributed power amplifier in an ultra wide band is effectively improved; secondly, a multi-layer stacked transistor with a Peaking inductor is adopted as a power unit, so that the gain and the high-frequency efficiency of the device are improved; and finally, by adopting a plurality of unequal-weight power units and non-uniform traveling wave lines, a non-uniform distributed architecture is formed, the impedance matching condition of each power unit is improved, and the overall output power and efficiency of the distributed power amplifier in an ultra wide band are improved.

Description

Technical Field

[0001] The invention belongs to the technical field of wireless communications, and in particular relates to an ultra-wideband high-efficiency distributed power amplifier with reconfigurable frequency band. Background Art

[0002] With the further development of communication technology, the current military and civilian aircraft, ship radar communication systems and electronic warfare systems have put forward higher requirements on the performance of the RF front-end system. As the core component of the final stage of the transmission system and the main DC power consumer, the power amplifier has important performance requirements in this context, such as ultra-wideband, high power, high efficiency, multi-frequency and multi-mode configurability. Therefore, the research on the reconfigurable ultra-wideband high-efficiency power amplifier architecture has important strategic value for the development of my country's future military equipment and civilian facilities.

[0003] The core feature of the distributed amplifier is to achieve ultra-wideband operation by absorbing transistor parasitic capacitance through artificial transmission lines. Compared with other broadband power amplifier technologies, it has an incomparable and significant advantage in expanding the working bandwidth. However, its low output power and efficiency have been its main shortcomings that have not been solved for a long time, which is contrary to its potential application demand as a power amplifier for radar transmission systems. One of the main reasons for this problem is the lack of a complete quantitative analysis of the impact of active load modulation in the distributed architecture, which makes it almost impossible to match the transistor load impedance of each gain unit, and ultimately the overall efficiency of the power amplifier is significantly low. In addition, the fixed traveling wave line structure cannot solve the large-scale variation of transistor parasitic capacitance within the ultra-wideband, which is another important factor that leads to the decline in its average efficiency within the band. Summary of the invention

[0004] In view of the problems existing in the background technology, the present invention provides a high-efficiency distributed power amplifier with reconfigurable frequency band and ultra-wideband. The amplifier uses a reconfigurable terminal load on the traveling wave line, which effectively solves the problem of reduced high-frequency efficiency in the ultra-wideband of the distributed power amplifier; in addition, the present invention uses multi-layer stacked transistors with peaking inductors as power units, and uses power units with different weights to form a non-uniform distributed architecture, which effectively improves the overall output power and efficiency of the power amplifier.

[0005] To achieve the above object, the technical solution of the present invention is as follows:

[0006] A frequency band reconfigurable ultra-wideband high-efficiency distributed power amplifier comprises n power units, a drain traveling wave line, a gate traveling wave line, a drain bias circuit and a gate bias circuit.

[0007] The gate traveling wave line comprises an input terminal, an input DC blocking capacitor, (n+1) gate inductors, and a gate reconfigurable terminal load connected in series in sequence;

[0008] The drain traveling wave line comprises a drain reconfigurable terminal load, (n+1) drain inductors, an output DC blocking capacitor, and an output end connected in series in sequence;

[0009] The input end of the power unit is connected to the node between adjacent gate inductors, and the output end is connected to the node between adjacent drain inductors. The n power units are connected in parallel in sequence to form a distributed architecture.

[0010] The RF power is input from the input end, distributed to each power unit through the gate traveling wave line for power amplification, and the amplified RF power is collected on the drain traveling wave line and output from the output end.

[0011] Furthermore, the input end and the output end are not on the same side of the power amplifier.

[0012] Furthermore, the drain reconfigurable terminal load and the gate reconfigurable terminal load have the same structure, both consisting of a resistor, an inductor, a ground-blocking capacitor, and two switches; wherein one end of the ground-blocking capacitor is grounded, and the other end is connected to the drain inductor or the gate inductor through a resistor; the inductor is arranged in parallel with the resistor, and the two switches are arranged at both ends of the inductor;

[0013] When the power amplifier operates in the low frequency band, the switch is disconnected and the reconfigurable terminal load is a pure resistor; when the power amplifier operates in the high frequency band, the switch is closed and the reconfigurable terminal load forms an equivalent bandpass characteristic, absorbing the increased transistor parasitic capacitance of the power unit under high frequency, effectively improving the efficiency of the power amplifier in the high frequency band, thereby realizing reconstruction to the high frequency band.

[0014] Furthermore, the switch is a transistor switch.

[0015] Furthermore, the n power units all adopt a multi-layer stacked transistor structure with Peaking inductors to improve gain and high-frequency efficiency, and the weights of the n power units are not exactly the same (ie, the transistor widths are not exactly the same).

[0016] Furthermore, the inductance values ​​of the (n+1) drain inductors are not completely the same, and at the same time, the inductance values ​​of the (n+1) gate inductors are not completely the same; the inductance values ​​of the drain inductor and the gate inductor are jointly determined by the parasitic capacitance of adjacent power units and the optimal load impedance, so that the characteristic impedance of the artificial transmission line formed by the parasitic capacitance of each power unit and the adjacent inductor gradually decreases from the input end side to the output end side, and better impedance matching is achieved for each power unit under the premise of achieving ultra-wideband, thereby improving the overall output power and efficiency of the power amplifier.

[0017] Furthermore, n is a positive integer greater than or equal to 2.

[0018] Furthermore, the drain bias circuit is composed of an inductor or multiple inductors connected in parallel; one end of the inductor is connected to the drain bias voltage, and the other end is connected to the drain traveling wave line, providing a bias voltage for the transistor drain in the power unit.

[0019] Furthermore, the gate bias circuit is composed of a resistor; one end of the resistor is connected to the gate bias voltage, and the other end is connected to the gate traveling wave line, so as to provide a bias voltage for the transistor gate in the power unit.

[0020] In summary, due to the adoption of the above technical solution, the beneficial effects of the present invention are:

[0021] The present invention firstly uses a reconfigurable terminal load on the traveling wave line to realize the reconstruction of the power amplifier to the high frequency band, effectively improving the high frequency efficiency of the distributed power amplifier in the ultra-wideband; secondly, by using multi-layer stacked transistors with peaking inductors as power units, the gain and high frequency efficiency of the power unit are improved; finally, by using multiple non-equally weighted power units and non-uniform traveling wave lines, a non-uniform distributed architecture is formed, the impedance matching of each power unit is improved, and the overall output power and efficiency of the distributed power amplifier in the ultra-wideband are improved. Combining the above three points, a high-efficiency distributed power amplifier with reconfigurable frequency band is realized. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 The system block diagram of the ultra-wideband high-efficiency distributed power amplifier with reconfigurable frequency band of the present invention.

[0023] Figure 2 1 is an overall circuit diagram of a reconfigurable ultra-wideband high-efficiency distributed power amplifier in an embodiment of the present invention.

[0024] Figure 3 Schematic diagram of the structure of the power unit in the embodiment of the present invention.

[0025] Figure 4 Schematic diagram of the structure of the drain traveling wave line in the embodiment of the present invention.

[0026] Figure 5 Schematic diagram of the structure of the gate traveling wave line in the embodiment of the present invention.

[0027] Figure 6 This is a diagram showing the power added efficiency simulation results of the reconfigurable ultra-wideband high-efficiency distributed power amplifier in an embodiment of the present invention. DETAILED DESCRIPTION

[0028] To make the purpose, technical solution and advantages of the present invention clearer, the present invention is further described in detail below in conjunction with the embodiments and drawings. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.

[0029] This embodiment provides a 2-18 GHz reconfigurable ultra-wideband high-efficiency distributed power amplifier based on a 65nm CMOS process, including four power units, a drain traveling wave line, a gate traveling wave line, a drain bias circuit, and a gate bias circuit. The overall architecture is as follows: Figure 2 shown.

[0030] In this embodiment, the four power units all use a three-layer stacked transistor structure with a Peaking inductor, such as Figure 3 As shown, it includes three transistors Q1-Q3 and two peaking inductors L P1 and L P2 The three-layer stacked transistors improve the gain of the power unit, while the Peaking inductor weakens the high-frequency parasitic capacitance of the upper transistor, reduces the leakage of high-frequency energy, and improves the high-frequency gain of the power unit.

[0031] The four power units have two weights in total. The power unit close to the input end is a high-weight unit, and the width of Q1-Q3 transistors is 192μm; the other three are low-weight units, and the width of Q1-Q3 transistors is 128μm.

[0032] The drain traveling wave line, such as Figure 4 As shown, it includes a drain reconfigurable terminal load, five inductors L connected in series. D1 ~L D5 、An output DC blocking capacitor C DC2 The characteristic admittance G of the artificial transmission line formed by these five drain inductors and the parasitic capacitance of the transistors of the adjacent power units is ATL,n (n=1,2,3,4) must satisfy the following relationship to form a non-uniform distributed architecture with good impedance matching:

[0033]

[0034] Among them, G opt,n (n=1,2,3,4) is the optimal load admittance of the four power units, G L is the load admittance of the entire power amplifier. In this embodiment, L D1 =911pH,L D2 =1213pH,L D3 =715pH,L D 4=332pH,L D5 =98pH.

[0035] The drain is reconstructed into a terminal load, consisting of a resistor R D , a transistor switch Q SW1 and Q SW2 Controlled shunt inductance L D , a DC-blocking capacitor C to ground DC1 Composition, transistor switch Q SW1 and Q SW2 It is controlled by an external voltage connected to its gate. D The value of satisfies R D =1 / (G opt,1 -G ATL,1 ), parallel inductance L D The value satisfies ωL D Less than R D 10% of the angular frequency. D =597Ω, L D =600pH.

[0036] like Figure 5 As shown, the gate wave line includes an input terminal, an input DC isolation capacitor C connected in series D C3 , 5 gate inductors L G1 ~L G5 , gate reconfigurable terminal load; in this embodiment, L G1 =240pH,L G2 =L G3 =L G4 =492pH,L G5 =232pH.

[0037] The gate reconfigurable terminal load consists of a resistor R G , a transistor switch Q SW3 and Q SW4 Controlled shunt inductance L G , a DC-blocking capacitor C to ground DC4 Composition, transistor switch Q SW3 and Q SW4 The working mechanism of the gate reconfigurable terminal load is basically the same as that of the drain reconfigurable terminal load. In this embodiment, the resistor R G Directly take 50Ω and connect inductor L in parallel G Take 243pH.

[0038] The drain bias circuit includes two parallel inductors L BD1 and L BD2 , the inductance of the two inductors is 5.7nH; the inductor L BD1 and L BD2One end is connected to the drain bias voltage, and the other end is connected to the inductance L of the drain traveling wave line. D1 and inductor L D2 , and the inductor L D3 and inductor L D4 The double connection point also effectively reduces the DC loss on the drain traveling wave line, thus improving the overall efficiency of the power amplifier to a certain extent.

[0039] The gate bias circuit contains a 3.9kΩ resistor R BG ; Resistance R BG One end is connected to the gate bias voltage, and the other end is connected to the inductor L of the gate traveling wave line G4 and inductor L G5 Between, provide gate bias voltage for power unit transistor.

[0040] Under the above settings, when the transistor switch is disconnected, the power amplifier has a higher efficiency in the low frequency band (2-9 GHz in this embodiment); when the transistor switch is closed, an equivalent bandpass characteristic is achieved, the frequency band is switched to high frequency, and the power amplifier has a higher efficiency in the high frequency band (9-18 GHz in this embodiment).

[0041] The simulation results in the simulation software ADS are as follows Figure 6 As shown, when the switch is disconnected (low-frequency mode), the power amplifier has a saturated output power of 19.2-20.2dBm and a saturated power added efficiency (PAE) of 31%-35% at 2-9GHz; when the switch is closed (high-frequency mode), the power amplifier has a saturated output power of 18.3-19.9dBm and a power added efficiency of 23%-31% at 9-18GHz, which is a maximum improvement of 10 percentage points compared to the low-frequency mode.

[0042] The above description is only a specific implementation mode of the present invention. Any feature disclosed in this specification, unless otherwise stated, can be replaced by other alternative features that are equivalent or have similar purposes; all the disclosed features, or all the steps in the methods or processes, except for mutually exclusive features and / or steps, can be combined in any way.

Claims

1. A band-reconfigurable ultra-wideband high-efficiency distributed power amplifier, characterized in that: It includes n power units, a drain traveling wave line, a gate traveling wave line, a drain bias circuit, and a gate bias circuit; The gate traveling wave line comprises an input terminal, an input DC blocking capacitor, (n+1) gate inductors, and a gate reconfigurable terminal load connected in series in sequence; The drain traveling wave line comprises a drain reconfigurable terminal load, (n+1) drain inductors, an output DC blocking capacitor, and an output end connected in series in sequence; The input end of the power unit is connected to the node between adjacent gate inductors, and the output end is connected to the node between adjacent drain inductors. The n power units are connected in parallel in sequence to form a distributed architecture. The RF power is input from the input end, distributed to each power unit through the gate traveling wave line for power amplification, and the amplified RF power is collected on the drain traveling wave line and output from the output end.

2. The band-reconfigurable ultra-wideband high-efficiency distributed power amplifier according to claim 1, characterized in that: The drain reconfigurable terminal load and the gate reconfigurable terminal load have the same structure, and are both composed of a resistor, an inductor, a DC-blocking capacitor to ground, and two switches; wherein one end of the DC-blocking capacitor to ground is grounded, and the other end is connected to the drain inductor or the gate inductor through a resistor; the inductor is arranged in parallel with the resistor, and the two switches are arranged at both ends of the inductor; When the power amplifier operates in the low frequency band, the switch is disconnected and the reconfigurable terminal load is a pure resistor; when the power amplifier operates in the high frequency band, the switch is closed and the reconfigurable terminal load forms an equivalent bandpass characteristic, absorbing the increased transistor parasitic capacitance of the power unit at high frequency and realizing reconstruction to the high frequency band.

3. The band-reconfigurable ultra-wideband high-efficiency distributed power amplifier according to claim 2, characterized in that: The input terminal and the output terminal are not on the same side of the power amplifier.

4. The band-reconfigurable ultra-wideband high-efficiency distributed power amplifier according to claim 3, characterized in that: The switch is a transistor switch.

5. The band-reconfigurable ultra-wideband high-efficiency distributed power amplifier according to claim 3 or 4, characterized in that: The n power units all adopt a multi-layer stacked transistor structure with a Peaking inductor to improve gain and high-frequency efficiency, and the weights of the n power units are not exactly the same.

6. The band-reconfigurable ultra-wideband high-efficiency distributed power amplifier according to claim 5, characterized in that: The inductance values ​​of the (n+1) drain inductors are not completely the same, and at the same time, the inductance values ​​of the (n+1) gate inductors are not completely the same; the inductance values ​​of the drain inductors and the gate inductors are jointly determined by the parasitic capacitance of adjacent power units and the optimal load impedance, so that the characteristic impedance of the artificial transmission line formed by the parasitic capacitance of each power unit and the adjacent inductors gradually decreases from the input end side to the output end side, and better impedance matching is achieved for each power unit under the premise of achieving ultra-wideband, thereby improving the overall output power and efficiency of the power amplifier.

7. The band-reconfigurable ultra-wideband high-efficiency distributed power amplifier according to claim 6, characterized in that: n is a positive integer greater than or equal to 2.

8. The band-reconfigurable ultra-wideband high-efficiency distributed power amplifier according to claim 7, characterized in that: The drain bias circuit is composed of an inductor or multiple inductors connected in parallel; one end of the inductor is connected to the drain bias voltage, and the other end is connected to the drain traveling wave line, providing a bias voltage for the transistor drain in the power unit.

9. The band-reconfigurable ultra-wideband high-efficiency distributed power amplifier according to claim 8, characterized in that: The gate bias circuit is composed of a resistor; one end of the resistor is connected to the gate bias voltage, and the other end is connected to the gate traveling wave line, so as to provide a bias voltage for the transistor gate in the power unit.

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