Rubidium atomic clock output stability adjusting method based on machine learning and related equipment

Abstract

The invention discloses a rubidium atomic clock output stability adjusting method based on machine learning and related equipment. The method comprises the following steps: respectively sending a measured signal and a reference signal into a measurement module, and measuring a frequency stability value; the upper computer calculates the measured frequency stability and judges whether adjustment is needed or not according to stability data; and under the condition that the stability does not conform to the expectation, the upper computer performs fine adjustment through the DDS adjustment module and outputs the adjusted signal to a user. The problem that in some application scenes with high requirements, the stability of the output frequency is still possibly influenced by various factors, such as external environment change, electromagnetic interference and tiny deviation in long-term operation can be solved.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of computers, and more specifically, to a method for adjusting the output stability of a rubidium atomic clock based on machine learning and related equipment. Background Art

[0002] As a high-precision frequency standard device, rubidium atomic clocks are widely used in satellite navigation, communication systems, precision measurement and other fields. In these application scenarios, the short-term stability of the frequency is directly related to the performance and accuracy of the system. However, the frequency stability of traditional rubidium atomic clocks is poor in the short term and is easily affected by environmental factors (such as temperature, electromagnetic interference, etc.) and physical processes within the system, resulting in frequency fluctuations, which significantly affects its application in high-precision scenarios. In addition, although the rubidium atomic clock has high frequency accuracy, in some high-demand application scenarios, its output frequency stability may still be affected by various factors, such as changes in the external environment, electromagnetic interference, and slight deviations in long-term operation. Summary of the invention

[0003] A series of simplified concepts are introduced in the Summary of the Invention, which will be further described in detail in the Detailed Description of the Invention. The Summary of the Invention does not mean to attempt to define the key features and essential technical features of the claimed technical solution, nor does it mean to attempt to determine the scope of protection of the claimed technical solution.

[0004] In order to solve the problem that the output frequency stability of a rubidium atomic clock may still be affected by various factors in certain high-demand application scenarios, such as changes in the external environment, electromagnetic interference, and slight deviations in long-term operation, in a first aspect, the present invention proposes a method for adjusting the output stability of a rubidium atomic clock based on machine learning, the method comprising:

[0005] The measured signal and the reference signal are respectively sent to the measurement module to measure the frequency stability value;

[0006] The host computer calculates the measured frequency stability and determines whether adjustment is needed based on the stability data;

[0007] When the stability does not meet expectations, the host computer performs fine-tuning through the DDS adjustment module and outputs the adjusted signal to the user.

[0008] Specifically, the DDS adjustment module uses an external atomic clock source to control the DDS output frequency F1 or F0 through FSELECT to maintain the stability of the signal phase, wherein when the DDS switches the frequency under the control of FSELECT, the phase of the signal is not changed.

[0009] Specifically, the DDS adjustment module uses the integral voltage of the phase difference to perform feedback adjustment, and controls the output frequency of the DDS by measuring the change of the phase difference.

[0010] Specifically, before sending the measured signal to the DDS adjustment module for fine adjustment, the method further includes:

[0011] The high-voltage-controlled crystal oscillator is fine-tuned through the correction voltage module in the stability adjustment module to ensure the stability of the output frequency of the atomic clock and compensate for short-term frequency fluctuations.

[0012] Specifically, the deviation correction voltage module converts the phase difference into an integral voltage, and then collects it with high precision through the A / D module, so that the system can respond accurately to slight changes in frequency.

[0013] Specifically, the correction voltage module is based on the frequency correction algorithm of the central processing unit, determines the system state through the locking indication module, and performs fine adjustment in combination with the D / A module.

[0014] Specifically, it also includes:

[0015] The host computer collects and processes the measurement data, combined with the frequency stability prediction algorithm, to predict the frequency fluctuation in advance and take adjustment measures.

[0016] In a second aspect, the present invention further proposes a rubidium atomic clock output stability adjustment device based on machine learning, comprising:

[0017] The measuring module is used to send the measured signal and the reference signal to the measuring module respectively to measure the frequency stability value;

[0018] The host computer is used to calculate the measured frequency stability and determine whether adjustment is required based on the stability data;

[0019] The DDS adjustment module is used to fine-tune the measured signal when the stability does not meet expectations, and output the adjusted signal to the user.

[0020] Specifically, it also includes a stability adjustment module, which is used to fine-tune the high-voltage-controlled crystal oscillator through the deviation correction voltage module to ensure the stability of the output frequency of the atomic clock and compensate for short-term frequency fluctuations.

[0021] Specifically, the stability adjustment module includes: a central processing unit, a correction module, a D / A module, a lock indication module and a high-stability voltage-controlled crystal oscillator connected to each other, wherein the central processing unit controls the correction voltage module, adjusts the output frequency of the voltage-controlled crystal oscillator to form a closed-loop control, and the central processing unit outputs a reference voltage and a correction voltage through the D / A module, adjusts the frequency of the voltage-controlled crystal oscillator, and realizes frequency stability control.

[0022] In summary, the method for adjusting the output stability of a rubidium atomic clock based on machine learning proposed in this application measures the frequency stability value by sending the measured signal and the reference signal into the measurement module respectively; the host computer calculates the measured frequency stability and determines whether adjustment is needed based on the stability data; when the stability does not meet expectations, the host computer fine-tunes the DDS adjustment module and outputs the adjusted signal to the user. As a result, the DDS adjustment module achieves high-precision and stable control of frequency and phase through technologies such as an external high-precision clock source, flexible frequency switching, extremely high fine-tuning accuracy, frequency multiplication and division functions, and phase difference feedback control. These innovative designs enable the device to show excellent performance in frequency adjustment and stability improvement, especially in high-demand frequency reference application scenarios. This module design not only has extremely high accuracy and real-time performance, but also has powerful adaptive capabilities and intelligent adjustment functions.

[0023] The machine learning-based rubidium atomic clock output stability adjustment method of the present invention, and other advantages, objectives and features of the present invention will be reflected in part through the following description, and in part will also be understood by technicians in this field through research and practice of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Various other advantages and benefits will become apparent to those of ordinary skill in the art by reading the detailed description of the preferred embodiments below. The accompanying drawings are only for the purpose of illustrating the preferred embodiments and are not to be considered as limiting the present specification. Also, the same reference symbols are used throughout the accompanying drawings to represent the same components. In the accompanying drawings:

[0025] Figure 1 A flowchart of a method for adjusting the output stability of a rubidium atomic clock based on machine learning provided in an embodiment of the present application;

[0026] Figure 2 A schematic diagram of the structure of a rubidium atomic clock output stability adjustment device based on machine learning provided in an embodiment of the present application;

[0027] Figure 3 A schematic diagram of the structure of a measurement module provided in an embodiment of the present application;

[0028] Figure 4 A structural diagram of a DDS processing module provided in an embodiment of the present application;

[0029] Figure 5 A schematic diagram of the structure of a DDS1 chip in a DDS processing module provided in an embodiment of the present application;

[0030] Figure 6A timing diagram of serial communication between a single chip microcomputer and DDS1 in a DDS processing module provided in an embodiment of the present application;

[0031] Figure 7 A schematic diagram of the structure of a DDS2 chip in a DDS processing module provided in an embodiment of the present application;

[0032] Figure 8 A schematic diagram of the structure of a phase difference acquisition module provided in an embodiment of the present application;

[0033] Fig. 9 A schematic diagram of a phase difference acquisition module provided in an embodiment of the present application;

[0034] Fig.10 A schematic diagram of a phase difference acquisition module provided in an embodiment of the present application;

[0035] Fig.11 A schematic diagram of a DDS module provided in an embodiment of the present application;

[0036] Fig.12 A timing diagram of serial communication in a DDS module provided in an embodiment of the present application;

[0037] Fig.13 A schematic diagram of the structure of another device for adjusting the output stability of a rubidium atomic clock based on machine learning provided in an embodiment of the present application;

[0038] Fig.14 A structural schematic diagram of a stability adjustment module provided in an embodiment of the present application;

[0039] Fig.15 A schematic diagram of the structure of a correction voltage module provided in an embodiment of the present application. DETAILED DESCRIPTION

[0040] The terms "first", "second", "third", "fourth", etc. (if any) in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchangeable where appropriate, so that the embodiments described herein can be implemented in an order other than that illustrated or described herein. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices. The technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all of the embodiments.

[0041] In order to solve the problem that the output frequency stability may still be affected by various factors in some high-demand application scenarios, such as external environment changes, electromagnetic interference, and slight deviations in long-term operation, please refer to Figure 1 , is a flow chart of a method for adjusting the output stability of a rubidium atomic clock based on machine learning provided in an embodiment of the present application, which may specifically include: steps S110 to S130.

[0042] S110, sending the measured signal and the reference signal to the measurement module respectively to measure the frequency stability value.

[0043] S120, the host computer calculates the measured frequency stability and determines whether adjustment is required based on the stability data.

[0044] S130, when the stability does not meet expectations, the host computer performs fine-tuning through the DDS adjustment module and outputs the adjusted signal to the user.

[0045] For example, Figure 2 As shown, the above method can be implemented by a rubidium atomic clock output stability adjustment device based on machine learning, which includes:

[0046] The measuring module is used to send the measured signal and the reference signal to the measuring module respectively to measure the frequency stability value;

[0047] The host computer is used to calculate the measured frequency stability and determine whether adjustment is required based on the stability data;

[0048] The DDS adjustment module is used to fine-tune the measured signal when the stability does not meet expectations, and output the adjusted signal to the user.

[0049] It can be understood that the measured frequency source signal f1 and the reference frequency source signal f2 are respectively sent to the measurement module, and the corresponding frequency stability values ​​are obtained and sent to the host computer for processing, and then the correction information is transmitted to the DDS adjustment module, so that it is fine-tuned based on the external reference of the atomic clock and then sent to the client.

[0050] For example, Figure 3 As shown, in the measurement module part, the measured frequency source signal f1 and the reference frequency source signal f2 are respectively sent to the DDS processing module, and two square wave frequency division signals with similar frequencies are obtained through the DDS digital synthesis technology. Then, the phase difference between the two signals is collected by the single-chip microcomputer in a signal rising edge triggering processing mode. At the same time, the single-chip microcomputer outputs a digital square wave signal representing the duty cycle change of the phase difference between the two signals, and it is sent to the integration circuit to be converted into a corresponding DC voltage. The A / D conversion module integrated in the single-chip microcomputer collects the DC voltage, and finally transmits the measurement data to the computer through the RS232 serial communication interface. The corresponding measurement value is obtained after computer data processing.

[0051] In the entire measurement module, the STM32 series microcontroller can be used as the core processing unit. We use the 16-bit timer in the STM32 series microcontroller as the clock signal for phase difference acquisition, and the 12-bit precision A / D as the recorder. The measurement data results are passed to the computer for processing through the RS232 serial interface, the data is stored in the hard disk, and the measurement curve is drawn on the display.

[0052] For example, Figure 4-Figure 7 As shown in the figure, for the DDS processing module, the reference clock signal f2 is sent to the time counter 1 after passing through the isolation amplifier 1. The time counter 1 counts the frequency of f2, and the count value of the time counter 1 is sampled and latched by the single-chip microcomputer enabling latch 1, thereby obtaining the specific reference clock signal frequency F2. After passing through the isolation amplifier 2, one of the measured frequency signals f1 is sent to the external clock input terminal of DDS1 as the reference clock for DDS1 to work. At the same time, the external data communication port of DDS1 (chip select), SCLK (write pulse), and SDIO (data) are connected to the microcontroller respectively to receive control word commands and data transmission from the microcontroller.

[0053] For example, the DDS chip actually selected has two 48-bit frequency control registers (F0, F1). For the measured frequency signal f1 of this device, when the PLL frequency multiplication function inside DDS1 is not used, when the 48-bit frequency control register F0 is fully filled with 1, DDS1 will have a clock signal output with a frequency of f1. However, in actual applications, in order to broaden the measurement range of the measured frequency signal by the phase comparison device, such as when the reference clock signal frequency is 10MHz, and the measured signal frequency is hundreds or even hundreds of Hz, it is necessary to perform frequency division processing on the measured frequency signal first, and reduce the frequency of the measured signal while ensuring that the frequency stability of the original signal is not affected. In this device, it is planned to perform 1 / 100 frequency division processing on the measured signal f1, and transmit the specific frequency division value to DDS1 through the single-chip microcomputer to realize signal frequency division processing. The calculation method of the numerical frequency division value is as follows:

[0054]

[0055] Where D is the specific frequency division value to be calculated, f1 is the measured signal frequency, and f is the specific frequency division signal frequency required. For f = (1 / 100) f1, the frequency division value D should be 2 48 ×10 -2 The communication between the microcontroller and DDS1 is carried out using the serial communication timing, such as Figure 6 As shown. When it is high level, SCLK and SDIO pins are in high impedance state. When it is low, DDS1 will be in the communication state. At this time, when the single-chip microcomputer inputs a rising edge pulse to the pin SCLK, the one-bit frequency division numerical data represented in binary on the data bus SDIO will be written into the DDS1 data buffer, until the final binary frequency division numerical data is written, and the required frequency division signal output will be obtained through the internal comparator processing of DDS1. The frequency signal f obtained after the 1 / 100 frequency division processing of the DDS1 module is sent to the time counter 2, and the time counter 2 counts the frequency of f. The single-chip microcomputer enables latch 2 to sample and latch the count value of the time counter 2. The single-chip microcomputer reads the count data of latch 2 and multiplies it by 100 to obtain the specific frequency value F1 of the measured signal. Through formula (2), the single-chip microcomputer determines the specific frequency division parameters transmitted to DDS2:

[0056]

[0057] Where F1 and F2 are the specific frequency values ​​obtained by sampling and counting the measured signal f1 and the reference clock signal f2 through the travel time counter 2 and the travel time counter 1, and Δf is a preset difference frequency value, the value of which determines the measured signal f that finally enters the phase acquisition. xThe frequency difference between the reference clock signal f0 and the reference clock signal f0 is the time value of a complete cycle in the phase comparison curve. The measured signal after isolation amplifier 2 is sent to the external clock input terminal of DDS2 as the reference clock for DDS2 to work. At the same time, the external data communication port of DDS2 (chip select), SCLK (write pulse), SDIO (data) are connected to the microcontroller to receive control word commands and data transmission from the microcontroller. After DDS2 divides the measured signal according to the preset frequency division value Data, the required f x The measured signal is output and then sent to the filter module for low-pass filtering before being output directly.

[0058] For example, Figure 8-9 As shown in the figure, in the phase difference acquisition link, the measured signal fx and the reference clock signal fo are sent to the pins P1.0 and P1.1 of the single-chip microcomputer respectively, and the output of the P2.0 pin is directly used as the level input terminal of the integration circuit after phase comparison. At the same time, in order to enable the single-chip microcomputer to work normally and stably, an external clock CLK signal is sent to the clock input terminal of the single-chip microcomputer. Software judgment is used in the design to complete the acquisition of the phase difference, and the square wave duty cycle is output through the pin P2.0 to reflect the specific phase difference value. The specific implementation process is as follows: In the program, a minimum timing time is set for a 16-bit timer inside the single-chip microcomputer, that is, the high 8 bits and low 8 bits of the 16-bit timer are set to 0xFF. When the next CPU execution cycle arrives, a timer overflow interrupt will be applied, and the arrival of the rising edge of the measured signal fx and the reference clock signal fo will be judged in the corresponding interrupt service program. For the reference clock signal fo, when the rising edge arrives, the phase difference output pin P2.0 is set to a high level, and the subsequent integration circuit will accumulate the integration voltage; for the measured signal fx, when the rising edge arrives, P2.0 will be set to a low level, and the integration voltage of the integration circuit will remain unchanged. In the minimum timing cycle of the 16-bit timer, that is, in a complete timer overflow interrupt service program, when the rising edges of fx and fo arrive at the same time, it represents the end of a complete phase comparison cycle, and the integrator integration voltage is set to 0.

[0059] It can be understood that, based on the above design, it can be considered that the timing time of the timer should be as small as possible. For the specific single-chip microcomputer used, the corresponding external clock input CLK signal frequency and frequency stability should be as high as possible. On the one hand, this shortens the time it takes for the single-chip microcomputer to execute a machine cycle code. On the other hand, when the frequency stability of the external input clock signal is relatively high, the time for each timer overflow interrupt response is more accurate, thereby improving the resolution of the phase difference acquisition of the measured signal fx and the reference clock signal fo. In the program, the square wave duty cycle of the signal output through the P2.0 pin reflects the phase difference between the two signals. When the phase difference between the two signals is large, the high level will account for the majority of the square wave output by P2.0, and the corresponding integral voltage will increase faster when connected to the input level end of the integration circuit. When the phase difference between the two signals is small, the low level will account for the majority of the square wave output by P2.0, and the corresponding integral voltage will increase slower when connected to the input level end of the integration circuit. When the phase difference between the two signals is 0 within the resolution range of the instrument, the total integral voltage in the integration circuit will be set to 0, which means that a complete phase comparison cycle is completed.

[0060] Exemplarily, the phase comparison integral voltage obtained by the integration circuit is sent to the A / D sampling pin P0.0 inside the single-chip microcomputer, and the single-chip microcomputer samples the specific integral voltage value of the integration circuit through the A / D. The single-chip microcomputer has a 12-bit precision A / D conversion module, which can represent a numerical range of 0-4096, that is, the numerical values ​​0 and 4096 represent 0° and 360° phase differences respectively. Then the minimum resolution of the designed measurement module is about 360° / 1024=0.1°, that is, there will be a measurement error of about ±0.1° in the actual phase comparison. In actual measurement, the frequency of the reference clock signal fo and the measured signal fx is usually set to a certain small difference frequency △f according to formula (2) to collect the phase difference and process the integral voltage. The single-chip microcomputer samples the integral voltage of the integration circuit through the internal integrated A / D, and transmits the collected results to the PC through the internal integrated enhanced UART interface TX, RX in RS232 serial communication mode, and the rest of the entire phase comparison result processing is completed by the PC end. Taking the actual 10-bit precision A / D sampling module of the microcontroller with a collection time of 10s as an example, the PC side calculates the hourly stability during the actual processing of the entire phase comparison result as follows: Fig.10 shown.

[0061] For example, the PC receives the integrated voltage data sent by the microcontroller, takes the 1st, 360th, 720th ... A / D sampling voltage values ​​(assuming that the A / D acquisition range is 0~V), and converts them into phase values. The specific conversion formula is:

[0062]

[0063] After formula (3) is rearranged, we get:

[0064]

[0065] Where N is the number of complete 360° cycles experienced in the i-th 3600 seconds, V1 and V2 are the A / D sampling voltages corresponding to the i-1th and i-2nd 3600 seconds respectively, and φ i That is, the total phase value experienced in the i-th 3600 seconds is obtained. Then the difference frequency data △f of the i-th 3600 seconds is i Calculated as:

[0066]

[0067] With the corresponding △f i The value can be substituted into the Allan variance calculation formula (6) or the Hadamard variance calculation formula (7) to calculate the corresponding frequency stability.

[0068]

[0069] Where τ is the sampling time and sampling period, indicating that the Allan variance is gapless sampling, f k is the corresponding frequency value within the sampling time, and N is the number of measurements.

[0070]

[0071] τ is the sampling time, y k The corresponding frequency value measured for each sampling time, m is the number of measurements.

[0072] The PC displays the calculated frequency stability results to the user. At the same time, it also needs to display the real-time measurement curve of the entire phase comparison process in a two-dimensional time domain graph based on the integrated voltage data transmitted from the microcontroller.

[0073] For example, Figure 11-12As shown, for the DDS adjustment module, the MCLK pin is connected to the external atomic clock external clock source, so that the stability of the frequency signal at the IOUT pin output of the DDS is consistent with the external clock source. FSELECT is the keyed frequency modulation signal input terminal. There are two frequency control registers inside the DDS. The pre-set frequency values ​​F0 and F1 are stored in the registers through programming. When there is a square wave signal input at the FSELECT terminal (that is, the rising edge or falling edge of the level conversion), the IOUT terminal of the DDS will read the F1 or F0 value from the frequency control register as the output, and the phase of the signal will be kept unchanged. The main communication timing between DDS and the outside world (such as F1 and F0 values) is completed through the pins FSYNC, SCLK, and SDATA. The timing of its serial communication is as follows. Fig.12 When FSYNC is high, the SCLK and SDATA pins are in high impedance state. When FSYNC is low, the DDS will be in communication state. At this time, when the pin SCLK has a falling edge pulse, the DATA on the data bus SDATA will be written into the DDS data buffer. When the last DATA is written, the DDS will select F1 or F0 as the output of the IOUT terminal according to the state on the pin FSELECT.

[0074] Here, taking the atomic clock outputting a 10MHz frequency signal as an example, the MCLK clock input signal frequency is 10MHz. There are two 48-bit frequency control registers (F0, F1) inside the DDS. In the above serial communication timing, the DATA bit should be 48 bits. It can be seen that when the MCLK external input clock frequency is 10MHz, the minimum frequency resolution of the DDS is:

[0075]

[0076] Then the corresponding frequency stability control can be in the order of 4E-8Hz / 10MHz=4E-15. It should be noted here that:

[0077] When IOUT outputs 10MHz, the corresponding 48-bit rate control register value is all 1, so I cannot adjust the IOUT output frequency upward (i.e. greater than 10MHz), so in actual applications we can multiply the external atomic clock external clock source signal input to the MCLK pin in the DDS before performing the above operation. Specifically, the above method may include:

[0078] 1. According to the patent principle diagram, the existing atomic clock is sampled according to the periodic sampling time T (e.g., 10 seconds);

[0079] 2. The real-time sampling time T stability data obtained by the measurement module is transmitted to the host computer;

[0080] 3. The host computer judges the stability data Y to see if it meets the expectations. For example, the theoretical expected value Y0 is 1E-13.

[0081] 4. When Y < Y0, no processing is done; when Y > Y0, the host computer controls the DDS adjustment module to make an adjustment of 1E-13.

[0082] 5. The adjusted signal is output to the user through the IOUT terminal.

[0083] In summary, the method for adjusting the output stability of a rubidium atomic clock based on machine learning provided by the embodiment of the present application measures the frequency stability value by separately sending the measured signal and the reference signal into the measurement module; the host computer calculates the measured frequency stability and judges whether adjustment is needed according to the stability data; in the case where the stability does not meet the expectations, the host computer makes fine-tuning through the DDS adjustment module and outputs the adjusted signal to the user. Thus, through technologies such as an external high-precision clock source, flexible frequency switching, extremely high fine-tuning accuracy, frequency multiplication and division functions, and phase difference feedback control, the DDS adjustment module achieves high-precision stable control of frequency and phase. These innovative designs enable the device to exhibit excellent performance in frequency adjustment and stability improvement, especially in high-requirement frequency reference application scenarios. This module design not only has extremely high accuracy and real-time performance but also has strong adaptive capabilities and intelligent adjustment functions.

[0084] It can be understood that this solution combines DDS technology with real-time feedback control to solve the problem of possible fluctuations in the frequency stability of traditional rubidium atomic clocks during long-term use. By measuring the frequency deviation of the output signal in real time, the host computer can make precise fine-tuning of the DDS to ensure the stability of the signal. Specifically, in the entire device, the signal frequency f1 and the reference signal f2 are compared through the measurement module, and the phase difference and frequency difference between the two are collected. When the deviation of the frequency stability exceeds the expectation (for example, deviates from the set threshold Y0), the host computer will automatically transmit the adjustment information to the DDS module, and adjust the output signal through the frequency division or frequency multiplication mechanism of the DDS. This automatic adjustment mechanism ensures that even in the case of external environmental changes or long-term operation, the small frequency deviation can be automatically corrected, significantly improving the long-term stability of the signal. Through real-time adjustment of the frequency, this solution effectively improves the frequency stability of the output signal of the rubidium atomic clock, enabling it to maintain high precision in complex application scenarios (such as communication, positioning, scientific research, etc.) and reducing the impact of frequency drift.

[0085] It is understandable that this solution introduces the automatic judgment and feedback control function of the host computer. Compared with the traditional manual frequency adjustment, this solution relies on the host computer for intelligent judgment, automatically controls the DDS adjustment module according to the frequency measurement results, and accurately adjusts the output frequency of the signal. The host computer receives data from the single-chip microcomputer and the measurement module in real time and analyzes the frequency change of the measured signal. If the frequency stability does not meet expectations, the system will automatically trigger the frequency adjustment program and fine-tune the frequency of the output signal through DDS. This automatic adjustment avoids the delay and error of manual intervention and improves the adaptive ability of the system. The design of the phase difference acquisition and integration circuit ensures the accuracy of the feedback data. The host computer can respond quickly and transmit correction information to the DDS module through these precise data. As a result, the automatic adjustment function improves the operating efficiency of the system, reduces the complexity and error rate of manual operation, ensures the timeliness and accuracy of frequency adjustment, and makes the entire device have a higher level of intelligence. This function is particularly important in applications where signal frequency needs to be adjusted frequently.

[0086] It can be understood that in this scheme, an integral voltage adjustment method based on phase difference is adopted. By comparing the phase difference of the signal, the corresponding integral voltage is obtained, and the frequency is fine-tuned. This design greatly improves the accuracy of frequency adjustment. The measured signal and the reference signal are detected by the single-chip microcomputer, and the phase difference is reflected by the square wave duty cycle of the P2.0 pin. The phase difference is collected by the integral circuit to obtain the integral voltage, and the integral voltage is sent to the A / D conversion module for sampling. These integral voltages are then processed by the host computer, and the change in frequency stability is calculated. Due to the use of a precise A / D conversion module, this scheme can achieve high-precision measurement of the signal phase difference, so that the frequency fine-tuning accuracy reaches the order of 10^-15. As a result, the high-precision phase difference acquisition and integral processing enable the system to maintain a high resolution when detecting small frequency deviations, thereby improving the accuracy of system frequency adjustment. This technical effect is very critical in application scenarios that require extremely high frequency accuracy, such as navigation systems and precision measuring instruments.

[0087] It can be understood that by dividing and doubling the signal, the scheme greatly expands the applicability of the frequency range. In particular, by dividing the measured signal by 1 / 100, a wider range of frequency signals can be measured while ensuring frequency stability. The DDS module is capable of dividing and doubling the external input signal, processing frequency signals ranging from several hundred hertz to several megahertz. By dividing the signal, the device can expand its adaptability to low-frequency signals while maintaining a high frequency stability. On the contrary, the upper limit of the output frequency can be increased through the frequency doubling function to meet the needs of high-frequency signals. This design enables the device to adapt to the signal processing needs of different frequency ranges, and can maintain a high frequency stability when processing high-frequency or low-frequency signals, thereby improving the versatility and applicability of the system.

[0088] It can be understood that in the scheme, the DDS module controls the frequency switching through the FSELECT pin, and can switch different frequency values ​​while maintaining the continuity of the signal phase, avoiding the phase jump problem during frequency switching. The two frequency control registers F0 and F1 inside the DDS store different frequency values ​​respectively, and the system switches the output frequency under the control of FSELECT as needed. During the frequency switching process, the DDS module ensures that the phase of the output signal does not jump and maintains the continuity of the phase, thereby avoiding transient instability that may be caused by frequency switching. This design ensures that the phase of the signal remains stable during the frequency adjustment process, eliminates the phase jump problem caused by frequency switching, and further improves the frequency stability of the system and the reliability of signal output.

[0089] By combining DDS technology, real-time feedback control, high-precision phase difference acquisition, and frequency division and multiplication technology, this solution significantly improves the output frequency stability of the rubidium atomic clock. Its automated and high-precision frequency adjustment design ensures that the system can adapt to the frequency stability requirements in complex environments and maintain excellent performance in long-term operation. These technical effects make this solution have broad application potential in the fields of navigation, communication, precision measurement, etc.

[0090] For example, Fig.13 As shown, the measured frequency source signal f1 and the reference frequency source signal f2 are respectively sent to the measurement module, and the corresponding frequency stability values ​​are obtained and sent to the host computer for processing. The correction information can be transmitted to the stability adjustment module, so that it can be fine-tuned based on the external reference of the atomic clock and then sent to the client.

[0091] For example, Fig.14 and 15As shown, the atomic clock is a prior art technology that includes a voltage-controlled crystal oscillator with high short-term stability. The quantum frequency discrimination signal output by the atomic clock is sent to the lock indication judgment module to complete the working status indication of the whole system, and the judgment result is sent to the central processing unit.

[0092] The correction voltage module works under the enablement of the central processing unit, and obtains the voltage-controlled voltage to act on the high-stable voltage-controlled crystal oscillator inside the atomic clock, causing its frequency to change, thereby completing the closed-loop process of the atomic clock.

[0093] Voltage reference 1 is used as the reference level of D / A1;

[0094] Voltage reference 2 is used as the reference level of D / A2;

[0095] The voltage value output by the central processor through D / A1 and the correction enable module and D / A2 acts on the high-stabilized voltage-controlled crystal oscillator.

[0096] The central processor stores the voltage control slope parameter value of the high-stable voltage-controlled crystal oscillator, which is the basis for the correction enable module to work. For example: VCXO outputs 10MHz, and its voltage control slope is 0.1Hz / V. When the quantum frequency discrimination signal gives a voltage difference of 10mV, and the system determines that it is in a closed-loop locked working state at this time, if it is directly applied to the high-stable voltage-controlled crystal oscillator according to traditional technology, it will cause the frequency of the output signal of the atomic frequency standard to fluctuate by (10mV×0.1Hz / V) / (1E-7)Hz=1E-10. Obviously, for the atomic frequency standard whose short-term frequency stability is 1E-11 / S, this is unacceptable.

[0097] It can be understood that based on this, the following method is adopted in this application to optimize the short-term stability of the signal:

[0098] (1) If the CPU determines that the atomic frequency standard is in an unlocked state according to the lock indication module, then for the above-mentioned 1E-10 or even larger fluctuations such as 5E-10, the D / A1 directly outputs the corresponding voltage to act on the high-voltage controlled crystal oscillator to change its output frequency. This situation usually occurs shortly after the atomic clock is powered on, during the relaxation oscillation period of the spectrum lamp, and the CPU needs to significantly change the output frequency of the high-voltage controlled crystal oscillator to achieve closed-loop locking of the entire machine.

[0099] (2) If the central processor determines that the atomic frequency standard is in a closed-loop locked state according to the lock indication module, then for the above-mentioned 1E-10 or even larger fluctuations such as 5E-10, the correction enable module is first turned on, and then the corresponding voltages are output by D / A1 and D / A2 respectively to act on the high-voltage controlled crystal oscillator to change its output frequency. The voltage output by D / A1 is the reference voltage, and the voltage output by D / A2 is the correction voltage. The specific value of the reference voltage is based on the first closed-loop lock achieved by the initial atomic clock mentioned in (1) above after power-on, that is, once the atomic clock achieves closed-loop lock, the value output by D / A1 will be fixed, and the subsequent correction work in the closed-loop locked state will be completed by D / A2.

[0100] Because the atomic clock is already in a closed-loop locked state at this time, theoretically, the frequency stability of the output signal of the high-stabilization voltage-controlled crystal oscillator will reflect the short- and long-term performance of the entire atomic clock. For the short-term stability required by this patent, for example, a short-term stability of 1E-11 in 1 second corresponds to a high-stabilization voltage-controlled crystal oscillator with an output frequency of 10MHz and a voltage control slope of 0.1Hz / V, so the magnitude of the correction voltage should not exceed 1mV. If the correction voltage value obtained by the central processor at a certain moment exceeds 1mV, such as a 10mV correction voltage that causes the stability of the atomic clock to fluctuate by 1E-10, then the central processor will abandon this correction at this moment, and the output of D / A2 will still maintain the voltage value output when the last correction was enabled. This phenomenon can often be seen in actual atomic clock stability test examples, that is, at a fixed sampling time, the frequencies of the atomic clock output signals are f and f respectively. N-1 、f N 、f N+1 , in f N The frequency value at the point jumps greatly. According to the traditional servo circuit solution, the jumping f N The value will have a huge impact on the short-term stability of the atomic clock, causing the short-term stability index to decline. Through the method of this patent, the occurrence of the above-mentioned jump can be known through the host computer's access to the measurement module, so after the corresponding patent technology processing, f N The jumps will be reasonably avoided so as not to affect the short-term stability of the atomic clock.

[0101] (3) Based on the above (2), a time value t is preset inside the central processor, for example, 10 seconds, which is used to assist in judging the working status of the system. The solution according to (2) has certain risks, because in actual applications, due to factors such as working environment temperature, electromagnetic radiation, internal physical system or circuit failure, it is possible to cause a large range of jumps in the frequency of the output signal of the atomic clock. If the high-voltage controlled crystal oscillator cannot be effectively corrected at this time, the atomic clock will be unlocked. Therefore, according to the above solution (2) and the time value t set in this section, this problem is solved: if the frequency of the output signal of the atomic clock jumps greatly at a certain moment, according to solution (2), within the time value t, D / A1 outputs a fixed level and D / A2 outputs the original level, that is, at this moment, the high-voltage controlled crystal oscillator is not effectively corrected. At this time, the stability index of the system is determined by the high-voltage controlled crystal oscillator itself... If the duration of the jump point exceeds the preset time value t, then the processor will perform effective correction, that is, D / A1 outputs a fixed level and D / A2 outputs the corresponding correction level. At this moment, due to the accumulation of the correction voltage for a long time t, the high-stabilization voltage-controlled crystal oscillator may change over a large range, and the short-term stability index will deteriorate seriously. However, the occurrence of this situation usually indicates that there is a fault in the atomic clock itself, so the index is out of the question.

[0102] It is understandable that DDS (digital direct synthesis) frequency division technology is one of the core technologies for improving frequency stability. By performing frequency division processing on the measured signal and the reference signal and maintaining frequency stability, the system can convert the high-frequency signal into a lower frequency signal suitable for measurement while ensuring that the signal frequency is not distorted. By performing frequency division processing on the high-frequency signal, the instantaneous jitter and noise of the signal will be relatively reduced, which makes the measurement and subsequent adjustment more accurate, thereby improving the frequency stability of the entire system. Frequency division processing expands the system's adaptability to signals of different frequencies, especially when the measured signal frequency is high (such as several hundred hertz or even higher), the system can still perform effective measurement and adjustment, which is difficult to achieve in traditional solutions.

[0103] It is understandable that through phase difference acquisition and integration processing, the system can convert the frequency offset (difference frequency) into a voltage signal. This design improves the measurement accuracy and signal stability. Therefore, using the STM32 microcontroller and 16-bit timer to accurately acquire the phase difference of the signal can significantly improve the resolution of the phase difference measurement compared to the traditional analog circuit solution. This design can capture extremely subtle frequency fluctuations and ensure that the frequency stability is not significantly disturbed in the short term. The phase difference is converted into a voltage signal by the integration circuit and then digitized by the A / D conversion module. This process accurately characterizes the slight change in the phase difference as a voltage value. The A / D module provides 12-bit accuracy, so that the minimum resolution of the measurement reaches 0.1 degree phase difference. Such high accuracy is crucial to improving frequency stability.

[0104] It is understandable that the above example uses the central processor to perform closed-loop feedback control on the system, combined with the correction voltage adjustment, to ensure that frequency fluctuations can be monitored and corrected in real time. This closed-loop control design adjusts the output frequency of the voltage-controlled crystal oscillator in real time through the correction voltage module when the frequency deviation is detected to ensure frequency stability. In particular, after the system achieves closed-loop locking, the correction voltage can be fine-tuned to make the frequency adjustment more accurate and avoid the frequency instability problem caused by large adjustments in traditional systems. By judging whether the system is in a locked state, the system adopts different correction strategies. In the case of large fluctuations, the correction mechanism can restore the system to a locked state through rapid adjustment; in the locked state, the correction voltage is only slightly adjusted to ensure short-term frequency stability. This mechanism ensures that the system can still maintain high stability in the short term when dealing with a large range of frequency jumps.

[0105] It is understandable that due to the introduction of machine learning algorithms, the law of frequency fluctuations can be extracted from historical measurement data and future frequency changes can be predicted. This data-driven prediction and adjustment mechanism can further optimize the frequency stability of the system. Through machine learning algorithms, the system can predict possible frequency fluctuations in advance and make pre-adjustments based on the predicted results. This function enables the system to make adjustments before frequency fluctuations to avoid excessive frequency deviations, significantly improving frequency stability. The system dynamically adjusts the size of the correction voltage and the adjustment frequency according to different operating conditions to avoid stability loss caused by excessive frequency fluctuations or slow adjustments. This adaptive adjustment mechanism enables the system to maintain a high frequency stability under complex operating conditions.

[0106] Those skilled in the art will appreciate that the embodiments of the present application may be provided as methods, systems, or computer program products. Therefore, the present application may adopt the form of a complete hardware embodiment, a complete software embodiment, or an embodiment in combination with software and hardware. Moreover, the present application may adopt the form of a computer program product implemented in one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) that include computer-usable program code.

[0107] The present application is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to the embodiments of the present application. It should be understood that each process and / or box in the flowchart and / or block diagram, as well as the combination of the processes and / or boxes in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded computer, or other programmable data processing device to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0108] These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0109] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0110] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working processes of the systems, devices and units described above can refer to the corresponding processes in the aforementioned method embodiments and will not be repeated here.

[0111] In the several embodiments provided in the present application, it should be understood that the disclosed systems, devices and methods can be implemented in other ways. For example, the device embodiments described above are only schematic. For example, the division of units is only a logical function division. There may be other division methods in actual implementation. For example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be an indirect coupling or communication connection through some interfaces, devices or units, which can be electrical, mechanical or other forms.

[0112] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0113] In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit. The above-mentioned integrated unit may be implemented in the form of hardware or in the form of software functional units.

[0114] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application is essentially or the part that contributes to the prior art or all or part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a storage medium, including a number of instructions to enable a computer device (which can be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the various embodiments of the present application. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (Read-Only Memory, ROM), random access memory (Random Access Memory, RAM), disk or optical disk and other media that can store program codes.

[0115] The above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present application.

Claims

1. A method for adjusting the output stability of a rubidium atomic clock based on machine learning, characterized in that: include: The measured signal and the reference signal are respectively sent to the measurement module to measure the frequency stability value; The host computer calculates the measured frequency stability and determines whether adjustment is needed based on the stability data; When the stability does not meet expectations, the host computer performs fine-tuning through the DDS adjustment module and outputs the adjusted signal to the user.

2. The method according to claim 1, characterized in that The DDS adjustment module uses an external atomic clock source to control the DDS output frequency F1 or F0 through FSELECT to maintain the stability of the signal phase, wherein when the DDS switches the frequency under the control of FSELECT, the phase of the signal is not changed.

3. The method according to claim 2, characterized in that The DDS adjustment module uses the integrated voltage of the phase difference to perform feedback adjustment, and controls the output frequency of the DDS by measuring the change of the phase difference.

4. The method according to claim 1, characterized in that Before sending the measured signal to the DDS adjustment module for fine adjustment, the method further includes: The high-voltage-controlled crystal oscillator is fine-tuned through the correction voltage module in the stability adjustment module to ensure the stability of the output frequency of the atomic clock and compensate for short-term frequency fluctuations.

5. The method according to claim 4, characterized in that The deviation correction voltage module converts the phase difference into an integral voltage, and then collects it with high precision through the A / D module, so that the system can respond accurately to slight changes in frequency.

6. The method according to claim 4, characterized in that The correction voltage module is based on the frequency correction algorithm of the central processing unit, determines the system status through the locking indication module, and performs fine adjustment in combination with the D / A module.

7. The method according to any one of claims 1 to 6, characterized in that Also includes: The host computer collects and processes the measurement data, combined with the frequency stability prediction algorithm, to predict the frequency fluctuation in advance and take adjustment measures.

8. A rubidium atomic clock output stability adjustment device based on machine learning, characterized in that: include: The measuring module is used to send the measured signal and the reference signal to the measuring module respectively to measure the frequency stability value; The host computer is used to calculate the measured frequency stability and determine whether adjustment is required based on the stability data; The DDS adjustment module is used to fine-tune the measured signal when the stability does not meet expectations, and output the adjusted signal to the user.

9. The device according to claim 8, characterized in that Also includes: The stability adjustment module is used to fine-tune the high-voltage-controlled crystal oscillator through the deviation correction voltage module to ensure the stability of the output frequency of the atomic clock and compensate for short-term frequency fluctuations.

10. The device according to claim 9, characterized in that: The stability adjustment module includes: a central processing unit, a correction module, a D / A module, a locking indication module and a high-stability voltage-controlled crystal oscillator connected to each other, wherein the central processing unit controls the correction voltage module, adjusts the output frequency of the voltage-controlled crystal oscillator to form a closed-loop control, and the central processing unit outputs a reference voltage and a correction voltage through the D / A module, adjusts the frequency of the voltage-controlled crystal oscillator, and realizes frequency stability control.

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