Security enhanced CAN controller based on encryption authentication and intrusion detection

Abstract

The invention discloses a security enhanced CAN (Controller Area Network) controller based on encryption authentication and intrusion detection, and aims to deal with security threats such as remote unlocking, starting and stopping of a vehicle by a hacker through the Internet of Vehicles. According to the invention, a security framework based on encryption authentication and intrusion detection is constructed, the pre-shared symmetric key is combined with the AES and HMAC-SHA256 algorithms, the encryption and authentication of CAN communication data are realized, and the confidentiality, integrity and authenticity of data transmission are guaranteed; meanwhile, an intrusion detection technology based on information entropy is introduced, and data frame injection attacks initiated through legal nodes are effectively defended. According to the method, a strategy of parallel processing of data frame transmission and encryption calculation is used, the problem that extra data carrying overhead is introduced due to the fact that a CAN controller and a security module are independently achieved in an existing method is solved, efficient transmission of CAN encrypted data is achieved, and the method has good development and application prospects.

Description

Technical Field

[0001] The present invention relates to the field of intelligent networked vehicle safety technology, and in particular to a security-enhanced CAN controller based on encryption authentication and intrusion detection. Background Art

[0002] The in-vehicle network is the core hub for realizing the functional collaboration and control of the whole vehicle, and undertakes the key tasks of data communication and interaction. The CAN bus has become the internal vehicle network for communication between ECUs due to its advantages of low cost, high integration, good real-time performance and high flexibility. The CAN bus protocol is widely used in the field of automobile transmission system and body control, connecting key functional components related to automobile movement behavior. It is currently the most mature and has the highest market share. It has been required to be implemented as a standard on every mass-produced car. The CAN bus protocol specification was not designed to take into account the situation that the vehicle bus is open to the outside, so the CAN bus protocol has almost no security measures. Once an attacker gains control of a legitimate node, he can control the movement behavior of the vehicle, seriously threatening the life safety of the associated personnel.

[0003] Many researchers at home and abroad have proposed several solutions to the security issues of vehicle-mounted CAN communication networks. According to the different security protection measures of the CAN bus, the current research work can be divided into two categories: security strategies based on encryption and authentication and security strategies based on intrusion detection. Security strategies based on encryption and authentication can ensure the confidentiality, integrity and authenticity of CAN data transmission, but there are defects that are incompatible with the CAN protocol. Compared with security strategies based on encryption and authentication, intrusion detection technology has the advantages of good compatibility, less resource bandwidth and convenient deployment, and can effectively identify known attack types, but there are problems such as complex algorithm design and inability to fully guarantee security.

[0004] At present, the research on CAN security strategy mainly focuses on the application layer. Most solutions assume that the ECU has powerful capabilities, but the on-board chips are usually 8-bit or 16-bit MCUs, which have limited computing power and storage space. Deploying complex and effective security strategies still faces certain challenges. Therefore, it is of great significance to study the hardware implementation of the security strategy of the on-board CAN communication network. Summary of the invention

[0005] In order to solve the above problems, the present invention proposes a network security framework based on intrusion detection strategy and encryption authentication mechanism to ensure the security of the vehicle-mounted CAN communication network, and at the same time ensures the real-time performance of the vehicle-mounted CAN communication network by implementing security strategies inside the CAN controller.

[0006] The present invention adopts the following technical solutions:

[0007] A security-enhanced CAN controller based on encryption authentication and intrusion detection, including the following contents:

[0008] The present invention completes the design of the CAN controller with reference to the internal structure diagram of SJA1000, and on this basis integrates intrusion detection, AES and HMAC-SHA256 algorithm modules to construct a CAN controller with security functions. Its overall architecture is as follows Figure 1 As shown. The intrusion detection module determines whether there is a security threat in the vehicle CAN communication network by receiving the information entropy of the data frame ID, so that it can respond quickly. The encryption authentication strategy is implemented inside the bit stream controller, and the encryption authentication calculation is completed by calling the AES and HMAC-SHA256 modules to ensure the confidentiality, integrity and authenticity of the data.

[0009] Specifically, it includes an intrusion detection module, a bit stream controller, an error logic management module, an HMAC-SHA256 module, an AES module, a register unit and a bit timing unit; wherein, the intrusion detection module determines whether there is a security threat in the vehicle-mounted CAN communication network by receiving the information entropy of the data frame ID, so as to be able to respond quickly; the bit stream controller completes the encryption authentication operation internally by calling the AES module and the HMAC-SHA256 module to ensure the confidentiality, integrity and authenticity of the data transmission; the error logic management module is used to manage the error state of the node in the CAN bus system by monitoring the sending error count and the receiving error count to ensure the high availability of the data transmission system in the event of a node failure; the HMAC-SHA256 module is used to calculate the MAC value to complete the identity authentication, the AES module is used for the encryption and decryption calculation of the CAN data, the functional description of some registers of the register unit is shown in Appendix 1, and the bit timing unit is used to provide sampling points and sending points for the bit stream controller, and is also responsible for the timing synchronization with other vehicle-mounted CAN communication network nodes.

[0010] Table 1 Register function table

[0011]

[0012] As a further improvement of the present invention, the intrusion detection module uses information entropy analysis technology to monitor data frame anomalies in the CAN network, promptly discover and respond to potential network security threats, and its working state is controlled by the ENTR field of the CAN_CFG register. When the ENTR field is set to a high level, the intrusion detection module is activated.

[0013] As a further improvement of the present invention, the intrusion detection module includes a TIME_WINDOW counter, an information entropy calculation module, an exception management unit and an exception ID buffer unit; the TIME_WINDOW counter is responsible for counting, and when the count value reaches a preset time window length, a calculation request is sent to the information entropy calculation module; when the information entropy calculation module receives the calculation request, the information entropy is calculated according to the IDs and their quantities recorded in the time window; after the information entropy calculation is completed, the information entropy calculation module compares the information entropy value with the legal interval, and if the information entropy in the time window exceeds the legal interval, an exception flag is sent to the exception management unit and the exception ID buffer; the exception ID buffer module is used to cache the ID in the abnormal time window for subsequent in-depth analysis by other devices; the exception management unit is used to receive an exception flag signal from the information entropy calculation module and dynamically adjust the abnormal window count value; if the entropy value deviates from the normal range, the abnormal window count value is increased by one; if the entropy value returns to the normal range, the abnormal window count value is reduced by one; when the abnormal count value exceeds the preset risk threshold, the intrusion detection module will trigger a risk interrupt.

[0014] As a further improvement of the present invention, the time window is configured by the TIME_WINDOW field of the DFT_CFG register, and can be set to a maximum of 64 seconds.

[0015] As a further improvement of the present invention, the legal interval is the ENTROPY_BOTTOM and ENTROPY_TOP fields. If the abnormal count value further exceeds the dangerous threshold, when the node is configured as an ECU, an abnormal notification data frame is sent and a dangerous interrupt is triggered; when the node is configured as a gateway, only a dangerous interrupt is triggered; the specific status of the ECU is displayed through the ABN_STAT field of the STAT register; when the ABN_STAT value is 0, it indicates that the node is in a normal working state; when the value is 1, it indicates that the node is in a risky state; when the value is 2, it indicates that the node is in a dangerous state.

[0016] As a further improvement of the present invention, the bit stream controller includes a sending bit stream controller, a receiving bit stream controller and a data path. When the sending conditions are met, the data path reads the original data from the sending buffer and parses it to obtain the ID, DATA and data frame type of the data frame to be sent, and then sets the SEND_VLD signal to a high level, so that the sending bit stream controller starts data frame transmission. At the same time, the ID and DATA signals are respectively assigned the ID and 0 of the data frame to be sent. When the encryption and authentication calculation is completed, the receiving bit stream controller assigns the DATA signal to the ciphertext result; if the encryption and authentication calculation is completed before the data frame is sent to the data field, the data transmission is guaranteed to be correct.

[0017] As a further improvement of the present invention, the HMAC-SHA256 module is used to execute the HMAC-SHA256 algorithm, including an HMAC_FSM module and a SHA256_CORE module; the SHA256_CORE module implements the SHA256 algorithm, and is composed of a W calculation unit, a K calculation unit, a compression function and a state machine, including the generation of W parameters and K parameters, iterative update of the compression function and calculation of the final hash value; the HMAC_FSM module is responsible for generating the data blocks inner_block and outer_block to be processed according to the input data, mode and key according to specific filling rules, and sending these data blocks to the SHA256_CORE module in batches for processing.

[0018] As a further improvement of the present invention, the AES module is used to execute the AES algorithm, and the bitstream controller first calls the HMAC-SHA256 module to complete the MAC calculation, and then concatenates {EX_DATA||DLC||TIME} and the 32-bit truncation of MAC into 128-bit encrypted plaintext and performs the AES encryption operation; in order to reduce the encryption authentication operation time, when the MAC calculation starts, the bitstream controller sends the encryption key to the AES module, and enables the AES module to start key expansion; when the MAC calculation is completed, the bitstream controller sends the 128-bit plaintext to the AES module and enables the AES module to start round function calculation.

[0019] As a further improvement of the present invention, the error logic management module is used to manage the error state of the node in the CAN bus system by monitoring the sending error count and the receiving error count. According to the sending error count register value and the receiving error count register value, the CAN node may be in: active error state, passive error state and bus off state; the active error state is the default state of the CAN node. When an error is detected, the node sends an active error data frame; when the sending error register value or the receiving error register value is greater than 127, the node enters the passive error state. At this time, if an error is detected, the node will send a passive error data frame; when the active register value or the receiving error register value is greater than 255, the node enters the bus off state and does not participate in bus communication; the sending error count register and the receiving error count register are both defined in the STAT register, the TEC field of the STAT register represents the sending error count register, the REC field represents the receiving error count register, and ERR_STAT represents the error state of the CAN node.

[0020] As a further improvement of the present invention, the CAN controller complies with the ISO11898 protocol, and its working process is as follows:

[0021] S1. When a node attempts to send a CAN data frame, the processor writes the raw data into the buffer of the CAN controller.

[0022] S2. When the sending conditions are met, the CAN controller calls the HMAC-SHA256 and AES modules to complete the encryption and authentication operations, and then sends the data frame to the CAN bus according to the CAN bus protocol rules and encryption and authentication strategies;

[0023] S3. When the bus data frame ID meets the screening conditions of the receiving node and the CRC check is correct, the receiving node completes the decryption, MAC comparison and count value comparison operations in sequence to determine whether the message is legal;

[0024] S4. If it is legal, the received data will be written into the receiving buffer and the ID of the successfully received data frame will be sent to the intrusion detection module; when the count value or MAC of the received data frame is illegal, if the device is a gateway node, an interrupt request will be sent to the processor to notify the processor that the count value or MAC is illegal during the reception of the data frame, and there may be an abnormal attack; if the device is an ECU node, in addition to sending an interrupt request to the processor, an abnormal notification data frame will be sent at the same time to notify the gateway node of the possible abnormal attack behavior; when the intrusion detection module detects that the entropy value deviates from the normal situation, an interrupt request will also be generated or an abnormal notification data frame will be sent.

[0025] The beneficial effects of the present invention are as follows: by designing a security module inside the CAN controller and using a strategy of parallel processing of data frame transmission and encryption calculation, the problem of independent implementation of the CAN controller and the security module in the existing method, which will introduce additional data handling overhead, is solved, and efficient transmission of CAN encrypted data is achieved, which has good development and application. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 This is a specific structural diagram of the security-enhanced CAN controller of the present invention.

[0027] Figure 2 This is the specific structure diagram of the intrusion detection module.

[0028] Figure 3 Figure 2 is a block diagram of a bit stream controller.

[0029] Figure 4 This is the HMAC-SHA256 structure diagram.

[0030] Figure 5 This is the state transition diagram of the AES algorithm. DETAILED DESCRIPTION

[0031] The present invention will be further explained below in conjunction with the accompanying drawings and specific implementations. It should be understood that the following specific implementations are only used to illustrate the present invention and are not used to limit the scope of the present invention.

[0032] Figure 1 The specific structure of the CAN controller is described, and the more important ones include the intrusion detection module, the bit stream controller module, the HMAC-SHA256 module and the AES module.

[0033] Figure 2 The specific structure of the intrusion detection module is described. The intrusion detection module consists of the TIME_WINDOW counter, anomaly management, information entropy calculation and anomaly ID buffer module. The intrusion detection module is a key link in the network security system. It realizes real-time monitoring of network traffic and rapid identification of potential threats through the coordinated work of carefully designed components.

[0034] The TIME_WINDOW counter is responsible for the counting function. When the count value reaches the expected time window length, it sends a calculation request to the information entropy calculation module. The time window length is controlled by the detection configuration register (DFT_CFG). The TIME_WINDOW field indicates the time window length used for information entropy calculation, in system clocks, and the maximum time window length supported is 64s.

[0035] Since the time window length is adjustable, if the FIFO structure is used to buffer the received ID, its capacity cannot be estimated. Therefore, 56 registers (28 registers are used to store the successfully received ID, and 28 registers are used to describe the number of occurrences of the corresponding ID) are used to store the reception of the data frame in the current time window. When the input ID is not within the recording range, the ID is recorded and the corresponding count register value is increased by one; when the input ID is within the recording range, the corresponding count register is increased by one.

[0036] When the information entropy calculation module receives a calculation request, the module calculates the information entropy based on the IDs buffered in the time window and the corresponding number. The module first converts the fixed-point number (the current number of IDs and the total number of IDs) into a floating-point number, calls the floating-point division module to obtain the probability p of the ID occurrence, and then calculates ln2 and lnp. The base-changing formula is used to obtain the information amount of the current ID. The above process is repeated until the calculation of all IDs is completed, and finally the information entropy is obtained.

[0037] After completing the information entropy calculation, the information entropy calculation module compares the information entropy value with the legal interval. If the information entropy exceeds the reasonable interval within the time window, the module sends an exception flag to the exception management unit and the exception ID buffer.

[0038] The function of the abnormal ID buffer module is to cache the ID within the abnormal time window for subsequent in-depth analysis by other devices. The abnormal management unit receives the abnormal flag signal from the information entropy calculation module and dynamically adjusts the abnormal window count value. If the entropy value deviates from the normal range, the abnormal window count value is increased by one; if the entropy value returns to the normal range, the abnormal window count value is reduced by one. When the abnormal count value exceeds the preset risk threshold, the intrusion detection module will trigger a risk interrupt. If the abnormal count value further exceeds the danger threshold, when the node is configured as an ECU, an abnormal notification data frame is sent and a danger interrupt is triggered; when the node is configured as a gateway, only a danger interrupt is triggered. The specific status of the ECU is displayed through the ABN_STAT field of the STAT register. When the ABN_STAT value is 0, it means that the node is in normal working state; when the value is 1, it means that the node is in a risk state; when the value is 2, it means that the node is in a dangerous state.

[0039] Figure 3 The design block diagram of the bitstream controller is described. In the architecture of the safety-enhanced CAN controller, the bitstream controller occupies a core position and is responsible for performing multiple key tasks. It greatly improves the readability, maintainability and overall performance of the code. The three components of the transmitting bitstream controller, the receiving bitstream controller and the data path each perform their respective duties and together weave an efficient and secure data transmission network.

[0040] The transmit bit stream controller has three key functions:

[0041] (1) Generate a bit stream for CRC calculation and call the CRC check module to generate a CRC check code.

[0042] (2) Complete bit filling and adding fixed bit operations, and generate output levels according to the protocol specifications and the data content sent into the data path.

[0043] (3) Complete multi-host arbitration and automatic retransmission mechanism to ensure efficient and orderly communication in the network.

[0044] When the SEND_VLD signal is valid, the send bit stream controller starts data frame transmission.

[0045] The receive bit stream controller has three key functions:

[0046] (1) When the CAN controller is in the sending state, it is responsible for monitoring the bus level status, comparing the controller output level with the bus level, and generating an arbitration result.

[0047] (2) When the CAN controller is in the receiving state, it is responsible for determining whether to receive the CAN data frame from the bus based on the contents of the filter register.

[0048] (3) Send the CAN data frame obtained from the bus to the data path.

[0049] When the start of a frame is detected from the bus, the receiving bit stream controller receives the CAN data frame from the bus according to the data frame format state machine. If an error occurs during the reception process, the controller will suspend data reception and report the corresponding error identification to the error handling logic unit. When no error occurs, the controller will check whether the ID of the data frame matches the content of the preset filter register group. If the two are inconsistent, the message will be discarded; if they match, the CAN data message will be further processed, and the ID, DATA and frame type of the data frame will be extracted and sent to the data path.

[0050] The data path mainly undertakes the following six key functions:

[0051] (1) Parse the original data obtained from the sending buffer to obtain the data frame type, ID field, DLC field and DATA field of the message to be sent.

[0052] (2) Combine the CAN message ID with the contents of the send permission register to detect illegal transmissions.

[0053] (3) When the encryption authentication mode is enabled, the session key and count value synchronization are completed.

[0054] (4) When the encryption authentication mode is enabled, the HMAC-SHA256 and AES modules are called to complete MAC calculation and data encryption.

[0055] (5) Pass the actual data frame content to the sending bit stream sensor.

[0056] (6) Processing data from the receiving bit stream controller. When the encryption authentication mode is not enabled, the successfully received data is directly converted into an original data frame; when the encryption authentication mode is enabled, decryption, MAC verification, and count value verification are completed, and the successfully received data frame is converted into an original data frame, which is then written into the receiving buffer and the corresponding register content is refreshed.

[0057] Figure 4 The structural diagram of HMAC-SHA256 is described. As a key encryption authentication method, the HMAC-SHA256 algorithm demonstrates its high efficiency and flexibility. The present invention plans the encryption authentication process before the data frame is sent in detail for the application scenario of HMAC-SHA256.

[0058] In order to achieve high-speed encryption authentication, the present invention designs an efficient hardware architecture, the core of which is composed of two modules: HMAC_FSM (HMAC finite state machine) and SHA256_CORE (SHA256 core processing unit).

[0059] SHA256_CORE is responsible for executing the core operations of the SHA256 algorithm, including the generation of W and K parameters, iterative updates of the compression function, and calculation of the final hash value. This module optimizes the internal data flow and control logic to ensure that the compression function calculation is completed once in each clock cycle, thereby meeting the system's demand for high-speed computing.

[0060] HMAC_FSM plays the role of data preprocessing and scheduling. It is responsible for generating the data blocks to be processed (inner_block and outer_block) according to the input data, mode and key according to the specific filling rules, and sending these data blocks to SHA256_CORE for processing in batches. By accurately controlling the flow direction and processing order of the data flow, HMAC_FSM ensures the smooth progress of the encryption and authentication process and finally outputs the correct MAC value.

[0061] Under the conditions of a system clock of 16 MHz and a communication rate of 1 Mbit / s, the present invention can complete encryption authentication calculations within 19 μs, fully meeting the real-time requirements.

[0062] Figure 5 The state transition diagram of the AES algorithm is described. The state machine has eight states: A_IDLE, A_EXT, A_EXTD, A_ADD, A_SUB, A_SHIFT, A_MIX and A_END. The solid arrows represent the encryption process state jumps, and the dotted arrows represent the decryption process state jumps.

[0063] A_IDLE: The default state after power-on reset. It jumps to A_EXT when the key initialization flag (key_init) is valid.

[0064] A_EXT: Generates the round key required for this operation through the initial key of the input port. When the extended key operation is completed, the state is transferred to A_EXTD.

[0065] A_EXTD: Indicates that the key extension is completed and waits for the calculation request signal (in_valid). When the in_valid signal is high, the state jumps to A_ADD.

[0066] A_ADD: Complete the XOR of the round key and the state matrix. When the module is in the encryption state and the round counter is less than 10, the state jumps to A_SUB after the operation is completed; when the module is in the encryption state and the round counter is equal to 10, the state transfers to A_END after the operation is completed. When the module is in the decryption state and the round counter is 0, the state jumps to A_SHIFT after the operation is completed; when the module is in the decryption state and the round counter is less than 10, the state jumps to A_MIX after the operation is completed; when the module is in the decryption state and the round counter is equal to 10, the state jumps to A_END after the operation is completed.

[0067] A_SUB: Complete byte substitution operation. When the module is in encryption state, after the operation is completed, the state jumps to A_SHIFT. When the module is in decryption state, after the operation is completed, the state jumps to A_ADD.

[0068] A_SHIFT: Complete the row shift operation. When the module is in the encryption state and the round counter is less than 10, after the operation is completed, the state jumps to A_MIX; when the module is in the encryption state and the round counter is equal to 10, after the operation is completed, the state jumps to A_END; when the module is in the decryption state, after the calculation is completed, the state jumps to A_SUB.

[0069] A_MIX: Complete column mixing calculation. After the column mixing calculation is completed, when the module is in encryption state, the state jumps to A_ADD; when the module is in decryption state, the state jumps to A_SHIFT.

[0070] A_END: ​​The final state after the operation is completed. The AES module writes the final output to the bitstream controller, and then the state jumps to A_IDLE.

[0071] In the AES algorithm, byte substitution and column mixing are computationally intensive, while row shift and round key addition are relatively simple and can be directly implemented with combinational logic to optimize resource usage. The state machine automatically jumps according to the encryption / decryption mode and round to ensure the correct execution of the algorithm. When the AES operation is completed, the encrypted data is sent back to the bitstream controller, ready to be sent, and the state machine is reset to A_IDLE to wait for the next operation.

[0072] It should be noted that the above content only illustrates the technical idea of ​​the present invention and cannot be used to limit the protection scope of the present invention. For ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principle of the present invention. These improvements and modifications all fall within the protection scope of the claims of the present invention.

Claims

1. A security-enhanced CAN controller based on encryption authentication and intrusion detection, characterized in that: It includes an intrusion detection module, a bit stream controller, an error logic management module, an HMAC-SHA256 module, an AES module, a register unit and a bit timing unit; wherein the intrusion detection module determines whether there is a security threat in the vehicle-mounted CAN communication network by receiving the information entropy of the data frame ID, so as to be able to respond quickly; the bit stream controller completes the encryption authentication operation internally by calling the AES module and the HMAC-SHA256 module to ensure the confidentiality, integrity and authenticity of the data transmission; the error logic management module is used to manage the error state of the node in the CAN bus system by monitoring the sending error count and the receiving error count to ensure the high availability of the data transmission system in the event of a node failure; the HMAC-SHA256 module is used to calculate the MAC value to complete the identity authentication, the AES module is used for the encryption and decryption calculation of the CAN data, and the bit timing unit is used to provide the bit stream controller with sampling points and sending points, and is responsible for the timing synchronization with other vehicle-mounted CAN communication network nodes.

2. A security-enhanced CAN controller based on encryption authentication and intrusion detection according to claim 1, characterized in that: The intrusion detection module uses information entropy analysis technology to monitor data frame anomalies in the CAN network, promptly discover and respond to potential network security threats. Its working status is controlled by the ENTR field of the CAN_CFG register. When the ENTR field is set to a high level, the intrusion detection module is activated.

3. A security-enhanced CAN controller based on encryption authentication and intrusion detection according to claim 2, characterized in that: The intrusion detection module includes a TIME_WINDOW counter, an information entropy calculation module, an exception management unit and an exception ID buffer unit; the TIME_WINDOW counter is responsible for counting, and when the count value reaches the preset time window length, a calculation request is sent to the information entropy calculation module; when the information entropy calculation module receives the calculation request, the information entropy is calculated according to the ID and its number recorded in the time window; after the information entropy calculation is completed, the information entropy calculation module compares the information entropy value with the legal interval, and if the information entropy in the time window exceeds the legal interval, an exception flag is sent to the exception management unit and the exception ID buffer; the exception ID buffer module is used to cache the ID in the abnormal time window for subsequent in-depth analysis by other devices; the exception management unit is used to receive the exception flag signal from the information entropy calculation module and dynamically adjust the abnormal window count value; If the entropy value deviates from the normal range, the abnormal window count value increases by one; if the entropy value returns to the normal range, the abnormal window count value decreases by one; when the abnormal count value exceeds the preset risk threshold, the intrusion detection module will trigger a risk interrupt.

4. A security-enhanced CAN controller based on encryption authentication and intrusion detection according to claim 3, characterized in that: The time window is configured by the TIME_WINDOW field of the DFT_CFG register and can be set to a maximum of 64 seconds.

5. A security-enhanced CAN controller based on encryption authentication and intrusion detection according to claim 3, characterized in that: The legal interval is the ENTROPY_BOTTOM and ENTROPY_TOP fields. If the abnormal count value further exceeds the dangerous threshold, when the node is configured as an ECU, an abnormal notification data frame is sent and a dangerous interrupt is triggered; when the node is configured as a gateway, only a dangerous interrupt is triggered; the specific status of the ECU is displayed through the ABN_STAT field of the STAT register; when the ABN_STAT value is 0, it indicates that the node is in normal working condition; when the value is 1, it indicates that the node is in a risky state; when the value is 2, it indicates that the node is in a dangerous state.

6. A security-enhanced CAN controller based on encryption authentication and intrusion detection according to claim 1, characterized in that: The bit stream controller includes a sending bit stream controller, a receiving bit stream controller and a data path. When the sending conditions are met, the data path reads the original data from the sending buffer and parses it to obtain the ID, DATA and data frame type of the data frame to be sent, and then sets the SEND_VLD signal to a high level, so that the sending bit stream controller starts data frame transmission. At the same time, the ID and DATA signals are respectively assigned the ID and 0 of the data frame to be sent. When the encryption and authentication calculations are completed, the receiving bit stream controller assigns the DATA signal to the ciphertext result; if the encryption and authentication calculations are completed before the data frame is sent to the data field, the data transmission is guaranteed to be correct.

7. A security-enhanced CAN controller based on encryption authentication and intrusion detection according to claim 1, characterized in that: The HMAC-SHA256 module is used to execute the HMAC-SHA256 algorithm, including the HMAC_FSM module and the SHA256_CORE module; the SHA256_CORE module implements the SHA256 algorithm, and is composed of a W calculation unit, a K calculation unit, a compression function and a state machine, including the generation of W parameters and K parameters, the iterative update of the compression function and the calculation of the final hash value; the HMAC_FSM module is responsible for generating the data blocks inner_block and outer_block to be processed according to the input data, mode and key according to specific filling rules, and sending these data blocks to the SHA256_CORE module in batches for processing.

8. The security-enhanced CAN controller based on encryption authentication and intrusion detection according to claim 1, characterized in that: The AES module is used to execute the AES algorithm. The bitstream controller first calls the HMAC-SHA256 module to complete the MAC calculation, and then concatenates {EX_DATA||DLC||TIME} and the 32-bit truncation of MAC into 128-bit encrypted plaintext and performs the AES encryption operation. In order to reduce the encryption authentication operation time, when the MAC calculation starts, the bitstream controller sends the encryption key to the AES module and enables the AES module to start key expansion. When the MAC calculation is completed, the bitstream controller sends the 128-bit plaintext to the AES module and enables the AES module to start round function calculation.

9. A security-enhanced CAN controller based on encryption authentication and intrusion detection according to claim 1, characterized in that: The error logic management module is used to manage the error state of the node in the CAN bus system by monitoring the sending error count and the receiving error count. According to the sending error count register value and the receiving error count register value, the CAN node may be in: active error state, passive error state and bus off state; the active error state is the default state of the CAN node. When an error is detected, the node sends an active error data frame; When the send error register value or the receive error register value is greater than 127, the node enters the passive error state. At this time, if an error is detected, the node will send a passive error data frame; When the active register value or the receive error register value is greater than 255, the node enters the bus-off state and does not participate in bus communication; The transmit error count register and receive error count register are both defined in the STAT register. The TEC field of the STAT register represents the transmit error count register, the REC field represents the receive error count register, and ERR_STAT represents the error status of the CAN node.

10. A security-enhanced CAN controller based on encryption authentication and intrusion detection according to claim 1, characterized in that: The CAN controller complies with the ISO11898 protocol, and its working process is as follows: S1. When a node attempts to send a CAN data frame, the processor writes the raw data into the buffer of the CAN controller. S2. When the sending conditions are met, the CAN controller calls the HMAC-SHA256 and AES modules to complete the encryption and authentication operations, and then sends the data frame to the CAN bus according to the CAN bus protocol rules and encryption and authentication strategies; S3. When the bus data frame ID meets the screening conditions of the receiving node and the CRC check is correct, the receiving node completes the decryption, MAC comparison and count value comparison operations in sequence to determine whether the message is legal; S4. If it is legal, the received data will be written into the receiving buffer and the ID of the successfully received data frame will be sent to the intrusion detection module; when the count value or MAC of the received data frame is illegal, if the device is a gateway node, an interrupt request will be sent to the processor to notify the processor that the count value or MAC is illegal during the reception of the data frame, and there may be an abnormal attack; if the device is an ECU node, in addition to sending an interrupt request to the processor, an abnormal notification data frame will be sent at the same time to notify the gateway node of the possible abnormal attack behavior; when the intrusion detection module detects that the entropy value deviates from the normal situation, an interrupt request will also be generated or an abnormal notification data frame will be sent.

Images