Method for forming isolation groove, preparation method of semiconductor device and process equipment

Abstract

The invention provides a method for forming an isolation groove, a preparation method of a semiconductor device and process equipment, and the method for forming the isolation groove comprises the steps: forming a mask layer on a stacking structure, and enabling a mask opening of the mask layer to expose a partial region of the stacking structure; the stacked structure comprises a laminated structure and a plurality of storage columns penetrating through the laminated structure along a first direction, and the first direction is the thickness direction of the laminated structure; and alternately and circularly etching the laminated structure and the storage column in the exposed region of the stack structure to form an isolation groove. According to the scheme, the storage columns in the isolation grooves can be removed, so that the stacked structure is completely divided into a plurality of storage areas by the isolation grooves, and the storage density and the storage capacity can be improved.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a method for forming an isolation trench, a method for preparing a semiconductor device, and process equipment. Background Art

[0002] In order to break through the upper limit of the storage capacity of two-dimensional memory, three-dimensional memory came into being. Three-dimensional memory has broad application prospects due to its advantages such as large storage capacity, high storage density and small physical space occupation.

[0003] like Figure 1D and Figure 2D As shown, the three-dimensional memory includes a stacking structure 11 and an isolation groove 13. The stacking structure 11 includes a stacking structure 111 and a storage column 112 that penetrates the stacking structure 111. The isolation groove 13 is used to separate the stacking structure 11 into a plurality of storage areas A1. The storage column 112 is used to store information. Figure 1A and Figure 2A As shown, in the related art, an area A0 to be etched where no storage pillar 112 is set is usually reserved on the stacked structure 111 of the stacked structure 11, and the area A0 to be etched is etched to form the isolation groove 13. However, the reserved area A0 to be etched occupies the area of ​​the stacked structure 111, which will limit the density of the storage pillar 112, and is not conducive to improving the storage capacity of the three-dimensional memory. Therefore, the related art also increases the layout area of ​​the storage pillar 112 by reducing the size of the area A0 to be etched or not reserving the area A0 to be etched, which will cause the exposed storage pillar 112 to be unable to be completely etched. Summary of the invention

[0004] The present application provides a method for forming an isolation trench, a method for preparing a semiconductor device, and a process equipment to solve the technical problems existing in the related art.

[0005] In a first aspect, the present application provides a method for forming an isolation groove, comprising: forming a mask layer on a stacked structure so that a mask opening of the mask layer exposes a partial area of ​​the stacked structure; the stacked structure comprises a stacked structure and a plurality of storage pillars extending through the stacked structure along a first direction, the first direction being a thickness direction of the stacked structure; and alternately cyclically etching the stacked structure and the storage pillars in the exposed area of ​​the stacked structure to form an isolation groove.

[0006] In one embodiment, alternately cyclically etching the stacked structure and the storage pillars in the exposed area of ​​the stacked structure includes: cyclically performing a stacked structure etching step and a storage pillar etching step in sequence until the stacked structure and the storage pillars in the exposed area are removed.

[0007] In one embodiment, the method further comprises at least one of the following:

[0008] Before each stack structure etching step is performed, a sacrificial layer deposition step is performed to deposit a first sacrificial layer on a side of the mask layer away from the stack structure; the first sacrificial layer is consumed during the stack structure etching step;

[0009] After each stacked structure etching step and before the storage column etching step, a sacrificial layer deposition step is performed to deposit a second sacrificial layer on the side of the mask layer away from the stacked structure; the second sacrificial layer is consumed during the storage column etching step.

[0010] In one embodiment, along the radial direction of the storage column, the storage column includes a first electrode and a storage functional layer surrounding the first electrode; during the etching step of the stacked structure, the etching rate of the first electrode is close to the etching rate of the stacked structure, and the etching rate of the storage functional layer is less than the etching rate of the stacked structure.

[0011] In one embodiment, the stacked structure includes a first insulating layer and a word line layer alternately stacked in a direction opposite to the first direction; during the stacked structure etching step, there is no etching selectivity for the first insulating layer, the word line layer and the first electrode.

[0012] In one embodiment, during the storage pillar etching step, the etching rate of the storage functional layer is greater than the etching rate of the stacked structure.

[0013] In one embodiment, the stacked structure includes a first stacked structure and a second stacked structure stacked in a direction opposite to the first direction, the stacked structure also includes a substrate located on a side of the first stacked structure away from the second stacked structure, and a second insulating layer located between the substrate and the first stacked structure and between the first stacked structure and the second stacked structure, the second insulating layer being penetrated by a storage column; the method also includes: during the execution of the stacked structure etching step, the etching stops at the surface of the second insulating layer to expose a partial area of ​​the second insulating layer; during the execution of the storage column etching step, the exposed area of ​​the second insulating layer is simultaneously etched.

[0014] In one embodiment, the etching gas in the stack structure etching step includes a fluorine-based gas that does not contain hydrogen.

[0015] In one embodiment, the etching gas in the stacked structure etching step further includes a chlorine-based gas.

[0016] In one embodiment, the etching in the storage pillar etching step is an etching mainly based on physical bombardment.

[0017] In one embodiment, the etching gas of the storage column etching step includes a first etching gas and a second etching gas, and the molecular mass of the first etching gas is greater than the molecular mass of the second etching gas; the bombardment force of the physical bombardment on the storage column is adjusted by adjusting the flow ratio between the first etching gas and the second etching gas.

[0018] In one embodiment, a flow ratio between the first etching gas and the second etching gas is equal to or greater than 2.

[0019] In one embodiment, both the stacked structure etching step and the storage column etching step are etched in a lower electrode pulse radio frequency mode, and the lower electrode power of the storage column etching step is greater than the lower electrode power of the stacked structure etching step.

[0020] In one embodiment, the deposition gas of the sacrificial layer deposition step includes a carbon-containing and hydrogen-containing gas.

[0021] A second aspect of the present application provides a method for preparing a semiconductor device, comprising: providing a stacking structure; the stacking structure comprises a laminated structure and a storage column extending through the laminated structure in a first direction; and using any one of the above-mentioned methods for forming an isolation trench to form at least one isolation trench in the stacking structure to separate the stacking structure into a plurality of storage areas.

[0022] The third aspect of the present application provides a semiconductor process equipment including: a process chamber, an air intake assembly, an upper electrode assembly, a lower electrode assembly and a controller, the controller including at least one processor and at least one memory, the memory storing a computer program, and when the computer program is executed by the processor, it implements the method for forming an isolation groove of any one of the above-mentioned embodiments or the method for preparing a semiconductor device of any one of the above-mentioned embodiments.

[0023] The advantages or beneficial effects of the above technical solution include at least: first forming a mask layer on the stacked structure, so that the mask opening of the mask layer exposes a partial area of ​​the stacked structure, and then alternately and cyclically etching the stacked structure and the storage column in the exposed area of ​​the stacked structure downward along the mask opening, so that an isolation groove penetrating the stacked structure along the first direction can be formed in the stacked structure, so that the isolation groove is clean and no storage column remains, and the isolation groove can completely separate the stacked structure into multiple storage areas, so that the storage areas constitute the page storage structure of the three-dimensional memory. In this way, the method of the present application can be more suitable for application in the scenario where the stacked structure is completely separated into multiple storage areas after reducing the area of ​​the reserved area to be etched or not reserving the area to be etched to densely distribute the storage columns, so as to realize the etching of narrow isolation grooves under the condition of densely distributed storage columns, which is conducive to improving the storage capacity of the three-dimensional memory. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] The accompanying drawings herein are incorporated into and constitute a part of the specification, illustrate embodiments consistent with the present application, and together with the specification are used to explain the principles of the present application. In addition, these drawings and text descriptions are not intended to limit the scope of the concept of the present application in any way, but to illustrate the concept of the present application for those skilled in the art by referring to specific embodiments.

[0025] Figures 1A to 1D It is a schematic plan view of the structure of each step in the method for forming an isolation trench in the related art.

[0026] FIG. 2A to FIG. 2D Shown Figures 1A to 1D A schematic diagram of the cross-sectional structure corresponding to the cutting line L1-L2 in the figure.

[0027] Figure 3A and Figure 3C FIG. 1 is a schematic plan view of the structure of each step in a method for forming an isolation trench according to another related art.

[0028] Figure 3B Shown Figure 3A Schematic diagram of the cross-sectional structure along the cutting line L1-L2.

[0029] Figure 3D Shown Figure 3C Schematic diagram of the cross-sectional structure along the cutting line L1-L2.

[0030] Figure 4A and Figure 4C FIG. 1 is a schematic plan view of the structure of each step in a method for forming an isolation trench according to another related art.

[0031] Figure 4B Shown Figure 4A Schematic diagram of the cross-sectional structure along the cutting line L1-L2.

[0032] Figure 4D Shown Figure 4C Schematic diagram of the cross-sectional structure along the cutting line L1-L2.

[0033] Figure 5 FIG. 1 is a schematic diagram showing a cross-sectional structure of an isolation trench formed by a method for forming an isolation trench according to another related technology.

[0034] Figure 6 FIG. 1 is a schematic flow chart of a method for forming an isolation trench according to an embodiment of the present application.

[0035] 7A to 7D Shown is a schematic plan view of the structure of each step in a method for forming a groove according to an embodiment of the present application.

[0036] FIG. 8A to FIG. 8GShown is a schematic cross-sectional structure diagram of each step in a method for forming a groove in an embodiment of the present application.

[0037] Fig.9A FIG. 1 is a schematic diagram of the cross-sectional structure of the etching morphology after forming the first sacrificial layer in one embodiment of the present application.

[0038] Fig. 9B FIG. 1 is a schematic diagram of the cross-sectional structure of the etching morphology after forming the second sacrificial layer in one embodiment of the present application.

[0039] Fig.10 The figure shows a structural schematic diagram of an isolation groove formed without providing a sacrificial layer deposition step in the process of implementing the present application.

[0040] Fig.11 Shown is a schematic structural diagram of a semiconductor process equipment according to an embodiment of the present application. DETAILED DESCRIPTION

[0041] In the following, only some exemplary embodiments are briefly described. As those skilled in the art will appreciate, the described embodiments may be modified in various ways without departing from the spirit or scope of the present application. Therefore, the drawings and descriptions are considered to be exemplary and non-restrictive in nature.

[0042] Figures 1A to 1D It is a schematic plan view of the structure of each step in the method for forming an isolation trench in the related art. FIG. 2A to FIG. 2D Shown Figures 1A to 1D A schematic diagram of the cross-sectional structure corresponding to the cutting line L1-L2 in the figure.

[0043] In the related art, a method for forming an isolation trench includes the following steps S110 to S140 .

[0044] Step S110: Figure 1A and Figure 2A As shown, a stacking structure 11 is provided; the stacking structure 11 includes a stacking structure 111 and a storage column 112 that penetrates the stacking structure 111 along a first direction D1, and the first direction D1 is the thickness direction of the stacking structure 111. The stacking structure 11 includes a first insulating layer 1111 and a word line layer 1112 that are alternately stacked in the opposite direction of the first direction D1. Along the radial direction of the storage column 112, the storage column 112 includes a first electrode 1121 and a storage function layer 1122 that surrounds the first electrode 1121.

[0045] Step S120: Figure 1B and Figure 2B As shown, a mask layer 12 is formed on the stacked structure 11 , and a mask opening 12 a of the mask layer 12 exposes a reserved area A0 to be etched on the stacked structure 111 .

[0046] Step S130: Figure 1C and Figure 2C As shown, the to-be-etched area A0 of the stacked structure 111 is etched downward along the mask opening 12a to form an isolation trench 13 penetrating the stacked structure 111 along a second direction D2. The second direction D2 is perpendicular to the first direction D1.

[0047] Step S140: Figure 1D and Figure 2D As shown, the mask layer 12 is removed.

[0048] In related technologies, such as FIG. 3A to FIG. 3D As shown, since the reserved area A0 to be etched on the stacked structure 111 occupies the area of ​​the stacked structure 111, the density of the storage pillars 112 is limited, which is not conducive to improving the storage capacity of the three-dimensional memory. Therefore, the layout area of ​​the storage pillars 112 can be increased by reducing the size of the area A0 to be etched or not reserving the area A0 to be etched, thereby improving the density of the storage pillars 112. The inventors found in the process of implementing the present application that: 4A to 4D , Figure 5 As shown, in the case where the size of the area A0 to be etched is reduced or the area A0 to be etched is not reserved, when the mask opening 12a exposes a partial area of ​​the stacking structure 11, a partial area of ​​the stacking structure 111 and at least a partial area of ​​a partial storage column 112 will be located in the exposed area of ​​the stacking structure 11; in the process of etching the stacking structure 111, since the storage column 112 located in the exposed area cannot be etched synchronously, it will stand in the isolation groove 13 that is finally formed, resulting in the isolation groove 13 being unable to completely separate the stacking structure 11 into multiple storage areas A1, and the storage area A1 cannot constitute the page storage structure required for the three-dimensional memory.

[0049] Specifically, for example, FIG. 3A to FIG. 3D As shown in FIG. 1 , when the area of ​​the to-be-etched region A0 reserved in the stacked structure 111 is reduced, the lateral size of the to-be-etched region A0 becomes narrower, and the lateral size of the mask opening 12a of the mask layer 12 on the stacked structure 11 needs to be reduced accordingly to adapt to the size of the to-be-etched region A0, and then after the to-be-etched region A0 is etched downward along the mask opening 12a, an isolation trench 13 with a smaller lateral size can be formed. However, as 4A to 4DAs shown, when the lateral dimensions of the to-be-etched area A0 and the mask opening 12a of the stacked structure 111 are both reduced, the difficulty of aligning the mask opening 12a with the to-be-etched area A0 will increase, and the mask opening 12a will be easily offset during the photolithography process, so that the to-be-etched area A0 and a portion of at least one storage column 112 are both located in the exposed area of ​​the stacked structure 11, and the related technology cannot synchronously etch the storage column 112 in the exposed area during the etching of the to-be-etched area A0, causing a portion of the storage column 112 located in the exposed area to stand in the isolation groove 13 and cannot be removed, resulting in the isolation groove 13 being unable to completely separate the stacked structure 11 into multiple storage areas A1.

[0050] For example, please also refer to Figure 5 When the stacked structure 111 does not reserve an area A0 to be etched, due to the high density of the storage column 112, a partial area of ​​the stacked structure 111 and at least one complete storage column 112 will be located in the exposed area of ​​the stacked structure 11, and the complete storage column 112 cannot be etched synchronously during the etching of the stacked structure 111, which will cause the storage column 112 to stand in the isolation groove 13 and cannot be completely removed, which will also cause the isolation groove 13 to be unable to completely separate the stacked structure 11 into multiple storage areas A1.

[0051] In view of this, the embodiment of the present application provides a method for forming an isolation trench, a method for manufacturing a semiconductor device and a process equipment, which can effectively solve the above technical problems existing in the related art. The embodiment of the present application is described in detail below with reference to the accompanying drawings.

[0052] Figure 6 FIG. 1 is a schematic flow chart of a method for forming an isolation trench according to an embodiment of the present application. 7A to 7D Shown is a schematic plan view of the structure of each step in a method for forming a groove according to an embodiment of the present application. FIG. 8A to FIG. 8G The figure shows the cross-sectional structure diagram of each step in the method for forming a groove in one embodiment of the present application. Fig. 8A , Figure 8B , Fig. 8E and Fig.8F One-to-one correspondence is 7A to 7D Schematic diagram of the cross-sectional structure along the cutting line L1-L2.

[0053] like Figure 6 As shown, the method for forming the isolation trench includes the following steps S210 to S220.

[0054] Step S210: FIG. 7A to FIG. 7B , FIG. 8A to FIG. 8BAs shown, a mask layer 12 is formed on the stacking structure 11 so that the mask opening 12a of the mask layer 12 exposes a partial area of ​​the stacking structure 11; the stacking structure 11 includes a stacking structure 111 and a plurality of storage pillars 112 penetrating the stacking structure 111 along a first direction D1, and the first direction D1 is the thickness direction of the stacking structure 111.

[0055] The mask opening 12a exposes a partial area of ​​the stacked structure 11, so that a partial area of ​​the stacked structure 111 and at least a partial area of ​​a portion of the storage pillars 112 are located in the exposed area of ​​the stacked structure 11. At least a partial area of ​​the storage pillars 112 are located in the exposed area of ​​the stacked structure 11, which may be: the entire area of ​​the first storage pillar 112a is located in the exposed area of ​​the stacked structure 11; and / or, a partial area of ​​the second storage pillar 112b is located in the exposed area of ​​the stacked structure 11.

[0056] The mask layer 12 may be a laminated structure of a dielectric anti-reflective coating 121 (DARC) and an advanced pattern film 122 (APF). The material of the dielectric anti-reflective coating 121 may be silicon oxynitride (SiON), and the material of the advanced pattern film 122 may be carbon.

[0057] Step S220: FIG. 8C to FIG. 8E , Figure 7C As shown, the stacked structure 111 and the storage pillar 112 in the exposed area of ​​the stacked structure 11 are etched alternately and cyclically to form an isolation trench 13. In this way, the stacked structure 111 and the storage pillar 112 in the exposed area of ​​the stacked structure 11 can be removed to form an isolation trench 13 that penetrates the stacked structure 11 along the first direction D1.

[0058] Exemplarily, the isolation trench 13 includes at least one. When there is one isolation trench 13, the isolation trench 13 separates the stack structure 11 into two storage areas A1; when there are N isolation trenches 13, the N isolation trenches 13 separate the stack structure 11 into N-1 storage areas A1, where N is an integer greater than 1. The isolation trench 13 may also penetrate the stack structure 11 along a second direction D2, where the second direction D2 is perpendicular to the first direction D1.

[0059] In the above scheme, a mask layer 12 is first formed on the stacked structure 11, so that the mask opening 12a of the mask layer 12 exposes a part of the stacked structure 11, and then the stacked structure 111 and the storage pillars 112 located in the exposed area of ​​the stacked structure 11 are alternately cyclically etched downward along the mask opening 12a, so that an isolation groove 13 penetrating the stacked structure 11 along the first direction D1 can be formed in the stacked structure 11, so that the isolation groove 13 is clean and no storage pillars 112 remain, and the isolation groove 13 can completely separate the stacked structure 11 into a plurality of storage areas A1, so that the storage areas A1 constitute the page storage structure of the three-dimensional memory. In this way, the method of the present application can be more suitable for application in the scenario where the stacked structure 111 is completely separated into a plurality of storage areas A1 after reducing the area of ​​the reserved area to be etched A0 or not reserving the area to be etched A0 to densely distribute the storage pillars 112, so as to realize the etching of the narrow isolation groove 13 under the condition of densely distributed storage pillars 112, which is conducive to improving the storage density and storage capacity of the three-dimensional memory.

[0060] For further information, please also refer to Fig.7D , Fig.8F and Figure 8G ,in, Figure 8G for Fig.7D The cross-sectional structure schematic diagram along the cutting line L3 - L4 , the method for forming the groove may further include: step S230 , removing the mask layer 12 .

[0061] It should be noted that if Fig.7D , Fig.8F and Figure 8G As shown, after the etching is completed, the first storage column 112a is completely removed, and after the portion of the second storage column 112b located in the exposed area is completely removed, the remaining portion of the second storage column 112b cannot constitute a complete storage column 112, and the remaining portion of the second storage column 112b cannot normally receive the electrical signal transmitted by the stacked structure 111 like a complete storage column, so that the remaining portion of the second storage column 112b cannot store information and will not affect the isolation performance of the isolation groove 13. The third storage column 112c located outside the exposed area of ​​the stacked structure 11 is a complete storage column with a normal storage function.

[0062] In one embodiment, FIG. 8C to FIG. 8E , Figure 7C As shown, the alternate cyclic etching of the stacked structure 111 and the storage pillar 112 in the exposed area of ​​the stacked structure 11 includes: sequentially and cyclically executing the stacked structure etching step and the storage pillar etching step until the stacked structure 111 and the storage pillar 112 in the exposed area are removed.

[0063] For example, in each cycle, the stacked structure etching step is first performed to etch the stacked structure 111 in the exposed area to a predetermined depth, so that the top surface of the storage column 112 in the exposed area protrudes from the top surface of the stacked structure 111 in the exposed area, and then the storage column etching step is performed to etch the protruding portion of the storage column 112 in the exposed area, so that the top surface of the stacked structure 111 in the exposed area is roughly flush with the top surface of the storage column 112 in the exposed area. In this way, by cyclically performing the stacked structure etching step and the storage column etching step to a preset total number of rounds, the stacked structure 111 and the storage column 112 in the exposed area can be completely removed, forming an isolation groove 13 that completely penetrates the stacked structure 11 along the first direction D1.

[0064] The preset total number of rounds is greater than or equal to 2. The preset total number of rounds can be selected and adjusted according to the thickness of the stacked structure 11 and the required etching depth, which is not limited in the embodiment of the present application.

[0065] In one embodiment, the method for forming the isolation trench further includes at least one of the following:

[0066] Please refer to Figure 8B , Fig.9A and Figure 8C , before each stack structure etching step is performed, a sacrificial layer deposition step is performed to deposit a first sacrificial layer 14 on the side of the mask layer 12 away from the stack structure 11; the first sacrificial layer 14 is consumed during the stack structure etching step;

[0067] Please refer to Figure 8C , Fig. 9B and Fig.8D After each stacked structure etching step and before the storage column etching step, a sacrificial layer deposition step is performed to deposit a second sacrificial layer 15 on the side of the mask layer 12 away from the stacked structure 11; the second sacrificial layer 15 is consumed during the storage column 112 etching step.

[0068] The inventor discovered during the implementation of this application that: Fig.10 As shown, in the process of alternately and cyclically etching the stacked structure 111 and the storage pillar 112 located in the exposed area downward along the mask opening 12a of the mask layer 12, the mask layer 12 will be consumed, and the lateral dimension of the mask opening 12a will gradually decrease along the first direction D1, so that the cross-section of the mask opening 12a will be trumpet-shaped; as the number of cycles increases, the mask layer 12 will be thinned and the trumpet-shaped morphology of the mask opening 12a will be transferred downward to the isolation groove 13, so that the top opening of the isolation groove 13 will also be trumpet-shaped, affecting the sidewall morphology of the isolation groove 13.

[0069] In the above scheme, in each cycle, before each stack structure etching step, a sacrificial layer deposition step is performed to deposit a first sacrificial layer 14 on the side of the mask layer 12 away from the stack structure 11, and the first sacrificial layer 14 is consumed in the process of executing the stack structure etching step; and / or, after each stack structure etching step and before the storage column etching step, a sacrificial layer deposition step is performed to deposit a second sacrificial layer 15 on the side of the mask layer 12 away from the stack structure 11, and the second sacrificial layer 15 is consumed in the process of executing the storage column etching step. The first sacrificial layer 14 and / or the second sacrificial layer 15 can be used to protect the mask layer 12, which can not only improve the selectivity of etching the stack structure 111 and / or the storage column 112 to the mask layer 12, but also avoid the top opening of the isolation groove 13 from forming a trumpet shape, which is conducive to ensuring that the isolation groove 13 is formed as shown in the figure. FIG. 8E to FIG. 8G The vertical sidewall morphology shown in any of the figures.

[0070] In one embodiment, Fig. 7A and Fig. 8A As shown, along the radial direction of the storage column 112, the storage column 112 includes a first electrode 1121 and a storage function layer 1122 surrounding the first electrode 1121; FIG. 8B to FIG. 8C As shown, during the stack structure etching step, the etching rate of the first electrode 1121 is close to the etching rate of the stack structure 111 , and the etching rate of the storage function layer 1122 is lower than the etching rate of the stack structure 111 .

[0071] Exemplarily, the materials of the first electrode 1121 of the storage column 112 and the storage function layer 1122 are different, so that in the process of executing the etching step of the stacked structure, the etching types of the first electrode 1121 and the storage function layer 1122 are different. For example, the etching of the first electrode 1121 is mainly chemical etching, and the chemical etching gas can also physically bombard the first electrode 1121, while the etching of the storage function layer 1122 is mainly physical bombardment, which leads to different etching rates of the two.

[0072] In the process of performing the stacked structure etching step, the etching rate of the first electrode 1121 is close to the etching rate of the stacked structure 111, and the first electrode 1121 in the exposed area can be etched and removed synchronously in the process of etching and removing the stacked structure 111 in the exposed area, which is beneficial to improving the etching efficiency of the first electrode 1121; the etching rate of the storage function layer 1122 is lower than the etching rate of the stacked structure 111, so that the removal of the storage function layer 1122 in the exposed area mainly depends on the storage column etching step, but in the process of performing the stacked structure etching step, part of the storage function layer 1122 can also be etched and removed, which is also beneficial to improving the etching efficiency of the storage function layer 1122. Based on this, in the process of performing the stacked structure etching step, the first electrode 1121 and part of the storage function layer 1122 in the exposed area can be etched synchronously, which is beneficial to improving the etching efficiency of the storage column 112.

[0073] In one embodiment, Fig. 8A As shown, the stacked structure 111 includes first insulating layers 1111 and word line layers 1112 alternately stacked in the opposite direction of the first direction D1; during the etching process of the stacked structure 111, there is no etching selectivity for the first insulating layer 1111, the word line layer 1112 and the first electrode 1121.

[0074] Exemplarily, the material of the first insulating layer 1111 may be silicon dioxide (SiO2), and the materials of the word line layer 1112 and the first electrode 1121 may both be metal materials, such as tungsten (W). By configuring the first insulating layer 1111, the word line layer 1112 and the first electrode 1121 to have no etching selectivity during the stacked structure etching step, the first electrode 1121 of the storage pillar 112 may be simultaneously etched during the etching of the stacked structure 111 composed of the alternately stacked first insulating layer 1111 and the word line layer 1112.

[0075] In one embodiment, please refer to FIG. 8C to FIG. 8D In the memory pillar etching step, the etching rate of the memory function layer 1122 is greater than the etching rate of the stacked structure 111. In this way, in each cycle, after the memory pillar etching step is performed, the top surface of the memory function layer 1122 can be made substantially flush with the top surface of the stacked structure 111, which is conducive to the synchronous removal of the stacked structure 111 and the memory pillar 112 in the exposed area.

[0076] In one embodiment, Fig. 8AAs shown, the stacked structure 111 includes a first stacked structure 111a and a second stacked structure 111b stacked in the opposite direction of the first direction D1, and the stacked structure 111 also includes a substrate 113 located on the side of the first stacked structure 111a away from the second stacked structure 111b, and a second insulating layer 114 located between the substrate 113 and the first stacked structure 111a and between the first stacked structure 111a and the second stacked structure 111b, and the second insulating layer 114 is penetrated by the storage column 112.

[0077] It should be noted that the storage column 112 is located in the core area of ​​the stack structure 11, and the stack structure 111 also includes a step area (not shown in the drawings). The step area of ​​the stack structure 11 has multiple steps and is provided with multiple conductive contact columns (not shown in the drawings). The multiple contact columns are all arranged in the stack structure 11 along the first direction D1, and one contact column stays on the word line layer 1112 at the top of each step. By setting the stack structure 11 as a first stack structure 111a and a second stack structure 111b stacked in the opposite direction of the first direction D1, the contact area between the contact column and the word line layer 1112 in the step area can be saved.

[0078] Exemplarily, the material of the second insulating layer 114 is an insulating material having a dielectric constant greater than that of the first insulating layer 1111. For example, the material of the first insulating layer 1111 is silicon dioxide, and the material of the second insulating layer 114 is aluminum oxide (Al2O3). By providing the second insulating layer 114 between the substrate 113 and the first stacked structure 111a, the influence between the stacked structure 113 and the substrate 113 can be isolated, and by providing the second insulating layer 114 between the first stacked structure 111a and the second stacked structure 111b, the influence between the first stacked structure 111a and the second stacked structure 111b can be isolated.

[0079] The method for forming the isolation trench also includes: FIG. 8C to FIG. 8E During the stack structure etching step, the etching stops at the surface of the second insulating layer 114 to expose a partial area of ​​the second insulating layer 114; during the storage column etching step, the exposed area of ​​the second insulating layer 114 is etched synchronously.

[0080] In the process of performing the stacked structure etching step, the second insulating layer 114 cannot be effectively etched, so that the etching stops on the surface of the second insulating layer 114, so that a part of the second insulating layer 114 is exposed from the mask opening 12a. In the process of performing the storage column etching step, the exposed area of ​​the second insulating layer 114 can be synchronously etched by the exposed area of ​​the second insulating layer 114 and the storage function layer 1122 of the storage column 112. In this way, in the process of performing the storage column etching step, the second insulating layer 114 in the exposed area can be synchronously etched, which is conducive to improving the etching efficiency and saving the etching process.

[0081] In one embodiment, please refer to FIG. 8B to FIG. 8C , the etching gas in the stack structure etching step includes a fluorine-based gas that does not contain hydrogen.

[0082] Exemplarily, the fluorine-based gas containing no hydrogen includes nitrogen trifluoride (NF3) and carbon tetrafluoride (CF4), wherein the flow rate of nitrogen trifluoride may range from 20 sccm to 200 sccm (including the end value), and the flow rate of carbon tetrafluoride may range from 10 sccm to 100 sccm (including the end value).

[0083] Please also read FIG. 8B to FIG. 8C The material of the first insulating layer 1111 of the stacked structure 111 may be silicon dioxide, and the material of the word line layer 1112 of the stacked structure 111 may be tungsten. Etching byproducts generated by etching the first insulating layer 1111 with nitrogen trifluoride include silicon tetrafluoride (SiF4), nitric oxide (NO) and nitrogen dioxide (NO2), and etching byproducts generated by etching the word line layer 1112 with nitrogen trifluoride include tungsten hexafluoride (WF6) and nitrogen (N2); etching byproducts generated by etching the first insulating layer 1111 with carbon tetrafluoride include silicon tetrafluoride, carbon monoxide (CO) and carbon dioxide (CO2).

[0084] In the related art, the etching gas of the stacked structure 111 includes hydrogen-containing fluorine-based gases such as difluoromethane (CH2CF2) and trifluoromethane (CHF3). In the process of etching the stacked structure 111 of the related art, too many carbon-containing and hydrogen-containing polymers will be generated, which are easy to hinder the etching reaction, thereby reducing the etching rate of the stacked structure 111. Compared with the related art, the above scheme uses a hydrogen-free fluorine-based gas as the etching gas for the stacked structure etching step, which is conducive to reducing the generation of carbon-containing and hydrogen-containing polymers, avoiding hindering the etching reaction, and thus helping to quickly etch the stacked structure 111 and improve the etching rate.

[0085] In one embodiment, the etching gas in the stacked structure etching step further includes a chlorine-based gas.

[0086] Exemplarily, the chlorine-based gas includes chlorine gas, and the flow rate of the chlorine gas is in the range of 10 sccm to 100 sccm (including end points).

[0087] Please also read FIG. 8B to FIG. 8C The word line layer 1112 is made of tungsten. Using chlorine gas to etch the word line layer 1112 can generate gaseous tungsten hexachloride (WCl6). In this way, in the stacked structure etching step, the chlorine-based gas can be used to accelerate the etching of the word line layer 1112.

[0088] Furthermore, the auxiliary gas of the stacked structure etching step includes nitrogen (N2) and argon (Ar), the flow rate of nitrogen is in the range of 10sccm to 100sccm (including the end value), and the flow rate of argon is in the range of 100sccm to 300sccm (including the end value). Selecting nitrogen and argon as the auxiliary gas of the stacked structure etching step can not only promote the electrolysis of the etching gas into plasma, but also improve the uniformity of etching.

[0089] In the above scheme, in the stacked structure etching step, by combining the fluorine-based gas, chlorine-based gas and auxiliary gas that do not contain hydrogen, the stacked structure 111 can be quickly etched, and the first electrode 1121 of the storage column 112 can be simultaneously etched, and the storage function layer 1122 of a part of the storage column 112 can be slowly etched, which is conducive to improving the etching rate. In addition, it is found in actual applications that if the flow rate of these gases is less than the minimum value of the corresponding flow rate range, the etching rate of the stacked structure 111 is too small; if the flow rate of these gases is greater than the maximum value of the corresponding flow rate range, the selectivity of the mask layer 12 will be seriously reduced, or the etching rate of the first electrode 1121 will be greater than the etching rate of the stacked structure 111, and it is impossible to achieve the process of etching the stacked structure 111. In the process of etching the stacked structure 111, the first electrode 1121 of the storage column 112 cannot be simultaneously etched. Therefore, by controlling these gases within the corresponding flow rate range, the stacked structure 111 can be quickly etched, and the first electrode 1121 of the storage column 112 can be simultaneously etched.

[0090] For further information, please also refer to FIG. 8B to FIG. 8C , the process conditions of the stacked structure etching step also include at least one of the following:

[0091] The pressure range of the process chamber is 4mTorr to 10mTorr (including the end values);

[0092] The upper electrode power ranges from 500W to 1200W (including the end points).

[0093] In the process of etching the stacked structure 111 , by controlling the pressure of the process chamber and the power of the upper electrode to be within corresponding numerical ranges, efficient electrolysis of the etching gas to generate plasma can be promoted.

[0094] In one embodiment, the etching in the storage pillar etching step is an etching mainly based on physical bombardment.

[0095] For example, please refer to FIG. 8B to FIG. 8C In the stacked structure etching step, the first electrode 1121 of the storage column 112 will be etched synchronously, such as Figure 8C As shown in FIG. D, the storage column etching step is mainly used to etch the storage function layer 1122 of the storage column 112. The material of the storage function layer 1122 is usually a high dielectric constant material (High-K), such as hafnium oxide or zirconium oxide, which is usually etched by an etching method based on physical bombardment. Therefore, by selecting the etching method of the storage column etching step as an etching method based on physical bombardment, the storage function layer 1122 of the storage column 112 can be effectively etched.

[0096] In one embodiment, please refer to FIG. 8C to FIG. 8D The etching gas of the storage column etching step includes a first etching gas and a second etching gas, and the molecular mass of the first etching gas is greater than the molecular mass of the second etching gas; the bombardment force of the physical bombardment on the storage column 112 is adjusted by adjusting the flow ratio between the first etching gas and the second etching gas.

[0097] Exemplarily, the first etching gas may be boron trichloride (BCl3), and the second etching gas may be chlorine (Cl2), wherein the molecular mass of boron trichloride is greater than the molecular mass of chlorine. In the storage column etching step, the greater the molecular mass of the etching gas, the greater the bombardment force of the physical bombardment on the storage function layer 1122 of the storage column 112. By adjusting the flow ratio between the first etching gas and the second etching gas, the bombardment force of the physical bombardment of the storage function layer 1122 by the etching gas can be flexibly adjusted to adapt it to the process requirements. It should be noted that the first etching gas and the second etching gas can be selected and adjusted according to actual needs, and the embodiments of the present application are not limited to this.

[0098] In one embodiment, a flow ratio between the first etching gas and the second etching gas is equal to or greater than 2.

[0099] For example, the flow rate of the first etching gas may be in the range of 60 sccm to 300 sccm (including the end value), and the flow rate of the second etching gas may be in the range of 30 sccm to 100 sccm (including the end value). By controlling the ratio between the first etching gas and the second etching gas to be equal to or greater than 2, the etching gas may be controlled to physically bombard the storage function layer 1122 of the storage column 112 with a suitable bombardment force, so as to quickly remove the storage function layer 1122 located in the exposed area.

[0100] For further information, please also refer to FIG. 8C to FIG. 8DThe process conditions of the storage column etching step also include at least one of the following:

[0101] The auxiliary gas includes argon (Ar), and the flow rate of the argon gas ranges from 50 sccm to 300 sccm (including the end value);

[0102] The pressure range of the process chamber is 4mTorr to 12mTorr (including the end values);

[0103] The upper electrode power ranges from 500W to 1200W (including the end points).

[0104] In the storage column etching step, the auxiliary gas is used to improve the etching uniformity and increase the physical bombardment effect, and the pressure of the process chamber and the upper electrode power are used to control the density of the first etching gas and the second etching gas electrolyzed into plasma.

[0105] In one embodiment, both the stacked structure etching step and the storage column etching step are etched in a lower electrode pulse radio frequency mode, and the lower electrode power of the storage column etching step is greater than the lower electrode power of the stacked structure etching step.

[0106] Exemplarily, both the stacked structure etching step and the storage column etching step adopt the lower electrode pulsed radio frequency mode for etching, including: in the stacked structure etching step and the storage column etching step, the radio frequency signal loaded on the lower electrode is a pulsed radio frequency signal. For example, in the stacked structure etching step, the radio frequency period of the pulsed radio frequency signal loaded on the lower electrode is 13MHz, the pulse frequency of the pulsed radio frequency signal is 500Hz, and the duty cycle is 25%; in the storage column etching step, the radio frequency period of the pulsed radio frequency signal loaded on the lower electrode is 2MHz, the pulse frequency of the pulsed radio frequency signal is 500Hz, and the duty cycle is 25%. Among them, since the etching of the storage column etching step is mainly physical etching, it is beneficial for the plasma to obtain a higher bombardment energy by loading a pulsed radio frequency signal with a smaller radio frequency period on the lower electrode.

[0107] Exemplarily, the power of the lower electrode in the stacked structure etching step ranges from 300W to 800W (including the end value), and the power of the lower electrode in the storage column etching step ranges from 700W to 1100W (including the end value), and the power of the lower electrode in the storage column etching step is greater than the power of the lower electrode in the stacked structure etching step. In this way, the bombardment energy of the plasma in the storage column etching step can be greater than the bombardment energy of the plasma in the stacked structure etching step.

[0108] In one embodiment, please refer to Fig.9A and Fig. 9B, the deposition gas in the sacrificial layer deposition step includes carbon-containing and hydrogen-containing gases. The first sacrificial layer 14 and the second sacrificial layer 15 can both be carbon films. Since carbon-hydrogen elements are the source of the carbon film, the carbon film is formed by selecting carbon-containing and hydrogen-containing gases to be deposited on the mask layer 12. The carbon film has good etching resistance and can be less deposited on the sidewall of the mask opening 12a. It can not only protect the mask layer 12 and improve the selectivity of the mask layer 12 during the etching process of the stacked structure 111 and / or the etching process of the storage column 112, but also avoid the mask opening 12a from being sealed by the carbon film, ensuring the smooth etching of the stacked structure 111 and / or the storage column 112 downward along the mask opening 12a.

[0109] Wherein, the deposition gas includes fluoromethane (CH3F) and difluoromethane, the flow rate range of fluoromethane is 20sccm to 200sccm (including the endpoint value), and the flow rate range of difluoromethane is 50sccm to 200sccm (including the endpoint value). Methane (CH4) can also be used as the deposition gas. It should be noted that the type of deposition gas and its flow rate can be selected and adjusted according to actual needs, as long as it is a carbon-containing and hydrogen-containing gas, and the embodiments of the present application do not limit this.

[0110] For further information, please also refer to Fig.9A and Fig. 9B , the process conditions of the sacrificial layer deposition step also include at least one of the following:

[0111] The auxiliary gas includes argon gas, and the flow rate of the argon gas ranges from 100 sccm to 300 sccm (including the end value);

[0112] The pressure range of the process chamber is 20mTorr to 60mTorr (including the end values);

[0113] The upper electrode power ranges from 300W to 700W (including the end value);

[0114] The power of the lower electrode ranges from 0W to 50W (including the end points).

[0115] Among them, argon gas is used to promote the electrolysis of fluoromethane and difluoromethane to generate plasma, and to improve the uniformity of the deposited first sacrificial layer 14 and the second sacrificial layer 15; the lower electrode power is controlled between 0W and 50W, which can optimize the uniformity of deposition to a certain extent. If the lower electrode power is higher than 50W, the first sacrificial layer 14 and the second sacrificial layer 15 cannot be deposited, but will become an etching condition; in addition, by controlling the above process conditions to be within the corresponding numerical range, the effective deposition can be ensured to obtain the required first sacrificial layer 14 and the second sacrificial layer 15.

[0116] The present application also provides a method for preparing a semiconductor device. 7A to 7D , FIG. 8A to FIG. 8G The preparation method includes the following steps S310 to S320.

[0117] Step S310 , providing a stacking structure 11 ; the stacking structure 11 includes a stacking structure 111 and a storage pillar 112 penetrating the stacking structure 111 along a first direction D1 .

[0118] Step S320 , using any of the above methods for forming the isolation trench 13 , to form at least one isolation trench 13 in the stack structure 11 , so as to separate the stack structure 11 into a plurality of storage areas A1 .

[0119] For example, Fig.7D and Fig.8F As shown, the stacked structure 111 includes a plurality of first insulating layers 1111 and a plurality of word line layers 1112 alternately stacked in the opposite direction of the first direction D1. In step S320, the isolation groove 13 penetrates the plurality of first insulating layers 1111 and the plurality of word line layers 1112 along the first direction D1, and the storage column 112 in the isolation groove 13 is removed to separate the stacked structure 11 into a plurality of storage areas A1.

[0120] In the radial direction of the storage column 112, the storage column 112 includes a first electrode 1121 and a storage function layer 1122 surrounding the first electrode 1121. The storage function layer 1122 is located between the first electrode 1121 and a plurality of word line layers 1112. The portion of each word line layer 1112 surrounding the storage function layer 1122 constitutes a second electrode (attached Fig.8F ). In each storage area A1, a storage column 112 constitutes a storage unit, and on each storage column 112, the portion of the first electrode 1121 opposite to the second electrode, the portion of the storage function layer 1122 opposite to the second electrode, and the second electrode constitute a storage point S1, and the number of storage points S1 is the same as the number of word line layers 1112. For example, the embodiment of the present application is described by taking the word line layer 1112 as 8 layers as an example, then each storage column 112 has 8 storage points S1. By dividing the stacked structure 11 into multiple storage areas A1, multiple storage columns 112 can be divided into the same storage area A1 to realize a page storage structure.

[0121] In the above scheme, since the storage pillars 112 in the isolation grooves 13 can be removed during the process of forming the isolation grooves 13, the isolation grooves 13 can completely separate the stacked structure 11 into multiple storage areas A1. Therefore, during the process of forming the isolation grooves 13, the area of ​​the reserved area A0 to be etched can be reduced on the stacked structure 111, or the area A0 to be etched can be not reserved, so as to increase the layout density of the storage pillars 112, thereby facilitating increasing the storage capacity of the storage area A1 and obtaining a three-dimensional memory with high storage density and high storage capacity.

[0122] It should be noted that the semiconductor device of the embodiment of the present application can be a three-dimensional memory, and the specific structure of the semiconductor device can refer to the above embodiment, which will not be repeated here. In addition, since the method for preparing the semiconductor device includes all embodiments of the method for forming the isolation trench 13, it at least has all the beneficial effects brought by the technical solutions of the above embodiments, which will not be repeated here.

[0123] Fig.11 Shown is a schematic structural diagram of a semiconductor process equipment according to an embodiment of the present application.

[0124] like Fig.11 As shown, the semiconductor process equipment 200 may include a process chamber 20, an inlet assembly 20A, an upper electrode assembly 20B and a lower electrode assembly 20C, a gas extraction assembly 20D and a controller ( Fig.11 The controller includes at least one processor and at least one memory, wherein a computer program is stored in the memory, and when the computer program is executed by the processor, the method of any one of the above embodiments is implemented.

[0125] Exemplarily, the controller can be a host computer or a slave computer. The controller can control the valve opening of the air inlet component 20A to introduce the corresponding process gas into the process chamber 20; the controller can also control the opening and closing degree of the valve of the air inlet component 20A to control the flow rate of the process gas. The controller can also control the exhaust component 20D to exhaust the interior of the process chamber 20, such as controlling the valve opening degree or the exhaust pump speed of the exhaust component 20D, to control the pressure inside the process chamber 20, discharge reaction byproducts, etc.

[0126] The upper electrode assembly 20B may include an RF coil 21, an upper RF power source 23 and an upper matcher 25. The controller is also used to control the upper RF power source 23 to provide RF power to the RF coil 21 through the upper matcher 25, so that the RF coil 21 excites the process gas inside the process chamber 20 to generate plasma 100.

[0127] The lower electrode assembly 20C may include a wafer carrier 22, a lower RF power supply 24, and a lower matcher 26. The controller is also used to control the lower RF power supply 24 to provide RF power to the wafer carrier 22 through the lower matcher 26 to provide RF bias. The wafer carrier 22 may be, for example, an electrostatic chuck, a mechanical chuck, or a vacuum adsorption chuck.

[0128] The semiconductor process equipment 200 of the embodiment of the present application may be an inductively coupled plasma (ICP) device or a capacitively coupled plasma (CCP) device. The embodiment of the present application does not limit the type of the semiconductor process equipment 200.

[0129] In addition, in this application, unless otherwise clearly specified and limited, the terms "connected", "connected", "stacked" and the like should be understood in a broad sense, for example, it can be fixedly connected, detachably connected, or integrated; it can be directly connected, or indirectly connected through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0130] The above description is only a preferred embodiment of the present application and is not intended to limit the present application. Any modifications, equivalent substitutions, etc. made within the spirit and principles of the present application shall be included in the protection scope of the present application.

Claims

1. A method for forming an isolation trench, characterized in that: include: forming a mask layer on the stacked structure, so that a mask opening of the mask layer exposes a partial area of ​​the stacked structure; The stacked structure includes a stacked structure and a plurality of storage pillars penetrating the stacked structure along a first direction, wherein the first direction is a thickness direction of the stacked structure; The stacked structure and the storage pillars in the exposed area of ​​the stacked structure are etched alternately and cyclically to form isolation trenches.

2. The method according to claim 1, characterized in that The alternate cyclic etching of the stacked structure and the storage pillar in the exposed area of ​​the stacked structure includes: sequentially and cyclically performing a stacked structure etching step and a storage pillar etching step until the stacked structure and the storage pillar in the exposed area are removed.

3. The method according to claim 2, characterized in that The method further comprises at least one of the following: Before each execution of the stack structure etching step, a sacrificial layer deposition step is executed to deposit a first sacrificial layer on a side of the mask layer away from the stack structure; the first sacrificial layer is consumed during the execution of the stack structure etching step; After each execution of the stacked structure etching step and before the execution of the storage column etching step, a sacrificial layer deposition step is executed to deposit a second sacrificial layer on the side of the mask layer away from the stacked structure; the second sacrificial layer is consumed during the execution of the storage column etching step.

4. The method according to claim 2, characterized in that: Along the radial direction of the storage column, the storage column includes a first electrode and a storage functional layer surrounding the first electrode; during the etching step of the stacked structure, the etching rate of the first electrode is close to the etching rate of the stacked structure, and the etching rate of the storage functional layer is lower than the etching rate of the stacked structure.

5. The method according to claim 4, characterized in that The stacked structure includes a first insulating layer and a word line layer alternately stacked in a direction opposite to the first direction; during the etching step of the stacked structure, there is no etching selectivity for the first insulating layer, the word line layer and the first electrode.

6. The method according to claim 4, characterized in that During the storage pillar etching step, the etching rate of the storage functional layer is greater than the etching rate of the stacked structure.

7. The method according to claim 2, characterized in that The stacked structure includes a first stacked structure and a second stacked structure stacked in a direction opposite to the first direction, the stacked structure also includes a substrate located on a side of the first stacked structure away from the second stacked structure, and a second insulating layer located between the substrate and the first stacked structure and between the first stacked structure and the second stacked structure, the second insulating layer being penetrated by the storage pillar; The method further comprises: during the process of performing the stack structure etching step, the etching stops at the surface of the second insulating layer to expose a partial area of ​​the second insulating layer; During the storage pillar etching step, the exposed area of ​​the second insulating layer is etched simultaneously.

8. The method according to claim 2, characterized in that: The etching gas in the stacked structure etching step includes a fluorine-based gas that does not contain hydrogen.

9. The method according to claim 8, characterized in that The etching gas in the stacked structure etching step also includes chlorine-based gas.

10. The method according to claim 2, characterized in that The etching in the storage column etching step is mainly based on physical bombardment.

11. The method according to claim 10, characterized in that The etching gas of the storage column etching step includes a first etching gas and a second etching gas, the molecular mass of the first etching gas is greater than the molecular mass of the second etching gas; the bombardment force of the physical bombardment on the storage column is adjusted by adjusting the flow ratio between the first etching gas and the second etching gas.

12. The method according to claim 11 is characterized in that A flow ratio between the first etching gas and the second etching gas is equal to or greater than 2.

13. The method according to claim 2, characterized in that The stacked structure etching step and the storage column etching step are both etched in a lower electrode pulse radio frequency mode, and the lower electrode power of the storage column etching step is greater than the lower electrode power of the stacked structure etching step.

14. The method according to claim 3, characterized in that The deposition gas in the sacrificial layer deposition step includes a carbon-containing and hydrogen-containing gas.

15. A method for preparing a semiconductor device, characterized in that: include: Providing a stacking structure; the stacking structure comprises a stacking structure and a storage column penetrating the stacking structure along a first direction; By using the method for forming an isolation trench according to any one of claims 1 to 14, at least one isolation trench is formed in the stack structure to separate the stack structure into a plurality of storage areas.

16. A semiconductor process equipment, characterized in that: include: A process chamber, an air intake assembly, an upper electrode assembly, a lower electrode assembly and a controller, wherein the controller includes at least one processor and at least one memory, wherein the memory stores a computer program, and when the computer program is executed by the processor, the method for forming an isolation groove as described in any one of claims 1 to 14 or the method for preparing a semiconductor device as described in claim 15 is implemented.

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