Power device with low input capacitance and preparation method

Abstract

The invention discloses a power device with low input capacitance and a preparation method, and relates to the field of semiconductor devices.The power device comprises a semiconductor substrate of a first conduction type and an active area arranged in the central area of the semiconductor substrate, and the active area comprises a plurality of groove type cells distributed in parallel; the groove type cell comprises a groove gate unit, the groove gate unit comprises a cell groove, a first electrode body used for reducing the input capacitance of the power device is arranged below the cell groove, and the first electrode body is in contact with the groove bottom of the cell groove. The device can effectively reduce the input capacitance, reduces the switching loss, and enables the power device to be better suitable for high-frequency application.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor devices, and in particular to a power device with low input capacitance and a preparation method thereof. Background Art

[0002] Insulated Gate Bipolar Transistor (IGBT) combines the advantages of thyristor and MOS tube, with low saturation voltage drop, high withstand voltage, easy drive, fast switching speed, etc. It has important applications in many power fields such as switching power supply, variable frequency speed regulation, new energy motor drive, etc. With the development of IGBT technology, IGBT high-frequency applications are increasing, which puts higher requirements on the working loss of IGBT.

[0003] At the same time, in order to reduce the saturation voltage drop of the IGBT, the existing IGBT usually introduces CS (Carrier Stored, carrier storage layer) in the substrate, so that when the IGBT device is turned on, holes accumulate under the CS layer to reduce the saturation voltage drop of the IGBT by enhancing the conductivity modulation effect. However, most of the existing carrier storage layers are formed by high-energy injection. This method is not only difficult to accurately control the distribution of the carrier storage layer, but also requires the support of FAB high-energy injection equipment and production capacity, with low preparation accuracy and high manufacturing cost. Summary of the invention

[0004] In view of the above problems and technical requirements, the inventors have proposed a power device with low input capacitance and a preparation method thereof. The technical solution of the present invention is as follows:

[0005] A power device with low input capacitance comprises a semiconductor substrate having a first conductivity type and an active region arranged in the central region of the semiconductor substrate, wherein the active region comprises a plurality of trench cells arranged in parallel, and the trench cells comprise trench gate units, wherein:

[0006] The trench gate unit includes a cell trench, and a first electrode body for reducing the input capacitance of the power device is arranged below the cell trench, and the first electrode body is in contact with the bottom of the cell trench.

[0007] A further technical solution is that the trench gate unit further includes a trench gate electrode body and a trench gate oxide layer;

[0008] The trench gate electrode body is filled in the cell trench and is insulated and isolated from the inner wall of the cell trench by the trench gate oxide layer;

[0009] A second electrode body is disposed in the trench gate electrode body, the second electrode body penetrates the bottom of the cell trench and contacts the first electrode body, and the second electrode body is insulated and isolated from the trench gate electrode body by an isolation oxide layer;

[0010] The second electrode body is in ohmic contact with a first electrode metal disposed on the semiconductor substrate for forming a first electrode;

[0011] The trench gate electrode body is in ohmic contact with a second electrode metal disposed above the semiconductor substrate for forming a second electrode.

[0012] A further technical solution is that a first conductive type carrier storage area is provided in the semiconductor substrate;

[0013] The first conductive type carrier storage region is located below the cell trench, and the first electrode body is located within the first conductive type carrier storage region;

[0014] The doping concentration of the first conductive type carrier storage region is greater than the doping concentration of the first conductive type semiconductor substrate.

[0015] A further technical solution is that the first conductivity type carrier storage areas in adjacent trench cells are isolated from each other by a first conductivity type semiconductor substrate.

[0016] A further technical solution is that a first conductive type source region and a second conductive type body region are provided on both sides of the cell trench;

[0017] The first conductive type source region is located in the second conductive type body region, and a junction depth of the first conductive type source region is not greater than a junction depth of the second conductive type body region.

[0018] A further technical solution is that a second conductive type source region is further provided in the second conductive type body region;

[0019] The junction depth of the second conductive type source region is not greater than the junction depth of the second conductive type body region, and the second conductive type source region is in contact with the first conductive type source region;

[0020] The second conductive type source region and the first conductive type source region are both in ohmic contact with a first electrode metal for forming a first electrode above the semiconductor substrate.

[0021] A method for preparing a power device with low input capacitance, used for preparing the above-mentioned power device, the method for preparing the power device comprising:

[0022] A substrate of a first conductive type is provided, and a front cell process is performed on the substrate to form a semiconductor substrate based on the substrate after the front cell process, and a plurality of trench cells distributed in parallel are prepared in an active area in a central area of ​​the semiconductor substrate, wherein:

[0023] The trench-type cell includes a trench gate unit, and the trench gate unit includes a cell trench. A first electrode body for reducing the input capacitance of the power device is arranged below the cell trench, and the first electrode body is in contact with the bottom of the cell trench.

[0024] A further technical solution is that the front cell process includes preparing a first conductive type carrier storage area;

[0025] When preparing the first conductive type carrier storage area, the method includes generating a first conductive type first epitaxial layer on the substrate, selectively etching the first conductive type first epitaxial layer using a first photolithography plate to prepare a first conductive type preliminary carrier storage area, wherein the doping concentration of the first conductive type first epitaxial layer is greater than the doping concentration of the substrate;

[0026] Generating a first conductivity type second epitaxial layer on the substrate, wherein the doping concentration of the first conductivity type second epitaxial layer is the same as the doping concentration of the substrate, and the thickness of the first conductivity type second epitaxial layer is the same as the thickness of the first conductivity type first epitaxial layer;

[0027] The surface of the substrate is ground flat and heated at high temperature, and the first conductive type preliminary carrier storage region diffuses at high temperature to form a first conductive type carrier storage region.

[0028] A further technical solution is that, when preparing the first electrode body, a first photolithography plate is used to etch a first filling groove in the first conductive type carrier storage region, and polysilicon is filled in the first filling groove to form the first electrode body;

[0029] A first conductive type third epitaxial layer is generated on the substrate after the first electrode body is prepared, and the doping concentration of the first conductive type third epitaxial layer is the same as the doping concentration of the first conductive type substrate to form a semiconductor substrate.

[0030] A further technical solution is that the front cell process further includes etching a cell trench in the third epitaxial layer of the first conductivity type using a first photolithography plate, preparing a trench gate oxide layer and a trench gate electrode body in the cell trench, and the trench gate electrode body is insulated and isolated from the inner wall of the cell trench by the trench gate oxide layer;

[0031] Etching a second filling groove in the trench gate electrode body, wherein the bottom of the second filling groove contacts the first electrode body and the groove width of the second filling groove is smaller than the groove width of the cell groove;

[0032] An oxide layer is formed on the inner wall of the second filling groove, and the oxide layer at the bottom of the second filling groove is removed by etching to prepare an isolation oxide layer;

[0033] Filling polysilicon in the second filling groove where the isolation oxide layer is prepared to form a second electrode body, wherein the second electrode body is in contact with the first electrode body; the second electrode body is insulated and isolated from the trench gate electrode body by the isolation oxide layer;

[0034] The second electrode body is in ohmic contact with a first electrode metal disposed on a semiconductor substrate for forming a first electrode; the trench gate electrode body is in ohmic contact with a second electrode metal disposed on a semiconductor substrate for forming a second electrode.

[0035] In the above-mentioned "first conductivity type" and "second conductivity type", for N-type power devices, the first conductivity type refers to N-type, and the second conductivity type is P-type; for P-type power devices, the types referred to by the first conductivity type and the second conductivity type are opposite to those of N-type devices.

[0036] The beneficial technical effects of the present invention are:

[0037] The present invention provides a power device with low input capacitance, which reduces the input capacitance of the power device by preparing a first electrode body under a cell groove, reduces the switching loss of the power device, and thus improves the device performance, making the power device better suitable for high-frequency applications.

[0038] In addition, the present invention also provides a method for preparing a power device with low input capacitance, which forms a carrier storage region by growing an epitaxial layer. Compared with the traditional method of forming a carrier storage region, the preparation accuracy of the carrier storage region can be improved, and the use of high-energy injection process is avoided, thereby reducing manufacturing costs. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] Figure 1 It is a cross-sectional schematic diagram of an embodiment of a power device with low input capacitance provided by the present invention.

[0040] Figure 2-Figure 14 1 is a cross-sectional view of the process steps of an embodiment of a method for preparing a power device with low input capacitance provided by the present invention, wherein:

[0041] Figure 2 It is a cross-sectional view of an embodiment of the present invention after the N-type first epitaxial layer is prepared.

[0042] Figure 3 It is a cross-sectional view of an embodiment of the present invention after preparing an N-type preliminary carrier storage area.

[0043] Figure 4 It is a cross-sectional view of an embodiment of the present invention in which an N-type second epitaxial layer is prepared.

[0044] Figure 5 It is a cross-sectional view of an embodiment of the present invention after the first CMP process is performed.

[0045] Figure 6 It is a cross-sectional view of an embodiment of the present invention in which an N-type carrier storage area is prepared.

[0046] Figure 7 It is a cross-sectional view of an embodiment of the present invention after the first filling groove is prepared.

[0047] Figure 8 It is a cross-sectional view of an embodiment of the present invention after the first electrode body is prepared.

[0048] Fig. 9 It is a cross-sectional view of an embodiment of the present invention after preparing the N-type third epitaxial layer.

[0049] Fig.10 It is a cross-sectional view of an embodiment of the present invention after the trench gate oxide layer is prepared.

[0050] Fig.11 It is a cross-sectional view of an embodiment of the present invention after the trench gate electrode body is prepared.

[0051] Fig.12 It is a cross-sectional view of an embodiment of the present invention after the second electrode body is prepared.

[0052] Fig.13 It is a cross-sectional view of an embodiment of the present invention after preparing the front metal layer.

[0053] Fig.14 It is a cross-sectional view of an embodiment of the present invention in which a back metal layer is prepared.

[0054] Explanation of the figure marks: 1-N-type substrate, 2-N-type second epitaxial layer, 3-N-type third epitaxial layer, 4-N-type carrier storage area, 5-first filling groove, 6-first electrode body, 7-cell trench, 8-trench gate oxide layer, 9-trench gate electrode body, 10-second filling groove, 11-isolation oxide layer, 12-second electrode body, 13-P-type body region, 14-N-type source region, 15-P-type source region, 16-insulating dielectric layer, 17-first electrode metal, 18-N-type buffer layer, 19-P-type collector region, 20-back metal layer, 21-N-type first epitaxial layer, 22-N-type preliminary carrier storage area, 23-first contact hole, 24-second contact hole. DETAILED DESCRIPTION

[0055] The specific implementation of the present invention will be further described below in conjunction with the accompanying drawings.

[0056] The present invention provides a power device with low input capacitance. Taking the first conductivity type as N-type as an example, in one embodiment of the present invention, the power device includes an N-type semiconductor substrate and an active area arranged in the central area of ​​the semiconductor substrate, the active area includes a plurality of trench cells distributed in parallel, and the trench cells include trench gate units;

[0057] The trench gate unit includes a cell trench 7 , and a first electrode body 6 for reducing the input capacitance of the power device is disposed below the cell trench 7 . The first electrode body 6 is in contact with the bottom of the cell trench 7 .

[0058] Specifically, the semiconductor substrate generally has a front side and a back side corresponding to the front side. For a power device, it generally includes an active area located on the semiconductor substrate and a terminal protection area surrounding the active area. The specific functions and distribution states of the active area and the terminal protection area can be consistent with the prior art. Generally, the active area includes a plurality of cells distributed in parallel. In one embodiment of the present invention, the cell adopts a groove-type cell, that is, the active area includes a plurality of groove-type cells.

[0059] The first electrode body 6 can form a capacitor in series with the original input capacitor with the trench gate unit, thereby reducing the input capacitance of the device, reducing the switching loss of the power device, and then improving the device performance, making the power device better suitable for high-frequency applications. At the same time, the first electrode body 6 can also improve the withstand voltage of the active area. The specific form of the capacitor formed by the first electrode body 6 and the trench gate unit in series with the original input capacitor can be referred to the following description. In this embodiment, the material of the first electrode body 6 can be polysilicon. During the specific implementation, the material of the first electrode body 6 can be selected according to the actual situation.

[0060] Furthermore, the trench gate unit further includes a trench gate electrode body 9 and a trench gate oxide layer 8;

[0061] The trench gate electrode body 9 is filled in the cell trench 7 and is insulated and isolated from the inner wall of the cell trench 7 by the trench gate oxide layer 8 .

[0062] Specifically, the input capacitor includes the junction capacitance of the first electrode and the trench gate electrode body 9. The first electrode body 6, the trench gate oxide layer 8 and the trench gate electrode body 9 form a capacitor connected in series with the junction capacitance of the first electrode trench gate electrode body 9 in the original input capacitor, that is, a capacitor connected in series with the original input capacitor is formed, thereby reducing the input capacitance of the power device.

[0063] Preferably, a second electrode body 12 is disposed in the trench gate electrode body 9, the second electrode body 12 penetrates the bottom of the cell trench 7 and contacts the first electrode body 6, and the second electrode body 12 is insulated and isolated from the trench gate electrode body 9 by an isolation oxide layer 11;

[0064] The second electrode body 12 is in ohmic contact with a first electrode metal 17 disposed on the semiconductor substrate for forming a first electrode;

[0065] The trench gate electrode body 9 is in ohmic contact with a second electrode metal disposed on the semiconductor substrate for forming a second electrode.

[0066] Generally, a front metal layer is provided on the front of the semiconductor substrate, and the front metal layer includes a first electrode metal 17 for forming a first electrode, and a second electrode metal for forming a second electrode. A back metal layer is also provided on the back of the semiconductor substrate, and the back metal layer 20 includes a third electrode metal for forming a third electrode. The power device described in the present application can form a MOSFET type device or an IGBT type device. For a MOSFET type device, the first electrode is a source electrode, the second electrode is a gate electrode, and the third electrode is a drain electrode. For an IGBT type device, the first electrode is an emitter electrode, the second electrode is a gate electrode, and the third electrode is a collector electrode.

[0067] In order to further reduce the input capacitance of the power device, a second electrode body 12 is provided in the trench gate electrode body 9. The materials of the trench gate electrode body 9 and the second electrode body 12 may also be polysilicon. The second electrode body 12 penetrates the bottom of the cell trench 7 and is connected to the first electrode body 6 as a whole. The second electrode body 12 is insulated and isolated from the trench gate electrode body 9 by an isolation oxide layer 11. Figure 1 As shown, in this embodiment, the isolation oxide layer 11 separates the polysilicon filled in the cell trench 7 into a first side trench gate polysilicon, a second side trench gate polysilicon and a second electrode body 12 located between the first side trench gate polysilicon and the second side trench gate polysilicon. The first side trench gate polysilicon and the second side trench gate polysilicon are both connected to the second electrode potential, and the first electrode body 6 and the second electrode body 12 are both connected to the first electrode potential. At this time, the specific principle of reducing the input capacitance of the power device is: the first electrode body 6 and the second electrode body 12 maintain the same potential, the second electrode body 12, the isolation oxide layer 11 and the trench gate electrode body 9 form a capacitor connected in series with the original input capacitance, thereby reducing the input capacitance of the power device.

[0068] Furthermore, an N-type carrier storage area 4 is provided in the semiconductor substrate;

[0069] The N-type carrier storage region 4 is located below the cell trench 7, and the first electrode body 6 is located in the N-type carrier storage region 4;

[0070] The doping concentration of the N-type carrier storage region 4 is greater than the doping concentration of the N-type semiconductor substrate.

[0071] Specifically, in order to make the preparation process of the first electrode body 6 compatible with that of the N-type carrier storage area 4 and simplify the preparation process, the first electrode body 6 is disposed in the N-type carrier storage area 4. In this embodiment, the semiconductor substrate includes an N-type substrate 1, an N-type second epitaxial layer 2 located on the N-type substrate 1, and an N-type third epitaxial layer 3 located on the N-type second epitaxial layer 2. The doping concentrations of the N-type substrate 1, the N-type second epitaxial layer 2, and the N-type third epitaxial layer 3 are the same and serve as the doping concentration of the N-type semiconductor substrate.

[0072] Furthermore, when the second electrode body 12 is provided in the trench gate electrode body 9, since the first electrode body 6 is electrically connected to the first electrode metal 17 through the second electrode body 12, the first electrode body 6 located in the N-type carrier storage area 4 is at a low potential when the device is turned off, which can effectively allow holes to recombine with more electrons in the N-type carrier storage area 4, thereby reducing the turn-off time and reducing the tail current.

[0073] Preferably, the N-type carrier storage areas 4 in adjacent trench cells are isolated from each other by an N-type semiconductor substrate. The area in the device where the N-type carrier storage area 4 is not provided can serve as a hole channel when the device is turned off to accelerate the hole extraction when it is turned off, further optimizing the switching speed of the power device.

[0074] Furthermore, both sides of the cell trench 7 are provided with an N-type source region 14 and a P-type body region 13;

[0075] The N-type source region 14 is located in the P-type body region 13 , and a junction depth of the N-type source region 14 is not greater than a junction depth of the P-type body region 13 .

[0076] Specifically, the junction depth of the N-type source region 14 is less than or equal to the junction depth of the P-type body region 13, and a P-type source region 15 is further provided in the P-type body region 13. The junction depth of the P-type source region 15 is less than or equal to the junction depth of the P-type body region 13, and the P-type source region 15 is in contact with the N-type source region 14. The P-type source region 15 is used to improve the avalanche resistance of the power device. The P-type source region 15 and the N-type source region 14 both extend vertically from the front side to the back side of the semiconductor substrate, and the P-type source region 15 and the N-type source region 14 both make ohmic contact with the first electrode metal 17 used to form the first electrode above the semiconductor substrate to form the first electrode of the power device.

[0077] For the above-mentioned power device with low input capacitance, the present invention provides a method for preparing the power device with low input capacitance, and the method for preparing the power device with low input capacitance comprises:

[0078] An N-type substrate 1 is provided, and a front cell process is performed on the substrate 1 to form a semiconductor substrate based on the substrate 1 after the front cell process, and a plurality of trench cells distributed in parallel are prepared in an active area of ​​the semiconductor substrate, wherein:

[0079] The trench-type cell includes a trench gate unit, and the trench gate unit includes a cell trench 7 . A first electrode body 6 for reducing the input capacitance of the power device is arranged below the cell trench 7 , and the first electrode body 6 is in contact with the bottom of the cell trench 7 .

[0080] Specifically, the front cell process includes preparing an N-type carrier storage area 4. When preparing the N-type carrier storage area 4, it includes generating an N-type first epitaxial layer 21 above the N-type substrate 1, and selectively etching the N-type first epitaxial layer 21 using a first photomask to prepare an N-type preliminary carrier storage area 22, wherein the doping concentration of the N-type first epitaxial layer 21 is greater than the doping concentration of the substrate 1.

[0081] An N-type second epitaxial layer 2 is generated above the substrate 1, and the doping concentration of the N-type second epitaxial layer 2 is the same as the doping concentration of the substrate 1, and the thickness of the N-type second epitaxial layer 2 is the same as the thickness of the N-type first epitaxial layer 21. The surface of the substrate 1 is ground flat, and the remaining N-type second epitaxial layer 2 after grinding is flush with the N-type preliminary carrier storage area 22 to form the surface of the substrate 1. The substrate 1 is heated at high temperature, and the N-type preliminary carrier storage area 11 diffuses to the surroundings at high temperature to form an N-type carrier storage area 4. The present application forms the N-type carrier storage area 4 by growing an epitaxial layer. Compared with the traditional ion implantation preparation method, it can improve the preparation accuracy of the carrier storage area, avoid the use of high-energy implantation process, and reduce the requirements for high-energy implantation equipment and production capacity. At the same time, when forming the carrier storage area by ion implantation, it is necessary to provide an additional photomask to prevent the carrier storage area from being injected into the terminal area. The preparation method of growing an epitaxial layer can save this photomask and further reduce the preparation cost.

[0082] Furthermore, when preparing the first electrode body 6, a first photolithography plate is used to etch the N-type carrier storage region 4 to obtain a first filling groove 5, and polysilicon is filled in the first filling groove 5 to form the first electrode body 6;

[0083] An N-type third epitaxial layer 3 is generated on the substrate 1 after the first electrode body 6 is prepared. The doping concentration of the N-type third epitaxial layer 3 is the same as the doping concentration of the substrate 1 to form a semiconductor substrate.

[0084] The front cell process also includes using a first photolithography plate to etch a cell trench 7 in the N-type third epitaxial layer 3, preparing a trench gate oxide layer 8 and a trench gate electrode body 9 in the cell trench 7, and the trench gate electrode body 9 is insulated and isolated from the inner wall of the cell trench 7 by the trench gate oxide layer 8.

[0085] Specifically, in this embodiment, the first filling groove 5 is a trapezoidal groove that is wide at the top and narrow at the bottom, that is, the groove width of the first filling groove 5 is greater than the groove bottom width. In specific implementation, according to different etching processes, the first filling groove 5 can also be a U-shaped groove or a rectangular groove. The materials of the first electrode body 6 and the trench gate electrode body 9 are both made of polysilicon. The first photolithography plate is the photolithography plate used in the existing process to etch and form the cell groove 7. The N-type carrier storage area 4 and the first filling groove 5 are both prepared using the first photolithography plate, so that the preparation process of the carrier storage area and the first filling groove 5 is compatible with the existing process, so as to realize the reuse of the first photolithography plate, save the number of photolithography plates required as much as possible, and reduce the preparation cost.

[0086] Furthermore, when the second electrode body 12 is disposed in the trench gate electrode body 9, the front cell process further includes etching a second filling groove 11 in the trench gate electrode body 9, the bottom of the second filling groove 11 is in contact with the first electrode body 6, and the groove width of the second filling groove 10 is smaller than the groove width of the cell groove 7;

[0087] An oxide layer is formed on the inner wall of the second filling groove 10, and the oxide layer at the bottom of the second filling groove 10 is removed by etching to prepare an isolation oxide layer 11;

[0088] The second filling groove 10 where the isolation oxide layer 11 is prepared is filled with polysilicon to form a second electrode body 12, wherein the second electrode body 12 is in contact with the first electrode body 6; the second electrode body 12 is insulated and isolated from the trench gate electrode body 6 by the isolation oxide layer 11;

[0089] The second electrode body 12 is in ohmic contact with a first electrode metal 17 disposed on the semiconductor substrate for forming a first electrode; the trench gate electrode body 9 is in ohmic contact with a second electrode metal disposed on the semiconductor substrate for forming a second electrode.

[0090] In this embodiment, the second filling groove 10 is located in the middle of the cell trench 7, the groove width of the second filling groove 10 is about one third of the groove width of the cell trench 7, the groove depth of the second filling groove 10 is greater than the groove depth of the cell trench 7, and it extends vertically from the front side of the semiconductor substrate, that is, the front side of the N-type third epitaxial layer 3, to the back side of the semiconductor substrate, passes through the bottom of the cell trench 7 and contacts the first electrode body 6. The material of the second electrode body 12 can be polysilicon, and the material of the isolation oxide layer 11 can be silicon dioxide.

[0091] Furthermore, the method for preparing the power device with low input capacitance also includes performing a back side process on the back side of the semiconductor substrate. Depending on the back side process, a MOSFET type device or an IGBT type device can be formed. Generally, the front side cell process is performed first and then the back side cell process. Figure 2-Figure 14 Taking IGBT type devices as an example, an embodiment of the process steps for preparing the above-mentioned power device with low input capacitance is shown. Figure 2-Figure 14 The specific process steps are described in detail. It should be noted that the second electrode body 12 can be selectively provided in the trench gate electrode body 9. Figure 2-Figure 14 Three unit cell structures are shown in total, in which a second electrode body 12 is disposed in a trench gate electrode body 9 in one unit cell structure. In specific implementation, the disposition of the second electrode body 12 in the trench gate electrode body 9 can be selected according to actual needs.

[0092] like Figure 2 As shown, an N-type substrate 1 is provided. The resistivity of the N-type substrate 1 is generally about 90 ohm·cm, and there is no oxide layer protection on the front and back sides of the substrate. An N-type epitaxial layer is grown on the front side of the N-type substrate 1 to form an N-type first epitaxial layer 21. The thickness of the N-type first epitaxial layer 21 is 3 μm. The doping concentration of the N-type first epitaxial layer 21 is at the order of magnitude of E13, which is greater than the doping concentration of the N-type substrate 1.

[0093] like Figure 3 As shown, a negative resist layer is coated on the N-type first epitaxial layer 21, a first photoresist is placed on the negative resist layer and the negative resist layer is exposed and developed to form a first mask, the N-type first epitaxial layer 21 is etched using the first mask formed by the negative resist layer and the first mask is removed to prepare an N-type preliminary carrier storage area 22.

[0094] like Figure 4 As shown, an N-type epitaxial layer is grown again on the front side of the N-type substrate 1 to form an N-type second epitaxial layer 2. The thickness of the N-type second epitaxial layer 2 is 3 μm, and the resistivity of the N-type second epitaxial layer 2 is the same as that of the N-type substrate 1, that is, the doping concentration of the N-type second epitaxial layer 2 is the same as that of the N-type substrate 1. Since there is an N-type reserve carrier storage area 22 above the N-type substrate 1, when the N-type epitaxial layer is grown to form the N-type second epitaxial layer 2, the N-type second epitaxial layer 2 grown in the area where the N-type reserve carrier storage area 22 is located will be formed above the N-type reserve carrier storage area 22, as shown in FIG. Figure 5 As shown, the substrate surface is polished flat by a CMP process to remove the N-type second epitaxial layer 2 above the N-type preliminary carrier storage region 22 .

[0095] like Figure 6As shown, the substrate is heated at high temperature, and the N-type preliminary carrier storage area 22 diffuses to the surroundings at high temperature to form the N-type carrier storage area 4. The high-concentration N-type preliminary carrier storage area 22 is diluted by the high-temperature process, and the doping concentration of the finally formed N-type carrier storage area 4 is about the order of magnitude of E12, which is close to the energy level formed by traditional high-energy injection.

[0096] like Figure 7 As shown, a positive resist layer is coated on the substrate 1, a first photoresist is placed on the positive resist layer and the positive resist layer is exposed and developed to form a second mask, the second mask is used to etch a first filling groove 5 in the N-type carrier storage area 4, and the second mask is removed.

[0097] like Figure 8 As shown, polysilicon is deposited on the substrate 1, and the polysilicon fills the first filling groove 5 to form a first electrode body 6. The polysilicon on the surface of the N-type second epitaxial layer 2 is removed by a CMP process.

[0098] like Fig. 9 As shown, an N-type epitaxial layer is grown again on the N-type second epitaxial layer 2 to prepare an N-type third epitaxial layer 3, and a semiconductor substrate is formed at this time. The thickness of the N-type third epitaxial layer 3 is 5 μm, and the resistivity of the N-type third epitaxial layer 3 is the same as that of the N-type second epitaxial layer 2, that is, the doping concentration of the N-type third epitaxial layer 3 is the same as that of the N-type second epitaxial layer 2.

[0099] like Fig.10 As shown, a hard mask layer is deposited and etched using a first photolithography board to obtain a cell groove 7, the bottom of the cell groove 7 is in contact with the surface of the first electrode body 6, oxide is deposited on the inner wall of the cell groove 7 to form a trench gate oxide layer 8 and the hard mask layer is removed, and the thickness of the trench gate oxide layer is about 1000 angstroms.

[0100] like Fig.11 As shown, polysilicon is deposited on the front side of the semiconductor substrate to fill the cell trench 7 to prepare the trench gate electrode body 9 , and the semiconductor substrate is photoetched to remove the polysilicon outside the cell trench 7 .

[0101] like Fig.12 As shown, when a second electrode body is provided in the trench gate electrode body 9, a second filling groove 10 is etched in the trench gate electrode body 9, the groove depth of the second filling groove 10 is greater than the groove depth of the cell trench 7, the groove bottom of the second filling groove 10 is in contact with the first electrode body 6, an oxide layer is grown in the second filling groove 10, and the oxide layer at the bottom of the second filling groove 10 is removed by isotropic dry etching to form an isolation oxide layer 11, and polycrystalline silicon is filled in the second filling groove 10 where the isolation oxide layer 11 is prepared to form a second electrode body 12, and the second electrode body 12 is in contact with the first electrode body 6.

[0102] like Fig.13 As shown, P-type doping ions are implanted into the N-type third epitaxial layer 3 to form a P-type body region 13, and the implantation dose of the P-type doping ions is of the order of E13. N-type doping ions are implanted into the P-type body region 13 to form an N-type source region 14, and the implantation dose of the N-type doping ions is of the order of E15. An insulating dielectric is deposited to form an insulating dielectric layer 16, and a first contact hole 23 and a second contact hole 24 are etched on the insulating dielectric layer 16, wherein the first contact hole 23 contacts the N-type source region 14, and the second contact hole 24 is located above the second electrode body 12. P-type doping ions are implanted into the P-type body region 13 using the first contact hole 23 to form a P-type source region 15. The implantation dose of the P-type doping ions is of the order of E14 or E15, and the implantation energy of the P-type doping ions is 50KeV-80KeV. Metal is deposited on the front side of the semiconductor substrate to form a front metal layer. The metal may be an aluminum-copper alloy. The thickness of the front metal layer may be 4-5 μm. The front metal layer includes a first electrode metal 17 and a second electrode metal. The first electrode metal 17 is in ohmic contact with the second electrode body 12, the P-type source region 15 and the N-type source region 14. The second electrode metal is in ohmic contact with the trench gate electrode body 9.

[0103] like Fig.14 As shown, a back side process is performed on the back side of the semiconductor substrate, the back side of the semiconductor substrate is thinned and N-type doping ions are injected to form an N-type buffer layer 18, and P-type doping ions are injected into the N-type buffer layer 18 to form a P-type collector region 19 below the N-type buffer layer 18, and a back side metal layer 20 is deposited on the back side of the semiconductor substrate, the back side metal layer 20 includes a third electrode metal for forming a third electrode, and the third electrode metal is in ohmic contact with the N-type substrate 1.

[0104] It should be noted that the words "front", "rear", "left", "right", "upper" and "lower" used in the above description refer to directions in the drawings of the present application specification, and the words "front" and "back", "inner" and "outer" refer to directions toward or away from a specific component, respectively. In addition, the terms "first" and "second" are used for descriptive purposes only and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features.

[0105] The above is only a preferred embodiment of the present invention, and the present invention is not limited to the above embodiments. It is understood that other improvements and changes directly derived or associated by those skilled in the art without departing from the spirit and concept of the present invention should be considered to be included in the protection scope of the present invention.

Claims

1. A power device with low input capacitance, characterized in that: It includes a semiconductor substrate with a first conductivity type and an active area arranged in the central area of ​​the semiconductor substrate, wherein the active area includes a plurality of trench cells distributed in parallel, and the trench cells include trench gate units, wherein: The trench gate unit includes a cell trench, and a first electrode body for reducing the input capacitance of the power device is arranged below the cell trench, and the first electrode body is in contact with the bottom of the cell trench.

2. The power device with low input capacitance according to claim 1, characterized in that: The trench gate unit also includes a trench gate electrode body and a trench gate oxide layer; The trench gate electrode body is filled in the cell trench and is insulated and isolated from the inner wall of the cell trench by the trench gate oxide layer; A second electrode body is disposed in the trench gate electrode body, the second electrode body penetrates the bottom of the cell trench and contacts the first electrode body, and the second electrode body is insulated and isolated from the trench gate electrode body by an isolation oxide layer; The second electrode body is in ohmic contact with a first electrode metal disposed on the semiconductor substrate for forming a first electrode; The trench gate electrode body is in ohmic contact with a second electrode metal disposed above the semiconductor substrate for forming a second electrode.

3. The power device with low input capacitance according to any one of claims 1 to 2, characterized in that: A first conductive type carrier storage area is provided in the semiconductor substrate; The first conductive type carrier storage region is located below the cell trench, and the first electrode body is located within the first conductive type carrier storage region; The doping concentration of the first conductive type carrier storage region is greater than the doping concentration of the first conductive type semiconductor substrate.

4. The power device with low input capacitance according to claim 3, characterized in that: The first conductivity type carrier storage regions in adjacent trench cells are isolated from each other by the first conductivity type semiconductor substrate.

5. The power device with low input capacitance according to claim 3, characterized in that: Both sides of the cell trench are provided with a first conductivity type source region and a second conductivity type body region; The first conductive type source region is located in the second conductive type body region, and a junction depth of the first conductive type source region is not greater than a junction depth of the second conductive type body region.

6. The power device with low input capacitance according to claim 5, characterized in that: A second conductivity type source region is also provided in the second conductivity type body region; The junction depth of the second conductive type source region is not greater than the junction depth of the second conductive type body region, and the second conductive type source region is in contact with the first conductive type source region; The second conductive type source region and the first conductive type source region are both in ohmic contact with a first electrode metal for forming a first electrode above the semiconductor substrate.

7. A method for preparing a power device with low input capacitance, characterized in that: Used to prepare a power device according to any one of claims 1 to 6, the method for preparing the power device comprising: A substrate of a first conductive type is provided, and a front cell process is performed on the substrate to form a semiconductor substrate based on the substrate after the front cell process, and a plurality of trench cells distributed in parallel are prepared in an active area of ​​the semiconductor substrate, wherein: The trench-type cell includes a trench gate unit, and the trench gate unit includes a cell trench. A first electrode body for reducing the input capacitance of the power device is arranged below the cell trench, and the first electrode body is in contact with the bottom of the cell trench.

8. The method for preparing a power device with low input capacitance according to claim 7, characterized in that: The front cell process includes preparing a first conductivity type carrier storage region; When preparing the first conductive type carrier storage area, the method includes generating a first conductive type first epitaxial layer on the substrate, selectively etching the first conductive type first epitaxial layer using a first photolithography plate to prepare a first conductive type preliminary carrier storage area, wherein the doping concentration of the first conductive type first epitaxial layer is greater than the doping concentration of the substrate; Generating a first conductivity type second epitaxial layer on the substrate, wherein the doping concentration of the first conductivity type second epitaxial layer is the same as the doping concentration of the substrate, and the thickness of the first conductivity type second epitaxial layer is the same as the thickness of the first conductivity type first epitaxial layer; The surface of the substrate is ground flat and heated at high temperature, and the first conductive type preliminary carrier storage region diffuses at high temperature to form a first conductive type carrier storage region.

9. The method for preparing a power device with low input capacitance according to claim 8, characterized in that: When preparing the first electrode body, a first photolithography plate is used to etch a first filling groove in the first conductive type carrier storage region, and polysilicon is filled in the first filling groove to form the first electrode body; A first conductive type third epitaxial layer is generated on the substrate after the first electrode body is prepared, and the doping concentration of the first conductive type third epitaxial layer is the same as the doping concentration of the first conductive type substrate to form a semiconductor substrate.

10. The method for preparing a power device with low input capacitance according to claim 9, characterized in that: The front cell process also includes etching a cell trench in the first conductivity type third epitaxial layer using a first photolithography plate, preparing a trench gate oxide layer and a trench gate electrode body in the cell trench, wherein the trench gate electrode body is insulated and isolated from the inner wall of the cell trench by the trench gate oxide layer; Etching a second filling groove in the trench gate electrode body, wherein the bottom of the second filling groove contacts the first electrode body and the groove width of the second filling groove is smaller than the groove width of the cell groove; An oxide layer is formed on the inner wall of the second filling groove, and the oxide layer at the bottom of the second filling groove is removed by etching to prepare an isolation oxide layer; Filling polysilicon in the second filling groove where the isolation oxide layer is prepared to form a second electrode body, wherein the second electrode body is in contact with the first electrode body; the second electrode body is insulated and isolated from the trench gate electrode body by the isolation oxide layer; The second electrode body is in ohmic contact with a first electrode metal disposed on a semiconductor substrate for forming a first electrode; the trench gate electrode body is in ohmic contact with a second electrode metal disposed on a semiconductor substrate for forming a second electrode.

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