Semiconductor device and IGBT chip

Abstract

The utility model provides a semiconductor device and an IGBT chip. According to the semiconductor device, the temperature sensor is embedded between the adjacent power devices, so that the temperature of the device can be accurately monitored in real time in the device, the working temperature of the device can be timely regulated and controlled, and the first electrode layer can simultaneously cover the cellular area and a part of the temperature sensing area; therefore, the source region of the power device and the first end of the temperature sensor are short-circuited to form Kelvin contact, so that external stray inductance can be shielded, the switching speed of the device is improved, and the switching loss is reduced.

Description

Technical Field

[0001] The utility model relates to the technical field of semiconductors, in particular to a semiconductor device and an IGBT chip. Background Art

[0002] Power devices are widely used in various fields due to their high voltage resistance, high efficiency and low loss. For example, the insulated gate bipolar field effect transistor IGBT combines the advantages of high switching frequency of MOS devices and large current handling capacity of BJT devices, and is widely used in intelligent power modules.

[0003] Power devices generate a lot of heat during use. If the heat is too high, it will affect the performance of the device and shorten its service life, or even directly damage the device. Therefore, it is necessary to monitor the device temperature in the module in real time and accurately to ensure the normal operation of the module. At present, a temperature sensor is installed in the power module to monitor the temperature. However, the temperature sensor is usually installed in the corner of the power module, which is far away from the power device and it is difficult to accurately sense the temperature of the device.

[0004] In addition, the performance of power devices is easily affected by external stray inductance. For example, the speed of the device is easily reduced under the influence of external stray inductance, which in turn leads to increased switching losses of the device. Utility Model Content

[0005] One of the purposes of the utility model is to provide a semiconductor device to improve the temperature monitoring accuracy inside the semiconductor device, and also to optimize the switching speed of the device and reduce the switching loss.

[0006] To this end, the utility model provides a semiconductor device, comprising: a substrate, wherein the substrate has a plurality of cell regions and at least one temperature sensing region, wherein the temperature sensing region is located between adjacent cell regions; a power device, formed in the cell region; a temperature sensor, formed in the temperature sensing region; a first electrode layer, covering the cell region to electrically connect to a source region of the power device, and the first electrode layer also covers a portion of the temperature sensing region to electrically connect to a first end of the temperature sensor; and a second electrode layer, covering a portion of the temperature sensing region to electrically connect to a second end of the temperature sensor.

[0007] Optionally, the temperature sensor includes a first branch having at least one PN junction structure connected in series, the first electrode layer is electrically connected to a cathode end of the first branch, and the second electrode layer is electrically connected to an anode end of the first branch.

[0008] Optionally, the temperature sensor further includes a second branch connected to a PN junction structure, the first electrode layer is electrically connected to an anode end of the second branch, and the second electrode layer is electrically connected to a cathode end of the second branch.

[0009] Optionally, the temperature sensor includes multiple N-type doped regions and multiple P-type doped regions formed on a substrate, so that multiple PN junction structures are formed by the multiple N-type doped regions and the multiple P-type doped regions, wherein different PN junction structures are spaced apart from each other, and the N-type doped regions and the P-type doped regions in the same PN junction structure are in contact with each other.

[0010] Optionally, the temperature sensing region extends along a first direction, and the N-type doping region and the P-type doping region both extend along the first direction; wherein the N-type doping region and the P-type doping region in the same PN junction structure are arranged along a second direction and contact each other.

[0011] Optionally, the plurality of PN junction structures in the temperature sensing region are arranged into two columns aligned along the second direction, and between adjacent PN junction structures, the N-type doping region of one PN junction structure is close to the P-type doping region of another PN junction structure. At least two PN junction structures arranged at the head and tail positions in the first column and all PN junction structures in the second column are connected in series to form the first branch; and at least one PN junction structure arranged between the head and tail positions in the first column forms the second branch.

[0012] Optionally, an isolation structure is formed in the temperature sensing area, and the temperature sensor is formed on the isolation structure.

[0013] Optionally, an inversion doping region is further formed in the substrate of the temperature sensing region, and the conductivity type of the inversion doping region is opposite to the conductivity type of the substrate.

[0014] Optionally, the cell region extends along a first direction, a plurality of cell regions are arranged in sequence along a second direction, and the temperature sensing region is arranged between adjacent cell regions and extends along the first direction.

[0015] The utility model also provides an IGBT chip, comprising the semiconductor device as described above, wherein the power device in the semiconductor device is an IGBT device, and the temperature sensor is arranged between adjacent IGBT devices.

[0016] In the semiconductor device provided by the utility model, the temperature sensor is embedded between adjacent power devices, so that the device temperature can be monitored in real time and accurately inside the device, which is conducive to timely regulating the operating temperature of the device and ensuring the reliability of the semiconductor device. In addition, it is also conducive to the first electrode layer covering the cell area and part of the temperature sensing area at the same time, so that the source area of ​​the power device and the first end of the temperature sensor are short-circuited through the first electrode layer to form a Kelvin contact (for example, a Kelvin emitter can be formed for an IGBT device), thereby shielding the external stray inductance, improving the switching speed of the device, and reducing the switching loss. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The included drawings are used to provide a further understanding of the embodiments of the utility model, which constitute a part of the specification, are used to illustrate the implementation of the utility model, and together with the text description, explain the principles of the utility model. Obviously, the drawings described below are only some embodiments of the utility model.

[0018] Figure 1 This is a regional distribution diagram of a semiconductor device in an embodiment of the present utility model.

[0019] Figure 2 It is a schematic structural diagram of a semiconductor device in one embodiment of the utility model.

[0020] Figure 3 FIG. 4 is an equivalent circuit diagram of a temperature sensor of a semiconductor device in an embodiment of the present invention.

[0021] Figure 4 and Figure 5 It is a schematic structural diagram of a temperature sensor of a semiconductor device in one embodiment of the utility model.

[0022] Figure 6 It is a schematic flow chart of a method for preparing a semiconductor device in one embodiment of the utility model.

[0023] Figure 7-Figure 13 It is a schematic structural diagram of a semiconductor device in an embodiment of the utility model during its preparation process.

[0024] The reference numerals are as follows:

[0025] 100-substrate;

[0026] 100C-cell region;

[0027] 100T-temperature sensing area;

[0028] 210-gate structure;

[0029] 220-well region;

[0030] 230-source area;

[0031] 240-carrier storage area;

[0032] 300a - semiconductor material layer;

[0033] 310-N-type doping region;

[0034] 320-P-type doping region;

[0035] 410- first electrode layer;

[0036] 420- second electrode layer;

[0037] 430-conductive thread;

[0038] 500-isolation structure;

[0039] 600- inversion doping region;

[0040] 700-conductive plug;

[0041] 800G-gate lead pad;

[0042] 800A-anode lead pad;

[0043] 800C-cathode lead pad;

[0044] 900-interlayer dielectric layer. DETAILED DESCRIPTION

[0045] The core idea of ​​the utility model is to provide a semiconductor device in which a temperature sensor is embedded between adjacent power devices, so that the device temperature can be monitored in real time and accurately inside the device; at the same time, it is also beneficial to short-circuit the source area of ​​the power device and one end of the temperature sensor, so as to form a Kelvin contact at the source of the power device, shield the influence of external stray inductance, and thus improve the switching speed of the device and reduce switching losses.

[0046] Specifically, the semiconductor device provided by the utility model includes: a substrate, wherein the substrate has a plurality of cell regions and at least one temperature sensing region, wherein the temperature sensing region is located between adjacent cell regions; a power device, formed in the cell region; a temperature sensor, formed in the temperature sensing region; a first electrode layer, covering the cell region to electrically connect to a source region of the power device, and the first electrode layer also covers a portion of the temperature sensing region to electrically connect to a first end of the temperature sensor; and a second electrode layer, covering a portion of the temperature sensing region to electrically connect to a second end of the temperature sensor.

[0047] The semiconductor device and the method for preparing the same proposed by the utility model are further described in detail below in conjunction with the accompanying drawings. According to the following description, the advantages and features of the utility model will be clearer. It should be noted that the drawings are all in a very simplified form and use non-precise proportions, which are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the utility model. It should be recognized that relative terms such as "above", "below", "top", "bottom", "above" and "below" shown in the drawings can be used to describe the relationship between various elements. These relative terms are intended to cover different orientations of elements other than the orientations depicted in the drawings. For example, if the device is inverted relative to the view in the drawing, an element described as "above" another element will now be below the element.

[0048] Figure 1 is a regional distribution diagram of a semiconductor device in an embodiment of the utility model, Figure 2 FIG. 1 is a schematic diagram of the structure of a semiconductor device in an embodiment of the present invention. Figure 1 and Figure 2 As shown, the semiconductor device includes a plurality of cell regions 100C and at least one temperature sensing region 100T, a power device 200 is arranged in the cell region 100C, and the power device may be, for example, an IGBT device, an SGT device or other MOS devices, and a temperature sensor 300 is arranged in the temperature sensing region 100T. The temperature sensing region 100T is arranged between adjacent cell regions 100C, that is, the temperature sensor 300 is arranged between adjacent power devices 200 and embedded in the device region, so that the temperature sensor 300 can monitor the temperature of the power device 200 in real time and accurately inside the device region, which is conducive to timely regulating the operating temperature of the device and ensuring the reliability of the semiconductor device.

[0049] In a specific example, each cell region 100C is a region extending along the first direction (X direction), and a plurality of cell regions 100C are sequentially arranged along the second direction (Y direction). Also, the temperature sensing region 100T may also extend along the first direction (X direction) and present a strip-shaped region, and be arranged between adjacent cell regions 100C.

[0050] exist Figure 1 In the example, the area located on the first side of the temperature sensing area 100T can be defined as the first area 110, and the area located on the second side of the temperature sensing area 100T can be defined as the second area 120. The first area 110 and the second area 120 both include a plurality of cell areas 100C arranged sequentially along the second direction (Y direction). The number of cell areas in the first area 110 and the number of cell areas in the second area 120 can be the same or different.

[0051] Figure 2 The structure shown is, for example, along Figure 1 A schematic cross-sectional view of the second direction (Y direction) in FIG. Figure 2 As shown, a gate trench is formed in the substrate of the cell region 100C, the gate trench extends along the first direction (X direction), and a gate structure 210 of the power device is formed in the gate trench. In addition, a body region 220 and a source region 230 are also formed in the substrate of the cell region 100C, and the body region 220 and the source region 230 are both located on the side of the gate structure 210. In this embodiment, taking the power device as an IGBT device as an example, a carrier storage region 240 can also be set below the body region 220 to enhance conductivity modulation and improve the trade-off relationship between Vcesat (collector-emitter saturation voltage) and Eoff (turn-off energy consumption).

[0052] Continue to refer Figure 2 As shown, a first electrode layer 410 is also formed on the substrate 100, and the first electrode layer 410 covers the cell region 100C to be electrically connected to the source region 230 of the power device. Taking the IGBT device as an example, the first electrode layer 410 is electrically connected to the source region 230 to form the emitter metal of the IGBT device. Exemplarily, the first electrode layer 410 and the source region 230 of the device can be connected to each other through a conductive plug 700, that is, one end of the conductive plug 700 is electrically connected to the source region 230, and the other end of the conductive plug 700 is electrically connected to the first electrode layer 410.

[0053] exist Figure 1 In the example, the first region 110 and the second region 120 are both covered with a first electrode layer 410, wherein the first electrode layer 410 on the first region 110 is electrically connected to the source regions 230 in each cell region within the region, and the first electrode layer 410 on the second region 120 is electrically connected to the source regions 230 in each cell region within the region.

[0054] Continue to refer Figure 2 As shown, the temperature sensor in the temperature sensing area 100T includes a first branch having at least one PN junction structure connected in series, and each PN junction structure can constitute a diode. At this time, for example, the property that the conductivity of the PN junction structure can change with the change of temperature can be used, so that the temperature change inside the semiconductor device can be determined by detecting the conductivity of the PN junction structure, so as to achieve real-time and accurate detection of the temperature of the semiconductor device. In addition, by connecting multiple PN junction structures in series, the sensitivity and accuracy of temperature detection can be effectively guaranteed when performing temperature detection.

[0055] Wherein, for the first branch including one or more PN junction structures connected in series, the cathode end and the anode end of the first branch are connected to the first end and the second end of the temperature sensor respectively. Further, the first electrode layer 410 also covers a portion of the temperature sensing area 100T to electrically connect the first end of the temperature sensor, that is, the first electrode layer 410 is electrically connected to the cathode end of the first branch; and a second electrode layer 420 is also formed on the substrate 100, and the second electrode layer 420 covers a portion of the temperature sensing area 100T to electrically connect the second end of the temperature sensor, that is, the second electrode layer 420 is electrically connected to the anode end of the first branch.

[0056] In this embodiment, the first electrode layer 410 is also electrically connected to the first end of the temperature sensor (for example, electrically connected to the cathode end of the first branch) to facilitate the formation of Kelvin contact. For example, a Kelvin emitter can be formed for an IGBT device, thereby shielding external stray inductance, improving the switching speed of the device, and reducing switching losses. On this basis, the first end of the temperature sensor and the source end of the power device can directly share a lead pad (PAD), reducing the area occupied by the lead pad and improving the utilization rate of the cell area.

[0057] Further, the temperature sensor may also include a second branch connected with a PN junction structure, the second branch and the first branch are connected in parallel, and the PN junction structure in the second branch is reversely connected to the PN junction structure in the first branch. It can be considered that the diode formed by the PN junction structure in the second branch constitutes a reverse diode relative to the diode formed by the PN junction structure in the first branch, and the reverse diode can be used to constitute an ESD electrostatic diode, for example. Specifically, the first electrode layer 410 can be electrically connected to the anode end of the second branch, and the second electrode layer 420 can be electrically connected to the cathode end of the second branch, so as to realize the parallel connection of the first branch and the second branch, and at the same time, the diode in the second branch is reversely connected to the first branch.

[0058] For example, please refer to Figure 3 The equivalent circuit diagram of the temperature sensor of the semiconductor device in one embodiment of the utility model is shown in FIG. Figure 3 In the example, five diodes are connected in series in the first branch of the temperature sensor, and a reverse diode is connected in the second branch. During the operation of the device, when a forward voltage is applied to the first branch, multiple diodes in the first branch are turned on and corresponding currents can be obtained. In this way, the internal temperature of the device can be determined based on the conduction performance of multiple diodes in the first branch. In addition, when static electricity is generated in the device, the static electricity can be discharged through the diode in the second branch, avoiding static electricity breakdown of the diode in the first branch, thereby protecting the entire circuit from static electricity.

[0059] Continue to refer Figure 2As shown, each PN junction structure includes an N-type doping region 310 and a P-type doping region 320 adjacent to each other. In addition, different PN junction structures can be arranged at intervals from each other. That is, a plurality of N-type doping regions 310 and a plurality of P-type doping regions 320 can be formed in the temperature sensing region 100T, so that a plurality of PN junction structures are formed by the plurality of N-type doping regions 310 and the plurality of P-type doping regions 320, wherein different PN junction structures are arranged at intervals from each other, and the N-type doping region and the P-type doping region in the same PN junction structure are in contact with each other.

[0060] In a specific example, a semiconductor material layer (e.g., a polysilicon layer) may be formed in the temperature sensing region 100T, and an N-type ion implantation process and a P-type ion implantation process may be performed on the semiconductor material layer, respectively, to form an N-type doped region 310 and a P-type doped region 320 in the semiconductor material layer. In a further embodiment, the semiconductor material layer further has an undoped region, that is, the semiconductor material layer has an area that is not ion-doped, and adjacent PN junction structures may be separated by an undoped region.

[0061] Combine the following Figure 4 The structure of the temperature sensor including multiple PN junction structures in this embodiment is described. Figure 4 As shown, in the temperature sensing region 100T, the N-type doping region 310 and the P-type doping region 320 may both extend along the first direction (X direction), and the N-type doping region 310 and the P-type doping region 320 in the same PN junction structure are arranged in contact along the second direction (Y direction), and the PN junction structure thus formed also extends along the first direction (X direction) as a whole to present a strip structure.

[0062] Furthermore, different PN junction structures can be arranged along a first direction (X direction), in which case the ends of the strip structures face each other between the PN junction structures arranged along the first direction and adjacent to each other; and / or, different PN junction structures can also be arranged along a second direction (Y direction), in which case the side surfaces of the strip structures face each other between the PN junction structures arranged along the second direction and adjacent to each other.

[0063] For example, for the PN junction structure in the first branch, the N-type doping region 310 of one PN junction structure can be close to the P-type doping region 320 of another PN junction structure between adjacent PN junction structures, that is, the multiple N-type doping regions 310 and the multiple P-type doping regions 320 in the first branch are arranged alternately in the first direction and the second direction. In this way, it is convenient to connect multiple PN junction structures in series, for example, the series connection can be achieved by connecting adjacent PN junction structures end to end.

[0064] For example Figure 4In the embodiment, the PN junction structures D1 to D5 are connected in series, wherein in the PN junction structures D1 and D2 adjacently arranged in the first direction (X direction), the end of the P-type doping region 320 of the PN junction structure D1 is directly opposite to the end of the N-type doping region 310 of the PN junction structure D2; and in the PN junction structures D2 and D3 adjacently arranged in the second direction (Y direction), the side surface of the P-type doping region 320 of the PN junction structure D2 is directly opposite to the side surface of the N-type doping region 310 of the PN junction structure D3. In a specific example, the PN junction structures D1 to D5 can be connected in series by using a conductive wire, and the N-type doping region 310 of the first PN junction structure D1 is connected to the cathode end, and the P-type doping region 320 of the last PN junction structure D5 is connected to the anode end.

[0065] In a specific example, the multiple PN junction structures in the temperature sensing area 100T can be arranged into two columns aligned along the second direction, and the multiple N-type doping regions 310 and the multiple P-type doping regions 320 are arranged alternately in the first direction and the second direction. Further, at least two PN junction structures arranged at the head and tail positions in the first column and all PN junction structures in the second column can constitute the PN junction structure in the first branch; and at least one PN junction structure arranged between the head and tail positions in the first column can constitute the PN junction structure in the second branch. In this way, it is not only conducive to connecting multiple diodes in the first branch in series, but also convenient to realize the reverse parallel connection of the diodes in the second branch and the first branch.

[0066] For example Figure 4 In the example, the PN junction structures D1 to D6 in the temperature sensing area 100T are arranged into two columns aligned along the second direction (Y direction), and the PN junction structures D1 and D5 arranged at the head and tail positions in the first column and all the PN junction structures in the second column are connected in series; and the PN junction structure D6 arranged between the head and tail positions in the first column is used to form the PN junction structure in the second branch.

[0067] In a specific example, for example Figure 5 As shown, multiple PN junction structures (diodes) in the temperature sensing area 100T can be connected by multiple conductive wires 430 to obtain a desired circuit. The conductive wires 430 cover the top of the PN junction structure to be connected, and the PN junction structures at the upper and lower ends of the conductive wires 430 can be connected by conductive plugs 700. For example, the conductive wires 430 can be electrically connected to form Figure 3 and Figure 4The circuit shown in FIG. 1 is a circuit that can use four conductive wires 430 to connect five forward diodes in sequence. Each conductive wire 430 simultaneously covers the cathode or anode of the diode to be connected. At the same time, the first electrode layer 410 extends to cover the cathode end of the first forward diode, and covers the second electrode layer 420 on the anode end of the fifth forward diode. In this example, the first electrode layer 410 also covers the anode end of the reverse diode, and the second electrode layer 420 also covers the cathode end of the reverse diode, so as to form a connection. Figure 3 The circuit shown.

[0068] The first electrode layer 410 , the second electrode layer 420 and the conductive line 430 may be formed using the same conductive material layer. For example, a conductive material layer is formed on the substrate 100 and then the conductive material layer is cut to form the first electrode layer 410 , the second electrode layer 420 and the conductive line 430 .

[0069] Continue to refer Figure 2 As shown, an isolation structure 500 may be provided in the temperature sensing region 100T, and the temperature sensor may be formed on the isolation structure 500, that is, the PN junction structure in the temperature sensor is formed on the isolation structure 500, so that the temperature sensor and the power device may be isolated from each other by using the isolation structure 500. In a specific example, the isolation structure 500 is, for example, a LOCOS isolation structure, and its thickness is, for example, 1 μm to 1.6 μm.

[0070] Furthermore, an inverted doping region 600 is formed in the substrate of the temperature sensing region 100T. In this embodiment, the inverted doping region 600 is formed in the substrate 100 below the isolation structure 500, and the conductivity type of the inverted doping region 600 is opposite to the conductivity type of the substrate 100, so as to stabilize the electric field of the region by using the inverted doping region 600. For example, if the substrate 100 is an N-type substrate, the inverted doping region 600 is a P-type doping. In a specific example, the doping type of the inverted doping region 600 is consistent with the doping type of the body region 220 in the cell region 100C, and the inverted doping region 600 and the body region 220 can be connected to each other. Furthermore, the depth of the inverted doping region 600 can be greater than the depth of the body region 220, so that the inverted doping region 600 extends to a deeper position in the substrate 100.

[0071] Continue to refer Figure 1 and Figure 5 As shown, the substrate 100 also has an electrode lead-out region, in which, for example, a gate lead-out pad 800G of a power device, an emitter lead-out pad (not shown), an anode lead-out pad 800A of a temperature sensor, and a cathode lead-out pad 800C may be provided. Figure 5 As shown, the first electrode layer 410 further extends to the cathode lead pad 800C, and the second electrode layer 420 further extends to the anode lead pad 800A.

[0072] For the semiconductor device as described above, a method for preparing the semiconductor device is described below by way of example. A method for preparing a semiconductor device includes: providing a substrate, wherein the substrate has a plurality of cell regions and at least one temperature sensing region, wherein the temperature sensing region is located between adjacent cell regions; forming a power device in the cell region, and forming a temperature sensor in the temperature sensing region; and forming a first electrode layer and a second electrode layer, wherein the first electrode layer covers the cell region to electrically connect to a source region of the power device, and the first electrode layer also covers a portion of the temperature sensing region to electrically connect to a first end of the temperature sensor, and the second electrode layer covers a portion of the temperature sensing region to electrically connect to a second end of the temperature sensor.

[0073] In a specific example, the power device formed in the cell region includes a gate structure, a body region and a source region, and its preparation method includes, for example: forming a gate structure in the substrate of each cell region, and then forming a body region and a source region in sequence on the side of the gate structure. Alternatively, its preparation method includes: forming a well-doped region and a source-doped region in the substrate, and then forming a gate structure in the substrate of each cell region, and using the gate structure to divide the well-doped region and the source-doped region into a plurality of body regions and a plurality of source regions. Furthermore, the power device in the cell region can be an IGBT device, an SGT device or other power device. Taking the IGBT device as an example, a carrier storage region can also be formed in the substrate at this time.

[0074] Furthermore, the temperature sensor formed in the temperature sensing area includes a PN junction structure formed by at least one group of N-type doping regions and P-type doping regions, and its preparation method, for example, includes: forming a semiconductor material layer (for example, a polysilicon layer) on a substrate in the temperature sensing area, and performing an N-type ion implantation process and a P-type ion implantation process on the semiconductor material layer, respectively, to form an N-type doping region and a P-type doping region in the semiconductor material layer.

[0075] It should be noted that the preparation process of the power device and the preparation process of the temperature sensor can be carried out separately, or the processes can be integrated with each other. In a specific example, the power device can be prepared first, and then the temperature sensor can be prepared; or, the temperature sensor can be prepared first, and then the power device can be prepared. Alternatively, the preparation process of the temperature sensor can be integrated in the process of preparing the power device. For example, when performing an ion implantation process to form the source region of the power device, the semiconductor material layer in the temperature sensing region can be implanted at the same time to form a doping region of the corresponding doping type in the PN junction structure.

[0076] And, the preparation method of the first electrode layer and the second electrode layer, for example, includes: forming a conductive material layer on the substrate, the conductive material layer covering the cell area and the temperature sensing area; then, etching the conductive material layer to separate the conductive material layer to form the first electrode layer and the second electrode layer.

[0077] Combine the following Figure 6 and Figure 7-Figure 13 A method for preparing a semiconductor device in this embodiment is described by way of example. In this example, an IGBT device is taken as an example.

[0078] First, step S100 is performed. Figure 1 and Figure 7 As shown, a substrate 100 is provided. The substrate 100 has a plurality of cell regions 100C and at least one temperature sensing region 100T. The temperature sensing region 100T is located between adjacent cell regions 100C.

[0079] In a specific example, each cell region 100C is a region extending along the first direction (X direction), and a plurality of cell regions 100C are sequentially arranged along the second direction (Y direction). Also, the temperature sensing region 100T may also extend along the first direction (X direction) and present a strip-shaped region, and be arranged between adjacent cell regions 100C.

[0080] Then execute step S200, and continue to refer to Figure 7 As shown, a carrier storage region 240 is formed in the substrate 100 of the cell region 100C, and an inversion doping region 600 is formed in the substrate of the temperature sensing region 100T. In a specific example, the substrate 100 is a substrate of a first conductivity type, the carrier storage region 240 is also a doping region of the first conductivity type, and the inversion doping region 600 is a doping region of a second conductivity type. In this embodiment, the inversion doping region 600 extends inward from the top surface of the substrate to a depth position of the substrate that is lower than the depth position of the carrier storage region 240.

[0081] Then execute step S300, and continue to refer to Figure 7 As shown, an isolation structure 500 is formed on the substrate of the temperature sensing region 100T. In a specific example, the isolation structure 500 may be formed by using a LOCOS process. Also, the isolation structure 500 is formed above the inversion doping region 600 .

[0082] Then, step S400 is performed. For details, refer to Figure 8As shown, a semiconductor material layer 300a is formed on the isolation structure 500 of the temperature sensing region 100T. In a specific example, a semiconductor material layer of the second conductivity type may be formed first, and then an ion implantation process is performed on a portion of the semiconductor material layer to form a doped region of the first conductivity type, thereby obtaining a PN junction structure including a P-type doped region and an N-type doped region.

[0083] For example, a P-type doped semiconductor material layer 300a may be formed on the substrate of the temperature sensing region 100T, and the method includes: first, forming a non-doped polysilicon material layer on the substrate 100, the polysilicon material layer covering the cell region 100C and the temperature sensing region 100T, and the thickness thereof is, for example, Then, an ion implantation process is performed to form a P-type polysilicon layer from the polysilicon material layer. In a specific example, a boron ion implantation process may be performed, and the ion dose may be, for example, 5E14-3E15 / cm 2 ; Afterwards, an etching process is performed to remove the polysilicon material outside the temperature sensing region 100T and retain the P-type doped semiconductor material layer 300a in the temperature sensing region 100T. In this embodiment, a P-type ion implantation process is performed before etching the polysilicon material. At this time, the P-type ion implantation process can be performed without a mask, which is conducive to simplifying the process and saving costs.

[0084] Then, step S500 is performed. For details, refer to Fig. 9 and Fig.10 As shown, a gate structure 210 and a body region 220 are formed in the substrate of the cell region 100C. In a specific example, the method for forming the gate structure 210 may include: etching the substrate of the cell region 100C to form a gate trench; then, forming a gate dielectric layer on the inner wall of the gate trench, and specifically, the gate dielectric layer may be grown by an oxidation process, and the thickness of the gate dielectric layer is, for example, Next, a gate conductive layer is filled in the gate trench to form the gate structure 210. Also, the body region 220 may be formed by an ion implantation process of the second conductivity type, and the doping dose thereof is, for example, 2E13-3E13 / cm 2 .

[0085] Then, step S600 is performed. For details, refer to Fig.11 As shown, a first conductivity type ion implantation process is performed to form a source region 230 in the body region 220, and a portion of the second conductivity type semiconductor material layer is transformed into a first conductivity type doping region to form a first conductivity type doping region in a portion of the semiconductor material layer, thereby forming a PN junction structure including a P-type doping region and an N-type doping region. Fig.11As shown, a portion of the P-type doped semiconductor material layer is converted into an N-type doped layer, thereby forming a PN junction structure including a P-type doped region 320 and an N-type doped region 310. The doping dose of the ion implantation process for the source region 230 is, for example, 2E15-6E15 / cm 2 .

[0086] Then, step S700 is executed. For details, refer to Fig.12 As shown, an interlayer dielectric layer 900 is formed on the substrate 100, and the interlayer dielectric layer 900 covers the cell area 100C and the temperature sensing area 100T, thereby protecting the device structures of the power device and the temperature sensor thereunder. The thickness of the interlayer dielectric layer 900 is, for example,

[0087] Then, step S800 is executed. For details, refer to Fig.13 As shown, a plurality of conductive plugs 700 are formed, and the plurality of conductive plugs 700 include a first conductive plug formed in the cell region 100C and a second conductive plug formed in the temperature sensing region 100T. The first conductive plug in the cell region 100C penetrates the interlayer dielectric layer 900 and is electrically connected to the source region 230; the second conductive plug in the temperature sensing region 100T penetrates the interlayer dielectric layer 900 and is electrically connected to the P-type doping region 320 and the N-type doping region 310.

[0088] In a specific example, the method for preparing the plurality of conductive plugs 700 includes, for example, etching the interlayer dielectric layer 900 in the cell region 100C, and further etching the source region 230 to the well region 220, so that the formed first contact hole passes through the interlayer dielectric layer 900 to the well region 220; and etching the interlayer dielectric layer 900 in the temperature sensing region 100T, and stopping the etching on the semiconductor material layer to form a second contact hole; and then filling each contact hole with a metal material to form the conductive plug 700, that is, filling the first contact hole with a metal material to form a first conductive plug, and filling the second contact hole with a metal material to form a second conductive plug. The metal material filled in the contact hole includes, for example, tungsten (W).

[0089] Then execute step S900, and continue to refer to Fig.13As shown, a first electrode layer 410, a second electrode layer 420 and a conductive line 430 are formed. The first electrode layer 410 covers the cell region 100C and a portion of the temperature sensing region 100T to electrically connect the source region 230 of the power device and the first end of the temperature sensor (e.g., the cathode end of the first branch) through the conductive plug 700. The second electrode layer 420 covers a portion of the temperature sensing region 100T and is electrically connected to the second end of the temperature sensor (e.g., the anode end of the first branch) through the conductive plug 700. In addition, the conductive line 430 is formed in the temperature sensing region 100T and connects different PN junction structures (diodes) through the conductive plug 700 to form a detection circuit of the temperature sensor.

[0090] In a specific example, a preparation method for forming a first electrode layer 410, a second electrode layer 420 and a conductive line 430 includes: depositing a conductive material layer, the conductive material layer including, for example, at least one of copper and aluminum, which covers the cell area 100C and the temperature sensing area 100T; then, etching the conductive material layer to pattern the conductive material layer to form the first electrode layer 410, the second electrode layer 420 and the conductive line 430.

[0091] In this embodiment, an IGBT device is taken as an example, and its preparation method further includes: forming a collector region of a second conductivity type and a back electrode layer on the back side of the substrate 100, and the back electrode layer is electrically connected to the collector region.

[0092] The semiconductor device as described above can be specifically applied to an IGBT chip, that is, the IGBT chip has multiple IGBT devices, and the temperature sensor is integrated inside the IGBT chip. The temperature sensor can be set in the central area of ​​the IGBT chip, for example, to improve the temperature sensor's monitoring accuracy of the chip temperature and enhance the safe use of the chip.

[0093] In addition, the first electrode layer on the IGBT chip is electrically connected to the emitter of the IGBT device and the first end of the temperature sensor at the same time, so that the first end of the temperature sensor is short-circuited with the emitter of the IGBT device to form a Kelvin emitter, which can shield the influence of external stray inductance, improve the switching speed of the IGBT device, and thus reduce switching losses. In addition, the first end of the temperature sensor and the source end of the power device can directly share a lead pad (PAD), reducing the occupied area of ​​the lead pad and improving the utilization rate of the cell area.

[0094] It should be noted that the various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments, and the same and similar parts between the various embodiments can be referred to each other. Also, although the utility model has been disclosed as above with preferred embodiments, the above embodiments are not intended to limit the utility model. For any technician familiar with the art, without departing from the scope of the technical solution of the utility model, the technical content disclosed above can be used to make many possible changes and modifications to the technical solution of the utility model, or modified into equivalent embodiments of equivalent changes. Therefore, any simple modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the utility model without departing from the content of the technical solution of the utility model still fall within the scope of protection of the technical solution of the utility model.

[0095] It should also be recognized that, unless otherwise specified or indicated, the terms "first", "second", "third", etc. in the specification are only used to distinguish between various components, elements, steps, etc. in the specification, and are not used to indicate the logical relationship or sequential relationship between various components, elements, steps, etc. It should also be understood that the singular forms "a" and "an" used herein and in the appended claims include plural references unless the context clearly indicates otherwise. For example, a reference to "a step" or "a device" means a reference to one or more steps or devices, and may include secondary steps and secondary devices.

Claims

1. A semiconductor device, characterized in that: include: A substrate having a plurality of cell regions and at least one temperature sensing region, wherein the temperature sensing region is located between adjacent cell regions; A power device is formed in the cell region; a temperature sensor formed in the temperature sensing area; a first electrode layer, covering the cell region to be electrically connected to the source region of the power device, and the first electrode layer also covers a portion of the temperature sensing region to be electrically connected to the first end of the temperature sensor; and The second electrode layer covers a portion of the temperature sensing area to be electrically connected to the second end of the temperature sensor.

2. The semiconductor device according to claim 1, wherein The temperature sensor comprises a first branch circuit having at least one PN junction structure connected in series, the first electrode layer is electrically connected to a cathode end of the first branch circuit, and the second electrode layer is electrically connected to an anode end of the first branch circuit.

3. The semiconductor device according to claim 2, wherein: The temperature sensor further includes a second branch connected with a PN junction structure, the first electrode layer is electrically connected to an anode end of the second branch, and the second electrode layer is electrically connected to a cathode end of the second branch.

4. The semiconductor device according to claim 3, characterized in that The temperature sensor includes a plurality of N-type doping regions and a plurality of P-type doping regions formed on a substrate, so that the plurality of N-type doping regions and the plurality of P-type doping regions constitute a plurality of PN junction structures, wherein different PN junction structures are arranged at intervals from each other, and the N-type doping regions and the P-type doping regions in the same PN junction structure are in contact with each other.

5. The semiconductor device according to claim 4, wherein: The temperature sensing region extends along a first direction, and the N-type doping region and the P-type doping region both extend along the first direction; wherein the N-type doping region and the P-type doping region in the same PN junction structure are arranged along a second direction and contact each other.

6. The semiconductor device according to claim 5, characterized in that The multiple PN junction structures in the temperature sensing area are arranged into two rows aligned along the second direction, and between adjacent PN junction structures, an N-type doped region of one PN junction structure is close to a P-type doped region of another PN junction structure; At least two PN junction structures arranged at the head and tail positions in the first column and all PN junction structures in the second column are connected in series to form the first branch; and at least one PN junction structure arranged between the head and tail positions in the first column forms the second branch.

7. The semiconductor device according to claim 1, wherein: An isolation structure is formed in the temperature sensing area, and the temperature sensor is formed on the isolation structure.

8. The semiconductor device according to claim 1, wherein An inversion doping region is also formed in the substrate of the temperature sensing region, and the conductivity type of the inversion doping region is opposite to the conductivity type of the substrate.

9. The semiconductor device according to any one of claims 1 to 8, characterized in that: The cell region extends along a first direction, a plurality of cell regions are arranged in sequence along a second direction, and the temperature sensing region is arranged between adjacent cell regions and extends along the first direction.

10. An IGBT chip, characterized in that: It comprises the semiconductor device according to any one of claims 1 to 9, wherein the power device in the semiconductor device is an IGBT device, and the temperature sensor is arranged between adjacent IGBT devices.

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