GaN-based LED epitaxial wafer and preparation method thereof

Abstract

The invention relates to the technical field of LED epitaxial wafers, and discloses a GaN-based LED epitaxial wafer and a preparation method thereof, and the GaN-based LED epitaxial wafer comprises a substrate, a buffer layer, an N-type semiconductor layer, a stress release layer, a multi-quantum well light-emitting layer, an electron blocking layer, and a P-type semiconductor layer. Wherein the N-type semiconductor layer sequentially comprises a first porous low-temperature GaN layer, a second porous AlGaN / GaN superlattice layer, a third high-temperature GaN layer, a fourth porous AlGaN / GaN superlattice layer and a fifth high-temperature GaN layer. By adopting the invention, the generation of defects in the growth process of the epitaxial material can be reduced, the dislocation density of the material is reduced, and the quality of the epitaxial wafer material is remarkably improved, so that the radiation recombination efficiency in the active region of the light-emitting diode is improved, and meanwhile, the proportion of the photon escape body material in the active region can be remarkably improved.

Description

Technical Field

[0001] The invention relates to the technical field of LED epitaxial wafers, and in particular to a GaN-based LED epitaxial wafer and a preparation method thereof. Background Art

[0002] Light Emitting Diode (LED) is a semiconductor light-emitting device that converts electrical energy directly into light energy with high conversion efficiency. As a new energy-saving and environmentally friendly light source, LED has received great attention in recent years, and many countries regard LED-related semiconductor lighting as a strategic technology. Through a lot of research and development and experiments, semiconductor lighting technology has made rapid progress and truly realized the commercialization of semiconductor lighting. Various types of LEDs are widely used in indication, display, backlight, projection and other fields. These achievements are mainly due to the progress of GaN-based LED-related technologies. With the improvement of production scale and luminous efficiency, the cost is constantly decreasing. Therefore, GaN-based LEDs have broad application prospects and high commercial value.

[0003] In order to obtain high-brightness LEDs, the key is to improve the internal quantum efficiency and external quantum efficiency of the device. The light-emitting diodes currently used in the market are all prepared by epitaxy on heterogeneous substrates. Due to the large lattice mismatch and thermal mismatch between the heterogeneous substrates (including sapphire substrates, silicon carbide substrates, silicon substrates, etc.) and the epitaxial materials, the epitaxial materials will be subjected to greater stress during the growth process, and are prone to dislocation defects, thereby reducing the light efficiency of the light-emitting diodes. In addition, the internal quantum efficiency of blue light GaN-based LEDs can reach more than 80%, but the external quantum efficiency of high-power LED chips is usually only about 40%. The main factor restricting the improvement of external quantum efficiency is the low light extraction efficiency of the chip. This is because the refractive index of GaN material (n = 2.5) is quite different from that of air (n = 1) and that of sapphire substrate (n = 1.75), resulting in the critical angles of total reflection at the air-GaN interface and the sapphire-GaN interface being only 23.6° and 44.4° respectively. Only a small amount of light generated in the active region can escape from the bulk material. In order to improve the light extraction efficiency of the chip, the main technical solutions currently used at home and abroad include the growth of distributed Bragg reflector (DBR) structure, patterned substrate (PSS) technology, surface roughening technology and photonic crystal technology. PSS The requirements for the regularity of the pattern are very high. In addition, the sapphire substrate is relatively hard. Whether it is dry etching or wet etching, there are certain difficulties in the consistency and uniformity of the entire pattern. The production process has very high requirements for equipment and process, resulting in high costs. The DBR and photonic crystal manufacturing processes are relatively complex and costly, and the surface roughening technology uses dry etching or wet etching processes, which also presents great challenges. Therefore, in order to improve the luminous efficiency of light-emitting diodes, that is, to improve the internal quantum efficiency and external quantum efficiency of the device, it is very necessary to improve the quality of epitaxial materials and increase the proportion of photon escape body materials in the active area by optimizing the epitaxial structure and process of light-emitting diodes.

[0004] The light-emitting diodes currently used in the market are all prepared by epitaxy on heterogeneous substrates. Due to the large lattice mismatch and thermal mismatch between the heterogeneous substrates (including sapphire substrates, silicon carbide substrates, silicon substrates, etc.) and the epitaxial materials, the epitaxial materials are subjected to large stress during the growth process and are prone to dislocation defects, thereby reducing the light efficiency of the light-emitting diodes. At the same time, the main factor restricting the improvement of external quantum efficiency is the low light extraction efficiency of the chip. This is because the refractive index of the GaN material (n = 2.5) is significantly different from the refractive index of air (n = 1) and the refractive index of the sapphire substrate (n = 1.75), resulting in the critical angles of total reflection at the air-GaN interface and the sapphire-GaN interface being only 23.6° and 44.4° respectively, and only a small amount of the light generated in the active area can escape from the bulk material. Summary of the invention

[0005] Based on the above technical background, the technical problem to be solved by the present invention is to provide a GaN-based LED epitaxial wafer and a preparation method, which can reduce the generation of defects in the epitaxial material during the growth process, reduce the dislocation density of the material, and significantly improve the quality of the epitaxial wafer material, thereby improving the radiation recombination efficiency in the active area of ​​the light-emitting diode, and at the same time can significantly increase the proportion of photon escape body materials in the active area.

[0006] The technical problem to be solved by the present invention is also to provide a method for preparing a GaN-based LED epitaxial wafer, which has simple method, strong operability and good industrial application prospect.

[0007] In order to solve the above technical problems, the present invention provides a GaN-based LED epitaxial wafer, comprising: a substrate, a buffer layer, an N-type semiconductor layer, a stress release layer, a multi-quantum well light-emitting layer, an electron blocking layer and a P-type semiconductor layer;

[0008] The N-type semiconductor layer includes, in sequence: a first porous low-temperature GaN layer, a second porous AlGaN / GaN superlattice layer, a third high-temperature GaN layer, a fourth porous AlGaN / GaN superlattice layer, and a fifth high-temperature GaN layer;

[0009] The first porous low-temperature GaN layer is provided with a first V-shaped hole penetrating through the first porous low-temperature GaN layer;

[0010] The second porous AlGaN / GaN superlattice layer is provided with a second V-shaped hole and a third V-shaped hole, the second V-shaped hole is grown on the basis of the first V-shaped hole, and the opening size of the second V-shaped hole is larger than the opening size of the third V-shaped hole;

[0011] The third high-temperature GaN layer completely fills the third V-shaped hole and is provided with a fourth V-shaped hole, wherein the fourth V-shaped hole is grown on the basis of the second V-shaped hole;

[0012] The fourth porous AlGaN / GaN superlattice layer is deposited on the third high-temperature GaN layer to form a fifth V-shaped hole and a stress release hole, wherein the fifth V-shaped hole is grown on the basis of the fourth V-shaped hole;

[0013] The fifth high temperature GaN layer completely fills the fifth V-shaped hole and the stress release hole.

[0014] As an improvement of the above technical solution, before depositing the first porous low-temperature GaN layer, the second porous AlGaN / GaN superlattice layer, and the fourth porous AlGaN / GaN superlattice layer, the surface of the epitaxial layer material needs to be treated with high-temperature H2 gas. The temperature of the high-temperature H2 gas treatment is 1020°C to 1250°C, and the pressure is 20torr to 360torr.

[0015] As an improvement of the above technical solution, before depositing the first porous low-temperature GaN layer, a first high-temperature H2 gas treatment is performed, wherein the H2 flow rate of the first high-temperature H2 gas treatment is 50 to 500 slm and the treatment time is 15 to 360 s;

[0016] Before depositing the second porous AlGaN / GaN superlattice layer, performing a second high-temperature H2 gas treatment, wherein the H2 flow rate of the second high-temperature H2 gas treatment is 30 to 390 slm and the treatment time is 10 to 240 s;

[0017] Before depositing the fourth porous AlGaN / GaN superlattice layer, a third high-temperature H2 gas treatment is performed, wherein the H2 flow rate of the third high-temperature H2 gas treatment is 20 to 350 slm, and the treatment time is 5 to 120 s.

[0018] As an improvement of the above technical solution, the first porous low-temperature GaN layer is a porous GaN material with a low Si doping content, a thickness of 5 nm to 500 nm, and a Si doping concentration of 2.06×10 17 / cm 3 ~1.2×10 19 / cm 3 The growth temperature is 850℃~1120℃, and the pressure is 30torr~320torr.

[0019] As an improvement of the above technical solution, the density of the second V-shaped holes is 1.28×10 8 ~5.68×10 11 / cm 2 ;

[0020] The density of the third V-shaped holes is 2.65×10 8 ~1.85×10 12 / cm 2 .

[0021] As an improvement of the above technical solution, the second porous AlGaN / GaN superlattice layer includes a second porous AlGaN layer and a second porous GaN layer stacked in sequence, and the number of alternating stacking cycles is 2 to 20;

[0022] The second porous AlGaN layer is low-doped with Si element, and the Si doping concentration is 5.2×10 17 / cm 3 ~1.6×10 19 / cm 3, Al component 0.2≤X2≤0.8, thickness 1.2nm~20nm, growth temperature 900℃~1150℃, pressure 30torr~320torr;

[0023] The second porous GaN layer is highly doped with Si element, and the Si doping concentration is 2.5×10 18 / cm 3 ~3.2×10 19 / cm3, thickness is 1.2nm~20nm, growth temperature is 900℃~1150℃, and pressure is 30torr~320torr.

[0024] As an improvement of the above technical solution, the third high temperature GaN layer is a high temperature GaN material that is not intentionally doped, the thickness of the third high temperature GaN layer is 0.03 μm to 2 μm, the growth temperature is 1050° C. to 1250° C., and the pressure is 30 torr to 320 torr.

[0025] As an improvement of the above technical solution, the fourth porous AlGaN / GaN superlattice layer includes a fourth porous AlGaN layer and a fourth porous GaN layer stacked in sequence, and the number of alternating stacking cycles is 3 to 50;

[0026] The fourth porous AlGaN layer is low-doped with Si element, and the Si doping concentration is 8.5×10 17 / cm 3 ~1.9×10 19 / cm 3 , Al component 0.02≤X4≤0.5, thickness 2nm~30nm, growth temperature 920℃~1180℃, pressure 30torr~320torr;

[0027] The fourth porous GaN layer is highly doped with Si element, and the Si doping concentration is 3.0×10 18 / cm 3 ~3.8×10 19 / cm 3 , thickness is 2nm~30nm, growth temperature is 920℃~1180℃, and pressure is 30torr~320torr.

[0028] As an improvement of the above technical solution, the fifth high temperature GaN layer is a high temperature GaN material highly doped with Si element, and the Si doping concentration is 3.6×10 18 / cm 3 ~5.6×10 19 / cm 3The thickness of the fifth high-temperature GaN layer is 2 μm to 8 μm, the growth temperature is 1050° C. to 1250° C., and the pressure is 30 torr to 320 torr.

[0029] Correspondingly, the present invention also discloses a method for preparing a GaN-based LED epitaxial wafer, comprising:

[0030] Selecting a substrate;

[0031] growing a buffer layer on the substrate;

[0032] A Si doping source is introduced to grow an N-type semiconductor layer on the buffer layer;

[0033] Growing a low-temperature stress release layer on the N-type semiconductor layer;

[0034] Growing a multi-quantum well light-emitting layer on the low-temperature stress release layer;

[0035] Growing an electron blocking layer on the multi-quantum well light-emitting layer;

[0036] Growing a P-type semiconductor layer on the electron blocking layer;

[0037] Among them, the N-type semiconductor layer includes, from bottom to top, a first porous low-temperature GaN layer, a second porous AlGaN / GaN superlattice layer, a third high-temperature GaN layer, a fourth porous AlGaN / GaN superlattice layer, and a fifth high-temperature GaN layer; before depositing the first porous low-temperature GaN layer, the second porous AlGaN / GaN superlattice layer, and the fourth porous AlGaN / GaN superlattice layer, the surface of the epitaxial layer material needs to be treated with high-temperature H2 gas, and the temperature of the high-temperature H2 gas treatment is 1020°C to 1250°C, and the pressure is 20torr to 360torr.

[0038] The present invention has the following beneficial effects:

[0039] The GaN-based LED epitaxial wafer of the present invention comprises five sublayers stacked sequentially from bottom to top, namely, a first porous low-temperature GaN layer, a second porous AlGaN / GaN superlattice layer, a third high-temperature GaN layer, a fourth porous AlGaN / GaN superlattice layer and a fifth high-temperature GaN layer. Among them, the first porous low-temperature GaN layer, the second porous AlGaN / GaN superlattice layer and the fourth porous AlGaN / GaN superlattice layer are all designed as porous structural materials, and the design of the porous structural materials is conducive to fully releasing the stress of the epitaxial layer material, can effectively reduce the large stress on the epitaxial layer material during the growth process, and improve the quality of the epitaxial layer material.

[0040] Both, before depositing the first porous low-temperature GaN layer, the second porous AlGaN / GaN superlattice layer, and the fourth porous AlGaN / GaN superlattice layer, the surface of the epitaxial layer material needs to be treated with high-temperature H2 gas, that is, the H2 and N2 mixed gas needs to be circulated and stabilized for a certain period of time. The material with poor crystallization quality on the surface of the epitaxial layer material treated with H2 gas will be decomposed, which is conducive to reducing the defect density of the epitaxial layer material and improving the crystal quality of the epitaxial layer material. At the same time, an uneven rough surface is formed, which is conducive to the subsequent deposition of the epitaxial layer material to form V-shaped holes and stress release holes of varying sizes, further fully releasing the stress of the epitaxial layer material, and reducing the defect density of the epitaxial layer material, and improving the quality of the epitaxial layer material. Moreover, the surface of the epitaxial layer material treated with H2 gas forms an uneven rough surface, that is, the N-type semiconductor layer is designed as a three-layer rough surface + three-layer porous structure material, which can reduce the in-plane total reflection of the N-type material and significantly increase the proportion of photon escape body materials in the active area, thereby improving the light extraction efficiency of the chip.

[0041] Thirdly, the third high-temperature GaN layer and the fifth high-temperature GaN layer are both high-temperature two-dimensional merged materials. In the process of completely filling the V-shaped holes and stress release holes of different sizes, some dislocation defects will be continuously deflected and merged, reducing the dislocation density of the epitaxial layer material, thereby improving the quality of the epitaxial material.

[0042] Therefore, the LED epitaxial wafer prepared by the present invention can reduce the generation of defects in the epitaxial material during the growth process, reduce the dislocation density of the material, and significantly improve the quality of the epitaxial wafer material, thereby improving the radiation recombination efficiency in the active region of the light-emitting diode, that is, the internal quantum efficiency, and at the same time can significantly increase the proportion of photon escaping body materials in the active region, that is, improve the light extraction efficiency of the chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] Figure 1 It is a structural schematic diagram of the GaN-based LED epitaxial wafer of the present invention. DETAILED DESCRIPTION

[0044] In order to make the objectives, technical solutions and advantages of the present invention more clear, the present invention will be further described in detail below with reference to the accompanying drawings.

[0045] like Figure 1 As shown, the present invention provides a GaN-based LED epitaxial wafer, comprising: a substrate 10, a buffer layer 20, an N-type semiconductor layer 30, a stress release layer 40, a multi-quantum well light-emitting layer 50, an electron blocking layer 60 and a P-type semiconductor layer 70;

[0046] The N-type semiconductor layer 30 includes, from bottom to top, a first porous low-temperature GaN layer 31, a second porous AlGaN / GaN superlattice layer 32, a third high-temperature GaN layer 33, a fourth porous AlGaN / GaN superlattice layer 34, and a fifth high-temperature GaN layer 35;

[0047] The first porous low-temperature GaN layer 31 is provided with a first V-shaped hole 311 penetrating through the first porous low-temperature GaN layer 31;

[0048] The second porous AlGaN / GaN superlattice layer 32 is provided with a second V-shaped hole 321 and a third V-shaped hole 322, wherein the second V-shaped hole 321 is grown on the basis of the first V-shaped hole 311, and the opening size of the second V-shaped hole 321 is larger than the opening size of the third V-shaped hole 322;

[0049] The third high-temperature GaN layer 33 completely fills the third V-shaped hole 322 and is provided with a fourth V-shaped hole 331 , wherein the fourth V-shaped hole 331 is grown on the basis of the second V-shaped hole 321 ;

[0050] The fourth porous AlGaN / GaN superlattice layer 34 is deposited on the third high-temperature GaN layer 33 to form a fifth V-shaped hole 341 and a stress release hole 342. The fifth V-shaped hole 341 is grown on the basis of the fourth V-shaped hole 331.

[0051] The fifth high temperature GaN layer 35 completely fills the fifth V-shaped hole 341 and the stress release hole 342 .

[0052] The GaN-based LED epitaxial wafer of the present invention comprises five sublayers stacked in sequence from bottom to top, namely, a first porous low-temperature GaN layer 31, a second porous AlGaN / GaN superlattice layer 32, a third high-temperature GaN layer 33, a fourth porous AlGaN / GaN superlattice layer 34, and a fifth high-temperature GaN layer 35. Among them, the first porous low-temperature GaN layer 31, the second porous AlGaN / GaN superlattice layer 32, and the fourth porous AlGaN / GaN superlattice layer 34 are all designed as porous structural materials. The design of the porous structural material is conducive to fully releasing the stress of the epitaxial layer material, which can effectively reduce the large stress on the epitaxial layer material during the growth process and improve the quality of the epitaxial layer material. The third high-temperature GaN layer 33 and the fifth high-temperature GaN layer 35 are both high-temperature two-dimensional merged materials. In the process of completely filling the V-shaped holes and stress release holes of different sizes, some dislocation defects will be continuously deflected and merged, reducing the dislocation density of the epitaxial layer material, thereby improving the quality of the epitaxial material.

[0053] In some preferred embodiments, before depositing the first porous low-temperature GaN layer 31, the second porous AlGaN / GaN superlattice layer 32, and the fourth porous AlGaN / GaN superlattice layer 34, the surface of the epitaxial layer material needs to be treated with high-temperature H2 gas. Specifically, the high-temperature H2 gas treatment is to intermittently and cyclically introduce a mixed gas of H2 and N2 into the reaction chamber and stabilize it for a certain period of time. The introduction time is preferably 10 to 360 seconds, and the temperature of the high-temperature H2 gas treatment is preferably 1020°C to 1250°C, and the pressure is preferably 20 torr to 360 torr. After the H2 gas treatment, the material with poor crystallization quality on the surface of the epitaxial layer material will be decomposed, which is beneficial to reduce the defect density of the epitaxial layer material and improve the crystal quality of the epitaxial layer material. At the same time, a rough surface with uneven surfaces is formed, which is beneficial to the subsequent deposition of the epitaxial layer material to form V-shaped holes and stress release holes of different sizes, thereby releasing the stress of the epitaxial layer material and improving the quality of the epitaxial layer material.

[0054] Preferably, three high-temperature H2 gas treatments are required during the deposition of the N-type semiconductor layer, wherein the first high-temperature H2 gas treatment is performed before depositing the first porous low-temperature GaN layer 31, the second high-temperature H2 gas treatment is performed before depositing the second porous AlGaN / GaN superlattice layer 32, and the third high-temperature H2 gas treatment is performed before depositing the fourth porous AlGaN / GaN superlattice layer 34. The H2 flow rate of the first high-temperature H2 gas treatment is greater than or equal to the H2 flow rate of the second high-temperature H2 gas treatment, and the H2 flow rate of the second high-temperature H2 gas treatment is greater than or equal to the H2 flow rate of the third high-temperature H2 gas treatment. The time of the first high-temperature H2 gas treatment is greater than or equal to the time of the second high-temperature H2 gas treatment, and the time of the second high-temperature H2 gas treatment is greater than or equal to the time of the third high-temperature H2 gas treatment.

[0055] More preferably, the H2 flow rate of the first high-temperature H2 gas treatment is 50-500slm, specifically 50slm, 100slm, 150slm, 200slm, 250slm, 300slm, 350slm, 400slm, 450slm, 500slm, but not limited to these; the treatment time is 15-360s, specifically 15s, 50s, 100s, 150s, 200s, 250s, 300s, 360s, but not limited to these.

[0056] The H2 flow rate of the second high-temperature H2 gas treatment is 30-390slm, specifically 30slm, 50slm, 100slm, 150slm, 200slm, 250slm, 300slm, 350slm, 390slm, but not limited to these; the treatment time is 10-240s, specifically 10s, 30s, 50s, 100s, 150s, 200s, 240s, but not limited to these.

[0057] The H2 flow rate of the third high-temperature H2 gas treatment is 20-350slm, specifically 20slm, 50slm, 100slm, 150slm, 200slm, 250slm, 300slm, 350slm, but not limited to these; the treatment time is 5-120s, specifically 5s, 25s, 50s, 100s, 120s, but not limited to these.

[0058] Before depositing the first porous low-temperature GaN layer, the second porous AlGaN / GaN superlattice layer, and the fourth porous AlGaN / GaN superlattice layer, the surface of the epitaxial layer material needs to be treated with high-temperature H2 gas, that is, a mixed gas of H2 and N2 needs to be circulated and stabilized for a certain period of time. The material with poor crystallization quality on the surface of the epitaxial layer material treated with H2 gas will be decomposed, which is beneficial to reduce the defect density of the epitaxial layer material and improve the crystal quality of the epitaxial layer material. At the same time, an uneven rough surface is formed, which is beneficial to the subsequent deposition of the epitaxial layer material to form V-shaped holes and stress release holes of varying sizes, further fully release the stress of the epitaxial layer material, and reduce the defect density of the epitaxial layer material, and improve the quality of the epitaxial layer material. Moreover, the surface of the epitaxial layer material treated with H2 gas forms an uneven rough surface, that is, the N-type semiconductor layer is designed as a three-layer rough surface + three-layer porous structure material, which can reduce the in-plane total reflection of the N-type material and significantly increase the proportion of photon escape body materials in the active area, thereby improving the light extraction efficiency of the chip.

[0059] In some preferred embodiments, the first porous low-temperature GaN layer 31 is provided with a first V-shaped hole 311 penetrating the first porous low-temperature GaN layer 31. The first porous low-temperature GaN layer 31 is made of a porous GaN material with a low Si doping, and has a thickness of 5nm to 500nm, specifically 5nm, 50nm, 100nm, 200nm, 300nm, 400nm, 500nm, but not limited thereto. The Si doping concentration is 2.06×10 17 / cm 3 ~1.20×10 19 / cm 3 , specifically 2.06×10 17 / cm 3 5.00×1017 / cm 3 , 1.00×10 18 / cm 3 3.00×10 18 / cm 3 8.00×10 18 / cm 3 , 1.00×10 19 / cm 3 , 1.20×10 19 / cm 3 , but not limited thereto. The growth temperature is 850°C to 1120°C, specifically 850°C, 950°C, 1050°C, 1100°C, 1120°C, but not limited thereto. The pressure is 30 torr to 320 torr, specifically 30 torr, 100 torr, 150 torr, 200 torr, 250 torr, 300 torr, 320 torr, but not limited thereto.

[0060] The first V-shaped holes 311 in the first porous low-temperature GaN layer 31 are V-shaped and penetrate the first porous low-temperature GaN layer. There are multiple V-shaped holes with the same size and uniform arrangement in the first porous low-temperature GaN layer. The preferred range of hole density is 1.28×10 8 ~5.68×10 11 / cm 2 , specifically 1.28×10 8 , 2.0×10 9 5.0×10 9 , 2.0×10 10 5.0×10 10 , 2.0×10 11 , 5.68×10 11 / cm 2 , but not limited to this.

[0061] In some preferred embodiments, the second porous AlGaN / GaN superlattice layer 32 is a porous AlGaN / GaN superlattice material with a high Al component, which includes a second porous AlGaN layer and a second porous GaN layer stacked in sequence, and the number of alternating stacking periods is 2 to 20, specifically 2, 5, 10, 15, 20, but not limited thereto.

[0062] The second porous AlGaN layer is low-doped with Si element, and the Si doping concentration is 5.2×10 17 / cm 3 ~1.6×10 19 / cm 3 , specifically 5.2×10 17 / cm3 8.00×10 17 / cm 3 , 1.00×10 18 / cm 3 3.00×10 18 / cm 3 8.00×10 18 / cm 3 , 1.00×10 19 / cm 3 , 1.60×10 19 / cm 3 , but not limited to this. Al component 0.2≤X2≤0.8, X2 can specifically be 0.2, 0.4, 0.6, 0.8, but not limited to this. The thickness is 1.2nm~20nm, specifically 1.2nm, 5nm, 10nm, 12nm, 15nm, 18nm, 20nm, but not limited to this. The growth temperature is 900℃~1150℃, specifically 900℃, 950℃, 1050℃, 1100℃, 1150℃, but not limited to this. The pressure is 30torr~320torr, specifically 30torr, 100torr, 150torr, 200torr, 250torr, 300torr, 320torr, but not limited to this.

[0063] The second porous GaN layer is highly doped with Si element, and the Si doping concentration is 2.5×10 18 / cm 3 ~3.2×10 19 / cm 3 , specifically 2.5×10 18 / cm 3 3.00×10 18 / cm 3 8.00×10 18 / cm 3 , 1.00×10 19 / cm 3 , 1.20×10 19 / cm 3 3.20×10 19 / cm 3, but not limited thereto. The thickness is 1.2nm to 20nm, specifically 1.2nm, 5nm, 10nm, 12nm, 15nm, 18nm, 20nm, but not limited thereto. The growth temperature is 900℃ to 1150℃, specifically 900℃, 950℃, 1050℃, 1100℃, 1150℃, but not limited thereto. The pressure is 30torr to 320torr, specifically 30torr, 100torr, 150torr, 200torr, 250torr, 300torr, 320torr, but not limited thereto.

[0064] The second porous AlGaN / GaN superlattice layer is deposited on the first porous low-temperature GaN layer that has been treated with high-temperature H2 gas for the second time, forming a porous structural material with two pore sizes - a second V-shaped pore 321 and a third V-shaped pore 322. The second V-shaped pore 321 is grown on the basis of the first V-shaped pore 311, and the opening size of the second V-shaped pore 321 is larger than the opening size of the third V-shaped pore 322.

[0065] The second porous AlGaN / GaN superlattice layer has a plurality of small V-shaped holes (i.e., the third V-shaped holes 322) of the same size and uniform distribution. The density of the second V-shaped holes 321 is preferably 1.28×10 8 ~5.68×10 11 / cm 2 , specifically 1.28×10 8 5.00×10 8 / cm 3 , 1.00×10 9 / cm 3 5.00×10 9 / cm 3 , 1.20×10 10 / cm 3 5.00×10 10 / cm 3 , 5.68×10 11 / cm 2 , but not limited thereto. The density of the third V-shaped holes 322 is 2.65×10 8 ~1.85×10 12 / cm 2 , specifically 2.65×10 8 5.00×10 8 / cm 3 , 1.00×10 9 / cm 3 5.00×10 9 / cm 3, 1.20×10 10 / cm 3 5.00×10 10 / cm 3 , 1.0×10 11 / cm 2 5.0×10 11 / cm 2 , 1.85×10 12 / cm 2 , but not limited to this.

[0066] In some preferred embodiments, the third high temperature GaN layer 33 is a high temperature GaN material that is not intentionally doped, and the thickness of the third high temperature GaN layer 33 is 0.03 μm to 2 μm, specifically 0.03 μm, 0.5 μm, 0.8 μm, 1 μm, 1.2 μm, 1.5 μm, 2 μm, but not limited thereto. The growth temperature is 1050°C to 1250°C, specifically 1050°C, 1100°C, 1150°C, 1200°C, 1250°C, but not limited thereto. The pressure is 30 torr to 320 torr, specifically 30 torr, 100 torr, 150 torr, 200 torr, 250 torr, 300 torr, 320 torr, but not limited thereto.

[0067] In some preferred embodiments, the fourth porous AlGaN / GaN superlattice layer 34 is a porous AlGaN / GaN superlattice material with a low Al component, which includes a fourth porous AlGaN layer and a fourth porous GaN layer stacked in sequence, and the number of alternating stacking periods is 3 to 50, specifically 3, 10, 15, 20, 25, 30, 35, 40, 45, 50, but not limited to this.

[0068] The fourth porous AlGaN layer is low-doped with Si element, and the Si doping concentration is 8.5×10 17 / cm 3 ~1.9×10 19 / cm 3 , specifically 8.5×10 17 / cm 3 , 1.00×10 18 / cm 3 3.00×10 18 / cm 3 8.00×10 18 / cm 3 , 1.00×10 19 / cm 3 , 1.90×10 19 / cm 3, but not limited to this. Al component 0.02≤X4≤0.5, X4 can be specifically 0.02, 0.1, 0.2, 0.3, 0.4, 0.5, but not limited to this. The thickness is 2nm~30nm, specifically 2nm, 5nm, 10nm, 12nm, 15nm, 20nm, 30nm, but not limited to this. The growth temperature is 920℃~1180℃, specifically 920℃, 950℃, 1050℃, 1100℃, 1180℃, but not limited to this. The pressure is 30torr~320torr, specifically 30torr, 100torr, 150torr, 200torr, 250torr, 300torr, 320torr, but not limited to this.

[0069] The fourth porous GaN layer is highly doped with Si element, and the Si doping concentration is 3.0×10 18 / cm 3 ~3.8×10 19 / cm 3 , specifically 3.0×10 18 / cm 3 , 8.0×10 18 / cm 3 , 1.0×10 19 / cm 3 , 2.0×10 19 / cm 3 , 3.8×10 19 / cm 3 , but not limited thereto. The thickness is 2nm to 30nm, specifically 2nm, 5nm, 10nm, 12nm, 15nm, 20nm, 30nm, but not limited thereto. The growth temperature is 920℃ to 1180℃, specifically 920℃, 950℃, 1050℃, 1100℃, 1180℃, but not limited thereto. The pressure is 30torr to 320torr, specifically 30torr, 100torr, 150torr, 200torr, 250torr, 300torr, 320torr, but not limited thereto.

[0070] The fourth porous AlGaN / GaN superlattice layer 34 is deposited on the third high-temperature GaN layer 33 that has been subjected to the third high-temperature H2 gas treatment to form a porous structure material with two hole sizes: the fifth V-shaped hole 341 and the stress release hole 342. The fourth porous AlGaN / GaN superlattice layer has a plurality of stress release holes 342 with the same size and uniform distribution. The stress release hole density is preferably 5.27×10 8 ~6.87×10 12 / cm 2 .

[0071] In some preferred embodiments, the fifth high-temperature GaN layer 35 is a high-temperature GaN material highly doped with Si elements, and completely fills the fifth V-shaped hole 341 and the stress release hole 342, and serves as the main material of the N-type semiconductor layer to provide electrons to the light-emitting diode device. The Si doping concentration is 3.6×10 18 / cm 3 ~5.6×10 19 / cm 3 , specifically 3.6×10 18 / cm 3 , 8.0×10 18 / cm 3 , 1.0×10 19 / cm 3 , 3.0×10 19 / cm 3 , 5.6×10 19 / cm 3 , but not limited to this. The thickness of the fifth high-temperature GaN layer 35 is 2μm to 8μm, specifically 2μm, 3μm, 4μm, 5μm, 6μm, 7μm, 8μm, but not limited to this. The growth temperature is 1050℃ to 1250℃, specifically 900℃, 950℃, 1050℃, 1100℃, 1150℃, but not limited to this. The pressure is 30torr to 320torr, specifically 30torr, 100torr, 150torr, 200torr, 250torr, 300torr, 320torr, but not limited to this.

[0072] The first porous low-temperature GaN layer, the third high-temperature GaN layer, and the fifth high-temperature GaN layer in the N-type semiconductor layer are all GaN materials, wherein the first porous low-temperature GaN layer is low-doped with Si elements, the third high-temperature GaN layer is not intentionally doped, and the fifth high-temperature GaN layer is highly doped with Si elements.

[0073] The second porous AlGaN / GaN superlattice layer and the fourth porous AlGaN / GaN superlattice layer in the N-type semiconductor layer are both porous AlGaN / GaN superlattice materials, and the Al component of the second porous AlGaN / GaN superlattice layer is greater than that of the fourth porous AlGaN / GaN superlattice layer, that is, X2>X4.

[0074] In order to improve the luminous efficiency of light-emitting diodes, that is, to improve the internal quantum efficiency and external quantum efficiency of the device, the quality of epitaxial materials and the proportion of photon escape material in the active area are improved by optimizing the epitaxial structure and process of the light-emitting diode. The GaN-based LED epitaxial wafer of the present invention is based on the above-mentioned structure and process design of the N-type semiconductor layer, including five sublayers stacked from bottom to top, a first porous low-temperature GaN layer, a second porous AlGaN / GaN superlattice layer, a third high-temperature GaN layer, a fourth porous AlGaN / GaN superlattice layer and a fifth high-temperature GaN layer. Among them, the first porous low-temperature GaN layer, the second porous AlGaN / GaN superlattice layer, and the fourth porous AlGaN / GaN superlattice layer are all designed as porous structure materials. The design of the porous structure material is conducive to fully releasing the stress of the epitaxial layer material, which can effectively reduce the large stress on the epitaxial layer material during the growth process and improve the quality of the epitaxial layer material.

[0075] Both, before depositing the first porous low-temperature GaN layer, the second porous AlGaN / GaN superlattice layer, and the fourth porous AlGaN / GaN superlattice layer, the surface of the epitaxial layer material needs to be treated with high-temperature H2 gas, that is, the H2 and N2 mixed gas needs to be circulated and stabilized for a certain period of time. The material with poor crystallization quality on the surface of the epitaxial layer material treated with H2 gas will be decomposed, which is conducive to reducing the defect density of the epitaxial layer material and improving the crystal quality of the epitaxial layer material. At the same time, an uneven rough surface is formed, which is conducive to the subsequent deposition of the epitaxial layer material to form V-shaped holes and stress release holes of varying sizes, further fully releasing the stress of the epitaxial layer material, and reducing the defect density of the epitaxial layer material, and improving the quality of the epitaxial layer material. Moreover, the surface of the epitaxial layer material treated with H2 gas forms an uneven rough surface, that is, the N-type semiconductor layer is designed as a three-layer rough surface + three-layer porous structure material, which can reduce the in-plane total reflection of the N-type material and significantly increase the proportion of photon escape body materials in the active area, thereby improving the light extraction efficiency of the chip.

[0076] Thirdly, the third high-temperature GaN layer and the fifth high-temperature GaN layer are both high-temperature two-dimensional merged materials. In the process of completely filling the V-shaped holes and stress release holes of different sizes, some dislocation defects will be continuously deflected and merged, reducing the dislocation density of the epitaxial layer material, thereby improving the quality of the epitaxial material.

[0077] Therefore, the LED epitaxial wafer prepared by the present invention can reduce the generation of defects in the epitaxial material during the growth process, reduce the dislocation density of the material, and significantly improve the quality of the epitaxial wafer material, thereby improving the radiation recombination efficiency in the active region of the light-emitting diode, that is, the internal quantum efficiency, and at the same time can significantly increase the proportion of photon escaping body materials in the active region, that is, improve the light extraction efficiency of the chip.

[0078] Correspondingly, the present invention also discloses a method for preparing a GaN-based LED epitaxial wafer, comprising:

[0079] (1) Selecting a substrate;

[0080] (2) growing a buffer layer on the substrate;

[0081] (3) introducing a Si doping source to grow an N-type semiconductor layer on the buffer layer;

[0082] Specifically, step (3) is to deposit a first porous low-temperature GaN layer 31, a second porous AlGaN / GaN superlattice layer 32, a third high-temperature GaN layer 33, a fourth porous AlGaN / GaN superlattice layer 34, and a fifth high-temperature GaN layer 35 on the buffer layer.

[0083] Among them, before depositing the first porous low-temperature GaN layer 31, the second porous AlGaN / GaN superlattice layer 32, and the fourth porous AlGaN / GaN superlattice layer 34, the surface of the epitaxial layer material needs to be treated with high-temperature H2 gas. The temperature of the high-temperature H2 gas treatment is 1020℃~1250℃, and the pressure is 20torr~360torr.

[0084] Preferably, step (3) comprises:

[0085] Performing a first high-temperature H2 gas treatment on the surface of the buffer layer 20;

[0086] Depositing a first porous low-temperature GaN layer 31 on the surface of the buffer layer 20;

[0087] Performing a second high-temperature H2 gas treatment on the first porous low-temperature GaN layer 31;

[0088] Depositing a second porous AlGaN / GaN superlattice layer 32 on the surface of the first porous low-temperature GaN layer 31;

[0089] Depositing a third high temperature GaN layer 33 on the surface of the second porous AlGaN / GaN superlattice layer 32;

[0090] Performing a third high temperature H2 gas treatment on the surface of the third high temperature GaN layer 33;

[0091] Depositing a fourth porous AlGaN / GaN superlattice layer 34 on the surface of the third high temperature GaN layer 33;

[0092] A fifth high temperature GaN layer 35 is deposited on the surface of the fourth porous AlGaN / GaN superlattice layer 34 .

[0093] More preferably, step (3) comprises:

[0094] The first high-temperature H2 gas treatment is performed on the surface of the buffer layer 20, specifically, a H2 and N2 mixed gas is circulated, the temperature of the high-temperature H2 gas treatment is 1020° C. to 1250° C., the pressure is 20 torr to 360 torr, the H2 flow rate is 50 to 500 slm, and the treatment time is 15 to 360 s;

[0095] Depositing a first porous low-temperature GaN layer 31 on the surface of the buffer layer 20;

[0096] A second high-temperature H2 gas treatment is performed on the first porous low-temperature GaN layer 31, specifically, a H2 and N2 mixed gas is circulated, the temperature of the high-temperature H2 gas treatment is 1020°C to 1250°C, the pressure is 20torr to 360torr, the H2 flow rate is 30 to 390slm, and the treatment time is 10 to 240s;

[0097] Depositing a second porous AlGaN / GaN superlattice layer 32 on the surface of the first porous low-temperature GaN layer 31;

[0098] Depositing a third high temperature GaN layer 33 on the surface of the second porous AlGaN / GaN superlattice layer 32;

[0099] A third high-temperature H2 gas treatment is performed on the surface of the third high-temperature GaN layer 33, specifically, a H2 and N2 mixed gas is circulated, the temperature of the high-temperature H2 gas treatment is 1020° C. to 1250° C., the pressure is 20 torr to 360 torr, the H2 flow rate is 20 to 350 slm, and the treatment time is 5 to 120 s;

[0100] Depositing a fourth porous AlGaN / GaN superlattice layer 34 on the surface of the third high temperature GaN layer 33;

[0101] A fifth high temperature GaN layer 35 is deposited on the surface of the fourth porous AlGaN / GaN superlattice layer 34 .

[0102] (4) growing a low-temperature stress release layer on the N-type semiconductor layer;

[0103] (5) growing a multi-quantum well light-emitting layer on the low-temperature stress release layer;

[0104] (6) growing an electron blocking layer on the multi-quantum well light-emitting layer;

[0105] (7) Growing a P-type semiconductor layer on the electron blocking layer.

[0106] In the preparation method provided by the present invention, before depositing the first porous low-temperature GaN layer, the second porous AlGaN / GaN superlattice layer, and the fourth porous AlGaN / GaN superlattice layer, the surface of the epitaxial layer material needs to be treated with high-temperature H2 gas. After three high-temperature H2 gas treatments, the material with poor crystallization quality on the surface of the epitaxial layer material will be decomposed, which is conducive to reducing the defect density of the epitaxial layer material and improving the crystal quality of the epitaxial layer material. At the same time, an uneven rough surface is formed, which is conducive to the subsequent deposition of the epitaxial layer material to form V-shaped holes and stress release holes of varying sizes, further fully releasing the stress of the epitaxial layer material, and reducing the defect density of the epitaxial layer material, and improving the quality of the epitaxial layer material. Moreover, the surface of the epitaxial layer material treated with H2 gas forms an uneven rough surface, that is, the N-type semiconductor layer is designed as a three-layer rough surface + three-layer porous structure material, which can reduce the in-plane total reflection of the N-type material, significantly increase the proportion of photon escape body materials in the active area, and thus improve the light extraction efficiency of the chip.

[0107] The present invention is further described below with examples

[0108] Example 1

[0109] The GaN-based LED epitaxial wafer includes: a substrate, a buffer layer, an N-type semiconductor layer, a stress release layer, a multi-quantum well light-emitting layer, an electron blocking layer and a P-type semiconductor layer; wherein the N-type semiconductor layer includes in sequence: a first porous low-temperature GaN layer, a second porous AlGaN / GaN superlattice layer, a third high-temperature GaN layer, a fourth porous AlGaN / GaN superlattice layer, and a fifth high-temperature GaN layer; wherein,

[0110] The first porous low-temperature GaN layer is provided with a first V-shaped hole penetrating the first porous low-temperature GaN layer. The first porous low-temperature GaN layer is a porous GaN material low-doped with Si elements, with a thickness of 50 nm and a Si doping concentration of 2.06×10 17 / cm 3 , the growth temperature is 850℃ and the pressure is 30torr;

[0111] The second porous AlGaN / GaN superlattice layer is provided with a second V-shaped hole and a third V-shaped hole, the second V-shaped hole is grown on the basis of the first V-shaped hole, and the opening size of the second V-shaped hole is larger than the opening size of the third V-shaped hole, wherein the second porous AlGaN / GaN superlattice layer comprises a second porous AlGaN layer and a second porous GaN layer stacked in sequence, and the number of alternating stacking cycles is 10; the second porous AlGaN layer is low-doped with Si element, and the Si doping concentration is 5.2×10 17 / cm 3, Al component is 0.4, thickness is 5nm, growth temperature is 900℃, pressure is 30torr; the second porous GaN layer is highly doped with Si element, Si doping concentration is 2.5×10 18 / cm 3 , thickness is 5nm, growth temperature is 900℃, pressure is 30torr;

[0112] The third high temperature GaN layer completely fills the third V-shaped hole and is provided with a fourth V-shaped hole, the fourth V-shaped hole is grown on the basis of the second V-shaped hole, the thickness of the third high temperature GaN layer 33 is 0.03 μm, the growth temperature is 1050° C., and the pressure is 30 torr;

[0113] The fourth porous AlGaN / GaN superlattice layer is deposited on the third high-temperature GaN layer to form a fifth V-shaped hole and a stress release hole. The fifth V-shaped hole is grown on the basis of the fourth V-shaped hole. The fourth porous AlGaN / GaN superlattice layer includes a fourth porous AlGaN layer and a fourth porous GaN layer stacked in sequence, and the number of alternating stacking cycles is 12. The fourth porous AlGaN layer is low-doped with Si element, and the Si doping concentration is 8.5×10 17 / cm 3 , Al component is 0.1, thickness is 2nm, growth temperature is 920℃, pressure is 30torr; the fourth porous GaN layer is highly doped with Si element, Si doping concentration is 3.0×10 18 / cm 3 , thickness is 2nm, growth temperature is 920℃, and pressure is 30torr.

[0114] The fifth high temperature GaN layer completely fills the fifth V-shaped hole and the stress release hole, and the Si doping concentration is 3.6×10 18 / cm 3 , thickness is 2μm, growth temperature is 1050℃, and pressure is 30torr.

[0115] Wherein, the preparation method of the N-type semiconductor layer is as follows:

[0116] The first high-temperature H2 gas treatment is performed on the surface of the buffer layer, specifically, a H2 and N2 mixed gas is circulated, the temperature of the high-temperature H2 gas treatment is 1020°C, the pressure is 20 torr, the H2 flow rate is 50 slm, and the treatment time is 15 s;

[0117] Depositing a first porous low-temperature GaN layer on the surface of the buffer layer;

[0118] The first porous low-temperature GaN layer is subjected to a second high-temperature H2 gas treatment, specifically, a H2 and N2 mixed gas is circulated, the temperature of the high-temperature H2 gas treatment is 1020°C, the pressure is 20 torr, the H2 flow rate is 30 slm, and the treatment time is 10 s;

[0119] Depositing a second porous AlGaN / GaN superlattice layer on the surface of the first porous low-temperature GaN layer;

[0120] Depositing a third high temperature GaN layer on the surface of the second porous AlGaN / GaN superlattice layer;

[0121] The third high temperature H2 gas treatment is performed on the surface of the third high temperature GaN layer, specifically, a H2 and N2 mixed gas is circulated, the temperature of the high temperature H2 gas treatment is 1020° C., the pressure is 20 torr, the H2 flow rate is 20 slm, and the treatment time is 5 s;

[0122] depositing a fourth porous AlGaN / GaN superlattice layer on the surface of the third high temperature GaN layer;

[0123] A fifth high temperature GaN layer is deposited on the surface of the fourth porous AlGaN / GaN superlattice layer.

[0124] Example 2

[0125] The GaN-based LED epitaxial wafer includes: a substrate, a buffer layer, an N-type semiconductor layer, a stress release layer, a multi-quantum well light-emitting layer, an electron blocking layer and a P-type semiconductor layer; wherein the N-type semiconductor layer includes in sequence: a first porous low-temperature GaN layer, a second porous AlGaN / GaN superlattice layer, a third high-temperature GaN layer, a fourth porous AlGaN / GaN superlattice layer, and a fifth high-temperature GaN layer; wherein,

[0126] The first porous low-temperature GaN layer is provided with a first V-shaped hole penetrating the first porous low-temperature GaN layer. The first porous low-temperature GaN layer is a porous GaN material low-doped with Si elements, with a thickness of 100 nm and a Si doping concentration of 1.0×10 18 / cm 3 , the growth temperature is 1000℃ and the pressure is 200torr;

[0127] The second porous AlGaN / GaN superlattice layer is provided with a second V-shaped hole and a third V-shaped hole, the second V-shaped hole is grown on the basis of the first V-shaped hole, and the opening size of the second V-shaped hole is larger than the opening size of the third V-shaped hole, wherein the second porous AlGaN / GaN superlattice layer comprises a second porous AlGaN layer and a second porous GaN layer stacked in sequence, and the number of alternating stacking cycles is 2 to 20; the second porous AlGaN layer is low-doped with Si element, and the Si doping concentration is 2.0×10 18 / cm 3 , Al component is 0.6, thickness is 10nm, growth temperature is 1000℃, pressure is 200torr; the second porous GaN layer is highly doped with Si element, Si doping concentration is 6.0×10 18 / cm 3 , thickness is 10nm, growth temperature is 1000℃, pressure is 200torr;

[0128] The third high temperature GaN layer completely fills the third V-shaped hole and is provided with a fourth V-shaped hole, the fourth V-shaped hole is grown on the basis of the second V-shaped hole, the thickness of the third high temperature GaN layer 33 is 1 μm, the growth temperature is 1100° C., and the pressure is 200 torr;

[0129] The fourth porous AlGaN / GaN superlattice layer is deposited on the third high-temperature GaN layer to form a fifth V-shaped hole and a stress release hole. The fifth V-shaped hole is grown on the basis of the fourth V-shaped hole. The fourth porous AlGaN / GaN superlattice layer includes a fourth porous AlGaN layer and a fourth porous GaN layer stacked in sequence, and the number of alternating stacking cycles is 30. The fourth porous AlGaN layer is low-doped with Si element, and the Si doping concentration is 2.5×10 18 / cm 3 , Al component is 0.2, thickness is 20nm, growth temperature is 1050℃, pressure is 200orr; the fourth porous GaN layer is highly doped with Si element, Si doping concentration is 9.0×10 18 / cm 3 , thickness is 20nm, growth temperature is 1050℃, and pressure is 200torr.

[0130] The fifth high temperature GaN layer completely fills the fifth V-shaped hole and the stress release hole, and the Si doping concentration is 7.2×10 18 / cm 3 , thickness is 5μm, growth temperature is 1150℃, and pressure is 200torr.

[0131] Wherein, the preparation method of the N-type semiconductor layer is as follows:

[0132] The first high-temperature H2 gas treatment is performed on the surface of the buffer layer, specifically, a H2 and N2 mixed gas is circulated, the temperature of the high-temperature H2 gas treatment is 1150°C, the pressure is 200 orr, the H2 flow rate is 300 slm, and the treatment time is 250 s;

[0133] Depositing a first porous low-temperature GaN layer on the surface of the buffer layer;

[0134] A second high-temperature H2 gas treatment is performed on the first porous low-temperature GaN layer, specifically, a H2 and N2 mixed gas is circulated, the temperature of the high-temperature H2 gas treatment is 1150°C, the pressure is 200 torr, the H2 flow rate is 200 slm, and the treatment time is 150 s;

[0135] Depositing a second porous AlGaN / GaN superlattice layer on the surface of the first porous low-temperature GaN layer;

[0136] Depositing a third high temperature GaN layer on the surface of the second porous AlGaN / GaN superlattice layer;

[0137] A third high-temperature H2 gas treatment is performed on the surface of the third high-temperature GaN layer, specifically, a H2 and N2 mixed gas is circulated, the temperature of the high-temperature H2 gas treatment is 1150° C., the pressure is 200 torr, the H2 flow rate is 100 slm, and the treatment time is 50 s;

[0138] depositing a fourth porous AlGaN / GaN superlattice layer on the surface of the third high temperature GaN layer;

[0139] A fifth high temperature GaN layer is deposited on the surface of the fourth porous AlGaN / GaN superlattice layer.

[0140] Example 3

[0141] The GaN-based LED epitaxial wafer includes: a substrate, a buffer layer, an N-type semiconductor layer, a stress release layer, a multi-quantum well light-emitting layer, an electron blocking layer and a P-type semiconductor layer; wherein the N-type semiconductor layer includes in sequence: a first porous low-temperature GaN layer, a second porous AlGaN / GaN superlattice layer, a third high-temperature GaN layer, a fourth porous AlGaN / GaN superlattice layer, and a fifth high-temperature GaN layer; wherein,

[0142] The first porous low-temperature GaN layer is provided with a first V-shaped hole penetrating the first porous low-temperature GaN layer. The first porous low-temperature GaN layer is a porous GaN material low-doped with Si elements, with a thickness of 500 nm and a Si doping concentration of 1.2×10 19 / cm 3 , the growth temperature is 1120℃ and the pressure is 320torr;

[0143] The second porous AlGaN / GaN superlattice layer is provided with a second V-shaped hole and a third V-shaped hole, the second V-shaped hole is grown on the basis of the first V-shaped hole, and the opening size of the second V-shaped hole is larger than the opening size of the third V-shaped hole, wherein the second porous AlGaN / GaN superlattice layer comprises a second porous AlGaN layer and a second porous GaN layer stacked in sequence, and the number of alternating stacking cycles is 20; the second porous AlGaN layer is low-doped with Si element, and the Si doping concentration is 1.6×10 19 / cm 3 , Al component is 0.8, thickness is 20nm, growth temperature is 1150℃, pressure is 320torr; the second porous GaN layer is highly doped with Si element, Si doping concentration is .2×10 19 / cm 3 , thickness is 20nm, growth temperature is 1150℃, pressure is 320torr;

[0144] The third high temperature GaN layer completely fills the third V-shaped hole and is provided with a fourth V-shaped hole, the fourth V-shaped hole is grown on the basis of the second V-shaped hole, the thickness of the third high temperature GaN layer 33 is 2 μm, the growth temperature is 1250° C., and the pressure is 320 torr;

[0145] The fourth porous AlGaN / GaN superlattice layer is deposited on the third high-temperature GaN layer to form a fifth V-shaped hole and a stress release hole. The fifth V-shaped hole is grown on the basis of the fourth V-shaped hole. The fourth porous AlGaN / GaN superlattice layer includes a fourth porous AlGaN layer and a fourth porous GaN layer stacked in sequence, and the number of alternating stacking cycles is 50. The fourth porous AlGaN layer is low-doped with Si element, and the Si doping concentration is 1.9×10 19 / cm 3 , Al component is 0.5, thickness is 30nm, growth temperature is 1180℃, pressure is 320torr; the fourth porous GaN layer is highly doped with Si element, Si doping concentration is 3.8×10 19 / cm 3 , thickness is 30nm, growth temperature is 1180℃, and pressure is 320torr.

[0146] The fifth high temperature GaN layer completely fills the fifth V-shaped hole and the stress release hole, and the Si doping concentration is 5.6×10 19 / cm 3 , thickness is 8μm, growth temperature is 1250℃, and pressure is 320torr.

[0147] Wherein, the preparation method of the N-type semiconductor layer is as follows:

[0148] The first high-temperature H2 gas treatment is performed on the surface of the buffer layer, specifically, a H2 and N2 mixed gas is circulated, the temperature of the high-temperature H2 gas treatment is 1250°C, the pressure is 360 torr, the H2 flow rate is 500 slm, and the treatment time is 360 s;

[0149] Depositing a first porous low-temperature GaN layer on the surface of the buffer layer;

[0150] The second high-temperature H2 gas treatment is performed on the first porous low-temperature GaN layer, specifically, a H2 and N2 mixed gas is circulated, the temperature of the high-temperature H2 gas treatment is 1250°C, the pressure is 360torr, the H2 flow rate is 390slm, and the treatment time is 240s;

[0151] Depositing a second porous AlGaN / GaN superlattice layer on the surface of the first porous low-temperature GaN layer;

[0152] Depositing a third high temperature GaN layer on the surface of the second porous AlGaN / GaN superlattice layer;

[0153] The third high temperature H2 gas treatment is performed on the surface of the third high temperature GaN layer, specifically, a H2 and N2 mixed gas is circulated, the temperature of the high temperature H2 gas treatment is 1250°C, the pressure is 360torr, the H2 flow rate is 350slm, and the treatment time is 120s;

[0154] depositing a fourth porous AlGaN / GaN superlattice layer on the surface of the third high temperature GaN layer;

[0155] A fifth high temperature GaN layer is deposited on the surface of the fourth porous AlGaN / GaN superlattice layer.

[0156] Comparative Example 1

[0157] Different from Example 2, the preparation method of the N-type semiconductor layer in Comparative Example 1 is as follows:

[0158] Depositing a first porous low-temperature GaN layer on the surface of the buffer layer;

[0159] Depositing a second porous AlGaN / GaN superlattice layer on the surface of the first porous low-temperature GaN layer;

[0160] Depositing a third high temperature GaN layer on the surface of the second porous AlGaN / GaN superlattice layer;

[0161] depositing a fourth porous AlGaN / GaN superlattice layer on the surface of the third high temperature GaN layer;

[0162] A fifth high temperature GaN layer is deposited on the surface of the fourth porous AlGaN / GaN superlattice layer.

[0163] Comparative Example 2

[0164] Different from Example 2, the preparation method of the N-type semiconductor layer in Comparative Example 2 is as follows:

[0165] The first high-temperature H2 gas treatment is performed on the surface of the buffer layer, specifically, a H2 and N2 mixed gas is circulated, the temperature of the high-temperature H2 gas treatment is 1150°C, the pressure is 200 orr, the H2 flow rate is 300 slm, and the treatment time is 250 s;

[0166] Depositing a first porous low-temperature GaN layer on the surface of the buffer layer;

[0167] Depositing a second porous AlGaN / GaN superlattice layer on the surface of the first porous low-temperature GaN layer;

[0168] Depositing a third high temperature GaN layer on the surface of the second porous AlGaN / GaN superlattice layer;

[0169] depositing a fourth porous AlGaN / GaN superlattice layer on the surface of the third high temperature GaN layer;

[0170] A fifth high temperature GaN layer is deposited on the surface of the fourth porous AlGaN / GaN superlattice layer.

[0171] Comparative Example 3

[0172] Different from Example 2, the preparation method of the N-type semiconductor layer in Comparative Example 3 is as follows:

[0173] Depositing a first porous low-temperature GaN layer on the surface of the buffer layer;

[0174] The first porous low-temperature GaN layer is subjected to the first high-temperature H2 gas treatment, specifically, a H2 and N2 mixed gas is circulated, the temperature of the high-temperature H2 gas treatment is 1150°C, the pressure is 200 torr, the H2 flow rate is 200 slm, and the treatment time is 150 s;

[0175] Depositing a second porous AlGaN / GaN superlattice layer on the surface of the first porous low-temperature GaN layer;

[0176] Depositing a third high temperature GaN layer on the surface of the second porous AlGaN / GaN superlattice layer;

[0177] depositing a fourth porous AlGaN / GaN superlattice layer on the surface of the third high temperature GaN layer;

[0178] A fifth high temperature GaN layer is deposited on the surface of the fourth porous AlGaN / GaN superlattice layer.

[0179] Comparative Example 4

[0180] Different from Example 2, the preparation method of the N-type semiconductor layer in Comparative Example 4 is as follows:

[0181] Depositing a first porous low-temperature GaN layer on the surface of the buffer layer;

[0182] Depositing a second porous AlGaN / GaN superlattice layer on the surface of the first porous low-temperature GaN layer;

[0183] Depositing a third high temperature GaN layer on the surface of the second porous AlGaN / GaN superlattice layer;

[0184] The first high-temperature H2 gas treatment is performed on the surface of the third high-temperature GaN layer, specifically, a H2 and N2 mixed gas is circulated, the temperature of the high-temperature H2 gas treatment is 1150° C., the pressure is 200 torr, the H2 flow rate is 100 slm, and the treatment time is 50 s;

[0185] depositing a fourth porous AlGaN / GaN superlattice layer on the surface of the third high temperature GaN layer;

[0186] A fifth high temperature GaN layer is deposited on the surface of the fourth porous AlGaN / GaN superlattice layer.

[0187] Comparative Example 5

[0188] Different from Example 2, the preparation method of the N-type semiconductor layer in Comparative Example 5 is as follows:

[0189] The first high-temperature H2 gas treatment is performed on the surface of the buffer layer, specifically, a H2 and N2 mixed gas is circulated, the temperature of the high-temperature H2 gas treatment is 1150°C, the pressure is 200 orr, the H2 flow rate is 300 slm, and the treatment time is 250 s;

[0190] Depositing a first porous low-temperature GaN layer on the surface of the buffer layer;

[0191] A second high-temperature H2 gas treatment is performed on the first porous low-temperature GaN layer, specifically, a H2 and N2 mixed gas is circulated, the temperature of the high-temperature H2 gas treatment is 1150°C, the pressure is 200 torr, the H2 flow rate is 200 slm, and the treatment time is 150 s;

[0192] Depositing a second porous AlGaN / GaN superlattice layer on the surface of the first porous low-temperature GaN layer;

[0193] Depositing a third high temperature GaN layer on the surface of the second porous AlGaN / GaN superlattice layer;

[0194] depositing a fourth porous AlGaN / GaN superlattice layer on the surface of the third high temperature GaN layer;

[0195] A fifth high temperature GaN layer is deposited on the surface of the fourth porous AlGaN / GaN superlattice layer.

[0196] Examples 1 to 3 and Comparative Examples 1 to 5 were used to prepare light emitting diode epitaxial wafers, and 3mil×5mil chips were prepared using the same chip process conditions. 300 LED chips were extracted and tested at 3mA current. Comparative Example 1 was used as a reference to calculate the luminous efficiency improvement rate of each example and comparative example. The specific test results are shown in Table 1:

[0197]

[0198]

[0199] In summary, the LED epitaxial wafer of the present invention can reduce the generation of defects in the epitaxial material during the growth process, reduce the dislocation density of the material, and significantly improve the quality of the epitaxial wafer material, thereby improving the radiation recombination efficiency in the active area of ​​the light-emitting diode. At the same time, it can significantly increase the proportion of photon escaping body materials in the active area, that is, improve the light extraction efficiency of the chip.

[0200] The above is a preferred embodiment of the present invention. It should be noted that, for those skilled in the art, several improvements and modifications can be made without departing from the principle of the present invention, and these improvements and modifications are also considered to be within the protection scope of the present invention.

Claims

1. A GaN-based LED epitaxial wafer, characterized in that: include: Substrate, buffer layer, N-type semiconductor layer, stress release layer, multi-quantum well light-emitting layer, electron blocking layer and P-type semiconductor layer; The N-type semiconductor layer includes, in sequence: a first porous low-temperature GaN layer, a second porous AlGaN / GaN superlattice layer, a third high-temperature GaN layer, a fourth porous AlGaN / GaN superlattice layer, and a fifth high-temperature GaN layer; The first porous low-temperature GaN layer is provided with a first V-shaped hole penetrating through the first porous low-temperature GaN layer; The second porous AlGaN / GaN superlattice layer is provided with a second V-shaped hole and a third V-shaped hole, the second V-shaped hole is grown on the basis of the first V-shaped hole, and the opening size of the second V-shaped hole is larger than the opening size of the third V-shaped hole; The third high-temperature GaN layer completely fills the third V-shaped hole and is provided with a fourth V-shaped hole, wherein the fourth V-shaped hole is grown on the basis of the second V-shaped hole; The fourth porous AlGaN / GaN superlattice layer is deposited on the third high-temperature GaN layer to form a fifth V-shaped hole and a stress release hole, wherein the fifth V-shaped hole is grown on the basis of the fourth V-shaped hole; The fifth high temperature GaN layer completely fills the fifth V-shaped hole and the stress release hole.

2. The GaN-based LED epitaxial wafer according to claim 1, characterized in that: Before depositing the first porous low-temperature GaN layer, the second porous AlGaN / GaN superlattice layer, and the fourth porous AlGaN / GaN superlattice layer, the surface of the epitaxial layer material needs to be treated with high-temperature H2 gas. The temperature of the high-temperature H2 gas treatment is 1020℃~1250℃, and the pressure is 20torr~360torr.

3. The GaN-based LED epitaxial wafer according to claim 2, characterized in that: Before depositing the first porous low-temperature GaN layer, a first high-temperature H2 gas treatment is performed, wherein the H2 flow rate of the first high-temperature H2 gas treatment is 50 to 500 slm and the treatment time is 15 to 360 s; Before depositing the second porous AlGaN / GaN superlattice layer, performing a second high-temperature H2 gas treatment, wherein the H2 flow rate of the second high-temperature H2 gas treatment is 30 to 390 slm and the treatment time is 10 to 240 s; Before depositing the fourth porous AlGaN / GaN superlattice layer, a third high-temperature H2 gas treatment is performed, wherein the H2 flow rate of the third high-temperature H2 gas treatment is 20 to 350 slm, and the treatment time is 5 to 120 s.

4. The GaN-based LED epitaxial wafer according to claim 1, characterized in that: The first porous low-temperature GaN layer is a porous GaN material doped with Si element at low level, with a thickness of 5nm to 500nm and a Si doping concentration of 2.06×10 17 / cm 3 ~1.2×10 19 / cm 3 The growth temperature is 850℃~1120℃, and the pressure is 30torr~320torr.

5. The GaN-based LED epitaxial wafer according to claim 1, characterized in that: The density of the second V-shaped holes is 1.28×10 8 ~5.68×10 11 / cm 2 ; The density of the third V-shaped holes is 2.65×10 8 ~1.85×10 12 / cm 2 .

6. The GaN-based LED epitaxial wafer according to claim 1, characterized in that: The second porous AlGaN / GaN superlattice layer comprises a second porous AlGaN layer and a second porous GaN layer stacked in sequence, and the number of alternating stacking cycles is 2 to 20; The second porous AlGaN layer is low-doped with Si element, and the Si doping concentration is 5.2×10 17 / cm 3 ~1.6×10 19 / cm 3 , Al component 0.2≤X2≤0.8, thickness 1.2nm~20nm, growth temperature 900℃~1150℃, pressure 30torr~320torr; The second porous GaN layer is highly doped with Si element, and the Si doping concentration is 2.5×10 18 / cm 3 ~3.2×10 19 / cm 3 , thickness is 1.2nm~20nm, growth temperature is 900℃~1150℃, and pressure is 30torr~320torr.

7. The GaN-based LED epitaxial wafer according to claim 1, characterized in that: The third high temperature GaN layer is a high temperature GaN material that is not intentionally doped, has a thickness of 0.03 μm to 2 μm, a growth temperature of 1050° C. to 1250° C., and a pressure of 30 torr to 320 torr.

8. The GaN-based LED epitaxial wafer according to claim 1, characterized in that: The fourth porous AlGaN / GaN superlattice layer comprises a fourth porous AlGaN layer and a fourth porous GaN layer stacked in sequence, and the number of alternating stacking cycles is 3 to 50; The fourth porous AlGaN layer is low-doped with Si element, and the Si doping concentration is 8.5×10 17 / cm 3 ~1.9×10 19 / cm 3 , Al component 0.02≤X4≤0.5, thickness 2nm~30nm, growth temperature 920℃~1180℃, pressure 30torr~320torr; The fourth porous GaN layer is highly doped with Si element, and the Si doping concentration is 3.0×10 18 / cm 3 ~3.8×10 19 / cm 3 , thickness is 2nm~30nm, growth temperature is 920℃~1180℃, and pressure is 30torr~320torr.

9. The GaN-based LED epitaxial wafer according to claim 1, characterized in that: The fifth high temperature GaN layer is a high temperature GaN material highly doped with Si elements, and the Si doping concentration is 3.6×10 18 / cm 3 ~5.6×10 19 / cm 3 The thickness of the fifth high-temperature GaN layer is 2 μm to 8 μm, the growth temperature is 1050° C. to 1250° C., and the pressure is 30 torr to 320 torr.

10. The method for preparing a GaN-based LED epitaxial wafer according to any one of claims 1 to 9, characterized in that: include: Selecting a substrate; growing a buffer layer on the substrate; A Si doping source is introduced to grow an N-type semiconductor layer on the buffer layer; Growing a low-temperature stress release layer on the N-type semiconductor layer; Growing a multi-quantum well light-emitting layer on the low-temperature stress release layer; Growing an electron blocking layer on the multi-quantum well light-emitting layer; Growing a P-type semiconductor layer on the electron blocking layer; Among them, the N-type semiconductor layer includes, from bottom to top, a first porous low-temperature GaN layer, a second porous AlGaN / GaN superlattice layer, a third high-temperature GaN layer, a fourth porous AlGaN / GaN superlattice layer, and a fifth high-temperature GaN layer; before depositing the first porous low-temperature GaN layer, the second porous AlGaN / GaN superlattice layer, and the fourth porous AlGaN / GaN superlattice layer, the surface of the epitaxial layer material needs to be treated with high-temperature H2 gas, and the temperature of the high-temperature H2 gas treatment is 1020°C to 1250°C, and the pressure is 20torr to 360torr.

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