Systems and methods for graphene-based layer transfer

Abstract

A graphene-based layer transfer (GBLT) technique is disclosed. In this method, a device layer comprising a III-V semiconductor, Si, Ge, III-N semiconductor, SiC, SiGe or II-VI semiconductor is produced on a graphene layer, which in turn is disposed on a substrate. The graphene layer or the substrate may be lattice matched with the device layer to reduce defects in the device layer. The fabricated device layer may then be removed from the substrate by, for example, a stressor attached to the device layer. In GBLT, the graphene layer acts as a reusable and versatile platform for growth equipment layers, and also acts as a release layer that allows rapid, accurate, and repeatable release at the graphene surface.

Description

[0001] This application is a divisional application of the invention patent application with application date of September 8, 2016, application number 201680059078.8, and invention name “System and method for graphene-based layer transfer”.

[0002] CROSS-REFERENCE TO RELATED APPLICATIONS

[0003] This application claims the benefit of priority under 35 U.S.C. §119(e) to U.S. Application No. 62 / 215,223, filed on September 8, 2015, entitled “GRAPHENE-BASEDLAYER TRANSFER PROCESS FOR ADVANCED COST-EFFICIENT ELECTRONICS / PHOTONICS,” the entire contents of which are hereby incorporated by reference herein.

[0004] This application also claims the benefit of priority under 35 U.S.C. §119(e) to U.S. Application No. 62 / 335,784, filed on May 13, 2016, entitled “DISLOCATION-FREE III-V INTEGRATION ON A SI WAFER,” the entire contents of which are hereby incorporated by reference herein.

[0005] This application claims the benefit of priority under 35 U.S.C. §119(e) to U.S. Application No. 62 / 361,717, filed on July 13, 2016, entitled “COST-EFFECTIVE LAYER-TRANSFER TECHNIQUE FOR ALL ELECTRONIC / PHOTONIC / MAGNETIC MATERIALS,” the entire contents of which are hereby incorporated by reference herein. Background of the Invention

[0007] In advanced electronic and photonic technologies, devices are typically made of functional semiconductors, such as III-N semiconductors, III-V semiconductors, II-VI semiconductors, and Ge, etc. The lattice constants of these functional semiconductors are typically mismatched with the lattice constants of silicon substrates. As understood in the art, the lattice constant mismatch between the substrate and the epitaxial layer on the substrate can introduce strain into the epitaxial layer, thereby preventing the epitaxial growth of thicker layers from being defect-free. Therefore, non-silicon substrates are typically used as seeds for epitaxial growth of most functional semiconductors. However, non-Si substrates whose lattice constants match those of the functional materials may be expensive, thus limiting the development of non-Si electronic / photonic devices.

[0008] One approach to addressing the high cost of non-silicon substrates is a "layer transfer" technique, in which a functional device layer is grown on a lattice-matched substrate, which is then removed and transferred to a different substrate. The remaining lattice-matched substrate can then be reused to fabricate another device layer, reducing costs. To significantly reduce manufacturing costs, the following properties of a layer transfer approach may be required: 1) substrate reusability; 2) minimal substrate refurbishment steps after layer release; 3) fast release rates; and 4) precise control of release thickness.

[0009] Conventional methods for removing and transferring device layers from lattice-matched substrates include chemical exfoliation (also known as epitaxial lift-off or ELO), optical exfoliation (also known as laser lift-off or LLO), and mechanical exfoliation (also known as controlled exfoliation). Unfortunately, none of these methods possess all four desired properties simultaneously.

[0010] Chemical lift-off techniques can be used to lift off device layers made of III-V semiconductors from GaAs wafers. A sacrificial layer of AlAs is usually epitaxially inserted between the device layer and the substrate. Chemical lift-off techniques selectively etch the sacrificial layer in a wet chemical solution to release the device layer.

[0011] Despite its continued development over the past three decades, chemical stripping still has several disadvantages. For example, the release rate is slow (e.g., a single 8-inch wafer is typically released over several days) due to the slow penetration of the chemical etchant through the sacrificial layer. Second, the etch residues tend to become surface contamination after release. Third, chemical stripping has limited reusability due to the chemical mechanical planarization (CMP) performed after release to restore the rough substrate surface to an epitaxial-ready surface. Fourth, processing the released epitaxial layer in a chemical solution can be challenging.

[0012] Optical lift-off technology typically uses a high-power laser to irradiate the back side of a lattice-matched substrate (e.g., a transparent sapphire or SiC substrate) and selectively heat the device-substrate interface, thereby causing decomposition of the interface and release of the device layer (e.g., III-N film). This technology can reduce the cost of manufacturing III-N-based light-emitting diodes (LEDs) and solve the heat accumulation problem of the device by transferring the released III-N to a substrate with high thermal conductivity.

[0013] However, optical lift-off has its own limitations. First, because the melted III-N / substrate interface roughens the substrate, a repair step is usually performed before reuse, reducing reusability by a factor of less than five. Second, local stressing at the interface caused by high-power thermal radiation can induce cracks or dislocations. Third, laser scanning speeds can be too slow to achieve high throughput.

[0014] Compared to optical exfoliation, controlled exfoliation can have a higher throughput. In this technique, a high stress film (also called a "stressor") is deposited on the epitaxial film, inducing fractures in the underlying epitaxial layer and resulting in separation of the active material from the substrate. When sufficient tensile stress is applied to the interface, K II Shear mode can initiate cracks, and K I The open mode allows the crack to propagate parallel to the interface between the epitaxial layer and the substrate. By controlling the internal stress and thickness of the stressor, it is possible to provide enough stress to reach the critical K I The strain energy of the film / substrate interface is generated, resulting in fracture of the film / substrate interface. Because spalling occurs through crack propagation, the spalling process can cause rapid release of the film.

[0015] However, controlled exfoliation is not mature enough for commercial manufacturing for at least the following reasons. First, because crack propagation usually occurs through a cleavage plane that is not always aligned perpendicular to the surface, the surface may need to be polished for reuse. Second, thick stressors are usually used to provide enough energy to separate strong covalent bonds, especially when used with high Young's modulus materials such as III-N semiconductors. Third, the internal stress of the stressor may only be controlled within a narrow range, which limits the obtainable thickness of the resulting exfoliated film. For example, because the maximum internal stress in a typical Ni stressor is about 1 GPa, the critical Ni thickness under 1 GPa tensile stress that triggers GaAs film exfoliation is about 1.5 μm, and if the GaAs film is about 10 μm thick, then the exfoliation of the GaAs film itself can be induced. Therefore, when using Ni stressors, it may be challenging to make GaAs films with a thickness less than 10 μm, but most devices usually use much thinner films. Summary of the invention

[0016] Embodiments of the present invention include apparatus, systems, and methods for nanofabrication. In one example, a method for manufacturing a semiconductor device includes forming a graphene layer on a first substrate, and transferring the graphene layer from the first substrate to a second substrate. The method also includes forming a single crystal film on the graphene layer.

[0017] In another example, a semiconductor processing method includes forming a graphene monolayer on a silicon carbide substrate, and transferring the graphene monolayer from the silicon carbide substrate to a semiconductor substrate. The method also includes forming a plurality of holes in the graphene monolayer, and forming a first single crystalline layer of semiconductor material on the graphene monolayer. The semiconductor substrate acts as a seed for the first single crystalline layer of semiconductor material. The method also includes removing the first single crystalline layer of semiconductor material from the graphene monolayer, and forming a second single crystalline layer of semiconductor material on the graphene monolayer. The semiconductor substrate acts as a seed for the second single crystalline layer of semiconductor material. The method also includes removing the second single crystalline layer of semiconductor material from the graphene monolayer.

[0018] In yet another example, a semiconductor processing method includes forming a graphene layer on a first substrate, and transferring the graphene layer from the first substrate to a second substrate. The method also includes depositing a semiconductor layer on the graphene layer, and depositing a stressor layer on the semiconductor layer. The stressor layer causes crack propagation between the semiconductor layer and the graphene layer. The method also includes placing a flexible tape on the stressor layer, and pulling the semiconductor layer and the stressor layer away from the graphene layer with the flexible tape.

[0019] It should be understood that all combinations of the aforementioned concepts and additional concepts discussed in more detail below (assuming these concepts are not mutually contradictory) are considered to be part of the inventive subject matter disclosed herein. Specifically, all combinations of the claimed subject matter appearing at the end of this disclosure are considered to be part of the inventive subject matter disclosed herein. It should also be understood that the terms explicitly adopted herein that may also appear in any disclosure incorporated by reference should be given the meaning most consistent with the specific concepts disclosed herein.

[0020] Description of the drawings

[0021] Those skilled in the art will appreciate that the drawings are primarily for illustrative purposes and are not intended to limit the scope of the inventive subject matter described herein. The drawings are not necessarily drawn to scale; in some cases, various aspects of the inventive subject matter disclosed herein may be exaggerated or enlarged in the drawings to facilitate understanding of different feature structures. In the drawings, the same reference numerals generally refer to the same feature structures (e.g., functionally similar and / or structurally similar elements).

[0022] Figures 1A-1D A method for fabricating semiconductor devices using a graphene-based layer transfer process is presented.

[0023] Figure 2 is shown for use Figures 1A-1DMaterials used to make devices based on graphene technology as shown in Figure 1, along with a plot of their lattice constants and lattice mismatch.

[0024] Figures 3A-3F A method of graphene-based layer fabrication and transfer using a stressor layer and tape is demonstrated.

[0025] Figure 4A-4B The effect of graphene layer thickness and underlying substrate on the growth of device layers on the graphene layer is shown.

[0026] Figures 5A-5E Demonstrating a method for graphene-based layer transfer using thin graphene layers.

[0027] Fig. 6A A high resolution X-ray diffraction (HRXRD) scan of GaN grown on graphene disposed on a SiO2 substrate is shown.

[0028] Figure 6B Shown is a HRXRD scan of GaN grown on graphene disposed on a SiC substrate.

[0029] Figures 7A-7C Three structures demonstrating graphene-based fabrication techniques using graphene layers of varying thicknesses.

[0030] Figures 8A-8H Demonstrate the use of Figure 7C Method for fabricating and transferring graphene-based layers of porous graphene constructed as shown in FIG.

[0031] Fig.9A and 9B Scanning electron microscope (SEM) images of Ge and GaAs epilayers grown on damaged graphene, respectively.

[0032] Fig. 10A and 10B They are Fig.9A and 9B SEM images of the Ge and GaAs epilayers shown in Figure 2 after release from the substrate.

[0033] Figures 11A-11H Demonstrating methods for fabricating light emitting diodes using graphene-based layer fabrication and transfer techniques.

[0034] Figures 12A-12G Demonstrating a method for fabricating GaAs solar cells using graphene-based layer fabrication and transfer techniques.

[0035] Figures 13A-13E Demonstrate methods for fabricating multi-junction solar cells using graphene-based layer fabrication and transfer techniques.

[0036] Figures 14A-14CDemonstrating methods for fabricating transistors using graphene-based layer fabrication and transfer techniques.

[0037] Figures 15A-15F Demonstrate methods for heterogeneous integration using graphene-based layer fabrication and transfer techniques.

[0038] Figures 16A-16F Demonstrates a method for preparing a platform for fabricating III-V devices using graphene-based layer fabrication and transfer techniques. DETAILED DESCRIPTION

[0039] Graphene-based layer growth

[0040] As described above, the layer transfer process may be required to have substrate reusability, minimum requirements for post-release processing, fast release rate, precise control of the release interface, and versatility for a wide range of device materials. Conventional layer transfer processes may exhibit some of the desired characteristics. For example, for mechanical stripping, layer release is much faster than chemical stripping or optical stripping, and the release position can be better controlled in chemical stripping and optical stripping. However, the surface of the conventional layer transfer method becomes rough after the layer is released, thereby limiting the reusability of the substrate. In fact, the process cost of refurbishing the substrate surface with a conventional layer transfer method usually exceeds the substrate cost, so the practical application in manufacturing may be challenging. In addition, each conventional method is generally applicable to a limited number of specific materials (for example, chemical stripping of III-V materials with a lattice close to that of GaAs, and optical stripping of materials that can be grown on transparent substrates). Therefore, the widespread use of these methods is also challenging.

[0041] In order to address the shortcomings of conventional layer transfer methods, the systems and methods described herein use a graphene-based layer transfer (GBLT) method to manufacture equipment. In this method, a functional device is manufactured on a graphene layer, and then the graphene layer is arranged on a substrate that is lattice-matched with the functional device layer. In one example, the graphene layer is directly deposited on a lattice-matched substrate. In another example, the graphene layer is transferred from another substrate to a lattice-matched substrate. Then, the manufactured functional device can be removed from the lattice-matched substrate by, for example, a stressor attached to the functional device.

[0042] In this GBLT method, graphene acts as a reusable and versatile platform for growing device layers, and also provides a release layer that allows rapid, accurate and repeatable release at the graphene surface. Compared with conventional methods, GBLT has several advantages. First, because graphene is a crystalline film, it is a suitable substrate for growing epitaxial capping layers. Second, the interaction of graphene with other materials is weak, so that the lattice mismatch rule of epitaxial growth can be fully alleviated, potentially allowing the growth of most semiconductor films with low defect density. Third, due to the weak van der Waals interaction of graphene, the epitaxial layer (e.g., functional device) grown on the graphene substrate can be easily and accurately released from the substrate, which allows the rapid mechanical release of the epitaxial layer without readjustment after releasing the released surface. Fourth, the mechanical robustness of graphene can maximize its reusability for multiple growth / release cycles.

[0043] The realization of GBLT for general material systems could have significant impact on both the scientific and industrial communities, as GBLT has the potential to manufacture devices without the expensive millimeter-thick single-crystal wafers used in current semiconductor processing. Additionally, entire functional devices could be transferred from graphene layers for additional flexible functionality.

[0044] Figures 1A-1D A method 100 for fabricating a device layer using graphene as a platform is shown. Figure 1A As shown in FIG. 1 , a graphene layer 120 is fabricated on a first substrate 110 (such as a Si substrate, a SiC substrate, or a copper foil). Then, the fabricated graphene layer 120 is removed from the first substrate 110, as shown in FIG. Figure 1B Then, the removed graphene layer 120 is disposed on a second substrate 130 (such as a Ge substrate), as shown in Figure 1C shown. Figure 1D An epitaxial layer 140 (eg, a single crystalline film having high electronic and optical device properties) is shown to be subsequently fabricated on the graphene layer 120. The epitaxial layer 140 is also referred to as a device layer or a functional layer in this application.

[0045] The graphene layer 120 can be manufactured on the first substrate 110 by various methods. In one example, the graphene layer 120 may include epitaxial graphene having a single crystal orientation, and the substrate 110 may include a (0001) 4H-SiC wafer having a silicon surface. The manufacture of the graphene layer 120 may include a multi-step annealing step. The first annealing step may be performed in H2 gas for surface etching and vicinal crystallization, and the second annealing step may be performed in Ar for graphitization at a high temperature (e.g., about 1,575°C).

[0046] In another example, the graphene layer 120 can be grown on the first substrate 110 by a chemical vapor deposition (CVD) process. The substrate 110 can include a nickel substrate or a copper substrate. Alternatively, the substrate 110 can include an insulating substrate of SiO2, HfO2, Al2O3, Si3N4, and virtually any other high temperature compatible planar material grown by CVD.

[0047] In yet another example, the first substrate 110 may be any substrate capable of supporting the graphene layer 120 , and the fabrication may include a mechanical exfoliation process. In this example, the first substrate 110 may serve as a temporary support for the graphene layer 120 .

[0048] Various methods can also be used to transfer the graphene layer 120 from the first substrate 110 to the second substrate. In one example, a carrier film can be attached to the graphene layer 120. The carrier film can include a thick film of poly (methyl methacrylate) (PMMA) or a thermal release tape, and the attachment can be achieved by a spin coating process. After the combination of the carrier film and the graphene layer 120 is disposed on the second substrate 130, the carrier film can be dissolved (e.g., in acetone) to further fabricate the epitaxial layer 140 on the graphene layer 120.

[0049] In another example, a stamp layer comprising an elastomeric material such as polydimethylsiloxane (PDMS) can be attached to the graphene layer 120, and the first substrate can be etched away, leaving a combination of the stamp layer and the graphene layer 120. After the stamp layer and the graphene layer 120 are placed on the second substrate 130, the stamp layer can be removed by mechanical separation, resulting in a clean surface of the graphene layer 120 for further processing.

[0050] In another example, the graphene layer 120 can be transferred to the second substrate 130 using a self-release transfer method. In this method, a self-release layer is first spin-casted on the graphene layer 120. Then, an elastic stamp is placed in conformal contact with the self-release layer. The first substrate 110 can be etched away, leaving a combination of the stamp layer, the self-release layer, and the graphene layer. After this combination is placed on the second backing plate 130, the stamp layer can be mechanically removed, and the self-release layer can be dissolved in a suitable solvent under mild conditions. The release layer can include polystyrene (PS), poly(isobutylene) (PIB), and polytetrafluoroethylene (poly[4,5-difluoro-2,2-bis(trifluoromethyl)-1,3-dioxole-co-tetrafluoroethylene]).

[0051] The epitaxial layer 140 may include III-V semiconductors, Si, Ge, III-N semiconductors, SiC, SiGe, and II-VI semiconductors, etc. In one example, the lattice of the second substrate 130 is matched to the epitaxial layer 140, in which case, if the graphene layer 120 is porous or thin enough (for example, if the graphene layer 120 is one layer thick), the second substrate 130 acts as a seed for the growth of the epitaxial layer 140. Sandwiching the graphene layer 120 between the second substrate 130 and the epitaxial layer 140 can facilitate rapid and damage-free release and transfer of the epitaxial layer 140.

[0052] In another example, the graphene layer 120 may be thick enough (e.g., several layers thick) to act as a seed for growing the epitaxial layer 140, in which case the epitaxial layer 140 may be lattice matched to the graphene layer 120. This example also allows for the reuse of the second substrate 130. In yet another example, the second substrate 130 and the graphene layer 120 may act together as a seed for growing the epitaxial layer 140.

[0053] Using graphene as a seed to make the epitaxial layer 140 can also increase the tolerance of the lattice constant mismatch between the epitaxial layer material and the graphene. Without being limited to any particular theory or mode of operation, the surface of a two-dimensional (2D) material (e.g., graphene) or a quasi-2D layered crystal generally does not have dangling bonds and interacts with the material above it through, for example, weak van der Waals forces. Due to the weak interaction, the epitaxial layer can grow with its own lattice constant from the beginning, thereby forming an interface with a small number of defects. This growth can be called van der Waals epitaxy (VDWE). For VDWE, the lattice matching conditions can be thoroughly relaxed, allowing a wide variety of different heterostructures even for highly lattice-mismatched systems.

[0054] In practice, the lattice mismatch can be about 0% to about 70% (e.g., about 0%, about 10%, about 20%, about 30%, about 40%, about 50%, about 60%, and about 70%, including any values ​​and sub-ranges therebetween).

[0055] In one example, the epitaxial layer 140 includes a 2D material system. In another example, the epitaxial layer 140 includes a 3D material system. The flexibility of fabricating both 2D and 3D material systems allows for the fabrication of a wide range of optical, optoelectronic, and photonic devices known in the art.

[0056] Figure 2 is a diagram showing materials that may be deposited on the graphene layer 120 to form the epitaxial layer 140 . Figure 2The lattice constants of these materials and the mismatch of these lattice constants relative to graphene are also shown. These materials include SiC, AlN, GaN, InN, GaP, AlP, silicon, AlAs, Ge, GaAs, and InP. Figure 2 The materials listed in FIG. 1 are for illustration purposes only. In practice, other materials having a lattice mismatch similar to that of graphene may also be used to form the epitaxial layer 140 .

[0057] The epitaxial layer 140 can be manufactured using semiconductor manufacturing techniques known in the art. For example, low-pressure metal organic chemical vapor deposition (MOCVD) can be used to grow an epitaxial layer 140 (e.g., a GaN film) on a graphene layer 120, which is in turn disposed on a second substrate 130 (e.g., a SiC substrate). In this example, the graphene layer 120 and the second substrate 130 can be baked (e.g., at >1,100°C, H2 for >15 min) to clean the surface. Then, the deposition of the epitaxial layer 140 including GaN can be performed at, for example, 200 mbar. Trimethylgallium, ammonia, and hydrogen can be used as gallium source, nitrogen source, and carrier gas, respectively. A modified two-step growth can be used to obtain a flat GaN epitaxial film on the epitaxial graphene 120. The first step can be performed at a growth temperature of 1,100°C for a few minutes, which can promote guided nucleation at the edge of the platform. The second growth step can be performed at a high temperature of 1,250°C to promote lateral growth. The vertical GaN growth rate in this case may be about 20 nm per minute.

[0058] Graphene-based layer transfer

[0059] Figures 3A-3F A method 300 of graphene-based layer transfer is presented. Figure 3A The graphene layer 320 is shown formed or disposed on a donor wafer 310, which may be a single crystal wafer. For example, as is known in the art, the graphene layer 320 may include epitaxial graphene grown on the donor wafer 310. Alternatively, the graphene layer 320 may be peeled off from another wafer (not shown) and transferred to the donor wafer 310. In yet another example, the above reference Figures 1A-1D Any of the graphene transfer techniques described herein may be used to prepare a graphene layer 320 disposed on a donor wafer 320 .

[0060] Figure 3B An epitaxial layer 330 is shown epitaxially grown on the graphene layer 320. The epitaxial layer 330 may include an electronic layer, a photonic layer, or any other functional device layer. The method of manufacturing the epitaxial layer 330 may include the above-mentioned Figures 1A-1D Any methods and techniques described.

[0061] Figure 3CIt is shown that a stressor 340 is disposed on the epitaxial layer 330. For example, the stressor 330 may include a high stress metal film (such as a Ni film). In this example, the Ni stressor may be disposed at 1×10 -5 The precipitate was deposited in an evaporator under a vacuum of 10 torr.

[0062] Figure 3D A tape layer 350 is shown disposed on the stressor 340 for handling the stressor 340. The epitaxial layer 330 may be mechanically exfoliated from the graphene layer 320 at a fast release rate using the tape 350 and the stressor 340 by applying high strain energy to the interface between the epitaxial layer 330 and the graphene layer 320. The release rate may be fast due at least to the weak van der Waals bonding between graphene and other materials such as the epitaxial layer 330.

[0063] exist Figure 3E In the embodiment, the released epitaxial layer 330 is disposed on the main wafer 360 together with the stressor 340 and the tape layer 350. Figure 3F In the embodiment, the tape layer 350 and the stressor 340 are removed, thereby leaving the epitaxial layer 330 for further processing, such as forming a more complex device or depositing additional materials on the epitaxial layer 330. In one example, the tape layer 350 and the stressor 340 can be etched away by a FeCl3-based solution.

[0064] In method 300, upon releasing Figure 3D After the epitaxial layer 330 shown in FIG. 3 is formed, the remaining donor wafer 310 and graphene layer 320 can be reused for the next epitaxial layer manufacturing cycle. Alternatively, the graphene layer 320 can also be released. In this case, a new graphene layer can be placed on the donor wafer 310 before the next epitaxial layer manufacturing cycle. In either case, the graphene layer 320 protects the donor wafer 310 from damage, thereby allowing multiple uses and reducing costs.

[0065] In contrast, conventional processes typically include chemical mechanical planarization (CMP) after release to repair the wafer surface. CMP may consume relatively thick materials, and repeated CMP may increase the chance of damaging the wafer. GBLT can increase or maximize reusability because it can produce an atomically smooth release surface. In GBLT, layer release can occur precisely at the interface between the epitaxial layer 330 and the graphene layer 320 because the weak van der Waals force of graphene does not allow strong bonding with adjacent materials. In this way, the graphene layer 320 can be reused for multiple growth / peeling cycles without the need for a polishing step, and the graphene will not be damaged due to its mechanical robustness. In addition, GBLT can ensure a fast release rate and universal application for different materials. Because the epitaxial layer 330 is mechanically released from the weaker graphene surface, the layer release rate in GBLT may be higher. However, conventional layer transfer methods are limited to specific materials, but GBLT can be universally applied because VDWE can overcome extremely high lattice mismatches and most semiconductor films can be epitaxially grown on graphene.

[0066] In addition, if Figure 3D As shown in , by having a highly strained freestanding epitaxial layer 330 after release, a device made from the epitaxial layer 330 can have a higher electron or hole mobility. An optoelectronic device made from the epitaxial layer 330 can also have an enhanced optical response.

[0067] In order to mechanically release the epitaxial layer 330 from the graphene layer 320, it may be necessary for the material of the stressor 340 to provide sufficient strain energy to the epitaxial layer / graphene interface to promote damage-free peeling / transfer. One concern about the mechanical release process may be the bending of the epitaxial layer 330 during peeling and the self-peeling of the stressor 340 during deposition. If the radius of curvature decreases during peeling, the strain energy in the epitaxial layer 330 may increase. When the strain energy reaches a critical point, cracks may form. In addition, if the strain energy in the stressor exceeds the epitaxial layer / graphene interface energy, the epitaxial layer 330 may be delaminated during the stressor deposition. To address this issue, the transfer of the epitaxial layer on the graphene can be performed by feedback closed-loop control.

[0068] Effect of substrate field on epitaxial layer

[0069] exist Figures 1A-1D and Figures 3A-3FIn the presented method, a device layer is fabricated on a graphene layer. Since graphene is typically on the order of one atom thick (e.g., about 3 angstroms), any covalently bonded substrate surface immediately below the graphene can affect the epitaxial growth of the device layer by, for example, changing the crystal orientation of the device layer. Therefore, it may be beneficial to understand the effect of the underlying substrate on the growth of the device layer, for example, to reduce the defect density on the device layer and control the properties of the device layer (such as, crystal orientation).

[0070] Figure 4A-4B A schematic diagram of a graphene-based fabrication system is shown to illustrate the impact of the underlying substrate on the growth of device layers. Figure 4A A system 401 is shown including a substrate 411 and a graphene layer 421 disposed on the substrate 411. A device layer 431 is fabricated on the graphene layer 421. The substrate 411 has a potential field 441 (e.g., via van der Waals forces or other atomic or molecular forces), such as Figure 4A In this case, the graphene layer 421 includes only a single graphene monolayer (i.e., the graphene layer 421 is one atom thick), and the potential field 441 reaches outside the graphene layer 421 and can interact with the device layer 431. Therefore, the potential field 441 depending on the material properties of the substrate 411 (such as crystal orientation) can affect the growth of the device layer 431. At the same time, the graphene layer 421 also has its own potential field ( Figure 4A ), the potential field can similarly affect the growth of device layer 431. The end result can be that device layer 431 includes two films 431a and 431b with different orientations (such as (100) and (111) orientations). Alternatively, the substrate force can be strong enough to overcome the graphene field, in which case a single crystalline film similar to the substrate can be grown.

[0071] Figure 4B A system 402 is shown including a substrate 412 and a graphene layer 422 disposed on the substrate 412. A device layer 432 is fabricated on the graphene layer 422. The substrate 412 has a potential field 442, such as Figure 4B Indicated by the arrow in Figure 4A Compared with the graphene layer 421 in Figure 4B 4. The graphene layer 422 in the substrate 412 includes multiple stacks of single-layer graphene (i.e., the graphene layer 422 is thicker than one atom). Therefore, the potential field 442 may interact only with the graphene layer 422 and may not reach the device layer 432. In other words, the VDWE of the device layer 432 appears outside the potential field 442 of the substrate 412. In this case, the potential field of the graphene layer 422 affects the growth of the device layer 432.

[0072] Figure 4A-4BThe effect of the substrate (e.g., 411 and 412) on the growth of the device layer (e.g., 431 and 432) is shown to depend on the distance between them. In other words, the thickness of the graphene layer (e.g., 421 and 422) sandwiched between the substrate and the device layer determines the interaction strength. Beyond a critical distance, the underlying substrate may not have any effect on the epitaxial growth of the device layer. This critical distance can be verified by using high resolution X-ray diffraction (HRXRD) to monitor the crystal orientation of the epitaxial layer as the graphene thickness changes, because the epitaxial layer may be similar to the graphene lattice when the critical distance is exceeded.

[0073] Figures 5A-5E A method 500 of graphene-based layer transfer using a thin graphene layer is presented. Figure 5A In the embodiment, a donor wafer 510a is provided to grow a graphene layer 520 (eg Figure 5B ). Figure 5B The graphene layer 520 , which may include a III-N semiconductor, a II-IV semiconductor, a III-V semiconductor, and a IV semiconductor, is shown subsequently being transferred to a second wafer 510 b .

[0074] exist Figure 5C In the embodiment, a film 530 is epitaxially grown on the graphene layer 520. Since the graphene layer 520 is thin enough in this case, the growth of the film 530 is seeded by the second wafer 510b below the graphene layer 520. Figure 5D In the embodiment of the present invention, a stressor 540 is deposited on the film 530 to facilitate subsequent layer transfer. The stressor 540 may include a high stress metal material (such as nickel). Figure 5E In the method 500, a tape layer 550 is provided on the stressor 540 to process the stressor 540 for releasing the film 530 from the graphene layer 520 and the second wafer 510b. In the method 500, the graphene layer 520 is thin enough and the graphene seed effect can disappear, while the substrate seed effect is strong. In this way, people can manufacture any releasable film by the method 500.

[0075] Figure 6A-6B Shown is the variation in crystallographic orientation of epitaxial layers grown on graphene using different underlying substrates. Fig. 6A Shown is the ω–2θ scan in HRXRD of GaN on graphene / SiO2 (graphene on SiO2 substrate). Figure 6B Shown is the ω–2θ scan of GaN on graphene / SiC (graphene on SiC substrate).

[0076] In order to eliminate the epitaxial relationship between epitaxial graphene and SiC substrate, Fig. 6AThe epitaxial graphene used in the study was exfoliated from SiC and then transferred to an amorphous Si substrate coated with SiO2. GaN can then be grown on the substrate. HRXRD ω-2θ scanning revealed that the GaN film on the epitaxial graphene grown on top of SiO2 is (0002) textured polycrystalline, while the GaN film on the epitaxial graphene grown on top of SiC has a single (0002) orientation (see Fig. 6A and 6B ). This means that the substrate directly below the graphene layer plays a role in determining the epitaxial orientation. Therefore, the material (or crystal orientation) of the substrate can be used to control the epitaxial orientation of the device layer.

[0077] Control of seed position in graphene-based layer fabrication and transfer

[0078] In practical applications of graphene-based layer fabrication and transfer, it may be beneficial that the epitaxial registry can be tuned to the graphene or the substrate in order to obtain high-quality single-crystalline films on the graphene. By such control of the seed position, direct epitaxy on graphene or remote epitaxy catalyzed from the substrate can be achieved. In direct epitaxy on graphene, the graphene plays the role of seed as well as release layer. In remote epitaxy catalyzed from the substrate, the graphene becomes only a release layer, and the substrate serves as a seed.

[0079] Figures 7A-7C Schematic diagram showing three different types of graphene-based manufacturing systems using graphene layers of varying thicknesses. When applied, the user can choose to use one of these systems based on the desired interaction strength between the device layer and the underlying substrate, or alternatively depending on the desired interaction strength between the device layer and the graphene. These three options can provide a lot of flexibility to accommodate different manufacturing tasks.

[0080] Fig. 7A A system 701 (also referred to as a Type I system) is shown that includes a substrate 711 and a graphene layer 721 grown on the substrate 711. Then, an epitaxial layer 731 is epitaxially grown on the graphene layer 721. In the Type I system 701, both the graphene layer 721 and the substrate 711 interact with the epitaxial layer 731, as shown in FIG. Fig. 7A Indicated by the arrow in .

[0081] In one example, epitaxial graphene 721 (e.g., single-layer graphene) can be grown on a SiC substrate for use in a Type I system. In this example, because the crystal orientations of graphene and SiC are consistent, they can both be used to <0001> The wurtzite structure provides hexagonal seeds. Since the lattice mismatch between III-N semiconductors and graphene is small, this substrate can be used to grow single-crystalline wurtzite III-N (or SiC) films. This epitaxial graphene / SiC substrate can also be used to grow (111) cubic III-V, Si, and Ge films, because both graphene and SiC become (111) oriented seeds.

[0082] In another example, the substrate 711 includes germanium (Ge) to epitaxially grow the graphene layer 721. The lattice mismatch between Ge and other cubic materials is generally smaller than the lattice mismatch between SiC and cubic materials. In this example, the graphene layer 721 can be grown on the Ge substrate 711 by MOCVD technology. In another example, graphene can be directly grown on other semiconductor wafers (such as GaAs, InP and GaN).

[0083] Figure 7B A system 702 (also referred to as a Type II system) is shown that includes a substrate 712 and a graphene layer 722 grown on the substrate 712. Then, an epitaxial layer 732 is epitaxially grown on the graphene layer 722. In the Type II system 702, the thickness of the graphene layer 722 is substantially equal to or greater than the critical distance for interaction between the substrate 712 and the epitaxial layer 732. Therefore, the epitaxial layer 732 interacts only with the epitaxial graphene 722 that provides a pure VDWE. This Type II system can be suitable for growing III-N semiconductor films or SiC single crystal films because their lattice mismatch with graphene is not substantially high. Copper foil can be used to make large-sized (e.g., greater than 8 inches, greater than 12 inches, or greater) polycrystalline graphene.

[0084] Figure 7C A system 703 (also referred to as a Type III system) is shown that includes a substrate 713 and a graphene layer 723 grown on the substrate 713. Then, an epitaxial layer 733 is epitaxially grown on the graphene layer 723. In the Type III system 703, the graphene layer 723 serves only as a release layer and the epitaxial growth is catalyzed only from the substrate 713. A substrate material having the same or similar lattice as the epitaxial layer 733 can be used. The graphene layer 723 does not participate in determining the crystal orientation of the epitaxial layer 733. Therefore, the graphene layer 723 can include single-crystalline graphene or polycrystalline graphene.

[0085] Type III systems assign the registration of the epitaxial layer 733 to the substrate. One advantage of this configuration is that high quality epitaxial layers can be grown on lattice matched substrates, as in homoepitaxy, while the epitaxial layers can be released from the graphene surface. To achieve this advantage, it may be desirable for the graphene layer 723 to be substantially transparent to the epitaxial layer 733 during growth. This can be achieved by amorphizing or damaging the graphene by ions (e.g., by dry etching). Damage to the graphene layer 723 can allow direct interaction of the epitaxial layer 733 and the substrate 713 through the graphene layer 723, such that the graphene layer 723 does not guide the crystal orientation of the epitaxial layer 733.

[0086] In one example, the substrate has polarity (e.g., oxide, perovskite) such as a III-V substrate, a III-N substrate, a II-V substrate, and / or an ionically bonded substrate, the pristine graphene can be transferred to a wafer, and the epitaxial layer can have the same crystallinity as the wafer, and the grown film can be ready to be peeled off. In another example, the substrate may not have polarity (e.g., group IV), and damaging the graphene can help promote substrate / epitaxial layer interaction.

[0087] Figures 8A-8H A method 800 of graphene-based layer fabrication and transfer using graphene with periodic holes (hereinafter referred to as porous graphene) is presented. The method 800 can be implemented with a Type III system, where the graphene acts as a release layer and the substrate catalyzes the epitaxial growth of one or more functional layers.

[0088] exist Fig. 8A In the embodiment, a graphene layer 820 is disposed on a substrate 810. For example, the graphene layer 820 may be grown on the substrate 810 by chemical vapor deposition. Alternatively, the graphene layer 820 may be transferred to the substrate 810. Then, a porous film 830 (e.g., an oxide, a nitride, or a photoresist film) is disposed on the graphene layer 820, such as Figure 8B As shown in . The porous membrane 830 has a high density of pinholes (e.g., about one hole per square micron). Alternatively, the porous membrane 830 may include any membrane having pores to allow Figures 8C-8H The subsequent processing is shown in FIG.

[0089] exist Figure 8CIn the embodiment of the present invention, dry etching is performed using Ar plasma or O2 plasma to open pinholes in the porous membrane 830. The etching creates a plurality of holes 835 in the porous membrane 830, thereby allowing ions in the etching plasma to pass through the porous membrane 830 and reach the graphene layer 820. Then, the etching plasma etches a portion of the graphene layer 820 directly below the pinholes 835 in the porous membrane 830. The ions in the etching plasma can damage the graphene layer 820 by creating a plurality of holes 825 in the graphene layer 820, which now becomes a porous graphene layer 820. In one example, the etching of the porous membrane 830 and the etching of the graphene layer 820 can be achieved with the same etching plasma. In another example, the etching of the porous membrane 830 and the etching of the graphene layer 820 can be achieved with different etching plasmas.

[0090] exist Fig. 8E In the embodiment of the present invention, the porous membrane 830 is removed, thereby exposing the now porous graphene layer 820 for further processing. In one example, the porous membrane 830 includes a photoresist material and can be removed by acetone. In another example, the porous membrane 830 includes an oxide or a nitride and can be removed by hydrogen fluoride (HF). Fig. 8E Also shown is the growth of an epitaxial layer 840 on the porous graphene layer 820. The growth starts from the region where the pores 825 are created. The pores 825 allow direct interaction of the substrate 810 with the epitaxial layer 840, thereby allowing the substrate 810 to guide the crystal orientation of the epitaxial layer 840. The growth of the epitaxial layer 840 then extends to cover the entire graphene layer 820, thereby forming a planar epitaxial layer 840.

[0091] exist Figure 8G In the process, the formed epitaxial layer 840 is released from the graphene layer 820 and the substrate 810. The released epitaxial layer 840 is transferred to the target substrate 850, as shown in FIG. Figure 8H for further processing (such as forming a functional device). Figure 8G After forming the epitaxial layer 840 shown in FIG. 8 , the graphene layer 820 and the substrate 810 are reused to fabricate another epitaxial layer, and the cycle may be repeated multiple times.

[0092] Fig.9A and 9B Scanning electron microscope (SEM) images of Ge and GaAs films grown on damaged graphene, respectively. Although pits appear on the surface due to limited nucleation on graphene and incomplete impact of the growth front, fully catalyzed planar (100) crystals from the substrate are observed.

[0093] Fig. 10A and 10B They are Fig.9A and 9BSEM images of Ge and GaAs films after exfoliation using Ni stressors are shown in. The smooth exfoliated surface implies precise release of the layers from graphene, and this is confirmed by observing traces of graphene-like wrinkles during wet transfer.

[0094] like Figures 8A-8H and is shown in Figures 9A-9B and Figures 10A-10B This porous graphene approach experimentally investigated in can be applied to several other material systems. In one example, an InP film can be made on damaged graphene disposed on an InP wafer. In another example, a Si film can be grown on damaged graphene disposed on a Si wafer. In yet another example, a GaN film can be grown on damaged graphene disposed on a GaN wafer. The epitaxial registration of the epitaxial layer can be tuned to the substrate to ensure successful epitaxial growth of graphene onto the substrate.

[0095] Fabrication and heterogeneous integration of functional flexible devices

[0096] Graphene-based layer manufacturing and transfer techniques can be used to manufacture various functional devices based on epitaxial layers grown on graphene. In one example, III-N high electron mobility transistors (HEMTs) can be manufactured from III-N epitaxial layers. Then, the transistors can be transferred to polycrystalline diamond substrates for heat dissipation. GaN power devices can also be made of these films. In another example, flexible GaAs solar cells can be made from III-V epitaxial layers. Optoelectronic devices integrated with Si integrated circuits can also be made from III-V epitaxial layers. In another example, Ge-based LEDs and photodetectors can be made by growing IV epitaxial layers on graphene, peeling off the IV epitaxial layers, stretching freestanding Ge to tensile strained Ge, and transferring the IV epitaxial layers to Si integrated circuits. In another example, Ge can be grown on 12-inch Si wafers and then used as seeds to grow single-crystalline graphene. Then, III-V optoelectronic materials can be grown on graphene on Ge / Si wafers without any dislocations.

[0097] Figures 11A-11H A method 1100 for manufacturing a light emitting diode (LED) using the graphene-based layer transfer technique described above is shown. Fig.11A In the process, a graphene layer 1120 is grown on a substrate 1110 (e.g., a 6-inch SiC substrate). Then, the graphene layer 1120 is released from the substrate 1110, as shown in FIG. Fig. 11B and transferred to a target substrate 1130, as shown in Fig. 11C The target substrate 1130 may be, for example, Fig.11A The SiC wafers used in the process are cheap.

[0098] exist Fig.11D , an LED stack 1140 (e.g., a visible LED stack) is fabricated on a graphene layer 1120. In this example, the LED stack 1140 includes three periods of III-nitride multiple quantum wells (InGaN wells and GaN barriers) sandwiched between p-GaN and n-GaN layers. As will be readily appreciated by those skilled in the art, other types of LED stacks may also be grown on the graphene layer 1120.

[0099] The fabricated LED stack 1140 can then be processed in at least two ways. In one approach, Fig.11E As shown, an electrode 1150 can be deposited on the LED stack 1140 to form an electrical contact. For example, a thin Ni / Au (5nm / 5nm) can be deposited on the LED stack 1140 and then annealed at 500° C. for 10 min. This results in an LED including the substrate 1130.

[0100] Alternatively, if Fig.11F 1140, the LED stack 1140 can be removed from the substrate 1130. To remove the LED stack 1140 from the substrate 1130, a stressor layer 1160 is disposed on the LED stack 1140 to release the LED stack 1140 from the target substrate 1130 and the graphene 1120. The combination of the stressor layer 1160 and the LED stack 1140 is then flipped over and placed on a second target substrate 1135, as shown in FIG. Fig.11G The stressor layer 1160 is contacted with the second target substrate 1135 and the LED stack 1140 is exposed for further processing. For example, Fig.11G LED mesas 1145 are shown being etched from LED stack 1140. Fig.11F In FIG. 1 , additional electrical contacts 1170 are integrated with the LED mesa 1145 and the stressor layer 1160 .

[0101] In one example, the graphene layer 1120 can catalyze the growth of the LED stack 1140, and the target substrate 1130 can have no effect on the growth of the LED stack 1140. In another example, a type III catalyst (e.g., Figure 7C ). In this case, the graphene layer 1120 can be thin, and the target substrate 1130 can catalyze the growth of the LED stack 1140. The target substrate 1130 can include a GaN substrate.

[0102] Figures 12A-12G A method 1200 for fabricating GaAs solar cells using a graphene-based layer transfer technique is shown. Fig. 12AIn the process, a graphene layer 1220 (e.g., a single-crystal graphene layer) is fabricated on a substrate 1210 (e.g., a 6-inch SiC wafer). Then, as Fig. 12B As can be seen, the graphene layer 1220 is transferred to a target substrate 1230 . Fig. 12C A GaAs solar cell 1240 is shown fabricated on a graphene layer 1220 by, for example, epitaxial growth techniques known in the art. Fig.12D A stressor layer 1250 is then shown deposited on the solar cell 1240 to facilitate subsequent device transfer. A tape layer 1260 is disposed on the stressor 1250 to aid in handling the device transfer, such as Fig.12E as shown in .

[0103] After being released from the target substrate 1230, the solar cell 1240 becomes freestanding and can be processed in two ways. In one way, as Fig.12F As shown in FIG. 1 , the solar cell 1240 can be placed on the metal 1240 for subsequent module manufacturing. The solar cell 1240 can be placed on the metal 1240 by direct bonding or any other technique known in the art. Alternatively, as Figure 12G As shown in FIG. 1 , the freestanding solar cell 1240 together with the stressor layer 1250 and the tape layer 1260 form a lightweight and flexible solar cell assembly in its own way. Such a flexible solar cell assembly can be easily integrated into other systems, including power electronics.

[0104] In one example, the graphene layer 1220 may catalyze the growth of the solar cell 1240, and the target substrate 1230 may have no effect on the growth of the solar cell 1240. In another example, a type III catalyst (e.g., Figure 7C ). In this case, the graphene layer 1220 may be thin, and the target substrate 1230 may catalyze the growth of the solar cell 1240. The target substrate 1230 may include a GaAs substrate.

[0105] Figures 13A-13E A method 1300 for fabricating a multi-junction solar cell using a graphene-based layer transfer technique is shown. The method 1300 begins by providing a graphene layer 1320 on a glass substrate 1310 having a transparent conductive oxide (TCO) surface, such as Fig.13A The graphene layer 1320 may be transferred to the glass substrate 1310 by any method described in this application or any other method known in the art.

[0106] Fig. 13BThree material layers are shown deposited on the graphene layer 1320 , including an InGaP layer 1330 , a GaAs layer 1340 on the InGaP layer 1330 , and a second graphene layer 1350 on the GaAs layer 1340 . Fig. 13C An InGaAs layer 1360 is shown deposited on the second graphene layer 1350. The second graphene layer 1350 can help with lattice matching during the fabrication of the InGaAs layer 1360. A metal contact 1370 is then placed on the InGaAs layer 1360 to provide electrical conduction, such as Fig.13D Then, in Fig.13E The stack of the InGaP layer 1330 , the GaAs layer 1340 , the second graphene layer 1350 , and the InGaAs layer 1350 is etched into two solar cell mesas 1380 , each of which is located below a corresponding metal contact 1370 .

[0107] Figures 14A-14C A method 1400 of manufacturing a transistor is shown. Fig.14A In the embodiment, a graphene layer 1420 is provided on a substrate 1410 (such as a SiC wafer). An InGaAs layer 1430 is deposited on the graphene layer 1420. Fig. 14B As shown in , the InGaAs layer 1430 is then transferred to a silicon wafer 1440, on the surface of which an oxide layer 1450 is disposed. Then, an Al2O3 layer 1470 is deposited on the InGaAs layer 1430 as a top gate dielectric. Fig. 14C As shown in FIG. 1 , a gate 1480 is fabricated on the Al 2 O 3 layer 1470 to form a transistor.

[0108] In one example, the graphene layer 1420 may catalyze the growth of the InGaAs layer 1430, and the silicon wafer 1440 may have no effect on the growth of the InGaAs layer 1430. In another example, type III seeding (e.g., Figure 7C ). In this case, the graphene layer 1420 can be very thin and the silicon wafer 1440 can be replaced with an InP substrate to seed the growth of the InGaAs layer 1430.

[0109] Figures 15A-15F A method 1500 of forming a heterostructure using a graphene-based transfer technique is shown. Fig.15A In the embodiment of the present invention, a graphene layer 1520 (eg, a single-layer graphene) is provided on a substrate 1510 (eg, a SiC wafer). Then, an h-BN layer 1530 (ie, hexagonal boron nitride) is epitaxially grown on the graphene layer 1520. Fig. 15BA stressor layer 1540 (e.g., a nickel film) is shown coated on the h-BN layer 1530, and a tape layer 1550 is disposed on the stressor layer 1540. As previously described, the tape layer 1550 and the stressor layer 1540 can transfer the h-BN layer 1530 to a second substrate including a silicon wafer 1560 having an oxide layer 1565 (e.g., silicon oxide) on top, as shown in FIG. Fig. 15C As shown in . Fig. 15C Also shown is the stressor layer 1540 and the tape layer 1550 being etched away, leaving the h-BN layer 1530 for further processing.

[0110] exist Fig.15D In the embodiment, a MoS 2 layer 1570 is deposited on the h-BN layer 1530 , and a second h-BN layer 1580 is deposited on the MoS 2 layer 1570 to form an h-BN / MoS 2 heterostructure. Fig.15F A HfO 3 layer 1590 is shown deposited on the second h-BN layer 1580 as a top gate dielectric, and a top gate 1595 is deposited on the HfO 3 layer 1590 to provide power conduction.

[0111] Figures 16A-16F A method 1600 is shown for preparing a platform for fabricating III-V devices using graphene-based layer fabrication and transfer techniques. Fig.16A A 12-inch silicon wafer 1610 is shown. Then, a relaxed Ge film 1620 is disposed on the wafer 1610 by, for example, epitaxial growth, as shown in FIG. Fig. 12B Then, the Ge film 1620 acts as a seed to epitaxially grow a graphene layer 1630, as shown in Fig. 16C As can be seen, the graphene layer 1630 may include single-crystalline graphene.

[0112] exist Fig.16D In the embodiment, the graphene layer 1630 is patterned by, for example, photolithography techniques known in the art. The patterning results in gaps 1635 in the graphene layer 1630. In other words, the graphene layer 1630 can be patterned into separate and smaller graphene layer fragments. Fig.16E , a device layer 1640 is fabricated on the graphene layer 1620. The device layer 1640 may include, for example, III-V materials or structures such as metal oxide semiconductor field effect transistors (MOSFETs), lasers, or any other structures known in the art. The device layer 1640 then acts as a platform to form additional devices 1650, as shown in FIG1610.

[0113] in conclusion

[0114] Although various embodiments of the present invention have been described and shown herein, a person of ordinary skill in the art will readily conceive of various other methods and / or structures for performing the functions described herein and / or obtaining the results and / or one or more advantages described herein, and each of such variations and / or modifications is considered to be within the scope of the embodiments of the present invention described herein. More generally, it will be readily understood by those skilled in the art that all parameters, dimensions, materials, and structures described herein are exemplary, and actual parameters, dimensions, materials, and / or structures will depend on the specific application using the teachings of the present invention. A person skilled in the art will recognize that, or simply using routine experiments, many equivalents of the specific embodiments of the present invention described herein can be determined. Therefore, it should be understood that the aforementioned embodiments are presented only by way of example, and within the scope of the appended claims and their equivalents, embodiments of the present invention can be practiced in a manner other than the manner specifically described and claimed. The embodiments of the present invention disclosed herein are directed to each individual feature, system, article, material, kit, and / or method described herein. In addition, if such features, systems, articles, materials, kits, and / or methods do not contradict each other, any combination of two or more such features, systems, articles, materials, kits, and / or methods is included within the scope of the present invention disclosed herein.

[0115] The embodiments described above may be implemented in any of a variety of ways. For example, the design and manufacture of embodiments of the technology disclosed herein may be implemented using hardware, software, or a combination thereof. When implemented in software, the software code may be executed on any suitable processor or collection of processors, whether provided in a single computer or distributed in multiple computers.

[0116] In addition, it should be understood that the computer can be implemented in any of a variety of forms, such as a rack-mounted computer, a desktop computer, a laptop computer, or a tablet computer. In addition, the computer can be embedded in a device that is not generally considered a computer but has suitable processing capabilities, including a personal digital assistant (PDA), a smart phone, or any other suitable portable or fixed electronic device.

[0117] In addition, the computer may have one or more input and output devices. Among other things, these devices may be used to present a user interface. Examples of output devices that may be used to provide a user interface include a printer or display screen for visual presentation of the output, and a speaker or other sound generating device for audible presentation of the output. Examples of input devices that may be used for a user interface include a keyboard and a pointing device, such as a mouse, a touch pad, and a digitizing input board. As another example, a computer may receive input information by speech recognition or in other audible formats.

[0118] Such computers may be interconnected in any suitable form via one or more networks, including local or wide area networks, such as enterprise networks and intelligent networks (IN) or the Internet, etc. Such networks may be based on any suitable technology and may operate according to any suitable protocol and may include wireless networks, wired networks or fiber optic networks.

[0119] The various methods or processes outlined herein may be encoded as software that can be executed on one or more processors using any of a variety of operating systems or platforms. In addition, such software may be written using any of a variety of suitable programming languages ​​and / or programming or scripting tools, and may also be compiled into executable machine language code or intermediate code that is executed on a framework or virtual machine.

[0120] In this regard, various inventive concepts may be implemented as a computer-readable storage medium (or multiple computer-readable storage media) encoded with one or more programs (e.g., computer memory, one or more floppy disks, compact disks, optical disks, tapes, flash memory, circuit configurations in field programmable gate arrays or other semiconductor devices, or other non-transitory media or tangible computer storage media), which, when executed on one or more computers or other processors, perform methods that implement the various embodiments of the present invention discussed above. The one or more computer-readable media may be removable so that the one or more programs stored thereon can be loaded onto one or more different computers or other processors to implement various aspects of the present invention as discussed above.

[0121] The term "program" or "software" is used herein in a general sense to refer to any type of computer code or computer executable instruction set that can be used to program a computer or other processor to implement various aspects of the embodiments as discussed above. In addition, it should be understood that one or more computer programs that, when executed, accomplish the methods of the present invention need not reside on a single computer or processor, but can be distributed in a modular manner among multiple different computers or processors to implement various aspects of the present invention.

[0122] Computer executable instructions can be in many forms, such as program modules that are executed by one or more computers or other devices. Generally speaking, program modules include routine programs, programs, objects, components, data structures, etc. that perform specific tasks or implement specific abstract data types. Typically, the functions of program modules can be combined or distributed as needed in various implementations.

[0123] In addition, the data structure can be stored in a computer-readable medium in any suitable form. To simplify the description, the data structure can be shown as having fields that are related by position in the data structure. Such relationships can also be achieved by allocating storage to the fields with positions in the computer-readable medium that convey the relationship between the fields. However, any suitable mechanism can be used to establish the relationship between the information in the fields of the data structure, including by using pointers, tags, or other mechanisms that establish relationships between data elements.

[0124] In addition, various inventive concepts can be implemented as one or more methods for which examples have been provided. The actions performed as a part of the method can be sequenced in any suitable manner. Therefore, embodiments that perform actions in a sequence different from that shown can be constructed, and the embodiments can include performing some actions simultaneously, even if these actions are shown as sequential actions in the illustrative embodiments.

[0125] All definitions, as defined and used herein, should be understood to control over dictionary definitions, definitions in documents incorporated by reference, and / or ordinary meanings of the defined terms.

[0126] As used in the specification and claims herein, the indefinite articles "a" and "an" should be understood to mean "at least one", unless explicitly stated to the contrary.

[0127] "And / or" as used in the specification and claims herein should be understood to mean "one or both" of the elements so combined, i.e., "one or both" of the elements that are present in combination in some cases and separately in other cases. Multiple elements listed with "and / or" should be interpreted in the same manner, i.e., "one or more" of the elements so combined. In addition to the elements explicitly identified by the "and / or" clause, other elements may optionally be present, whether related or unrelated to those elements explicitly identified. Thus, as a non-limiting example, when referring to "A and / or B" used in conjunction with open language (such as "comprising"), in one embodiment, it may refer to only A (optionally including elements other than B); in another embodiment, it may refer to only B (optionally including elements other than BA); in yet another embodiment, it may refer to both A and B (optionally including other elements); and so on.

[0128] "Or" as used in the specification and claims herein should be understood to have the same meaning as "and / or" as defined above. For example, when separating the items in the list, "or" or "and / or" should be interpreted as inclusive, i.e. including at least one element in a plurality of elements or element lists, but also including more than one element, and optionally including items not listed in addition. Only terms such as "only one of" or "just one of" clearly indicate the opposite, or when "consisting of..." is used in the claims, it will refer to including just one element in a plurality of elements or element lists. In short, only when there is an exclusive term in front, such as "one of the two", "one of", "only one of" or "just one of", the term "or" as used herein should be interpreted as indicating an exclusive alternative (i.e., one or the other, not both). "Substantially consisting of..." should have its usual meaning used in the field of patent law when used in the claims.

[0129] The phrase "at least one" as used in the specification and claims herein in relation to a list of one or more elements should be understood to mean at least one element selected from any one or more elements in the list of elements, but does not necessarily include at least one of each element explicitly listed in the list of elements, and does not exclude any combination of elements in the list of elements. This definition also allows that in addition to the elements explicitly identified in the list of elements to which the phrase "at least one" refers, other elements may optionally be present, whether related or unrelated to those elements explicitly identified. Thus, as a non-limiting example, "at least one of A and B" (or equivalently, "at least one of A or B", or equivalently, "at least one of A and / or B") may refer to at least one A, optionally including more than one A, but no B (and optionally including elements other than B) in one embodiment; to at least one B, optionally including more than one B, but no A (and optionally including elements other than A) in another embodiment; to at least one A, optionally including more than one A, and at least one B, optionally including more than one B (and optionally including other elements) in yet another embodiment; and so on.

[0130] In the claims and the foregoing description, all transitional phrases such as "comprising," "including," "carrying," "having," "containing," "involving," "retaining," "consisting of," etc. shall be understood to be open-ended, i.e., meaning including but not limited to. As set forth in the U.S. Patent Office Manual of Patent Examining Procedures, Section 2111.03, only the transitional phrases "consisting of" and "consisting essentially of" shall be closed or semi-closed transitional phrases, respectively.

[0131] More specifically, the present application provides the following:

[0132] 1. A method for manufacturing a semiconductor device, the method comprising:

[0133] forming a graphene layer on a first substrate;

[0134] transferring the graphene layer from the first substrate to a second substrate; and

[0135] A single crystal film is formed on the graphene layer.

[0136] 2. The method of claim 1, wherein the first substrate comprises silicon carbide, and the graphene layer comprises a single-crystalline graphene layer.

[0137] 3. The method of claim 1, wherein the first substrate comprises a copper foil, and the graphene layer comprises a polycrystalline graphene layer.

[0138] 4. The method of claim 1, wherein the first substrate comprises a silicon substrate, and forming the graphene layer comprises:

[0139] forming a germanium layer on the silicon substrate; and

[0140] The graphene layer is formed on the germanium layer.

[0141] 5. The method of item 1, wherein the graphene layer is composed of a single layer of graphene, and forming the single crystal film on the graphene layer includes using the second substrate as a seed crystal for the single crystal film and using the graphene layer as a release layer.

[0142] 6. The method of claim 5, wherein the graphene layer comprises polycrystalline graphene and the first substrate comprises copper foil.

[0143] 7. The method of item 1, wherein the graphene layer comprises more than one layer of graphene, and forming the single crystalline film on the graphene layer comprises using the graphene layer as a seed for the single crystalline film.

[0144] 8. A method as described in item 7, wherein the graphene layer comprises single-crystalline graphene.

[0145] 9. The method of item 1, wherein forming the single crystalline film on the graphene layer comprises using a combination of the second substrate and the graphene layer as a seed crystal for the single crystalline film.

[0146] 10. The method of item 1, wherein forming the single crystalline film comprises depositing a material of the second substrate on the graphene layer.

[0147] 11. The method of claim 1, further comprising:

[0148] forming a plurality of holes in the graphene layer, and

[0149] Wherein forming the single crystalline film includes depositing a material in the plurality of holes and on the graphene layer.

[0150] 12. The method of claim 1, further comprising:

[0151] The single crystal film is removed from the graphene layer.

[0152] 13. The method of item 12, wherein removing the single crystal film from the graphene film comprises peeling off the single crystal film.

[0153] 14. The method of clause 12, wherein removing the single crystal film from the graphene film comprises:

[0154] forming a metal stressor on the single crystal film;

[0155] placing a flexible tape on the metal stressor; and

[0156] The single crystal film and the metal stressor are pulled away from the graphene layer by the flexible tape.

[0157] 15. The method of claim 12, further comprising:

[0158] The single crystal film is deposited on a third substrate.

[0159] 16. The method of claim 12, further comprising:

[0160] Another single crystal film is formed on the graphene layer.

[0161] 17. The method of claim 1, further comprising:

[0162] A material is deposited on the single crystal film.

[0163] 18. The method of claim 1, further comprising:

[0164] The single crystal film and the graphene layer are removed from the second substrate.

[0165] 19. A semiconductor device formed by the method of item 1.

[0166] 20. A semiconductor processing method, the method comprising:

[0167] forming a graphene monolayer on a silicon carbide substrate;

[0168] transferring the graphene monolayer from the silicon carbide substrate to a semiconductor substrate;

[0169] forming a plurality of holes in the graphene monolayer;

[0170] forming a first single crystal layer of semiconductor material on the graphene monolayer, the semiconductor substrate acting as a seed for the first single crystal layer of semiconductor material;

[0171] removing the first single crystalline layer of semiconductor material from the graphene monolayer;

[0172] forming a second single crystalline layer of semiconductor material on the graphene monolayer, the semiconductor substrate acting as a seed for the second single crystalline layer of semiconductor material; and

[0173] A second single crystalline layer of semiconductor material is removed from the graphene monolayer.

[0174] 21. A method as described in item 20, wherein removing the first single crystalline layer of semiconductor material from the graphene monolayer includes peeling off the first single crystalline layer of semiconductor material.

[0175] 22. The method of claim 20, further comprising:

[0176] forming a plurality of holes in the graphene monolayer, and

[0177] Wherein forming the first single crystalline layer of semiconductor material comprises depositing material in the plurality of holes.

[0178] 23. A device formed by the method of claim 20.

[0179] 24. A semiconductor processing method, the method comprising:

[0180] forming a graphene layer on a first substrate;

[0181] transferring the graphene layer from the first substrate to a second substrate;

[0182] depositing a semiconductor layer on the graphene layer;

[0183] depositing a stressor layer on the semiconductor layer, the stressor layer causing crack propagation between the semiconductor layer and the graphene layer; and

[0184] placing a flexible tape on the stressor layer; and

[0185] The semiconductor layer and the stressor layer are pulled away from the graphene layer using the flexible tape.

Claims

1. A method for manufacturing a semiconductor device, the method comprising: forming a continuous graphene layer on a first substrate, wherein the continuous graphene layer consists of a single layer of graphene; transferring the continuous graphene layer from the first substrate to a second substrate having a potential field; forming a single crystalline film on the continuous graphene layer, wherein only the lattice of the second substrate matches the single crystalline film, so that only the second substrate catalyzes the growth of the single crystalline film and the continuous graphene layer functions only as a release layer; as well as The single crystal film and the second substrate are separated.

2. The method of claim 1, wherein the second substrate comprises a metal, an oxide, a nitride, a III-V semiconductor, a II-IV semiconductor, a IV semiconductor, or an ion-bonded substrate.

3. The method of claim 1, wherein the first substrate comprises silicon carbide and the continuous graphene layer comprises a single crystalline graphene layer.

4. The method of claim 1, wherein the first substrate comprises a copper foil and the continuous graphene layer comprises a polycrystalline graphene layer.

5. The method of claim 1, wherein the first substrate comprises a silicon substrate, and forming the continuous graphene layer comprises: forming a germanium layer on the silicon substrate; as well as The continuous graphene layer is formed on the germanium layer.

6. The method of claim 1, wherein the continuous graphene layer comprises single crystalline graphene.

7. The method of claim 1, wherein forming the single crystalline film comprises depositing a material of the second substrate on the continuous graphene layer.

8. The method of claim 1, further comprising: The single crystalline film is removed from the continuous graphene layer.

9. The method of claim 8, wherein removing the single crystalline film from the continuous graphene layer comprises peeling the single crystalline film.

10. The method of claim 8, wherein removing the single crystalline film from the continuous graphene layer comprises: forming a metal stressor on the single crystal film; Disposing a flexible adhesive tape on the metal stress object; as well as The single crystal film and the metal stressor are pulled away from the continuous graphene layer by the flexible tape.

Images