A DC current comparator bridge and a current source calibration method thereof

Abstract

The present application discloses a DC current comparator bridge and a current source calibration method thereof, and relates to the field of measuring devices. The DC current comparator bridge includes a master / slave current source, a main circuit integer turn / fractional turn adjustable winding, an integer turn / fractional turn switch matrix, an integer turn / fractional turn drive module, a slave circuit fixed turn winding, a differential compensation module, a modulation module, a demodulation module, a conditioning module, an ADC, a control module and other structures; wherein the master and slave current sources both include a reference DAC and a transconductance amplifier; the reference DAC receives a code value from the control module, and outputs a voltage corresponding to the code value to the transconductance amplifier; the transconductance amplifier converts the voltage signal output by the reference DAC into a current signal; the control module calculates the correction value corresponding to the master and slave current sources according to the ADC sampling data, and corrects the code value received by the master and slave current sources based on the correction value, completes the self-calibration of the master and slave current sources, and can improve the accuracy of the current value output by the current source.

Description

Technical Field

[0001] The present application relates to the technical field of measuring devices, and in particular to a direct current comparator bridge and a current source calibration method thereof. Background Art

[0002] A DC current comparator is a high-accuracy DC current comparison device, and its common application is a high-accuracy DC current measuring instrument. In addition, with a DC current comparator as the core, in conjunction with a resistor bridge arm, a current feedback system, and an unbalanced voltage detection system, a DC current comparator bridge for resistance ratio measurement can also be constructed. Depending on the key components and measurement accuracy, the DC current comparator bridge is further divided into a conventional DC current comparator bridge (DCC bridge for short) and a low-temperature DC current comparator bridge (CCC bridge for short). Among them, the measurement accuracy of the DCC bridge is generally 10 -7 ~10 -8 The measurement accuracy of CCC bridge is generally 10 -9 ~10 -10 The DC current comparator bridge itself has the ability to track the current of the master and slave loops, so it is generally used with an accuracy of 10 -4 ~10 -5 The master and slave current sources with the same level of accuracy can obtain a current ratio value with higher accuracy, which can meet the requirements of 10 -7 ~10 -8 Measurement of resistance ratios with order of magnitude accuracy.

[0003] However, with the development of science and technology and industry, its application field is expanding. Since the DC current comparator bridge can set the current value and the measured resistance value at the same time, it can easily realize the resistance scanning measurement with the current load as the independent variable, so it has been used to measure the load factor of precision resistors. In this application scenario, there is a problem of mismatch between the current accuracy and the resistance measurement accuracy, that is, of the two parameters (current value and resistance value) used to calculate the resistor load factor, the current value accuracy is significantly lower than the resistance value measurement accuracy, thereby limiting the accuracy of the final measurement result to the accuracy of the current source. Summary of the invention

[0004] In order to solve the problem of mismatch between the current value accuracy and the resistance value measurement accuracy in the current comparator bridge, the present application provides a DC current comparator bridge and a current source calibration method thereof to improve the accuracy of the current value output by the current source.

[0005] To achieve the above objectives, this application provides the following solutions.

[0006] On the one hand, the present application provides a DC current comparator bridge, comprising: a main current source, a slave current source, a standard resistance terminal, a resistance terminal to be measured, an iron core, a main circuit integer turn adjustable winding, an integer turn switch matrix, an integer turn drive module, a main circuit fractional turn adjustable winding, a fractional turn switch matrix, a fractional turn drive module, a slave circuit fixed turn winding, a differential compensation module, a modulation module, a demodulation module, a conditioning module, an ADC and a control module; the modulation module comprises a modulation circuit and a modulation dedicated winding; the demodulation module comprises a demodulation dedicated winding and a demodulation circuit;

[0007] The control module is respectively connected to the main current source, the slave current source, the integer turn driving module, the fractional turn driving module, the micro-difference compensation module and the ADC;

[0008] The main current source includes a reference DAC and a transconductance amplifier; the reference DAC receives a code value from a control module and outputs a voltage corresponding to the code value to the transconductance amplifier; the transconductance amplifier converts a voltage signal output by the reference DAC into a current signal; the sampling resistor in the transconductance amplifier is switched by a switch to realize current gear switching; the structure of the slave current source is the same as that of the main current source;

[0009] The standard resistor terminal and the slave loop fixed turns winding are connected in the slave loop where the slave current source is located; the standard resistor terminal is used to connect an external standard resistor, a standard resistor replacement relay or a slave loop standby resistor;

[0010] The resistor to be measured connection terminal, the main circuit integer-turn adjustable winding, the main circuit fractional-turn adjustable winding and the differential compensation module are connected in the main circuit where the main current source is located; the resistor to be measured connection terminal is used to connect an external resistor to be measured, a resistor to be measured replacing a relay or a main circuit standby resistor;

[0011] The iron core is used for winding the main circuit integer-turn adjustable winding, the main circuit fractional-turn adjustable winding, the slave circuit fixed-turn winding, the modulation-specific winding and the demodulation-specific winding;

[0012] The integer-turn switch matrix is ​​connected to the integer-turn drive module and the integer-turn adjustable winding of the main circuit respectively; the integer-turn drive module is used to provide a drive signal to the integer-turn switch matrix under the control instruction of the control module, so as to connect the windings with different turns of the integer-turn adjustable winding of the main circuit to the main circuit;

[0013] The fractional-turn switch matrix is ​​respectively connected to the fractional-turn drive module and the main circuit fractional-turn adjustable winding; the fractional-turn drive module is used to provide a drive signal to the fractional-turn switch matrix under the control instruction of the control module, so as to connect the windings with different turns of the main circuit fractional-turn adjustable winding to the main circuit;

[0014] The differential compensation module is used to extract the main circuit current from the main circuit and output it to the main circuit fractional turn adjustable winding after proportional attenuation;

[0015] The modulation circuit is connected to the modulation dedicated winding; the modulation module is used to modulate the residual magnetic flux in the iron core to generate a modulated detection signal;

[0016] The demodulation circuit is connected to the demodulation dedicated winding; the demodulation module is used to demodulate the modulated detection signal into a DC voltage signal;

[0017] The conditioning module is connected to the demodulation circuit and the ADC respectively; the conditioning module is used to filter and amplify the DC voltage signal output by the demodulation module, and output the conditioned voltage signal to the ADC;

[0018] The ADC is used to sample the conditioned voltage signal and send the sampled data to the control module;

[0019] The control module is used to calculate the correction values ​​corresponding to the main current source and the slave current source according to the sampled data, and to correct the code values ​​received by the main current source and the slave current source based on the correction values ​​to complete the self-calibration of the main current source and the slave current source.

[0020] Optionally, the reference DAC uses a single DAC device.

[0021] Optionally, the reference DAC adopts a composite DAC composed of a dual DAC and a proportional adder; the dual DAC includes a first DAC and a second DAC, which are respectively denoted as DACa and DACb.

[0022] On the other hand, the present application also provides a current source calibration method for a DC current comparator bridge, which is applied to the DC current comparator bridge; the current source calibration method comprises:

[0023] Step 1, switching the integer-turn switch matrix so that the integer turns of the integer-turn adjustable winding of the main circuit are equal to the fixed turns of the fixed-turn winding of the slave circuit; switching the fractional-turn switch matrix so that the fractional turns of the fractional-turn adjustable winding of the main circuit are 0;

[0024] Step 2, switch the main current source and the slave current source to the same current gear, short-circuit the terminals of the resistor to be measured through the resistor to be measured instead of the relay or connect them to the main circuit standby resistor, and short-circuit the terminals of the standard resistor through the standard resistor instead of the relay or connect them to the slave circuit standby resistor;

[0025] Step 3: The reference DAC of the main current source is recorded as DAC1, and the reference DAC of the slave current source is recorded as DAC2. The number of bits of DAC1 and DAC2 is recorded as NHigh N H and low N L Two parts, initializing all of DAC1 and DAC2 N The bit value is 0;

[0026] Step 4: Refresh the output voltages of DAC1 and DAC2 according to the currently received code value. Driven by the output voltages of DAC1 and DAC2, the main current source and the slave current source output current to the main loop and the slave loop respectively.

[0027] Step 5: Read the sampled data through ADC, and record the reading as , where the subscript Indicates the current high-order code value of DAC1. Indicates the current high-order code value of DAC2; ;

[0028] Step 6: If the current , go to step 7; if the current , then end this round of loop and jump to step 8;

[0029] Step 7: If the current = , increase the code value of DAC1 by 1, that is = +1, keep it up unchanged; otherwise, increase the code value of DAC2 by 1, that is, = +1, at the same time No change; jump to step 4;

[0030] Step 8: After this cycle ends, the ADC collects sampling data, denoted as ;

[0031] Step 9: Take The first The sampling data are grouped in pairs according to the order of front and back, and the difference between each adjacent two sampling data is calculated by subtracting the previous value from the next value in each group. ;in Value 0~ and is an integer, and the total indivual ;

[0032] Step 10: indivual Sum and calculate ;

[0033] Step 11: According to and Calculate the DNL error between adjacent code values ​​of DAC2 high bit ;

[0034] Step 12: Calculate the correction value of DAC2 ;

[0035] Step 13: Take The latter of the sampled data The sampling data are grouped in pairs according to the order of front and back, and the difference between each adjacent two sampling data is calculated by subtracting the previous value from the next value in each group. ;in Value 1~ , a total of indivual ;

[0036] Step 14: indivual Sum and calculate ;

[0037] Step 15: and Calculate the DNL error between adjacent code values ​​of DAC1 high bit ;

[0038] Step 16: Calculate the correction value of DAC1 ;

[0039] Step 17: When the DC current comparator bridge is in normal measurement mode, use the correction value and The code values ​​received by the master current source and the slave current source are modified respectively.

[0040] Optionally, the step 11, according to and Calculate the DNL error between adjacent code values ​​of DAC2 high bit , specifically including:

[0041] .

[0042] Optionally, the step 12, according to Calculate the correction value of DAC2 , specifically including:

[0043] .

[0044] Optionally, the step 15, according to and Calculate the DNL error between adjacent code values ​​of DAC1 high bit , specifically including:

[0045] .

[0046] Optionally, the step 16, according to Calculate the correction value of DAC1 , specifically including:

[0047] .

[0048] Optionally, in step 3, the number of bits of DAC1 and DAC2 is N High N H and low N L Two parts, including:

[0049] When the reference DAC uses a single DAC device, according to the formula Determine the number of digits N Low in N L , the rest are high N H ;in INL is the maximum integral nonlinearity error of the reference DAC.

[0050] Optionally, in step 3, the number of bits of DAC1 and DAC2 is N High N H and low N L Two parts, including:

[0051] When the reference DAC uses a composite DAC consisting of a dual DAC and a proportional adder, if the resistance ratio of the proportional adder is 1 / 2 m , then the effective number of DACa is taken as the high bit N H ,Will m As a low N L , the total number of digits is N = N H + N L Reference DAC.

[0052] According to the specific embodiments provided in this application, this application discloses the following technical effects:

[0053] The present application provides a DC current comparator bridge and a current source calibration method thereof. Through a control module built into the DC current comparator bridge, correction values ​​corresponding to the master and slave current sources are calculated according to ADC sampling data, and the correction values ​​are used to correct the current source output in the conventional measurement mode. The nonlinear error of the overall output of the current source can be reduced to within 1LSB, greatly improving the accuracy of the current value of the current source output. BRIEF DESCRIPTION OF THE DRAWINGS

[0054] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0055] Figure 1 It is a schematic diagram of the basic structure of the DC current comparator bridge;

[0056] Figure 2 A schematic diagram of a current source structure using a single DAC device for reference DAC;

[0057] Figure 3 The schematic diagram of the current source structure of the composite DAC is used as the reference DAC. DETAILED DESCRIPTION

[0058] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0059] In order to improve the accuracy of the current source in a DC current comparator bridge, the present application provides a DC current comparator bridge and a current source calibration method thereof. The method is implemented by a control module built into the DC current comparator bridge, and the current source output in the conventional measurement mode is corrected using self-calibration data (correction value), thereby improving the accuracy of the current parameters in the DC current comparator bridge.

[0060] In order to make the above-mentioned objects, features and advantages of the present application more obvious and easy to understand, the present application is further described in detail below in conjunction with the accompanying drawings and specific implementation methods.

[0061] like Figure 1As shown, in an exemplary embodiment, the present application provides a DC current comparator bridge (hereinafter referred to as a bridge), including: a main current source, a slave current source, a standard resistor terminal, a resistor terminal to be measured, an iron core T , Integer turns adjustable winding of main circuit W 11 , integer-turn switch matrix, integer-turn drive module, main circuit fractional-turn adjustable winding W 12 , fractional-turn switch matrix, fractional-turn drive module, fixed-turn winding from the loop W 2. Micro-difference compensation module, modulation module, demodulation module, conditioning module, ADC and control module. The modulation module includes a modulation circuit and a dedicated modulation winding. W m The demodulation module includes a dedicated demodulation winding W d In other embodiments, the DC current comparator bridge may further include an unbalanced voltage detection module and / or an optical isolation module.

[0062] The control module is respectively connected to the main current source, the slave current source, the integer turn driving module, the fractional turn driving module, the differential compensation module and the ADC. In other embodiments, the control module is also respectively connected to the unbalanced voltage detection module and / or the optical isolation module.

[0063] like Figure 2 and Figure 3 As shown, the main current source is mainly composed of a reference DAC (Digital-to-Analog Converter) and a transconductance amplifier. The reference DAC described in this application can be used Figure 2 The single DAC device shown in Figure 3 The composite DAC is composed of a dual DAC and a proportional adder as shown in FIG. The dual DAC includes a first DAC and a second DAC, which are respectively denoted as DACa and DACb. The reference DAC receives control instructions and code values ​​from a control module, and outputs a code value corresponding to a voltage. To the transconductance amplifier. The transconductance amplifier converts the voltage signal output by the reference DAC into a current signal. The sampling resistor in the transconductance amplifier can be switched by a switch to achieve current gear switching. The structure of the slave current source is the same as that of the master current source.

[0064] Figure 2 and Figure 3In the exemplary embodiment shown, the input end of the transconductance amplifier uses an operational amplifier Q1 to form a buffer circuit to achieve impedance matching of the front-stage and rear-stage circuits. The rear-stage buffer circuit is connected to the ground in parallel with capacitors C1 and C2 to filter the front-stage signal to reduce noise. Operational amplifiers Q2, Q3, sampling resistors Ra, Rb, Rc, and resistors R1, R2, R3, and R4 with equal resistance values ​​together form a Holland current source circuit to convert the output voltage of the buffer circuit into current for output. The output point of the current is the common connection point of the sampling resistors Ra, Rb, and Rc.

[0065] The sampling resistors in the transconductance amplifier are Ra, Rb and Rc. By controlling the multiple-select switch S0, only one sampling resistor among Ra, Rb or Rc is connected to the circuit at any time. Since the output current is equal to ,in is the voltage at the input of the sampling resistor, It is the resistance value of the sampling resistor connected to the circuit in Ra, Rb or Rc. Therefore, if the resistance value of Ra, Rb or Rc is selected in decimal form, the current gear can be switched by switching the sampling resistor. Of course, in practical applications, the transconductance amplifier is not limited to this circuit form, and other circuit forms can also be used to realize the function of the transconductance amplifier; the gear selection is not limited to three gears, and it can be designed according to the needs.

[0066] The control module can send control instructions to the DAC to configure the parameters of the DAC device. For example, the output range and polarity of the DAC device can be configured. When the DAC parameters are configured in advance, the control module sends the code value to the DAC, and the DAC can convert the code value into voltage for output according to the configured parameters and output characteristics (the conversion formula specified by the device itself).

[0067] Figure 3 In the composite DAC circuit structure shown, the proportional adder is composed of an operational amplifier Q4 and four high-precision resistors R5, R6, R7 and R8. The components in the composite DAC circuit structure have the following relationship:

[0068] .

[0069] If you set , then:

[0070] .

[0071] in , , and They are the resistance values ​​of four high-precision resistors R5, R6, R7 and R8 respectively. is the voltage output by the reference DAC; and are the output amplitude voltages of DACa and DACb respectively.

[0072] In the resistance configuration, if the resistance ratio , then ;in Is a positive integer.

[0073] Generally, DACa and DACb can select DAC devices with the same specifications, with the same output range and resolution. Then the total output voltage of the dual DAC after being synthesized by the proportional adder is , which is equivalent to the output amplitude voltage attenuation of DACa After multiples, it is synthesized with DACa. This is equivalent to DACa giving the high bit of the total output voltage signal N H DACb gives the low bit of the total output voltage signal N L Compared with a single DAC output, the composite DAC increases the adjustable resolution by times. Converted to binary, it is 2 m , m Also a positive integer.

[0074] The structure of the slave current source is the same as that of the master current source. In this application, both the master and slave current sources are calibrated objects.

[0075] like Figure 1 As shown in the figure, when the DC current comparator bridge is in the normal measurement mode, the standard resistor terminal is used to connect the external standard resistor R s , that is, the standard resistor terminal block is Figure 1 R s The four circles at both ends indicate whether the standard resistor terminal is connected to R s This has no impact on the current source calibration method of the present application, that is, the self-calibration process can be completed when the standard resistor terminals are left hanging.

[0076] like Figure 1 As shown, the standard resistor terminal and the fixed turns winding from the loop W 2 is connected to the slave loop where the slave current source is located. When calibrating the current source, the standard resistor terminal is used to connect the standard resistor to replace the relay or the slave loop standby resistor R z .

[0077] When the DC current comparator bridge is in normal measurement mode, the resistor terminal is used to connect the external resistor R x , that is, the resistance to be measured is connected to the terminal Figure 1 R x The four circles at both ends indicate whether the terminals of the resistor to be tested are connected to R x This has no impact on the current source calibration method of the present application, that is, the self-calibration process can be completed when the terminals of the resistor to be measured are suspended.

[0078] like Figure 1 As shown, the resistance terminal to be measured and the main circuit integer turn adjustable winding W 11 , the main circuit fractional turns adjustable winding W 12 The differential compensation module is connected to the main circuit where the main current source is located. When calibrating the current source, the resistor to be measured terminal is used to connect the resistor to be measured to replace the relay or the main circuit standby resistor R y .

[0079] The standby resistor refers to the resistor R connected in parallel to the standard resistor R s Or the resistance to be measured R x The resistors at the positions correspond to the standby resistors R z And the main circuit standby resistor R y , which can avoid the current source open circuit fault in the master and slave circuits when the external resistor is not connected. When calibrating the current source, the master and slave circuits can be switched to the standby resistor, so there is no need to connect the standard resistor R s and the resistance to be measured R x According to circuit theory, the current source must not be open-circuited. When there is no standby resistor, the standard resistor or the resistor to be measured is not connected, which will cause the current source to be open-circuited and damage the circuit. The standby resistor can ensure that when the standard resistor or the resistor to be measured is not connected, it can switch to the standby resistor to ensure that the current source is not open-circuited. It should be noted that the DCC generally has a standby resistor inside to achieve this operation. If there is no standby resistor, you can use the bridge arm resistor (that is, the standard resistor R s Or the resistance to be measured R x ) are provided with relays at both ends and controlled to be short-circuited, which are respectively referred to as standard resistance replacement relay and resistance replacement relay to be tested in the present embodiment. Specifically, the control module sends a control signal, which can make the moving contact of the relay change from R s or R x Switch the connection line to R z or R y For example, by closing the moving contact S of the relay 11 , S 12 And disconnect R x The resistance terminals to be tested at both ends can switch the main circuit to R y On the connecting line; through the moving contact S of the closing relay21 , S 22 And disconnect R s Standard resistor terminals at both ends can be switched from the loop to R z If there is no standby resistor, connect the relay's moving contact from R s or R x The connection line of the resistor to be tested should be switched to the connection line of the standard resistor replacement relay or the resistor to be tested replacement relay.

[0080] The iron core T Used to wind the main circuit integer turn adjustable winding W 11 , Main circuit fractional turns adjustable winding W 12 , Fixed number of turns winding from the loop W 2. Modulation dedicated winding W m And the demodulation dedicated winding W d In the embodiment of the present application, the circuit through which the output current of the main current source flows is called the main circuit, which includes the main current source, the resistance to be measured R x , Integer turns adjustable winding of main circuit W 11 , differential compensation module, main circuit fractional turns adjustable winding W 12 The circuit through which the output current from the current source flows is called the slave circuit, which includes the slave current source and the fixed-turn winding of the slave circuit. W 2. Standard resistance R s wait.

[0081] Among them, the main circuit integer turns adjustable winding W 11 It is an integer-turn winding connected in series in the main circuit with an adjustable number of turns. Its function is to adjust the current in the main circuit in the iron core by changing the integer number of turns. T The magnetic flux generated in the main circuit. W 12 It is a winding with adjustable number of turns connected in series in the output circuit of the differential compensation module. Its function is to fine-tune the main circuit current in the iron core by changing the fractional number of turns. T The magnetic flux generated in the fixed number of turns winding W 2 is the winding connected in series in the slave circuit, with a fixed number of turns, which is used to make the slave circuit current flow in the core. T Generates magnetic flux in the modulation dedicated winding W m The role is in the iron core T The modulated flux signal is generated in the master and slave circuits. W 11 , W12 , W 2. The current in the iron core T The magnetic flux generated in the circuit cancels each other out, and the remaining magnetic flux is modulated by a dedicated winding. W m Modulation, demodulation dedicated winding W d The induced electromotive force is induced in the circuit, and the voltage signal proportional to the residual magnetic flux is restored through the demodulation circuit. After the conditioning module matches the input range of the ADC, the ADC finally collects the signal and digitizes it, and then transmits it to the control module as sampling data.

[0082] Integer turns adjustable winding in main circuit W 11 A switch matrix is ​​required to realize whether windings with different turns are connected to the main circuit. The switch matrix is ​​generally composed of multiple relays, and the drive module provides the drive signal for the switch matrix. W 11 The switch matrix and its driving module are respectively called integer-turn switch matrix and integer-turn driving module. Figure 1 As shown, the integer-turn switch matrix is ​​connected to the integer-turn drive module and the integer-turn adjustable winding of the main circuit respectively. W 11 The integer-turn driving module is used to provide a driving signal for the integer-turn switch matrix under the control instruction of the control module to switch the integer-turn adjustable winding of the main circuit. W 11 Windings with different numbers of turns are connected to the main circuit.

[0083] Similarly, the main circuit fractional turn adjustable winding W 12 A switch matrix is ​​also required to realize whether windings with different turns are connected to the main circuit. The switch matrix is ​​generally composed of multiple relays, and the drive module provides the drive signal for the switch matrix. W 12 The switch matrix and its driving module are respectively called fractional-turn switch matrix and fractional-turn driving module. Figure 1 As shown, the fractional-turn switch matrix is ​​connected to the fractional-turn drive module and the main circuit fractional-turn adjustable winding respectively. W 12 The fractional-turn driving module is used to provide a driving signal to the fractional-turn switch matrix under the control instruction of the control module, so as to switch the fractional-turn adjustable winding of the main circuit. W 12 Windings with different numbers of turns are connected to the main circuit.

[0084] The differential compensation module is used to extract the main circuit current from the main circuit and output it to the main circuit fractional turn adjustable winding after proportional attenuation. W 12 The differential compensation module can be roughly divided into passive compensator form and active compensator form.

[0085] In the modulation module, the modulation circuit and the modulation dedicated winding W m The modulation module is used to modulate the internal part of the DC current comparator bridge, i.e. the core T The residual magnetic flux in the sensor is modulated to generate a modulated detection signal.

[0086] In the demodulation module, the demodulation circuit and the demodulation dedicated winding W d Connection; the demodulation module is used to demodulate the detection signal modulated by the DC current comparator bridge into a DC voltage signal.

[0087] The conditioning module is connected to the demodulation circuit and the ADC respectively. The conditioning module is used to filter and amplify the DC voltage signal output by the demodulation module, and output the conditioned voltage signal to the ADC.

[0088] The ADC (Analog-to-Digital Converter) is used to sample the conditioned voltage signal and send the sampled data to the control module. In the conventional measurement mode of the DC current comparator bridge, the sampled data is used for feedback control so that the slave loop can track the main loop current. When the current source is calibrated, the control module is used to calculate the correction values ​​corresponding to the main current source and the slave current source based on the sampled data, and correct the code values ​​received by the main current source and the slave current source based on the correction values ​​to complete the self-calibration process of the main current source and the slave current source.

[0089] The control module is generally an embedded processor, such as ARM, FPGA, etc. In the normal measurement mode, the generation and sending of control instructions such as current setting, feedback, switch switching, etc. are realized. When the current self-calibration is performed, the self-calibration process and correction algorithm are stored in the control module. After the user starts the corresponding function, the calibration process is automatically completed, the calibration data is stored, and the automatic correction of the current is realized after exiting the self-calibration mode.

[0090] because Figure 1 The upper and lower parts of the bridge shown use different power supply systems, so an optical isolation module is set up to isolate the control module from all the analog circuits above through optical signals to reduce the interference of the control module on the analog circuits.

[0091] The input of the unbalanced voltage detection module has two ends, which are respectively connected to the resistance to be measured R x And the standard resistor R s The voltage high end is connected to the x And the standard resistor R s Unbalanced voltage between.

[0092] In order to more clearly introduce the implementation scheme of the present application, the basic composition of the DC current comparator bridge is introduced above. Most modules of the DC current comparator bridge, such as differential compensation module, switch matrix, drive module, modulation module, demodulation module, conditioning module, etc., may be implemented in a specific system using different technical routes, which are not the focus of protection of this application. However, no matter what solution is used to implement these modules, their basic functions can meet the implementation of the current source calibration method of this application, and ultimately improve the accuracy of current output in the original system.

[0093] based on Figure 1 The DC current comparator bridge system structure shown in the figure, the present application also proposes a current source calibration method, including the following steps 1 to 17.

[0094] Step 1: Switch the integer-turn switch matrix to make the main circuit integer-turn adjustable winding W 11 The integer number of turns and the fixed number of turns from the loop winding W 2 is equal to the fixed number of turns; switch the fractional turn switch matrix to make the main circuit fractional turn adjustable winding W 12 The number of fractional turns is 0.

[0095] Specifically, the control module sends a control instruction to switch the integer turns of the main circuit adjustable winding. W 11 The integer-turn switch matrix makes the integer turns and the fixed turns winding from the loop W 2 have the same number of fixed turns, and the main circuit fractional turns adjustable winding is switched at the same time W 12 The fractional turn switch matrix of the main circuit is set to 0. The proportional error of the winding turns is much smaller than the calibrated current error. At this time, the master and slave current sources are connected through each winding in the iron core. T The induction generates magnetic flux and cancels it out, and the remaining magnetic flux is reflected as output voltage through the modulation module and the demodulation module.

[0096] Step 2: Switch the main current source and the slave current source to the same current range, and short-circuit the terminals of the resistor to be tested through the resistor to be tested instead of the relay or connect them to the main circuit standby resistor R y , short-circuit the standard resistor terminal through the standard resistor instead of the relay or connect the slave circuit standby resistor Rz .

[0097] It should be noted that since the transconductance amplifier may have different nonlinear characteristics in different gears, in order to obtain more accurate calibration data, it is recommended to perform the self-calibration process of the current source in all gears. In this embodiment, one gear is selected to illustrate the specific self-calibration method.

[0098] The bridge arm resistors (standard resistor R s and the resistance to be measured R x The current end of the DCC is short-circuited or connected to the internal standby resistor. It should be noted that the DCC generally has a standby resistor to achieve this operation. If not, the bridge arm resistor (i.e. the standard resistor R s Or the resistance to be measured R x ) Relays are set at both ends and controlled to short-circuit. The unbalanced voltage detection module is not used in the present application method. In order to avoid saturation caused by the unbalanced voltage generated during the self-calibration process, it is controlled to disconnect it from the bridge circuit at this time.

[0099] Step 3: The reference DAC of the main current source is recorded as DAC1, and the reference DAC of the slave current source is recorded as DAC2. The number of bits of DAC1 and DAC2 is recorded as N High N H and low N L two parts, and initializes DAC1 and DAC2 in their entirety N The bit value is 0.

[0100] The number of bits of the reference DAC N There are two options for segmentation.

[0101] Solution 1, when the reference DAC uses Figure 2 For a single DAC device as shown, according to the formula Determine the number of digits N Low in N L , the rest are high N H .in INL is the maximum integral nonlinearity error of the reference DAC. In other words, assuming the maximum integral nonlinearity error is INL , then take a value greater than its maximum integral nonlinear error INL The minimum number of digits is N L , and the rest are N H .

[0102] Solution 2: When the reference DAC uses a composite DAC consisting of a dual DAC and a proportional adder, such as Figure 3 As shown, the output voltages of the two DACs (DACa and DACb) are divided by 1 / M The resistance ratio of the proportional adder is set to M =1 / 2 m , then the effective number of DACa is taken as the high bit N H ,Will m As a low N L , the total number of digits is N = N H + N L The composite DAC is used as the reference DAC.

[0103] In the embodiment of the present application, a 16-bit single DAC device is used for illustration, that is, N =16, divided into high N H =14 and low N L =2 two parts. Digits N Refers to the number of binary bits of DAC, which is the basic parameter of DAC. High bits refer to bits with relatively large weights, and low bits refer to bits with relatively small weights. For example, the decimal number 1234 has 4 bits, the thousands and hundreds can be considered as high bits, and the tens and ones are low bits. Binary is similar. The code value is the value represented by the binary code. In scheme 2, DACa and DACb together constitute a composite DAC, and its high and low bits refer to the high and low bits of the composite DAC.

[0104] Step 4: Refresh the output voltages of DAC1 and DAC2 according to the currently received code value. Driven by the output voltages of DAC1 and DAC2, the main current source and the slave current source output current to the main loop and the slave loop respectively.

[0105] DAC stands for Digital-to-Analog Converter. Digital refers to the value represented by binary code, and analog refers to the voltage as an analog signal. The basic mode of DAC is that when a set of binary codes (referred to as code values ​​in this application) is input, DAC outputs a corresponding voltage. Every time a code value is input to the control module, the DAC output changes accordingly. Refresh is a name for this change.

[0106] Step 5: Read the sampled data through ADC, and record the reading as , where the subscript Indicates the current high-order code value of DAC1. Indicates the current high-order code value of DAC2; .

[0107] In the present application examples, the subscript Indicates the current high 14-bit code value of DAC1. Indicates the current high 14-bit code value of DAC2; .

[0108] Step 6: If the current , go to step 7; if the current , then end this round of loop and jump to step 8.

[0109] In the present application embodiment, 2 14 -1=16383. If the current , then execute step 7; if the current =16383, skip the next step and end this cycle.

[0110] Step 7: If the current = , increase the code value of DAC1 by 1, that is = +1, keep it up unchanged; otherwise, increase the code value of DAC2 by 1, that is, = +1, at the same time No change; jump to step 4.

[0111] The loop process changes the code values ​​of DAC1 and DAC2, that is, the code value of DAC1 is increased by 1 or the code value of DAC2 is increased by 1.

[0112] Step 8: After this cycle ends, the ADC collects sampling data, denoted as .

[0113] During the cycle and Alternately change, the end of this cycle satisfies the end condition of step 6, then just collect A numerical value.

[0114] Step 9: Take The first The sampling data are grouped in pairs according to the order of front and back, and the difference between each adjacent two sampling data is calculated by subtracting the previous value from the next value in each group. ;in Value 0~ and is an integer, and the total indivual .

[0115] In the same formula, The values ​​are the same. is a subscript number used to represent the sampled data obtained in step 8 in a unified form. For example, =0, equivalent to In the embodiment of the present application, in step 9 The value range is 0~16382, and a total of 16383 are calculated .

[0116] Step 10: indivual Sum and calculate .

[0117] Step 11: According to and Calculate the DNL error between adjacent code values ​​of DAC2 high bit ;Specifically, .

[0118] In the embodiment of the present application, in step 11 The value range is 0~16382, and a total of 16383 are calculated . That is, the upper 14 bits of DAC2 can represent the DNL error between adjacent code values. The DNL error value obtained by self-calibration , that is, in routine measurements, by setting a low N L =2-bit value to correct the DNL error of DAC2, thus obtaining a more accurate current output.

[0119] DNL (Differential Non-Linearity) error, full name is differential nonlinearity error. Since the self-calibration process uses the upper 14 bits, the error value is represented by the upper 14 bits. One unit of the lowest bit in the upper 14 bits is equal to 4 times (2 to the square of 2 times) one unit in the lower 2 bits. In other words, the voltage represented by the lower 2 bits is more detailed than that of the upper 14 bits. If the error value represented by the upper 14 bits has a decimal part, the lower 2 bits can be used to compensate for it more carefully.

[0120] Step 12: Calculate the correction value of DAC2 ;Specifically, .

[0121] Step 13: Take The latter of the sampled data The sampling data are grouped in pairs according to the order of front and back, and the difference between each adjacent two sampling data is calculated by subtracting the previous value from the next value in each group. ;in Value 1~ , a total of indivual .

[0122] In the embodiment of the present application, in step 13 The value range is 1 to 16383, and a total of 16383 are calculated Numeric value.

[0123] Step 14: indivual Sum and calculate .

[0124] Step 15: and Calculate the DNL error between adjacent code values ​​of DAC1 high bit ;Specifically, .

[0125] In the embodiment of the present application, in step 14 The value range is 1 to 16383, and a total of 16383 are calculated Numeric value. That is, the upper 14 bits of DAC1 can represent the DNL error between adjacent code values. The meaning is the same as above.

[0126] Step 16: Calculate the correction value of DAC1 ;Specifically, .

[0127] The correction value obtained from the self-calibration and Stored in the control module for use in normal measurement mode.

[0128] Step 17: When the DC current comparator bridge is in normal measurement mode, use the correction value and The code values ​​received by the master current source and the slave current source are modified respectively.

[0129] When the DC current comparator bridge is in normal measurement mode, after the user sets the test current through the control module, the current value is converted into the corresponding DAC setting code value by the control module. Assume that the user sets the setting code value of the corresponding DAC (for example, DAC1) of a current source to D 1, then follow steps 17.1 to 17.5 to correct the code value and then output it to the reference DAC. The correction process described below will correct the value and Subscript Specifically replaced by D 1 Hand D 1 L Equal values ​​are expressed.

[0130] Step 17.1. D 1 is split into 14 and 2 bits in binary, and the high 14 bits are recorded as D 1 H , the lower 2-bit code value is recorded as D 1 L .

[0131] Step 17.2: Query In ,calculate . It is a variable set to simplify expressions.

[0132] Step 17.3: If , execute step 17.4;

[0133] like <0, then let , and return to step 17.2 for execution;

[0134] like , then let , and return to step 17.2.

[0135] Step 17.4, take , and the current D 1 H Composition of the complete corrected code value D 11, that is .

[0136] Step 17.5, the control module sets the code value of DAC1 to D 11 and output, used to control the output voltage of DAC1.

[0137] When the current source reference DAC is a single DAC device, a 16-bit DAC device is used, and its technical manual gives an integral nonlinearity of less than ±2LSB. It should be noted that the overall nonlinear error of the current source output also includes the nonlinear error introduced by the subsequent transconductance amplifier. In this embodiment, this part is converted to a DAC output of less than ±1LSB. Therefore, the maximum integral nonlinear error of the current source as a whole is ±3LSB. According to the above method, the present application can reduce the nonlinear error of the overall output of the current source to within 1LSB. When the current source reference DAC is a composite DAC, it is equivalent to improving the resolution of the DAC, and more accurate data can be obtained through the self-calibration process.

[0138] According to the method of the above embodiment, the error of the current source in Scheme 1 can be reduced several times. If you want to get higher accuracy, you can use Scheme 2. In Scheme 2, the DAC in the current source is composed of two devices, DACa and DACb, combined by a proportional adder. In this embodiment, DACa and DACb use the same type of 14-bit DAC devices, and the nonlinear error is less than 1LSB. By setting the resistance ratio of the proportional adder M =1 / 2 m , so that the output voltage of DACa and DACb is 1 / 2 6 =1 / 64 ratio addition output, then N H =14, N L = m =6, the overall effective number of bits of the composite DAC is N =20 bits. It should be noted that in this solution 2, only the upper 6 bits of DACb are used, and the unused lower 8 bits can be set to zero. The subsequent self-calibration process and correction process are the same as those in solution 1 and will not be repeated here. By adopting the method of solution 2, the nonlinear error of the overall output of the current source can be reduced by dozens of times, that is, 1~2 orders of magnitude. Solution 2 improves the effective resolution of the DAC. When measuring and correcting errors, both can be operated with a resolution lower than 1LSB, so the effect of error correction can be improved.

[0139] This article uses specific examples to illustrate the principles and implementation methods of this application. The description of the above embodiments is only used to help understand the method and core ideas of this application. At the same time, for those skilled in the art, according to the ideas of this application, there will be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as limiting this application.

Claims

1. A DC current comparator bridge, characterized in that: include: A main current source, a slave current source, a standard resistance terminal, a resistance terminal to be measured, an iron core, an integer-turn adjustable winding of a main circuit, an integer-turn switch matrix, an integer-turn drive module, a fractional-turn adjustable winding of a main circuit, a fractional-turn switch matrix, a fractional-turn drive module, a fixed-turn winding of a slave circuit, a differential compensation module, a modulation module, a demodulation module, a conditioning module, an ADC and a control module; the modulation module includes a modulation circuit and a dedicated modulation winding; the demodulation module includes a dedicated demodulation winding and a demodulation circuit; The control module is respectively connected to the main current source, the slave current source, the integer turn driving module, the fractional turn driving module, the micro-difference compensation module and the ADC; The main current source includes a reference DAC and a transconductance amplifier; the reference DAC receives a code value from a control module and outputs a voltage corresponding to the code value to the transconductance amplifier; the transconductance amplifier converts a voltage signal output by the reference DAC into a current signal; the sampling resistor in the transconductance amplifier is switched by a switch to realize current gear switching; the structure of the slave current source is the same as that of the main current source; The standard resistor terminal and the slave loop fixed turns winding are connected in the slave loop where the slave current source is located; the standard resistor terminal is used to connect an external standard resistor, a standard resistor replacement relay or a slave loop standby resistor; The resistor to be measured connection terminal, the main circuit integer-turn adjustable winding, the main circuit fractional-turn adjustable winding and the differential compensation module are connected in the main circuit where the main current source is located; the resistor to be measured connection terminal is used to connect an external resistor to be measured, a resistor to be measured replacing a relay or a main circuit standby resistor; The iron core is used for winding the main circuit integer-turn adjustable winding, the main circuit fractional-turn adjustable winding, the slave circuit fixed-turn winding, the modulation-specific winding and the demodulation-specific winding; The integer-turn switch matrix is ​​connected to the integer-turn drive module and the integer-turn adjustable winding of the main circuit respectively; the integer-turn drive module is used to provide a drive signal to the integer-turn switch matrix under the control instruction of the control module, so as to connect the windings with different turns of the integer-turn adjustable winding of the main circuit to the main circuit; The fractional-turn switch matrix is ​​respectively connected to the fractional-turn drive module and the main circuit fractional-turn adjustable winding; the fractional-turn drive module is used to provide a drive signal to the fractional-turn switch matrix under the control instruction of the control module, so as to connect the windings with different turns of the main circuit fractional-turn adjustable winding to the main circuit; The differential compensation module is used to extract the main circuit current from the main circuit and output it to the main circuit fractional turn adjustable winding after proportional attenuation; The modulation circuit is connected to the modulation dedicated winding; the modulation module is used to modulate the residual magnetic flux in the iron core to generate a modulated detection signal; The demodulation circuit is connected to the demodulation dedicated winding; the demodulation module is used to demodulate the modulated detection signal into a DC voltage signal; The conditioning module is connected to the demodulation circuit and the ADC respectively; the conditioning module is used to filter and amplify the DC voltage signal output by the demodulation module, and output the conditioned voltage signal to the ADC; The ADC is used to sample the conditioned voltage signal and send the sampled data to the control module; The control module is used to calculate the correction values ​​corresponding to the main current source and the slave current source according to the sampled data, and to correct the code values ​​received by the main current source and the slave current source based on the correction values ​​to complete the self-calibration of the main current source and the slave current source.

2. The DC current comparator bridge according to claim 1, characterized in that: The reference DAC uses a single DAC device.

3. The DC current comparator bridge according to claim 1, characterized in that: The reference DAC adopts a composite DAC composed of a dual DAC and a proportional adder; the dual DAC includes a first DAC and a second DAC, which are respectively denoted as DACa and DACb.

4. A method for calibrating a current source of a DC current comparator bridge, characterized in that: A DC current comparator bridge applied to any one of claims 1 to 3; the current is derived from a calibration method comprising: Step 1, switching the integer-turn switch matrix so that the integer turns of the integer-turn adjustable winding of the main circuit are equal to the fixed turns of the fixed-turn winding of the slave circuit; switching the fractional-turn switch matrix so that the fractional turns of the fractional-turn adjustable winding of the main circuit are 0; Step 2, switch the main current source and the slave current source to the same current gear, short-circuit the terminals of the resistor to be measured through the resistor to be measured instead of the relay or connect them to the main circuit standby resistor, and short-circuit the terminals of the standard resistor through the standard resistor instead of the relay or connect them to the slave circuit standby resistor; Step 3: The reference DAC of the main current source is recorded as DAC1, and the reference DAC of the slave current source is recorded as DAC2. The number of bits of DAC1 and DAC2 is recorded as N High N H and low N L Two parts, initializing all of DAC1 and DAC2 N The bit value is 0; Step 4: Refresh the output voltages of DAC1 and DAC2 according to the currently received code value. Driven by the output voltages of DAC1 and DAC2, the main current source and the slave current source output current to the main loop and the slave loop respectively. Step 5: Read the sampled data through ADC, and record the reading as , where the subscript Indicates the current high-order code value of DAC1. Indicates the current high-order code value of DAC2; ; Step 6: If the current , go to step 7; if the current , then end this round of loop and jump to step 8; Step 7: If the current = , increase the code value of DAC1 by 1, that is = +1, keep it up unchanged; otherwise, increase the code value of DAC2 by 1, that is, = +1, at the same time No change; jump to step 4; Step 8: After this cycle ends, the ADC collects sampling data, denoted as ; Step 9: Take The first The sampling data are grouped in pairs according to the order of front and back, and the difference between each adjacent two sampling data is calculated by subtracting the previous value from the next value in each group. ;in Value 0~ and is an integer, and the total indivual ; Step 10: indivual Sum and calculate ; Step 11: According to and Calculate the DNL error between adjacent code values ​​of DAC2 high bit ; Step 12: Calculate the correction value of DAC2 ; Step 13: Take The latter of the sampled data The sampling data are grouped in pairs according to the order of front and back, and the difference between each adjacent two sampling data is calculated by subtracting the previous value from the next value in each group. ;in Value 1~ , a total of indivual ; Step 14: indivual Sum and calculate ; Step 15: and Calculate the DNL error between adjacent code values ​​of DAC1 high bit ; Step 16: Calculate the correction value of DAC1 ; Step 17: When the DC current comparator bridge is in normal measurement mode, use the correction value and The code values ​​received by the master current source and the slave current source are modified respectively.

5. The current source calibration method according to claim 4, characterized in that: The step 11, according to and Calculate the DNL error between adjacent code values ​​of DAC2 high bit , specifically including: 。 6. The current source calibration method according to claim 4, characterized in that: Step 12, according to Calculate the correction value of DAC2 , specifically including: 。 7. The current source calibration method according to claim 4, characterized in that: Step 15, according to and Calculate the DNL error between adjacent code values ​​of DAC1 high bit , specifically including: 。 8. The current source calibration method according to claim 4, characterized in that: Step 16, according to Calculate the correction value of DAC1 , specifically including: 。 9. The current source calibration method according to claim 4, characterized in that: In step 3, the number of bits of DAC1 and DAC2 is N High N H and low N L Two parts, including: When the reference DAC uses a single DAC device, according to the formula Determine the number of digits N Low in N L , the rest are high N H ;in INL is the maximum integral nonlinearity error of the reference DAC.

10. The current source calibration method according to claim 4, characterized in that: In step 3, the number of bits of DAC1 and DAC2 is N High N H and low N L Two parts, including: When the reference DAC uses a composite DAC consisting of a dual DAC and a proportional adder, if the resistance ratio of the proportional adder is 1 / 2 m , then the effective number of DACa is taken as the high bit N H ,Will m As a low N L , the total number of digits is N = N H + N L Reference DAC.

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