Method and device for improving design efficiency of TFT (Thin Film Transistor) semiconductor device

Abstract

The invention belongs to the technical field of semiconductor device design and simulation, and provides a method and a device for improving the design efficiency of a TFT (Thin Film Transistor) semiconductor device. The method comprises the following steps: S1, obtaining design data of a geometric model of a TFT semiconductor device, wherein the model comprises geometric models of a plurality of device assemblies; s2, boundary conditions, material attributes and grid generation control parameters are given to the geometric model of each device assembly; s3, performing primary processing on the geometric model to obtain a base grid; s4, generating a coarse grid according to the generated base grid and the parameters of the geometric model; s5, carrying out mesh refinement on a region with a small angle in the coarse mesh by adopting a concentric shell segmentation strategy to generate a fine mesh; and S6, inputting the generated fine grids into a device simulation solver for solving, and adjusting design data according to a solving result. According to the method, the design efficiency is improved and the design period is remarkably shortened through fine grid division and an optimized simulation process.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor device design and simulation, and in particular to a method and device for improving the design efficiency of TFT semiconductor devices. Background Art

[0002] Thin Film Transistor (TFT) is a semiconductor device. TFT display screen is the mainstream display device on various laptops and desktops. Each liquid crystal pixel on this type of display screen is driven by a thin film transistor integrated behind the pixel, so TFT display screen is also a type of active matrix liquid crystal display device. It is one of the best LCD color displays. TFT display has the advantages of high responsiveness, high brightness, high contrast, etc., and its display effect is close to that of CRT display.

[0003] In the design process of TFT semiconductor devices, accurate simulation of device performance is crucial for optimizing the design. The simulation of device performance is achieved by establishing a discrete mathematical model based on the mesh obtained by device segmentation. The quality of the generated mesh has a decisive influence on the accuracy of the simulated device performance. However, due to the limitation of the principle, the mesh segmentation method used in traditional device design is prone to segmentation failure due to dead loops. To avoid this problem, relaxing the generation accuracy of the mesh will lead to unreasonable mesh division, which will lead to problems such as inaccurate simulation calculations, resulting in low design efficiency.

[0004] Therefore, it is particularly important to develop a method that can effectively improve design efficiency and ensure simulation accuracy. Summary of the invention

[0005] In view of this, an embodiment of the present invention provides a method and apparatus for improving the design efficiency of a TFT semiconductor device. The method achieves a dual improvement in design efficiency and simulation accuracy through fine grid division and optimized simulation process.

[0006] In a first aspect, an embodiment of the present invention provides a method for improving the design efficiency of a TFT semiconductor device, comprising the following steps: S1: Acquire design data of a geometric model of a TFT semiconductor device, wherein the geometric model of the TFT semiconductor device includes geometric models of several device components; S2: assigning boundary conditions, material properties and geometric model mesh generation control parameters to the geometric model of each device component; S3: Preliminarily processing the geometric model of the TFT semiconductor device to obtain a substrate grid; S4: generating a coarse mesh of the TFT semiconductor device according to the generated substrate mesh and the boundary conditions, material properties, and mesh generation control parameters of the geometric model of the TFT semiconductor device; S5: using a concentric shell segmentation strategy to refine the mesh in the region where a small angle appears in the coarse mesh, so as to generate a fine mesh; S6: inputting the generated fine grid into a device simulation solver for solving, and adjusting the design data of the TFT semiconductor device according to the solution result.

[0007] According to a specific implementation manner of the embodiment of the present invention, the device component is a gate, a drain or an insulating layer, etc.

[0008] According to a specific implementation method of an embodiment of the present invention, in step S2, the boundary conditions include metal-semiconductor boundary, metal-metal boundary, metal-insulator boundary, semiconductor-semiconductor boundary, semiconductor-insulator boundary, applied voltage, applied current, etc.; the material properties include doping type and concentration, defect model and its corresponding parameters, dielectric constant, mobility model and its corresponding parameters, etc.; the geometric model mesh generation control parameters include mesh unit type, mesh minimum size, mesh gradient coefficient, etc.

[0009] According to a specific implementation method of an embodiment of the present invention, in step S3, the preliminary processing includes interference analysis, component position adjustment, feature parameter adjustment, and construction of a topological model based on the geometric model and calculation properties of the TFT semiconductor device; the topological model generates control parameters according to the geometric model grid, discretizes the geometric model of the TFT semiconductor device, and obtains a base grid.

[0010] According to a specific implementation method of an embodiment of the present invention, in step S3, the base grid is further optimized, and the optimization includes performing regional decomposition on the base grid to obtain multiple sub-regions, and performing discretization according to the characteristics of the edges on the boundaries of each sub-region.

[0011] According to a specific implementation of an embodiment of the present invention, in step S4, the coarse grid includes a point grid, a line grid, a surface grid and a volume grid, which are respectively generated based on geometric points, geometric lines, geometric surfaces and a topological model in the base grid.

[0012] According to a specific implementation of an embodiment of the present invention, in step S5, the concentric shell segmentation strategy is specifically: taking the shared vertex of the line mesh in the small angle area as the center, and constructing concentric circle shells with a radius of 2 as the segmentation point. Analyze the coarse grid data to identify the small angle grid area; use the improved grid refinement algorithm to segment the line mesh in the small angle area in a non-central way, and use the concentric circle shells as the segmentation point, effectively preventing the generation of dead loops and improving the grid quality.

[0013] According to a specific implementation of the embodiment of the present invention, in step S6, the simulation solver is used to perform simulation calculations on the fine grid and output device performance parameters.

[0014] In a second aspect, an embodiment of the present invention provides a device for improving the design efficiency of a TFT semiconductor device, comprising: An acquisition module, used for acquiring design data of a geometric model of a TFT semiconductor device, wherein the geometric model of the TFT semiconductor device includes geometric models of several device components; An assignment module, used to assign boundary conditions, material properties and geometric model mesh generation control parameters to the geometric model of each device component; A processing module, used for preliminarily processing the geometric model of the TFT semiconductor device to obtain a substrate grid; A coarse mesh module, used to generate a coarse mesh of the TFT semiconductor device according to the generated substrate mesh and the boundary conditions, material properties, and mesh generation control parameters of the geometric model of the TFT semiconductor device; A fine grid module, used to refine the grid by adopting a concentric shell segmentation strategy for the area with small angles in the coarse grid to generate a fine grid; A solving module is used to input the generated fine grid into a device simulation solver for solving, and adjust the design data of the TFT semiconductor device according to the solving result.

[0015] In a third aspect, an embodiment of the present invention further provides an electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein when the processor executes the program, the steps of the method for improving the design efficiency of TFT semiconductor devices in the aforementioned first aspect or any implementation method of the first aspect are implemented.

[0016] The embodiments of the present invention have at least the following technical effects: First, the present invention improves design efficiency and significantly shortens the design cycle through fine grid division and optimized simulation process.

[0017] Second, the improved mesh refinement algorithm of the present invention effectively solves the problem of unstable simulation in small-angle areas and improves the accuracy of simulation results.

[0018] Third, the timely feedback of the simulation results of the present invention provides strong support for device design and enhances the flexibility and adjustability of the design. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] In order to more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the following is a brief introduction to the drawings required for the specific embodiments or the description of the prior art. In all the drawings, similar elements or parts are generally identified by similar reference numerals. In the drawings, the elements or parts are not necessarily drawn according to the actual scale.

[0020] Figure 1 A flow chart showing a method for improving the design efficiency of a TFT semiconductor device provided by an embodiment of the present invention; Figure 2 A schematic diagram of concentric shell segmentation in an embodiment of the present invention is shown; Figure 3 A structural block diagram of a device for improving the design efficiency of a TFT semiconductor device provided by an embodiment of the present invention is shown; Figure 4 A schematic structural diagram of an electronic device provided by an embodiment of the present invention is shown. DETAILED DESCRIPTION

[0021] The following embodiments of the technical solution of the present invention are described in detail in conjunction with the accompanying drawings. The following embodiments are only used to more clearly illustrate the technical solution of the present invention, and are therefore only used as examples, and cannot be used to limit the protection scope of the present invention.

[0022] It should be noted that, unless otherwise specified, the technical terms or scientific terms used in this application should have the common meanings understood by those skilled in the art to which the present invention belongs.

[0023] Figure 1 A flowchart of a method for improving the design efficiency of a TFT semiconductor device provided by an embodiment of the present invention is shown in FIG. Figure 1 , the method comprises the following steps: S1: Acquire design data of a geometric model of a TFT semiconductor device, where the geometric model of the TFT semiconductor device includes geometric models of several device components.

[0024] The geometric model of a TFT semiconductor device includes geometric models of several device components, generally including a gate, a drain, an insulating layer, etc.

[0025] S2: Assign boundary conditions, material properties and geometric model mesh generation control parameters to the geometric model of each device component.

[0026] Specifically: The boundary conditions, material properties and geometric model mesh generation control parameters are assigned to the geometric model of each device component involved in the design.

[0027] Boundary conditions include: metal-semiconductor boundary, metal-metal boundary, metal-insulator boundary, semiconductor-semiconductor boundary, semiconductor-insulator boundary, applied voltage, applied current, etc.

[0028] Material properties include: doping type and concentration, defect model and its corresponding parameters, dielectric constant, mobility model and its corresponding parameters, etc.

[0029] The control parameters of geometric model mesh generation include: mesh unit type, minimum mesh size, mesh gradient coefficient, etc.

[0030] S3: Perform preliminary processing on the geometric model of the TFT semiconductor device to obtain the substrate grid.

[0031] Specifically: Interference analysis is performed on the geometric model of TFT semiconductor devices. The geometric interference between device components is eliminated by adjusting the component positions and characteristic parameters. The boundary conditions, material properties and other computational properties assigned in S2 are mapped to each other to obtain a topological model based on the geometric model and computational properties of the semiconductor device. The obtained topological model is then used to discretize the geometric model of the semiconductor device according to the grid generation control parameters in S2 to obtain a preliminary base grid.

[0032] Furthermore, the preliminary base mesh is decomposed based on the attribute regions (of each device component) contained in the topological model to obtain multiple sub-regions, each of which corresponds to each device component. For the edge on the boundary of each sub-region, if the angle where the endpoint is located is a right angle, the fractional knapsack algorithm is used to discretize the edge according to the given control parameters such as the minimum grid size and grid gradient coefficient, otherwise no discretization is performed; thus, the optimized base mesh is obtained.

[0033] S4: Generate a coarse grid of the TFT semiconductor device according to the generated substrate grid and boundary conditions, material properties, and grid generation control parameters of the geometric model of the TFT semiconductor device.

[0034] Specifically: According to the generated substrate mesh and boundary conditions, material properties, and mesh generation control parameters (determined by each device component) of the semiconductor device geometric model, point meshes, line meshes, surface meshes, and volume meshes, i.e., coarse meshes, are generated for the semiconductor device.

[0035] Based on each geometric point in the base grid obtained in S3, a point grid is obtained; at the same time, each geometric line in the semiconductor device geometric model is discretized using the points in the two point grids as endpoint constraints, thereby obtaining a line grid; combining the line grid and the topological model obtained in S3, the line grid data is encapsulated according to the geometric surface in the semiconductor device geometric model, thereby obtaining a surface grid; the surface grid is further encapsulated according to the topological model and the semiconductor device geometric model, thereby obtaining a volume grid.

[0036] S5: The concentric shell segmentation strategy is used to refine the mesh in the area with small angles in the coarse mesh to generate a fine mesh.

[0037] Specifically: Analyze the coarse grid data generated in S4 and identify the grid areas with small angles (the areas where the edge angles in the line grid are less than 90°).

[0038] Since small-angle regions are prone to numerical instability in device simulation solutions, resulting in divergent solutions and thus failure in the semiconductor simulation design process, mesh refinement is generally performed in mesh regions with small angles. Traditional mesh refinement algorithms are implemented by inserting points in the middle of the line mesh in small-angle mesh regions. However, in practice, when the edge angle is less than 60°, the mesh quality will be significantly reduced. When the angle is less than 45°, this method can easily fall into an infinite loop and cause the mesh quality to further deteriorate, leading to refinement failure.

[0039] This step is a meshing strategy for processing small angle areas. This strategy splits the line mesh in the small angle area in a non-central way to avoid the problem of mesh quality degradation that may be caused by traditional midpoint segmentation.

[0040] like Figure 2 As shown in the figure, when one edge of the small-angle mesh area in the line mesh is connected to another edge at an angle less than 90°, it is no longer simply split at the midpoint of the sub-line segment, but a circular shell centered on the shared vertex is selected as the split point, and the radius of these circular shells is a power of 2 (2i, where i is an integer); this concentric shell splitting strategy can effectively prevent the problem of dead loop generation, so that the mesh can be stably refined successfully, improve the numerical calculation stability of the device simulation algorithm in this area, and thus enhance the success rate of simulation design. When the angle between one edge in the line mesh and another edge is greater than 90°, no splitting is performed.

[0041] Then, the surface mesh and volume mesh are regenerated based on the segmented line mesh to obtain a fine mesh.

[0042] S6: Input the generated fine grid into the device simulation solver for solving, and adjust the design data of the TFT semiconductor device according to the solution result.

[0043] S6 is specifically: The device simulation solver can use existing tools such as Nuwa, input the generated fine grid into the device simulation solver for solving, and adjust the device design according to the results. Since the grid is successfully refined, the numerical stability of the simulation solution is steadily improved, and the results can be smoothly output to guide the optimization design.

[0044] It should be noted that the modules are arranged in a stream layout, which is only one embodiment of the present invention. Other arrangements may also be adopted, and the present invention is not limited thereto.

[0045] The embodiments of the present invention have the following technical effects: First, improving design efficiency: The present invention significantly shortens the design cycle through fine grid division and optimized simulation process.

[0046] Second, improving simulation accuracy: The improved mesh refinement algorithm of the present invention effectively solves the problem of unstable simulation in small-angle areas and improves the accuracy of simulation results.

[0047] Third, enhancing design flexibility: The timely feedback of the simulation results of the present invention provides strong support for device design and enhances the flexibility and adjustability of the design.

[0048] Figure 3 The present invention provides a structural block diagram of a device for improving the design efficiency of a TFT semiconductor device, the device comprising: An acquisition module is used to acquire design data of a geometric model of a TFT semiconductor device, wherein the geometric model of the TFT semiconductor device includes geometric models of several device components; An assignment module is used to assign boundary conditions, material properties and geometric model mesh generation control parameters to the geometric model of each device component; A processing module, used for preliminarily processing the geometric model of the TFT semiconductor device to obtain a substrate grid; A coarse mesh module, used to generate a coarse mesh of the TFT semiconductor device according to the generated substrate mesh and boundary conditions, material properties, and mesh generation control parameters of the geometric model of the TFT semiconductor device; The fine grid module is used to refine the grid by adopting the concentric shell segmentation strategy for the areas with small angles in the coarse grid to generate fine grids; The solving module is used to input the generated fine grid into the device simulation solver for solving, and adjust the design data of the TFT semiconductor device according to the solving result.

[0049] Figure 3 The functions of each module in the embodiment correspond to the contents in the corresponding method embodiment and will not be repeated here.

[0050] Figure 4 The structural schematic diagram of an electronic device 40 provided by an embodiment of the present invention is shown, and the electronic device 40 includes at least one processor 401 (such as a CPU), at least one input and output interface 404, a memory 402, and at least one communication bus 403, which is used to realize the connection and communication between these components. At least one processor 401 is used to execute computer instructions stored in the memory 402, so that the at least one processor 401 can execute any of the aforementioned embodiments of the method for improving the design efficiency of TFT semiconductor devices. The memory 402 is a non-transitory memory, which may include a volatile memory, such as a high-speed random access memory (RAM: Random Access Memory), and may also include a non-volatile memory (non-volatile memory), such as at least one disk storage. The communication connection with at least one other device or unit is realized through at least one input and output interface 404 (which may be a wired or wireless communication interface).

[0051] In some implementations, the memory 402 stores a program 4021, and the processor 401 executes the program 4021 to execute the content of any of the aforementioned table partitioning method embodiments.

[0052] The electronic device may exist in a variety of forms, including but not limited to: (1) Mobile communication equipment: This type of equipment is characterized by having mobile communication functions and its main purpose is to provide voice and data communications. This type of terminal includes: smart phones, multimedia phones, functional phones, and low-end phones.

[0053] (2) Ultra-mobile personal computer devices: These devices fall into the category of personal computers, have computing and processing functions, and generally also have mobile Internet access features. These terminals include: PDA, MID and UMPC devices, etc.

[0054] (3) Portable entertainment devices: These devices can display and play multimedia content. They include audio and video players, handheld game consoles, e-books, smart toys, and portable car navigation devices.

[0055] (4) Specific server: A device that provides computing services. The server consists of a processor, hard disk, memory, system bus, etc. The server is similar to a general computer architecture, but because it needs to provide highly reliable services, it has higher requirements in terms of processing power, stability, reliability, security, scalability, and manageability.

[0056] (5) Other electronic devices with data interaction functions.

[0057] It should be understood that various parts of the present invention can be implemented by hardware, software, firmware or a combination thereof.

[0058] In the above embodiments, multiple steps or methods may be implemented by software or firmware stored in a memory and executed by a suitable instruction execution system. For example, if implemented by hardware, as in another embodiment, it may be implemented by any one of the following technologies known in the art or a combination thereof: a discrete logic circuit having a logic gate circuit for implementing a logic function on a data signal, a dedicated integrated circuit having a suitable combination of logic gate circuits, a programmable gate array (PGA), a field programmable gate array (FPGA), etc.

[0059] The above is only a specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily thought of by a person skilled in the art within the technical scope disclosed by the present invention should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.

Claims

1. A method for improving the design efficiency of a TFT semiconductor device, characterized in that: The following steps are involved: S1: Acquire design data of a geometric model of a TFT semiconductor device, wherein the geometric model of the TFT semiconductor device includes geometric models of several device components; S2: assigning boundary conditions, material properties and geometric model mesh generation control parameters to the geometric model of each device component; S3: Preliminarily processing the geometric model of the TFT semiconductor device to obtain a substrate grid; S4: generating a coarse mesh of the TFT semiconductor device according to the generated substrate mesh and the boundary conditions, material properties, and mesh generation control parameters of the geometric model of the TFT semiconductor device; S5: using a concentric shell segmentation strategy to refine the mesh in the region where a small angle appears in the coarse mesh, so as to generate a fine mesh; S6: inputting the generated fine grid into a device simulation solver for solving, and adjusting the design data of the TFT semiconductor device according to the solution result.

2. The method for improving the design efficiency of a TFT semiconductor device according to claim 1, characterized in that: The device component is a gate, a drain or an insulating layer.

3. The method for improving the design efficiency of a TFT semiconductor device according to claim 1, characterized in that: In step S2, the boundary conditions include metal-semiconductor boundary, metal-metal boundary, metal-insulator boundary, semiconductor-semiconductor boundary, semiconductor-insulator boundary, applied voltage, and applied current; the material properties include doping type and concentration, defect model and its corresponding parameters, dielectric constant, mobility model and its corresponding parameters; the geometric model mesh generation control parameters include mesh unit type, mesh minimum size, and mesh gradient coefficient.

4. The method for improving the design efficiency of a TFT semiconductor device according to claim 1, characterized in that: In step S3, the preliminary processing includes interference analysis, component position adjustment, feature parameter adjustment, and construction of a topological model based on the geometric model and calculation properties of the TFT semiconductor device; the topological model generates control parameters according to the geometric model grid, discretizes the geometric model of the TFT semiconductor device, and obtains a base grid.

5. The method for improving the design efficiency of a TFT semiconductor device according to claim 4, characterized in that: In the step S3, the base grid is further optimized. The optimization includes performing region decomposition on the base grid to obtain a plurality of sub-regions, and performing discretization according to the features of the edges on the boundaries of the sub-regions.

6. The method for improving the design efficiency of a TFT semiconductor device according to claim 5, characterized in that: In the step S4, the coarse grid includes a point grid, a line grid, a surface grid and a volume grid, which are respectively generated based on the geometric points, geometric lines, geometric surfaces in the base grid and the topological model.

7. The method for improving the design efficiency of a TFT semiconductor device according to claim 1, characterized in that: In step S5, the concentric shell segmentation strategy is specifically: taking the shared vertex of the line mesh in the small angle area as the center and constructing concentric circle shells with a power of 2 as the radius as the segmentation point.

8. The method for improving the design efficiency of a TFT semiconductor device according to claim 1, characterized in that: In the step S6, the simulation solver is used to perform simulation calculations on the fine grid and output performance parameters of the TFT semiconductor device.

9. A device for improving the design efficiency of a TFT semiconductor device, characterized in that: The method for improving the design efficiency of a TFT semiconductor device according to claims 1 to 8 comprises: An acquisition module, used for acquiring design data of a geometric model of a TFT semiconductor device, wherein the geometric model of the TFT semiconductor device includes geometric models of several device components; An assignment module, used to assign boundary conditions, material properties and geometric model mesh generation control parameters to the geometric model of each device component; A processing module, used for preliminarily processing the geometric model of the TFT semiconductor device to obtain a substrate grid; A coarse mesh module, used to generate a coarse mesh of the TFT semiconductor device according to the generated substrate mesh and the boundary conditions, material properties, and mesh generation control parameters of the geometric model of the TFT semiconductor device; A fine grid module, used to refine the grid by adopting a concentric shell segmentation strategy for the area with small angles in the coarse grid to generate a fine grid; A solving module is used to input the generated fine grid into a device simulation solver for solving, and adjust the design data of the TFT semiconductor device according to the solving result.

10. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein: When the processor executes the program, the steps of the method for improving the design efficiency of TFT semiconductor devices as described in any one of claims 1 to 8 are implemented.

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