Storage device

Abstract

The invention discloses a storage device. The storage device comprises a storage array, a burning storage circuit, a command decoder and a processing circuit, the processing circuit is coupled with the burning storage circuit, the command decoder and the storage array, and word line mapping addresses stored in the burning storage circuit comprise at least two types of word line mapping addresses. Each type of word line mapping address corresponds to one type of redundant word line group, and the numbers of redundant word lines in the various types of redundant word line groups are different, so that the processing circuit responds to the word line addressing address and is matched with at least one word line mapping address; and generating a corresponding redundant word line enable signal to drive the redundant word line mapping in the at least one redundant word line group corresponding to the matched at least one word line mapping address to replace a group of common word lines corresponding to the word line addressing address. According to the invention, the memory chip repairing efficiency and flexibility are improved.

Description

Technical Field

[0001] The disclosed embodiments of the present application relate to the field of semiconductor storage technology, and more specifically, to a storage device. Background Art

[0002] If the word line (WL) or bit line (BL) of the dynamic random access memory (DRAM) is damaged (for example, short or open), it is necessary to replace these WL and BL with redundant WL / BL. It can be understood by those skilled in the art that, due to the factors of the process technology, when a word line WL is damaged, one or more other word lines WL adjacent to the word line WL are also very likely to be damaged. Therefore, based on the replacement efficiency, when the manufacturer performs redundant replacement of the word line WL, it is usually replaced by multiple adjacent word lines WL at the same time, such as 8WL simultaneous replacement, 4WL simultaneous replacement or 2WL simultaneous replacement, etc. However, the existing simultaneous replacement method requires the preset number of word lines WL to be replaced at the same time, and then the preset number of word lines WL are replaced at the same time; once the number of word lines WL to be replaced at the same time is set, it is not easy to modify it later. Therefore, this simultaneous replacement method is very inflexible and has many problems. For example, when performing 2WL simultaneous replacement, although the repair efficiency of the memory chip is improved compared with the replacement of a single word line WL, its repair efficiency is still relatively low and cannot meet the use of high-performance memory chips; when performing 8WL simultaneous replacement, its repair efficiency is higher, but sometimes the number of adjacent word lines WL that need to be redundantly replaced is less than 8, or even far less than 8. For example, only 3 adjacent WLs need to be redundantly replaced, and it can only perform 8WL simultaneous replacement, which greatly wastes the resources of word lines and redundant word lines, resulting in a waste of memory chip area. Summary of the invention

[0003] According to an embodiment of the present application, the present application proposes a storage device to solve the above-mentioned problem of a single word line replacement method and improve the efficiency and flexibility of chip repair.

[0004] The present application discloses a storage device, comprising: a storage array, comprising a normal storage array and a redundant storage array, wherein the redundant word lines in the redundant storage array are used to map and replace the normal word lines in the normal storage array, so that the redundant storage cells in the redundant storage array map and replace the damaged normal storage cells in the normal storage array; a burning storage circuit, configured to store at least one word line mapping address, wherein each of the word line mapping addresses corresponds to a redundant word line of a redundant word line group; a command decoder, configured to generate a corresponding word line addressing address in response to a user instruction; a processing circuit, coupling the burning storage circuit, the command decoder and the storage array; wherein the processing circuit is configured to receive the word line addressing address and the word line mapping address; in response to the word line addressing address matching at least one of the word line mapping addresses, generate a corresponding redundant word line enable signal to drive the redundant word line mapping in at least one redundant word line group corresponding to the matched at least one word line mapping address to replace a group of ordinary word lines corresponding to the word line addressing address; wherein the word line mapping addresses stored in the burn-in storage circuit include at least two types of word line mapping addresses, each type of the word line mapping address corresponds to a type of the redundant word line group, and the number of redundant word lines in each type of the redundant word line group is different.

[0005] The beneficial effects of the present application are as follows: The storage device includes a storage array, a programming storage circuit, a command decoder, and a processing circuit. The processing circuit is coupled to the programming storage circuit, the command decoder, and the storage array. Among them, the word line mapping addresses stored in the programming storage circuit include at least two types of word line mapping addresses. Each type of word line mapping address corresponds to a type of redundant word line group, and the number of redundant word lines in each type of the redundant word line groups is different. Further, the processing circuit will generate a corresponding redundant word line enable signal to drive the redundant word lines in at least one redundant word line group corresponding to the at least one word line mapping address that matches the word line addressing address to map and replace a group of normal word lines corresponding to the word line addressing address, thereby improving the efficiency and flexibility of storage chip repair. Further, when some of the first type of redundant word lines (M) in the first type of redundant word line group are also damaged, in an embodiment of the present invention, the second type of redundant word lines in the second type of redundant word line group are used to replace some of the first type of redundant word lines (N) to map and replace the normal word lines corresponding to the word line addressing address, without occupying an additional group of the first type of redundant word line group (M, where N < M), thereby saving redundant word line resources. In addition, even if N ≥ M, when some of the first type of redundant word lines (M) in the first type of redundant word line group are damaged, in an embodiment of the present invention, the second type of redundant word lines (N) in the second type of redundant word line group can also be used to replace the first type of redundant word lines to map and replace the normal word lines corresponding to the word line addressing address, avoiding the situation where replacement cannot be achieved when the first type of redundant word lines in the first type of redundant word line group are exhausted. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The present application will be further described below in conjunction with the drawings and embodiments. In the drawings:

[0007] Figure 1 is a schematic structural diagram of a storage device according to an embodiment of the present application;

[0008] Figure 2 is a schematic diagram of a storage device according to another embodiment of the present application;

[0009] Figure 3 is a schematic diagram of a storage device according to another embodiment of the present application;

[0010] Figure 4 is a schematic diagram of a storage device according to another embodiment of the present application. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0011] Reference to "embodiments" in this application means that a particular feature, structure, or characteristic described in conjunction with the embodiments may be included in at least one embodiment of the present application. The appearance of the phrase in various locations in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment that is mutually exclusive with other embodiments. It is explicitly and implicitly understood by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0012] The term "and / or" in this application is only a description of the association relationship of associated objects, indicating that there may be three relationships. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. In addition, the character " / " in this article generally indicates that the objects associated before and after are in an "or" relationship. In addition, "many" in this article means two or more than two. In addition, the term "at least one" in this article means any combination of at least two of any one or more of a plurality of, for example, including at least one of A, B, and C, and can mean including any one or more elements selected from the set consisting of A, B, and C. In addition, the terms "first", "second", and "third" in this application are used for descriptive purposes only and cannot be understood as indicating or implying relative importance or implicitly indicating the number of indicated technical features.

[0013] In order to enable those skilled in the art to better understand the technical solution of the present application, the technical solution of the present application is further described in detail below in conjunction with the accompanying drawings and specific implementation methods.

[0014] See also Figure 1 , Figure 1 1 is a schematic diagram of the structure of a storage device according to an embodiment of the present application. The storage device 10 includes a storage array 11, a burning storage circuit 12, a command decoder 13 and a processing circuit 14. The storage device 10 may be a dynamic random access memory (DRAM), wherein the storage device 10 may be applied to an electronic device including a storage system, a graphics system, a computing system or a mobile system, for example, the electronic device may include a data storage, a memory controller, a cache memory, etc.

[0015] Specifically, the memory array 11 includes a normal memory array 111 and a redundant memory array 112, wherein the normal memory array 111 includes a plurality of normal word lines WL, a plurality of normal bit lines BL, and a plurality of normal memory cells, and by performing row addressing operations on the normal word lines WL and / or performing column addressing operations on the normal bit lines BL, the corresponding normal memory cells are selected to perform memory operations, such as read, write, erase, and the like.

[0016] The redundant memory array 112 includes a plurality of redundant word lines and a plurality of redundant memory cells. The redundant word lines in the redundant memory array 112 can be used to map and replace the ordinary word lines in the ordinary memory array 111, so that the redundant memory cells in the redundant memory array 112 can be mapped to replace the damaged ordinary memory cells in the ordinary memory array 111, that is, when a damaged ordinary word line appears in the ordinary memory array 111, the redundant word line in the redundant memory array 112 can be used for redundant replacement.

[0017] The burn-in storage circuit 12 is configured to store at least one word line mapping address Efsadd, wherein each word line mapping address Efsadd corresponds to a redundant word line of a redundant word line group. The burn-in storage circuit 12 stores at least one word line mapping address Efsadd, and the word line mapping address Efsadd may be the corresponding address of a faulty word line found when the DRAM is tested before leaving the factory. Each word line mapping address Efsadd may correspond to a redundant word line of a redundant word line group, and the word line mapping address Efsadd is used to perform simultaneous mapping replacement of multiple redundant word lines in the corresponding redundant word line group. For example, if a redundant word line group corresponding to a certain word line mapping address Efsadd includes 8 redundant word lines, then when the word line mapping address Efsadd is matched and selected, the 8 redundant word lines in the corresponding redundant word line group are simultaneously mapped to replace 8 normal word lines.

[0018] The command decoder 13 is configured to generate a corresponding word line addressing address in response to a user instruction. Specifically, when a user issues a user instruction, the command decoder 13 can generate a corresponding word line addressing address RA and a word line addressing operation trigger signal Act_en in response to the user instruction, wherein the word line addressing operation trigger signal Act_en is used to trigger a back-end circuit (e.g., a back-end processing circuit 14) to perform a word line addressing operation, and the word line addressing address RA can be a word line address that the user wants to access.

[0019] The processing circuit 14 is coupled to the burning storage circuit 12, the command decoder 13 and the storage array 11. The processing circuit 14 is configured to receive the word line addressing address RA and the word line mapping address Efsadd, and receive the word line addressing operation trigger signal Act_en sent by the command decoder 13. In response to the word line addressing address RA matching at least one word line mapping address Efsadd, the processing circuit 14 determines whether the word line addressing address is a faulty word line address. Further, if the word line addressing address RA matches at least one word line mapping address Efsadd, a corresponding redundant word line enable signal is generated to drive the redundant word line mapping in at least one redundant word line group corresponding to the matched at least one word line mapping address Efsadd to replace a group of normal word lines corresponding to the word line addressing address RA. That is to say, when the processing circuit 14 matches at least one word line mapping address Efsadd according to the word line addressing address RA, it means that a group of ordinary word lines WL corresponding to the word line addressing address RA is faulty or damaged, and the group of ordinary word lines WL corresponding to the word line addressing address RA needs to be replaced, and the replacement object is the redundant word line in at least one redundant word line group corresponding to the matching at least one word line mapping address Efsadd.

[0020] In the present application, the word line mapping address Efsadd stored in the burned storage circuit 12 includes at least two types of word line mapping addresses, for example, it can be a two-word line mapping address, a four-word line mapping address, an eight-word line mapping address, etc., wherein the two-word line mapping address can be understood as a word line mapping address that replaces two word lines together, the four-word line mapping address can be understood as a word line mapping address that replaces four word lines together, and the eight-word line mapping address can be understood as a word line mapping address that replaces eight word lines together.

[0021] The number of redundant word lines in one type of redundant word line group corresponding to each type of word line mapping address is different from the number of redundant word lines in another type of redundant word line group corresponding to other types of word line mapping addresses. For example, the number of redundant word lines in the redundant word line group corresponding to two word line mapping addresses is 2, the number of redundant word lines in the redundant word line group corresponding to four word line mapping addresses is 4, and the number of redundant word lines in the redundant word line group corresponding to eight word line mapping addresses is 8, and the numbers of redundant word lines in the corresponding redundant word line groups are not the same.

[0022] In some embodiments, Figure 1 As shown, the processing circuit 14 includes an address matching circuit 141 , and the address matching circuit 141 is coupled to the programming storage circuit 12 and the command decoder 13 .

[0023] Among them, the address matching circuit 141 is configured to cache the word line mapping address Efsadd from the burning storage circuit 12, receive the word line addressing address RA from the command decoder 13, and compare the word line addressing address RA with the word line mapping address Efsadd to determine whether the word line addressing address RA matches at least one of the word line mapping addresses Efsadd.

[0024] Specifically, the address matching circuit 141 may also include a latch unit (latch) for caching or temporarily storing the word line mapping address Efsadd from the burning storage circuit 12, so as to compare it with the word line addressing address RA corresponding to the user instruction one by one to determine whether redundant replacement of the word line is required. In addition, the address matching circuit 141 also receives the word line addressing address RA and the word line addressing operation trigger signal Act_en from the command decoder 13 to perform a word line addressing operation based on the word line addressing operation trigger signal Act_en; wherein the word line addressing operation first compares the word line addressing address RA and the word line mapping address Efsadd to determine whether redundant replacement of the word line is required. In response to at least one of the word line addressing address RA and the word line mapping address Efsadd matching, it is determined that redundant replacement of the word line is required.

[0025] Furthermore, if Figure 1 As shown, in some embodiments, the processing circuit 14 further includes a redundant word line decoding circuit 142 , and the redundant word line decoding circuit 142 is coupled to the address matching circuit 141 .

[0026] In response to the address matching circuit 141 determining that the word line addressing address RA matches at least one word line mapping address Efsadd, that is, the address matching circuit 141 determines that redundant replacement of the word line is required, and therefore, the redundant word line decoding circuit 142 is selected. Based on at least one word line mapping address Efsadd matching the word line addressing address RA, the redundant word line decoding circuit 142 generates a corresponding redundant word line enable signal RWL_en to drive the redundant word line mapping replacement word line corresponding to the word line addressing address RA in at least one redundant word line group corresponding to the matched at least one word line mapping address Efsadd. That is to say, when the address matching circuit 141 determines that the word line addressing address RA matches at least one word line mapping address Efsadd, a group of word lines corresponding to the word line addressing address RA is faulty or damaged, and redundant word line replacement is required. The redundant word line decoding circuit 142 generates a corresponding redundant word line enable signal RWL_en to replace a group of ordinary word lines corresponding to the word line addressing address RA. The replacement object is a redundant word line in at least one redundant word line group corresponding to at least one word line mapping address Efsadd that matches the word line addressing address RA.

[0027] In some embodiments, Figure 1As shown, the processing circuit 14 further includes a common word line decoding circuit 143 , and the common word line decoding circuit 143 is coupled to the address matching circuit 141 .

[0028] Among them, in response to the address matching circuit 141 determining that the word line addressing address RA and the word line mapping address Efsadd do not match, that is, when redundant replacement of the word line is not required, the ordinary word line decoding circuit 143 is selected and receives the word line addressing address RA from the command decoder 13, and generates the corresponding ordinary word line enable signal WL_en based on the word line addressing address RA to drive the ordinary word line corresponding to the word line addressing address RA, thereby completing the relevant operations of ordinary word line addressing.

[0029] That is, in the present application, the address matching circuit 141 sends a selection signal Select according to the matching result between the word line addressing address RA and the word line mapping address Efsadd, thereby selecting the normal word line decoding circuit 143 or the redundant word line decoding circuit 142. When the address matching circuit 141 determines that at least one of the word line addressing address RA and the word line mapping address Efsadd matches, the address matching circuit 141 selects the redundant word line decoding circuit 142 to perform redundant mapping replacement of the word line based on the word line mapping address Efsadd; when the address matching circuit 141 determines that the word line addressing address RA and the word line mapping address Efsadd do not match, the address matching circuit 141 selects the normal word line decoding circuit 143 to perform a normal word line addressing operation based on the word line addressing address RA.

[0030] To summarize, in the present application, since the word line mapping address Efsadd stored in the burn storage circuit 12 includes at least two types of word line mapping addresses, the number of redundant word lines in one type of redundant word line group corresponding to each type of word line mapping address is different from the number of redundant word lines in another type of redundant word line group corresponding to other types of word line mapping addresses, therefore, when the word line addressing address RA matches one type of word line mapping address Efsadd (for example, 8 word line mapping addresses), redundant replacement of 8 word lines can be performed simultaneously; when the word line addressing address RA matches another type of word line mapping address Efsadd (for example, 2 word line mapping addresses), redundant replacement of 2 word lines can be performed simultaneously; when the word line addressing address RA matches multiple different types of word line mapping addresses, mixed redundant replacement of multiple different types of word line mapping addresses can be performed (explained in detail later). Therefore, the storage device 10 of the present application has great flexibility when performing word line redundancy replacement operations. It can flexibly configure the type of word line mapping address according to actual needs to perform different types of word line redundancy replacements, which can provide repair efficiency and avoid wasting word line and redundant word line resources.

[0031] For ease of understanding, Figure 2-4 As shown, Figure 2-4 FIG. 2 is a schematic diagram of a storage device according to another embodiment of the present application. In this embodiment, the present application is specifically explained in the form of examples.

[0032] In this embodiment, the working principle of the present application is described by taking the word line mapping address Efsadd stored in the burning storage circuit 12 as an example including two types of word line mapping addresses. Of course, those skilled in the art can understand that the word line mapping address Efsadd stored in the burning storage circuit 12 in the present application is not limited to two types of word line mapping addresses, and may also include three types of word line mapping addresses, four types of word line mapping addresses, ... and so on, and the present application does not limit this, as long as it complies with the working principle described in the present application.

[0033] Specifically, the word line mapping address Efsadd stored in the burning storage circuit 12 includes a first type word line mapping address and a second type word line mapping address, wherein the first type redundant word line group corresponding to the first type word line mapping address includes M redundant word lines, and the second type redundant word line group corresponding to the second type word line mapping address includes N redundant word lines, M and N are natural numbers, and M is not equal to N. In this embodiment, M=8, N=2, the first type redundant word line group corresponding to the first type word line mapping address includes 8 redundant word lines, that is, 8 redundant word lines are the word line mapping address corresponding to a redundant word line group, and the second type redundant word line group corresponding to the second type word line mapping address includes 2 redundant word lines, that is, 2 redundant word lines are the word line mapping address corresponding to a redundant word line group. It can be understood that in other embodiments, the first type word line mapping address and the second type word line mapping address can also be other types of word line mapping addresses, such as 16 word line mapping addresses, 4 word line mapping addresses, etc.

[0034] like Figure 3 As shown, the address matching circuit 141 includes a first address matching circuit 1411 and a second address matching circuit 1412. The first address matching circuit 1411 can be used to match a first type of address, i.e., a first type of address matching circuit, and the second address matching circuit 1412 is used to match a second type of address, i.e., a second type of address matching circuit. The redundant word line decoding circuit 142 includes a first redundant word line decoding circuit 1421 and a second redundant word line decoding circuit 1422. The first redundant word line decoding circuit 1421 can be a first type of redundant word line decoding circuit, and the second redundant word line decoding circuit 1422 can be a second type of redundant word line decoding circuit.

[0035] Specifically, when the address matching circuit 1411 determines that the word line addressing address RA matches the first type word line mapping address Efsadd, the address matching circuit 1411 selects the first redundant word line decoding circuit 1421 to perform redundant mapping replacement of the word line based on the first type word line mapping address Efsadd. When the address matching circuit 1412 determines that the word line addressing address RA matches the second type word line mapping address Efsadd, the address matching circuit 1412 selects the second redundant word line decoding circuit 1422 to perform redundant mapping replacement of the word line based on the second type word line mapping address Efsadd.

[0036] like Figure 4 As shown, the programming storage circuit 12 includes a first programming unit 121 and a second programming unit 122, wherein the first programming unit 121 is programmed with a first type word line mapping address (eg, Figure 4 Efsadd as shown <RA<14:3> , G<1:0>, flag>), the second programming unit 122 is programmed with a second type word line mapping address (eg, Figure 4 Efsadd as shown <RA<14:1> ,flag>). The first type redundant word line group corresponding to the first type word line mapping address includes M redundant word lines. In this embodiment, M=8, that is, the first type redundant word line group includes 8 redundant word lines, which are used to implement redundant replacement of 8 word lines; the second type redundant word line group corresponding to the second type word line mapping address includes N redundant word lines. In this embodiment, N=2, that is, the second type redundant word line group includes 2 redundant word lines, which are used to implement redundant replacement of 2 word lines.

[0037] The address matching circuit 141 receives the word line addressing address RA<14:0> transmitted from the command decoder 13 and determines whether the word line addressing address RA<14:0> matches the cached word line mapping address.

[0038] Correspondingly, the redundant word line decoding circuit 142 includes a plurality of first latch units 14211 and a plurality of second latch units 14221 (exemplarily, Figure 4Only one first latch unit 14211 and one first latch unit 14211 are shown, but the present invention is not limited thereto), wherein each first latch unit 14211 is used to generate a corresponding redundant word line enable signal RWL_en to drive a matching first type word line mapping address Efsadd <RA<14:3> , flag> The 8 redundant word lines in the first type redundant word line group corresponding to the mapping replacement word line addressing address RA<14:0> correspond to a group of ordinary word lines, and each second latch unit 14221 is used to generate a corresponding redundant word line enable signal RWL_en to drive the matching second type word line mapping address Efsadd <RA<14:1> , flag>, the two redundant word lines in the second type redundant word line group corresponding to the mapping replacement word line addressing address RA<14:0> corresponding to a group of ordinary word lines.

[0039] It is understood by those skilled in the art that the word line addressing address is composed of a multi-bit address signal. For example, in the present application, the word line addressing address may include an a-bit address signal, which may be recorded as RA <a-1:0>, that is, the address signal from the 0th bit to the a-1th bit, where a is a preset value. In this embodiment, a=15, then the word line addressing signal can be recorded as RA<(15-1=14):0>, that is, RA<14:0>.

[0040] The word line mapping address Efsadd also includes a multi-bit address signal, the number of bits of which is less than the number of bits of the address signal of the word line addressing address, which corresponds to the word line addressing address RA <a-1:0>For example, the first type word line mapping address includes a high address signal of (ab) bits, which can be recorded as Efsadd <RA <a-1:b>>, where RA <a-1:b>Corresponding word line address RA <a-1:0>The high-order address signal from the bth bit to the a-1th bit (a total of ab bits).

[0041] Therefore, when comparing and judging, when the word line addressing address RA <a-1:0>The high-order address signals of the b-th to a-1-th bits in the first type word line mapping address Efsadd are respectively <RA <a-1:b>>When the high-order address signals of the (ab) bits in the word line are consistent, the word line addressing address RA <a-1:0>Mapping address Efsadd with the first type word line <RA <a-1:b>>Match. Word line addressing address RA <a-1:0>The position address signals from bit 0 to bit (b-1) do not need to be compared again.

[0042] Word line address RA <a-1:0>The position address signal from bit 0 to bit (b-1) corresponds to 2 b A common word line; due to the word line addressing address RA <a-1:0>The position address signal from bit 0 to bit (b-1) in the first type word line mapping address Efsadd does not need to be mapped with the first type word line mapping address Efsadd. <RA <a-1:b>>Compare and judge, that is, the first type word line mapping address Efsadd <RA <a-1:b>>The corresponding first type redundant word line group includes M=2 b Redundant word lines, which implement M = 2 b Redundant word line pair 2 b In this embodiment, b=3, so the first type word line mapping address can be recorded as Efsadd <RA<14:3> >, which is compared with the high-order address signal of the 3rd to 14th bits in the word line addressing address RA<14:0>, that is, the first address matching circuit 1411 determines whether the high-order address signal of the 3rd to 14th bits in the 15-bit address signal RA<14:0> of the word line addressing address is consistent with the first type word line mapping address Efsadd <RA<14:3> >The 12-bit high-order address signals in are consistent.

[0043] To determine whether the word line addressing address RA<14:0> matches the first type word line mapping address Efsadd <RA<14:3> >Match; if it matches, execute M=2 3 Redundant word line pair 2 3 Redundant replacement of 8 common word lines, that is, redundant replacement of 8 word lines.

[0044] In addition, the first type word line mapping address may also include a 1-bit first identification signal flag, and the first type word line mapping address may be recorded as Efsadd <RA <a-1:b>,flag>. The first identification signal flag is used to indicate whether the current first type redundant word line group sequentially assigned to the first type word line mapping address is damaged. For example, the first type redundant word line group includes 8 redundant word lines, but 6 redundant word lines in the current first type redundant word line group sequentially assigned to the first type word line mapping address also have fault problems. Therefore, the current first type redundant word line group can be defined as damaged. Otherwise, even if 8 redundant word lines are replaced with 8 ordinary word lines, 6 of the replaced 8 redundant word lines are still faulty, and the repair is not meaningful.

[0045] Those skilled in the art will appreciate that, in some embodiments, the first identification signal flag is used to indicate that when a current first type redundant word line group corresponding to a first type word line mapping address sequentially assigned to the first type word line mapping address is damaged, the next group of first type redundant word line groups is sequentially assigned to the first type word line mapping address, and the next group of first type redundant word line groups is used as the corresponding first type redundant word line group to perform mapping replacement of M redundant word lines.

[0046] Correspondingly, the second type word line mapping address may include a high address signal of (ac) bits and a second identification signal of 1 bit, which may be recorded as Efsadd <RA <a-1:c>,flag>。RA <a-1:c>>Corresponding word line address RA <a-1:0>The high-order address signal from the cth bit to the a-1th bit (a total of ac bits).

[0047] When comparing and judging, when the word line addressing address RA <a-1:0>The high-order address signals of the c-th to a-1-th bits in the second type word line mapping address Efsadd <RA <a-1:c>>When the high-order address signals of the (ac) bits in the word line are consistent, the word line addressing address RA <a-1:0>Mapping address Efsadd with the first type word line <RA <a-1:c>>Match. Word line addressing address RA <a-1:0>The address signals of the 0th to (c-1th) bits in the second type word line mapping address Efsadd do not need to be compared. <RA <a-1:c>>The corresponding second type redundant word line group includes N=2 c Redundant word lines, which implement N = 2 c Redundant word line pair 2 c Redundant replacement of a normal word line.

[0048] In this embodiment, c=1, so the second type word line mapping address can be recorded as Efsadd <RA<14:1> , flag>, which is compared with the high address signal of the 1st to 14th bits in the word line addressing address RA<14:0>, that is, the second address matching circuit 1412 determines whether the high address signal of the 1st to 14th bits in the 15-bit address signal of the word line addressing address RA<14:0> is consistent with the second type word line mapping address Efsadd <RA<14:1> > is consistent with the 14-bit high address signal in the word line addressing address RA<14:0> to determine whether the word line addressing address RA<14:0> is consistent with the second type word line mapping address Efsadd <RA<14:1> >Match; if match, execute N=2 1 Redundant word line pair 2 1 Redundant replacement of two common word lines, that is, redundant replacement of two word lines.

[0049] The second identification signal flag is used to indicate whether the current second type redundant word line group sequentially assigned to the second type word line mapping address is damaged; if damaged, the next group of second type redundant word line groups is sequentially assigned to the second type word line mapping address, and the N redundant word lines in the next group of second type redundant word line groups are redundantly replaced.

[0050] Please also read Figure 2-4 The address matching circuit 141 is used to determine the word line addressing address RA <a-1:0>Whether it matches the word line mapping address Efsadd cached from the burning storage circuit 12.

[0051] When the word line address RA <a-1:0>Matches a first type word line mapping address, for example, word line addressing address RA <a-1:0>Mapping address Efsadd with the first type word line of the cache <RA <a-1:b>,flag>(for example, Figure 4 Efsadd as shown <RA<14:3> ,G<1:0>,flag>, where G<1:0> will be described later) matches, the first address matching circuit 1411 selects the first redundant word line decoding circuit 1421, and the first latch unit 14211 receives all the first type word line mapping addresses Efsadd <RA <a-1:b>,flag>.

[0052] The first redundant word line decoding circuit 1421 further receives a word line addressing address RA <a-1:0>, and one by one with the first type word line mapping address Efsadd temporarily stored in each first latch unit 14211 <RA <a-1:b>,flag> comparison, based on the matching first type word line mapping address Efsadd <RA <a-1:b>, flag> stores the position of the first latch unit 14211 (each first latch unit 14211 further includes M latches, each latch latch corresponds to a redundant word line enable signal RWL_en), generates corresponding M redundant word line enable signals RWL_en to drive the matching first type word line mapping address Efsadd <RA <a-1:b>, flag> The M redundant word lines in the corresponding first type redundant word line group are mapped to replace the word line addressing address RA <a-1:0>A corresponding set of normal word lines.

[0053] In this embodiment, M=8, a=15, b=3, and therefore, the above execution performs redundant replacement of 8 word lines.

[0054] Similarly, when the word line address RA <a-1:0>Matches a second type word line mapping address, for example, word line addressing address RA <a-1:0>The second type word line mapping address Efsadd with the cache <RA <a-1:c>,flag>(for example, Figure 4 Efsadd as shown <RA<14:1> , flag>) matches, the second address matching circuit 1412 selects the second redundant word line decoding circuit 1422, and the second latch unit 14221 receives all the second type word line mapping addresses Efsadd <RA <a-1:c>,flag>. The second redundant word line decoding circuit 1422 further receives the word line addressing address RA <a-1:0>, and one by one with the second type word line mapping address Efsadd temporarily stored in each second latch unit 14221 <RA <a-1:c>,flag> comparison, based on the matching second type word line mapping address Efsadd <RA <a-1:c>,flag> stores the position of the second latch unit 14221 (each second latch unit 14221 includes N latches, each latch latch corresponds to a redundant word line enable signal RWL_en), generates corresponding N redundant word line enable signals RWL_en to drive the matching second type word line mapping address Efsadd <RA <a-1:c>, flag> The N redundant word lines in the corresponding second type redundant word line group map to replace the word line addressing address RA <a-1:0>A corresponding set of normal word lines.

[0055] In this embodiment, N=2, a=15, c=1, and therefore, the above execution is the redundant replacement of 2 word lines.

[0056] In addition, it is understood by those skilled in the art that the redundant word lines in the redundant memory array 112 may also be damaged during the manufacturing process, and may also need to be replaced redundantly, that is, the redundant word line replacement. <a-1:0>It is possible to match more than one word line mapping address Efsadd.

[0057] Specifically, the word line addressing address RA <a-1:0>may match not only one first-type word line mapping address, but may also match at least one second-type word line mapping address; for example, the word line addressing address RA <a-1:0>High position <a-1:b>A first type word line mapping address Efsadd cached by a first latch unit 14211 <RA <a-1:b>,flag>(for example, Figure 4 Efsadd as shown <RA<14:3> ,G<1:0>,flag>) matches, and the word line addressing address RA <a-1:0>High position <a-1:c>The second type word line mapping address Efsadd cached by a second latch unit 14221 <RA <a-1:c>,flag>(for example, Figure 4 Efsadd as shown <RA<14:1> ,flag>) matches.

[0058] It can be understood by those skilled in the art that the first type word line mapping address Efsadd <RA <a-1:b>, the address signal in flag> is RA <a-1:b>, which corresponds to the address signals from the bth bit to the a-1th bit in the word line addressing signal. For example, in this embodiment, Figure 4 The first type word line mapping address Efsadd is shown <RA<14:3> ,G<1:0>,flag>, its address signal is RA<14:3>, corresponding to the address signal of the 3rd to 14th bits in the word line addressing signal.

[0059] The second type word line mapping address Efsadd <RA <a-1:c>, the address signal in flag> is RA <a-1:c>, which corresponds to the address signal of the cth bit to the a-1th bit in the word line addressing signal. For example, in this embodiment, Figure 4 The second type word line mapping address Efsadd is shown <RA<14:1> ,flag>, its address signal is RA<14:1>, which corresponds to the address signal from the 1st to the 14th bit in the word line addressing signal.

[0060] When the address matching circuit 141 performs a match determination, as long as the first type word line mapping address Efsadd <RA <a-1:b>,flag> medium and high address signal RA <a-1:b>and word line addressing signal RA <a-1:0>If the word line addressing signal is consistent with the first type word line mapping address Efsadd <RA <a-1:b>, flag> matches; similarly, as long as the second type word line mapping address Efsadd <RA <a-1:c>, flag> in the high address signal RA <a-1:c>and word line addressing signal RA <a-1:0>If the word line addressing signal RA <a-1:0>Mapping address Efsadd with the second type word line <RA <a-1:c>,flag>match. Therefore, when the address matching circuit 141 performs a match judgment, the word line addressing address RA may appear <a-1:0>That is, the first type word line mapping address Efsadd <RA <a-1:b>, flag> matches, and matches the second type word line mapping address Efsadd <RA <a-1:c>,flag>match.

[0061] Specifically, in response to the word line addressing address RA <a-1:0>Both the first type word line mapping address Efsadd <RA <a-1:b>, flag> matches, and matches the second type word line mapping address Efsadd <RA <a-1:c>, flag> matches, the first address matching circuit 1411 selects (or enables) the first redundant word line decoding circuit 1421 and outputs all first type word line mapping addresses Efsadd <RA <a-1:b>,flag> and the second type word line mapping address Efsadd <RA <a-1:c>,flag>to the redundant word line decoding circuit 142.

[0062] The redundant word line decoding circuit 142 is based on the word line addressing address RA <a-1:0>, the first type word line mapping address Efsadd <RA <a-1:b>,flag> and the second type word line mapping address Efsadd <RA <a-1:c>, flag>, generate the corresponding redundant word line enable signal RWL_en to drive the matching first type word line mapping address Efsadd <RA <a-1:c>, flag> The M redundant word lines in the corresponding first type redundant word line group are mapped to replace the word line addressing address RA <a-1:0>A corresponding set of ordinary word lines and a matching second type word line mapping address Efsadd <RA <a-1:c>,flag>The N redundant word lines in the corresponding second type redundant word line group are mapped to replace the N redundant word lines in the corresponding first type redundant word line group, where N is less than M.

[0063] In this embodiment, based on the matching first type word line mapping address Efsadd <RA<14:3> ,G<1:0>,flag>, using the matching first type word line mapping address Efsadd <RA<14:3> ,G<1:0>,flag>,8 redundant word lines in the first type redundant word line group corresponding to the mapping replacement word line addressing address RA<14:0> corresponding to a group of 8 normal word lines, perform redundant replacement of 8 word lines; and based on the matching second type word line mapping address Efsadd <RA<14:1> ,flag>, using the matching second type word line mapping address Efsadd <RA<14:1> ,flag>The two redundant word lines in the corresponding second type redundant word line group are mapped to replace the two redundant word lines in the first type redundant word line group.

[0064] In other words, among the 8 redundant word lines in the first type redundant word line group, 6 redundant word lines may be good, while 2 adjacent redundant word lines are damaged; therefore, when performing redundant replacement, a group of 8 normal word lines corresponding to the word line addressing address RA<14:0>, 6 of which are mapped and replaced to the 6 good redundant word lines in the first type redundant word line group, and 2 of which are mapped and replaced to the 2 redundant word lines in the second type redundant word line group.

[0065] In the present application, the first type word line mapping address may also include at least one group of (bc) bits of redundant word line replacement signal G <b-c-1:0>, then the first type word line mapping address can be recorded as <RA <a-1:b> ,G <b-c-1:0>,flag>, for example Figure 4 Efsadd as shown <RA<14:3> ,G<1:0>,flag>.

[0066] Wherein, the first type word line mapping address <RA <a-1:b> ,G <b-c-1:0>, flag> The first type of redundant word line group corresponding to can be divided into 2 (b-c) Redundant word line subgroups, each redundant word line subgroup includes N=2 c adjacent redundant word lines, the redundant word line replacement signal G of the above (bc) bits <b-c-1:0>It is used to indicate a corresponding redundant word line subgroup in the first type redundant word line group, wherein the redundant word lines therein may be faulty and need to be replaced by other redundant word line mappings.

[0067] In this embodiment, b=3, then the first type redundant word line group corresponding to the first type word line mapping address includes 8 redundant word lines; c=1, then the second type redundant word line group corresponding to the second type word line mapping address includes 2 redundant word lines.

[0068] Therefore, bc=2, the redundant word line replacement signal can be recorded as G<1:0>, a 2-bit signal, and the 8 redundant word lines in the first type redundant word line group can be divided into 2 2 There are four redundant word line subgroups, namely, four redundant word line subgroups; each redundant word line subgroup includes two adjacent redundant word lines.

[0069] When G<1:0>=00, it may indicate that the first redundant word line subgroup in the first type redundant word line group may have faults, that is, the 0th and 1st redundant word lines need to be replaced by other redundant word line mappings.

[0070] When G<1:0>=01, it may indicate that the second redundant word line subgroup in the first type redundant word line group may have faults, namely, the second and third redundant word lines, which need to be replaced by other redundant word line mappings.

[0071] When G<1:0>=10, it may indicate that the third redundant word line subgroup in the first type redundant word line group may have faults, namely, the 4th and 5th redundant word lines, which need to be replaced by other redundant word line mappings.

[0072] When G<1:0>=11, it may indicate that the fourth redundant word line subgroup in the first type redundant word line group may have faults, namely, the 6th and 7th redundant word lines, which need to be replaced by other redundant word line mappings.

[0073] In this embodiment, in response to the word line addressing address RA<14:0> matching the first type word line mapping address Efsadd <RA<14:3> ,G<1:0>,flag> and the second type word line mapping address Efsadd <RA<14:1> , flag>, and the first type word line mapping address Efsadd <RA<14:3> , G<1:0>, flag> also includes a redundant word line replacement signal G<1:0>, then the matching first type word line mapping address Efsadd <RA<14:3> ,G<1:0>,flag> The redundant word lines in the first type redundant word line group corresponding to the mapping replacement word line addressing address RA<14:0> corresponding to a group of 8 ordinary word lines, the matching second type word line mapping address Efsadd <RA<14:1> , flag> The redundant word lines in the second type redundant word line group corresponding to the redundant word line are used to map and replace the redundant word lines in the redundant word line subgroup indicated by the redundant word line replacement signal G<1:0> in the first type redundant word line group.

[0074] It can be understood that in response to the word line addressing address RA<14:0> matching the first type word line mapping address Efsadd <RA<14:3> , flag> and the first type word line mapping address also includes a (bc)-bit redundant word line replacement signal G<1:0>, the first redundant word line decoding circuit 1421 shields the redundant word line enable signals of the (bc=2) redundant word lines in the redundant word line subgroup indicated by the (bc=2)-bit redundant word line replacement signal in the first type redundant word line group, and generates a matching first type word line mapping address Efsadd <RA<14:3> , G<1:0>, flag> corresponding to the redundant word line enable signal of the remaining 6 redundant word lines of the 8 redundant word lines of the first type redundant word line group; in response to the word line addressing address RA<14:0> matching the second type word line mapping address Efsadd <RA<14:1> , flag>, the second redundant word line decoding circuit 1422 drives two redundant word lines in the second type redundant word line group corresponding to the matched second type word line mapping address. For example, the matched first type word line mapping address Efsadd <RA<14:3> ,G<1:0>,flag>The first type of redundant word line group corresponding to includes 8 redundant word lines RDN10, RDN11, RDN12, RDN13, RDN14, RDN15, RDN16, and RDN17, among which the redundant word lines RDN16 and RDN17 are damaged redundant word lines and need to be replaced; The matching second type word line mapping address Efsadd <RA<14:1> ,flag>The corresponding second type redundant word line group includes 2 redundant word lines, RDN26 and RDN27. Therefore, when redundantly replacing the eight ordinary word lines WL0, WL11, WL12, WL13, WL14, WL15, WL16, and WL17 corresponding to the word line addressing address RA<14:0>, the six redundant word lines RDN10, RDN11, RDN12, RDN13, RDN14, and RDN15 in the first type redundant word line group are mapped to replace WL0, WL11, WL12, WL13, WL14, and WL15 among the eight ordinary word lines respectively; G<1:0>=11, indicating that the redundant word lines RDN16 and RDN17 in the fourth group of redundant word line sub-groups are mapped to jump to RDN26 and RDN27 in the second type redundant word line group, and these two redundant word lines are used to map and replace WL16 and WL17 among the eight ordinary word lines.

[0075] The above embodiment uses the first type word line mapping address Efsadd <RA<14:3> ,G<1:0>,flag> includes a group of redundant word line replacement signals G<1:0> as columns to introduce the working principle of the present application, that is, the word line addressing address matches a first type word line mapping address and a second type word line mapping address. However, it can be understood by those skilled in the art that the first type word line mapping address can also include multiple groups of redundant word line replacement signals G1<1:0>, G2<1:0>... and so on, that is to say, the redundant word lines in the multiple redundant word line subgroups in the first type redundant word line group corresponding to the first type word line mapping address are respectively replaced by the redundant word line mappings in the multiple second type redundant word line groups corresponding to the multiple second type word line mapping addresses. For example, the 8 redundant word lines in the first type redundant word line group are divided into 4 redundant word line groups, among which 4 redundant word lines in 2 redundant word line groups are damaged, and they are replaced by the redundant word line mappings in the 2 second type redundant word line groups corresponding to the 2 second type word line mapping addresses.

[0076] Furthermore, in some embodiments, Figure 4 As shown, the programming storage circuit 12 further includes a bit line programming unit 123, wherein at least one bit line mapping address Efsadd (for example, Figure 4 Efsadd as shown <CA<9:3> , flag>), the bit line mapping address Efsadd can be the corresponding address of the faulty bit line found in the test before the DRAM leaves the factory. Each bit line mapping address Efsadd can correspond to a redundant bit line of a redundant bit line group, and the bit line mapping address Efsadd can be used to perform simultaneous mapping replacement of multiple redundant bit lines in the corresponding redundant bit line group.

[0077] Correspondingly, the processing circuit 14 further includes a bit line latch unit 144. The bit line latch unit 144 is used to cache the bit line mapping address programmed by the bit line programming unit 123. In addition, the bit line latch unit 144 also receives the bit line addressing address CA<9:3> transmitted from the command decoder 13, compares the bit line addressing address CA<9:3> with the bit line mapping address Efsadd <CA<9:3> , flag>, that is, determine whether the bit line addressing address CA<9:3> is consistent with the cached bit line mapping address Efsadd <CA<9:3> , flag> matches, where the bit line addressing address CA can be the bit line address that the user wants to access, and determines that the bit line addressing address CA<9:3> matches the cached bit line mapping address Efsadd <CA<9:3> ,flag>matches and generates the corresponding redundant bit line enable signal RBL_en.

[0078] In summary, the storage device 10 of the present application includes a storage array 11, a programming storage circuit 12, a command decoder 13, and a processing circuit 14. The processing circuit 14 is coupled to the programming storage circuit 12, the command decoder 13, and the storage array 11. Among them, the word line mapping addresses stored in the programming storage circuit 12 include at least two types of word line mapping addresses. Each type of word line mapping address corresponds to a type of redundant word line group, and the number of redundant word lines in various types of redundant word line groups is different. Furthermore, the processing circuit 14 can generate corresponding redundant word line enable signals to drive the redundant word lines in at least one redundant word line group corresponding to at least one matched word line mapping address to map and replace a group of normal word lines corresponding to the word line addressing address in response to the word line addressing address matching at least one word line mapping address. Therefore, the present application improves the efficiency and flexibility of storage chip repair.

[0079] Furthermore, when some of the first type of redundant word lines (M) in the first type of redundant word line group are also damaged, an embodiment of the present invention uses the second type of redundant word lines in the second type of redundant word line group to replace some of the first type of redundant word lines (N) to map and replace the normal word lines corresponding to the word line addressing address, without occupying an additional group of the first type of redundant word line group (M, where N < M), thus saving redundant word line resources. In addition, even when N ≥ M, when some of the first type of redundant word lines (M) in the first type of redundant word line group are damaged, an embodiment of the present invention can also use the second type of redundant word lines (N) in the second type of redundant word line group to replace the first type of redundant word lines to map and replace the normal word lines corresponding to the word line addressing address, avoiding the situation where replacement cannot be achieved when the first type of redundant word lines in the first type of redundant word line group are exhausted.

[0080] The descriptions of the above embodiments tend to emphasize the differences between the embodiments. Their similarities or similarities can be referred to each other. For the sake of brevity, they will not be elaborated herein.

[0081] In several embodiments provided by the present application, it should be understood that the disclosed methods and related devices can be implemented in other ways. For example, the above-described related device embodiments are merely illustrative. For example, the division of modules or units is only a logical function division. In actual implementation, there may be other division methods. For example, units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the displayed or discussed coupling or direct coupling or communication disconnection between each other can be through some interfaces. The indirect coupling or communication disconnection of devices or units can be in electrical, mechanical or other forms.

[0082] In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit. The above-mentioned integrated unit may be implemented in the form of hardware or in the form of software functional units.

[0083] It is easy for a person skilled in the art to know that many modifications and changes can be made to the device and method while maintaining the teaching content of the present application. Therefore, the above disclosure should be considered as limited only by the scope of the appended claims. < / a-1:b> < / a-1:b>

Claims

1. A storage device, characterized in that: include: A storage array, comprising a normal storage array and a redundant storage array, wherein the redundant word lines in the redundant storage array are used to map and replace the normal word lines in the normal storage array, so that the redundant storage cells in the redundant storage array map and replace the damaged normal storage cells in the normal storage array; A burning storage circuit is configured to store at least one word line mapping address, wherein each of the word line mapping addresses corresponds to a redundant word line of a redundant word line group; A command decoder configured to generate a corresponding word line address in response to a user command; a processing circuit coupled to the burn storage circuit, the command decoder and the storage array; wherein the processing circuit is configured to receive the word line addressing address and the word line mapping address; in response to the word line addressing address matching at least one of the word line mapping addresses, generate a corresponding redundant word line enable signal to drive the redundant word line mapping in at least one redundant word line group corresponding to the matched at least one word line mapping address to replace a group of normal word lines corresponding to the word line addressing address; The word line mapping addresses stored in the burning storage circuit include at least two types of word line mapping addresses, each type of word line mapping address corresponds to a type of redundant word line group, and the number of redundant word lines in each type of redundant word line group is different.

2. The storage device according to claim 1, characterized in that The processing circuit comprises: an address matching circuit, coupling the burn storage circuit and the command decoder, wherein the address matching circuit is configured to cache the word line mapping address from the burn storage circuit, receive the word line addressing address from the command decoder, and compare the word line addressing address with the word line mapping address to determine whether the word line addressing address matches at least one of the word line mapping addresses.

3. The storage device according to claim 2, characterized in that: The processing circuit further comprises: A redundant word line decoding circuit is coupled to the address matching circuit, wherein, in response to the address matching circuit determining that the word line addressing address matches at least one of the word line mapping addresses, the redundant word line decoding circuit is selected and receives the matched at least one word line mapping address from the address matching circuit, and generates a corresponding redundant word line enable signal based on the matched at least one word line mapping address to drive the redundant word line mapping in at least one of the redundant word line groups corresponding to the matched at least one word line mapping address to replace a group of the common word lines corresponding to the word line addressing address.

4. The storage device according to claim 1, characterized in that: The word line mapping addresses stored in the burn storage circuit include at least a plurality of first type word line mapping addresses and a plurality of second type word line mapping addresses, wherein each first type redundant word line group corresponding to each of the first type word line mapping addresses includes M redundant word lines, and each second type redundant word line group corresponding to each of the second type word line mapping addresses includes N redundant word lines, where M and N are natural numbers respectively, and M is not equal to N.

5. The storage device according to claim 4, characterized in that: In response to the word line addressing address matching a first type word line mapping address, the address matching circuit outputs the matched first type word line mapping address to the redundant word line decoding circuit; The redundant word line decoding circuit generates a corresponding redundant word line enable signal based on the matched first type word line mapping address to drive the M redundant word lines in the first type redundant word line group corresponding to the matched first type word line mapping address to map and replace a group of the common word lines corresponding to the word line addressing address; or In response to the word line addressing address matching a second type word line mapping address, the address matching circuit outputs the matched second type word line mapping address to the redundant word line decoding circuit; The redundant word line decoding circuit generates a corresponding redundant word line enable signal based on the matched second-type word line mapping address to drive the N redundant word lines in the second-type redundant word line group corresponding to the matched second-type word line mapping address to map and replace a group of the common word lines corresponding to the word line addressing address; or In response to the word line addressing address matching a first type word line mapping address and a second type word line mapping address, the address matching circuit outputs the matched first type word line mapping address and second type word line mapping address to the redundant word line decoding circuit; The redundant word line decoding circuit generates corresponding redundant word line enable signals based on the matched first type word line mapping address and the second type word line mapping address, so as to drive the M redundant word line mappings in the first type redundant word line group corresponding to the matched first type word line mapping address to replace a group of ordinary word lines corresponding to the word line addressing address, and drive the N redundant word line mappings in the second type redundant word line group corresponding to the matched second type word line mapping address to replace the corresponding N redundant word lines in the first type redundant word line group, wherein N is less than M.

6. The storage device according to claim 4, characterized in that: The word line addressing address includes an a-bit address signal; The first type word line mapping address includes a high address signal of (ab) bits and a first identification signal of 1 bit, wherein each of the first type word line mapping addresses corresponds to a first type redundant word line group, and the first type redundant word line group includes M=2 b the redundant word lines, the first identification signal indicates whether a first type redundant word line group corresponding to the first type word line mapping address is damaged; in response to the b-th to (a-1)-th address signals of the high bits in the a-bit address signal of the word line addressing address being consistent with the (ab)-th address signals of the high bits in the first type word line mapping address, the word line addressing address matches the first type word line mapping address; The second type word line mapping address includes a high address signal of (ac) bits and a second identification signal of 1 bit, wherein each second type word line mapping address corresponds to a second type redundant word line group, and the second type redundant word line group includes N=2 c the redundant word lines, the second identification signal represents whether a second type redundant word line group corresponding to the second type word line mapping address is damaged; in response to the high-order address signals of the cth to (a-1)th bits in the a-bit address signal of the word line addressing address being consistent with the high-order address signals of the (ac) bits in a second type word line mapping address, the word line addressing address matches the second type word line mapping address.

7. The storage device according to claim 6, characterized in that: The first type word line mapping address also includes a (bc)-bit redundant word line replacement signal, wherein the first type redundant word line group corresponding to the first type word line mapping address can be divided into two (b-c) Redundant word line subgroups, each of which includes N=2 c the redundant word lines, the (bc)-bit redundant word line replacement signal is used to indicate a corresponding redundant word line subgroup in the first type redundant word line group; In response to the word line addressing address matching a first type word line mapping address and a second type word line mapping address, and the first type word line mapping address also includes a (bc)-bit redundant word line replacement signal, the redundant word lines in the first type redundant word line group corresponding to the matched first type word line mapping address are driven to map and replace a group of the ordinary word lines corresponding to the word line addressing address, and the redundant word lines in the second type redundant word line group corresponding to the matched second type word line mapping address are used to map and replace the redundant word lines in the redundant word line subgroup indicated by the (bc)-bit redundant word line replacement signal in the first type redundant word line group.

8. The storage device according to claim 7, characterized in that: The first type redundant word line group corresponding to the first type word line mapping address includes 8 redundant word lines, where M=8; The second type redundant word line group corresponding to the second type word line mapping address includes two redundant word lines, wherein N=2; The word line addressing address includes a 15-bit address signal, defined as ra〈14:0〉, where a=15; The first type word line mapping address includes a 12-bit high address signal <14:3>, a 2-bit redundant word line replacement signal G<1:0> and a first identification signal flag, and the first type word line mapping address is defined as efsadd<14:3, G<1:0>, flag>, where b=3; The second type word line mapping address includes a 14-bit high address signal <14:1> and a second identification signal flag, and the second type word line mapping address is defined as efsadd <14:1, flag>, where c=1; Among them, the redundant word line replacement signal G〈1:0〉 in the first type word line mapping address is a 2-bit redundant word line replacement signal, used to indicate that the redundant word lines in a group of redundant word line sub-groups in 4 redundant word line sub-groups need to be replaced by the redundant word line mapping in the second type redundant word line group corresponding to the second type word line mapping address.

9. The storage device according to claim 2, characterized in that: The processing circuit further comprises: A common word line decoding circuit is coupled to the address matching circuit, wherein, in response to the address matching circuit determining that the word line addressing address and the word line mapping address do not match, the common word line decoding circuit is selected and receives the word line addressing address from the address matching circuit, and generates a corresponding common word line enable signal based on the word line addressing address to drive the common word line corresponding to the word line addressing address.

10. The storage device according to claim 7, characterized in that: The processing circuit further comprises: A redundant word line decoding circuit, wherein the redundant word line decoding circuit comprises a first type redundant word line decoding circuit and a second type redundant word line decoding circuit, wherein: In response to the word line addressing address matching the first type word line mapping address and the first type word line mapping address further comprising a (bc)-bit redundant word line replacement signal, the first type redundant word line decoding circuit masks redundant word line enable signals of N redundant word lines in the redundant word line subgroup indicated by the (bc)-bit redundant word line replacement signal in the first type redundant word line group, wherein bc=N, and generates redundant word line enable signals of the remaining MN redundant word lines in the M redundant word lines of the first type redundant word line group corresponding to the matched first type word line mapping address; In response to the word line addressing address matching the second type word line mapping address, the second type redundant word line decoding circuit drives the N redundant word lines in the second type redundant word line group corresponding to the matched second type word line mapping address.

11. The storage device according to claim 10, characterized in that: The processing circuit further comprises: The address matching circuit includes a first address matching circuit and a second address matching circuit, wherein: The first address matching circuit determines whether the address signals of the bth to (a-1)th bits in the a-bit address signal of the word line addressing address are consistent with the high-bit address signals of the (ab)th bits in the first type word line mapping address. The second address matching circuit determines whether the address signals of the cth to (a-1)th high bits in the a-bit address signal of the word line addressing address are consistent with the high-bit address signals of the (ac) bits in the second-type word line mapping address.

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