Semiconductor device and manufacturing method thereof

Abstract

The invention discloses a semiconductor device and a manufacturing method thereof, and the manufacturing method comprises the steps: providing a semiconductor device which comprises a substrate, a dielectric layer with a groove is formed on the substrate, and a barrier layer and a metal layer are sequentially formed on the dielectric layer; wherein the dielectric layer comprises a first dielectric layer, a second dielectric layer and a third dielectric layer which are arranged from bottom to top, and the third dielectric layer is a nitride layer; and executing a grinding process to remove the metal layer and the barrier layer on the outer side of the groove and the third dielectric layer. According to the invention, the surface of the remaining second dielectric layer can be prevented from generating defects, the current breakdown risk is reduced, and the reliability of the semiconductor device is improved.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a semiconductor device and a method for manufacturing the same. Background Art

[0002] In the integrated circuit manufacturing process, copper metal deposition usually requires a chemical mechanical polishing process for planarization.

[0003] In the related art, the process stack on the substrate is an NDC / LK / Oxide / TiN / Oxide structure, which causes the LK layer to easily produce depression defects after chemical mechanical polishing, resulting in the risk of current breakdown and reducing the reliability of the device. Summary of the invention

[0004] A series of simplified concepts are introduced in the Summary of the Invention section, which will be further described in detail in the Detailed Description of the Invention section. The Summary of the Invention section of this application does not mean to attempt to define the key features and essential technical features of the claimed technical solution, nor does it mean to attempt to determine the scope of protection of the claimed technical solution.

[0005] In view of the existing problems, the present application provides a method for manufacturing a semiconductor device, the method for manufacturing a semiconductor device comprising: A semiconductor device is provided, the semiconductor device comprising a substrate, a dielectric layer having a groove is formed on the substrate, a barrier layer and a metal layer are sequentially formed on the dielectric layer; wherein the dielectric layer comprises a first dielectric layer, a second dielectric layer and a third dielectric layer arranged from bottom to top, wherein the third dielectric layer is a nitride layer; A grinding process is performed to remove the metal layer and the barrier layer outside the trench, and the third dielectric layer.

[0006] In some embodiments of the present application, the performing of the grinding process to remove the metal layer and the barrier layer outside the trench, and the third dielectric layer, includes: Performing a first grinding process on a first grinding pad to remove a portion of the thickness of the metal layer; performing a second polishing process on a second polishing pad to remove the barrier layer and the metal layer above the third dielectric layer; A third polishing process is performed on the third polishing pad to remove the third dielectric layer.

[0007] In some embodiments of the present application, grinding endpoint detection is respectively provided in the first grinding process, the second grinding process and the third grinding process.

[0008] In some embodiments of the present application, the step of forming the semiconductor device includes: providing a substrate; Depositing a first dielectric layer, a second dielectric layer and a third dielectric layer in sequence on the substrate; forming a mask on the third dielectric layer, and performing etching based on the mask to form a trench in the dielectric layer; The barrier layer and the metal layer are deposited sequentially.

[0009] In some embodiments of the present application, the barrier layer includes titanium or titanium nitride.

[0010] In some embodiments of the present application, the metal layer includes copper.

[0011] In some embodiments of the present application, the first dielectric layer includes nitrogen-doped silicon carbide.

[0012] In some embodiments of the present application, the second dielectric layer includes a low dielectric constant material.

[0013] On the other hand, the present application provides a semiconductor device obtained by using any of the manufacturing methods described above.

[0014] According to the semiconductor device and the manufacturing method thereof of the embodiment of the present application, the provided semiconductor device has a first dielectric layer, a second dielectric layer and a third dielectric layer arranged from bottom to top formed on a substrate, and the third dielectric layer is a nitride layer. Then, the metal layer and the barrier layer outside the groove, as well as the third dielectric layer, are removed in the grinding process, which can avoid defects on the surface of the remaining second dielectric layer, reduce the risk of current breakdown, and improve the reliability of the semiconductor device. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] The following drawings of the present application are used as a part of the present application for understanding the present application. The drawings show the embodiments of the present application and their descriptions, which are used to explain the principle of the present application.

[0016] Figure 1 A cross-sectional schematic diagram of a semiconductor device provided in the related art is shown.

[0017] Figure 2 A schematic diagram showing a concave defect generated on the surface of a low dielectric constant material layer after chemical mechanical polishing of a semiconductor device in the related art is shown.

[0018] Figure 3 A flow chart of a method for manufacturing a semiconductor device according to a specific embodiment of the present application is shown.

[0019] FIG. 4A to FIG. 4D A cross-sectional schematic diagram of a structure obtained by sequentially implementing a method for preparing a semiconductor device according to a specific embodiment of the present application is shown.

[0020] FIG. 5A to FIG. 5E A cross-sectional schematic diagram of a structure obtained by sequentially implementing a method for forming a semiconductor device according to a specific embodiment of the present application is shown. DETAILED DESCRIPTION

[0021] In the following description, a large number of specific details are provided to provide a more thorough understanding of the present application. However, it is apparent to those skilled in the art that the present application can be implemented without one or more of these details. In other examples, in order to avoid confusion with the present application, some technical features well known in the art are not described.

[0022] It should be understood that the present application can be implemented in different forms and should not be construed as being limited to the embodiments presented herein. On the contrary, providing these embodiments will make the disclosure thorough and complete and fully convey the scope of the present application to those skilled in the art. In the accompanying drawings, the sizes and relative sizes of layers and regions may be exaggerated for clarity. The same reference numerals throughout represent the same elements.

[0023] It should be understood that when an element or layer is referred to as "on ...", "adjacent to ...", "connected to" or "coupled to" other elements or layers, it can be directly on, adjacent to, connected to or coupled to other elements or layers, or there can be intervening elements or layers. On the contrary, when an element is referred to as "directly on ...", "directly adjacent to ...", "directly connected to" or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. can be used to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, without departing from the teachings of the present application, the first element, component, region, layer or part discussed below can be represented as the second element, component, region, layer or part.

[0024] Spatial relationship terms such as "under", "below", "below", "under", "above", "above", etc., may be used here for convenience of description to describe the relationship between an element or feature shown in the figure and other elements or features. It should be understood that in addition to the orientation shown in the figure, the spatial relationship terms are intended to include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is turned over, then the elements or features described as "under other elements" or "under it" or "under it" will be oriented as "on" other elements or features. Therefore, the exemplary terms "under" and "under" may include both upper and lower orientations. The device can be oriented otherwise (rotated 90 degrees or other orientations) and the spatial descriptors used herein are interpreted accordingly.

[0025] The purpose of the terms used herein is only to describe specific embodiments and is not intended to be limiting of the present application. When used herein, the singular forms "one", "an" and "said / the" are also intended to include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "consisting of" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0026] like Figure 1 As shown, the semiconductor device provided in the related art includes a substrate 101, on which a nitrogen-doped silicon carbide layer 102 (NDC), a low dielectric constant material layer 103 (LK), a first oxide layer 104 (Oxide), a titanium nitride layer 105 (TiN) and a second oxide layer 106 (Oxide) are sequentially deposited, a groove is formed in the above-mentioned dielectric layer, and then a barrier layer 107 and a copper metal layer 108 are sequentially deposited.

[0027] When the semiconductor device is subjected to chemical mechanical polishing, a portion of the low dielectric constant material layer and the first oxide layer, titanium nitride layer, second oxide layer, barrier layer and copper metal layer thereon are removed through the polishing process. Due to the structure of the first oxide layer, titanium nitride layer and second oxide layer above the low dielectric constant material layer, the surface of the remaining low dielectric constant material layer of the semiconductor device after chemical mechanical polishing is prone to concave defects (the existing concave defects can be seen in Figure 2 ), causing the risk of current breakdown and reducing the reliability of semiconductor devices.

[0028] Therefore, in view of the existence of the above technical problems, the present application proposes a method for manufacturing a semiconductor device, such as Figure 3As shown, the method for manufacturing a semiconductor device includes: Step S1, providing a semiconductor device, wherein the semiconductor device comprises a substrate, a dielectric layer having a groove is formed on the substrate, and a barrier layer and a metal layer are sequentially formed on the dielectric layer; wherein the dielectric layer comprises a first dielectric layer, a second dielectric layer and a third dielectric layer arranged from bottom to top, wherein the third dielectric layer is a nitride layer; Step S2, performing a grinding process to remove the metal layer and the barrier layer outside the trench, as well as the third dielectric layer.

[0029] The manufacturing method of the semiconductor device of the present application provides a semiconductor device in which a first dielectric layer, a second dielectric layer and a third dielectric layer arranged from bottom to top are formed on a substrate, and the third dielectric layer is a nitride layer. The metal layer and the barrier layer outside the groove, as well as the third dielectric layer, are removed in the grinding process, which can avoid defects on the surface of the remaining second dielectric layer, reduce the risk of current breakdown, and improve the reliability of the semiconductor device.

[0030] In order to thoroughly understand the present application, detailed steps and structures will be presented in the following description to illustrate the technical solution proposed by the present application. The preferred embodiments of the present application are described in detail below, but in addition to these detailed descriptions, the present application may also have other implementation methods.

[0031] Below, reference 4A to 4D The manufacturing method of the semiconductor device of the present application is described in detail, wherein: FIG. 4A to FIG. 4D A cross-sectional schematic diagram of a semiconductor device obtained by sequentially implementing a method for manufacturing a semiconductor device according to a specific embodiment of the present application is shown.

[0032] Exemplarily, the method for manufacturing a semiconductor device of the present application includes the following steps: First, perform step 1, such as Figure 4A As shown, a semiconductor device is provided, which includes a substrate 401, a dielectric layer with a groove 405 is formed on the substrate 401, and a barrier layer 406 and a metal layer 407 are sequentially formed on the dielectric layer; wherein the dielectric layer includes a first dielectric layer 402, a second dielectric layer 403 and a third dielectric layer 404 arranged from bottom to top, wherein the third dielectric layer 404 is a nitride layer.

[0033] In some embodiments, FIG. 5A to FIG. 5E As shown, the method for forming a semiconductor device may include the following steps S111 to S115: Step S111, as Figure 5A As shown, a substrate 401 is provided.

[0034] The provided substrate 401 may be any suitable semiconductor substrate 401, such as a bulk silicon substrate 401, and may also be at least one of the following materials: Si, Ge, SiGe, SiC, SiGeC, InAs, GaAs, InP or other III / V compound semiconductors, including multilayer structures composed of these semiconductors, or silicon on insulator (SOI), stacked silicon on insulator (SSOI), stacked silicon germanium on insulator (S-SiGeOI), silicon germanium on insulator (SiGeOI) and germanium on insulator (GeOI), or may also be double-sided polished silicon wafers (Double Side Polished Wafers, DSP), or may be ceramic substrates 401 such as alumina, quartz or glass substrates 401, etc.

[0035] Step S112, as Figure 5B As shown, a first dielectric layer 402 , a second dielectric layer 403 and a third dielectric layer 404 are sequentially deposited on a substrate 401 .

[0036] Specifically, a first dielectric material may be deposited on the substrate 401 to form a first dielectric layer 402 , and then a second dielectric material may be deposited on the first dielectric layer 402 to form a second dielectric layer 403 , and then a third dielectric material may be deposited on the second dielectric layer 403 to form a third dielectric layer 404 .

[0037] In some embodiments, the deposited first dielectric material may be nitrogen-doped silicon carbide, and thus the first dielectric layer 402 formed on the substrate 401 may be a nitrogen-doped silicon carbide layer.

[0038] In some embodiments, the deposited second dielectric material may be a low dielectric constant material, and thus the second dielectric layer 403 formed on the first dielectric layer 402 may be a low dielectric constant material layer.

[0039] In some embodiments, the deposited third dielectric material may be a nitride, such as silicon nitride (SiN), etc., which is not limited thereto, and the third dielectric layer 404 formed on the second dielectric layer 403 may be a nitride layer.

[0040] Step S113, as Figure 5C As shown, a mask is formed on the third dielectric layer 404, and etching is performed based on the mask to form a trench 405 in the dielectric layer.

[0041] Specifically, a photoresist mask layer may be formed on the third dielectric layer 404 , and the photoresist mask layer may be patterned through processes such as exposure and development to form a mask that defines a pattern of the trench 405 to be formed.

[0042] Afterwards, anisotropic etching can be performed by dry etching or wet etching. Taking wet etching as an example, the semiconductor device with a mask formed on the surface can be placed in an etchant solution, and the etchant and the dielectric layer can react chemically to remove the dielectric layer of the device that is not blocked by the mask (specifically, the third dielectric layer 404, the second dielectric layer 403 and the first dielectric layer 402 are removed in sequence). Afterwards, the mask on the remaining third dielectric layer 404 can be removed.

[0043] Step S114, as Figure 5D and 5E As shown, a barrier layer 406 and a metal layer 407 are deposited in sequence.

[0044] Specifically, barrier layer 406 is first deposited, and the deposited barrier layer 406 covers the sidewalls and bottom walls of third dielectric layer 404 and trench 405. Barrier layer 406 can prevent the diffusion of subsequently deposited metal into the dielectric layer, and barrier layer 406 can be titanium or titanium nitride, tantalum or tantalum nitride, etc., which is not limited. Then, metal layer 407 is deposited, and the deposited metal layer 407 covers barrier layer 406 and fills trench 405. When depositing metal layer 407, a seed layer of metal material can be first grown on barrier layer 406, and then metal electroplating is performed, so as to form metal layer 407 on barrier layer 406.

[0045] In some embodiments, the deposited metal layer 407 may be a copper metal layer or a metal layer made of any other suitable metal material, which is not limited.

[0046] Next, execute step 2, such as Figure 4B to Figure 4D As shown, a grinding process is performed to remove the metal layer 407 and the barrier layer 406 outside the trench 405 , as well as the third dielectric layer 404 .

[0047] In some embodiments, Figure 4B to Figure 4D As shown, performing a grinding process to remove the metal layer 407 and the barrier layer 406 outside the groove 405 and the third dielectric layer 404 may include the following steps S211-S213: Step S211, as Figure 4B As shown, a first polishing process is performed on a first polishing pad to remove a partial thickness of the metal layer 407 .

[0048] Specifically, a first polishing pad is carried on the polishing table of a chemical mechanical polishing machine. When the first polishing process needs to be performed on the semiconductor device, the semiconductor device is adsorbed on the polishing head of the chemical mechanical polishing machine so that the surface to be polished of the semiconductor device is arranged opposite to the rotating first polishing pad. At this time, a polishing liquid composed of abrasive particles and chemical additives can be provided on the first polishing pad through a polishing liquid nozzle; then, the polishing head provides a controllable load such as pressure to the semiconductor device, and the surface to be polished of the semiconductor device is pressed tightly against the first polishing pad. With the relative movement between the semiconductor device and the first polishing pad, and the spraying of the polishing liquid on the first polishing pad, the semiconductor device is polished to form a flat surface.

[0049] In the first grinding process, the metal layer 407 can be ground at a relatively high grinding rate (rough grinding) to remove most of the thickness of the metal layer 407 above the barrier layer 406. In the first grinding process, a grinding endpoint detection is provided, and any suitable method can be used to determine the grinding endpoint, such as an optical endpoint detection method, an electrical endpoint detection method, a time endpoint detection method, a thickness endpoint detection method, etc., which is not limited thereto.

[0050] Step S212, as Figure 4C As shown, a second polishing process is performed on the second polishing pad to remove the barrier layer 406 and the metal layer 407 above the third dielectric layer 404 .

[0051] Similarly, a second polishing pad is carried on the polishing table of the chemical mechanical polishing machine. When the second polishing process needs to be performed on the semiconductor device, the semiconductor device is adsorbed on the polishing head of the chemical mechanical polishing machine so that the surface to be polished of the semiconductor device is arranged opposite to the rotating second polishing pad. At this time, a polishing liquid composed of abrasive particles and chemical additives can be provided on the second polishing pad through a polishing liquid nozzle; then, the polishing head provides a controllable load such as pressure to the semiconductor device, and the surface to be polished of the semiconductor device is pressed tightly against the second polishing pad. With the relative movement between the semiconductor device and the second polishing pad, and the spraying of the polishing liquid on the second polishing pad, the semiconductor device is polished to form a flat surface.

[0052] In the second grinding process, a relatively small grinding rate (fine grinding) can be used for grinding to remove the barrier layer 406 and the metal layer 407 above the third dielectric layer 404. In the second grinding process, a grinding endpoint detection is provided, and any suitable method can be used to determine the grinding endpoint, such as an optical endpoint detection method, an electrical endpoint detection method, a time endpoint detection method, a thickness endpoint detection method, etc., which is not limited.

[0053] It should be noted that, in the second polishing process, a portion of the third dielectric layer 404 may also be removed.

[0054] Step S213, as Figure 4D As shown, a third polishing process is performed on the third polishing pad to remove the third dielectric layer 404 .

[0055] Similarly, a third polishing pad is carried on the polishing table of the chemical mechanical polishing machine. When the third polishing process needs to be performed on the semiconductor device, the semiconductor device is adsorbed on the polishing head of the chemical mechanical polishing machine so that the surface to be polished of the semiconductor device is arranged opposite to the rotating third polishing pad. At this time, a polishing liquid composed of abrasive particles and chemical additives can be provided on the third polishing pad through a polishing liquid nozzle; then, the polishing head provides a controllable load such as pressure to the semiconductor device, and the surface to be polished of the semiconductor device is pressed tightly against the third polishing pad. With the relative movement between the semiconductor device and the third polishing pad, and the spraying of the polishing liquid on the third polishing pad, the semiconductor device is polished to form a flat surface.

[0056] In the third grinding process, a relatively small grinding rate (fine grinding) can be used for grinding to remove the third dielectric layer 404. In the third grinding process, a grinding end point detection is provided, and any suitable method can be used to determine the grinding end point, such as an optical end point detection method, an electrical end point detection method, a time end point detection method, a thickness end point detection method, etc., which are not limited thereto.

[0057] It should be noted that, in the second grinding process, a portion of the second dielectric layer 403 may also be removed.

[0058] In the above-mentioned grinding process, since the process stack on the substrate 401 is an NDC / LK / SiN structure, the polishing rate of the chemical mechanical grinding is easier to match, thereby reducing the process complexity of the chemical mechanical grinding, increasing the process window of the chemical mechanical grinding, avoiding defects on the surface of the remaining second dielectric layer 403, reducing the risk of current breakdown, and improving the reliability of the semiconductor device.

[0059] In any of steps SS211 to S213, taking the determination of the grinding endpoint by optical endpoint detection as an example, as the grinding proceeds, the material on the surface of the semiconductor device is gradually removed, and its surface roughness and optical properties change, resulting in changes in the intensity and characteristics of the reflected light. Therefore, an optical sensor or interferometer can be used to measure the intensity and wavelength of the reflected light. When the grinding approaches the endpoint, the intensity of the reflected light will change significantly, or the characteristics of the interference fringes will change. For example, a threshold value for the intensity of the reflected light can be set, and when the detected intensity of the reflected light reaches this threshold value, it is determined that the grinding has reached the endpoint.

[0060] Taking the electrical endpoint detection method to determine the grinding endpoint as an example, during the grinding process, the material on the surface of the semiconductor device is gradually removed, and its electrical properties (such as resistance, capacitance, etc.) will change. By using electrical sensors or testing equipment to measure the electrical parameters such as resistance and capacitance on the surface of the semiconductor device, it is determined whether the grinding has reached the corresponding structural layer (for example, in step S211, it is determined whether the grinding has reached the metal layer 407; in step S212, it is determined whether the grinding has reached the third dielectric layer 404; in step S213, it is determined whether the grinding has reached the second dielectric layer 403) to ensure that the grinding is stopped accurately.

[0061] Taking the determination of the grinding endpoint by the thickness endpoint detection method as an example, during the grinding process, the semiconductor device is measured regularly using a thickness measuring device to determine whether the thickness of the corresponding structural layer is close to the predetermined endpoint thickness (for example, in step S211, determine whether the thickness of the metal layer 407 remaining on the barrier layer 406 is close to the predetermined endpoint thickness; in step S212, determine whether the thickness of the third dielectric layer 404 remaining on the second dielectric layer 403 is close to the predetermined endpoint thickness; in step S213, determine whether the thickness of the second dielectric layer 403 remaining on the first dielectric layer 402 is close to the predetermined endpoint thickness). When the measured thickness is close to the predetermined endpoint thickness, the grinding pressure can be gradually reduced or the grinding parameters can be adjusted to ensure that the grinding is stopped accurately.

[0062] Taking the determination of the grinding endpoint by the time endpoint detection method as an example, an average grinding time can be determined through multiple experiments, and then grinding is performed according to this time, and grinding is stopped after the grinding time is reached.

[0063] In summary, according to the semiconductor device and the manufacturing method thereof of the embodiments of the present application, the provided semiconductor device has a first dielectric layer, a second dielectric layer and a third dielectric layer arranged from bottom to top formed on a substrate, and the third dielectric layer is a nitride layer. Then, the metal layer and the barrier layer outside the groove, as well as the third dielectric layer, are removed during the grinding process, which can avoid defects on the surface of the remaining second dielectric layer, reduce the risk of current breakdown, and improve the reliability of the semiconductor device.

[0064] Although example embodiments have been described herein with reference to the accompanying drawings, it should be understood that the above example embodiments are merely exemplary and are not intended to limit the scope of the present application to this. Those of ordinary skill in the art may make various changes and modifications therein without departing from the scope and spirit of the present application. All these changes and modifications are intended to be included within the scope of the present application as required by the appended claims.

[0065] Similarly, it should be understood that in order to streamline the present application and help understand one or more of the various application aspects, in the description of the exemplary embodiments of the present application, the various features of the present application are sometimes grouped together into a single embodiment, figure, or description thereof. However, the method of the present application should not be interpreted as reflecting the following intention: the claimed application requires more features than the features clearly stated in each claim. More specifically, as reflected in the corresponding claims, the application point is that the corresponding technical problem can be solved with less than all the features of a single disclosed embodiment. Therefore, the claims following the specific embodiment are hereby explicitly incorporated into the specific embodiment, wherein each claim itself serves as a separate embodiment of the present application.

[0066] In addition, those skilled in the art will appreciate that, although some embodiments described herein include certain features included in other embodiments but not other features, the combination of features of different embodiments is meant to be within the scope of the present application and form different embodiments. For example, in the claims, any one of the claimed embodiments can be used in any combination.

[0067] It should be noted that the above embodiments illustrate rather than limit the present application, and that those skilled in the art may devise alternative embodiments without departing from the scope of the appended claims. In the claims, any reference symbol between brackets should not be construed as a limitation to the claims. The use of the words first, second, and third, etc. does not indicate any order. These words may be interpreted as names.

Claims

1. A method for manufacturing a semiconductor device, characterized in that: The manufacturing method comprises: A substrate is provided, on which a dielectric layer having a groove is formed, and a barrier layer and a metal layer are sequentially formed on the dielectric layer; wherein the dielectric layer comprises a first dielectric layer, a second dielectric layer and a third dielectric layer arranged from bottom to top, wherein the third dielectric layer is a nitride layer; A grinding process is performed to remove the metal layer and the barrier layer outside the trench, and the third dielectric layer.

2. The method for manufacturing a semiconductor device according to claim 1, wherein: The performing of the grinding process to remove the metal layer and the barrier layer outside the trench, and the third dielectric layer, comprises: Performing a first grinding process on a first grinding pad to remove a portion of the thickness of the metal layer; performing a second polishing process on a second polishing pad to remove the barrier layer and the metal layer above the third dielectric layer; A third polishing process is performed on the third polishing pad to remove the third dielectric layer.

3. The method for manufacturing a semiconductor device according to claim 2, wherein: Polishing endpoint detection is provided in each of the first polishing step, the second polishing step, and the third polishing step.

4. The method for manufacturing a semiconductor device according to claim 1, wherein: The steps of forming the semiconductor device include: providing a substrate; Depositing a first dielectric layer, a second dielectric layer and a third dielectric layer in sequence on the substrate; forming a mask on the third dielectric layer, and performing etching based on the mask to form a trench in the dielectric layer; The barrier layer and the metal layer are deposited in sequence.

5. The method for manufacturing a semiconductor device according to claim 1, wherein: The barrier layer includes titanium or titanium nitride.

6. The method for manufacturing a semiconductor device according to claim 1, wherein: The metal layer includes copper.

7. The method for manufacturing a semiconductor device according to claim 1, wherein: The first dielectric layer includes nitrogen-doped silicon carbide.

8. The method for manufacturing a semiconductor device according to claim 1, wherein: The second dielectric layer includes a low dielectric constant material.

9. A semiconductor device, characterized in that: The method is obtained by the production method according to any one of claims 1 to 8.

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