Semiconductor structure and manufacturing method thereof

Abstract

The embodiment of the invention relates to the field of semiconductors, and provides a semiconductor structure and a manufacturing method thereof, and the structure comprises a word line which extends along a third direction; the semiconductor layer surrounds the side wall of the word line along the first direction; the bit line is located on one side, in the first direction, of the word line and extends in the second direction, the first direction is different from the second direction, and the bit line makes contact with the surface, away from the word line, of the semiconductor layer; the capacitor is located on the other side, in the first direction, of the word line and comprises a lower electrode layer, a dielectric layer and an upper electrode layer which are sequentially stacked, the lower electrode layer extends in the first direction, and the surface of the side, away from the word line, of the lower electrode layer is sunken in the direction pointing to the word line or protrudes in the direction away from the word line in the first direction; the dielectric layer covers part of the surface of the lower electrode layer, and the upper electrode layer covers the surface, away from the lower electrode layer, of the dielectric layer. According to the semiconductor structure and the manufacturing method thereof provided by the embodiment of the invention, the stability of the semiconductor structure is at least improved.

Description

Technical Field

[0001] The embodiments of the present disclosure relate to the semiconductor field, and in particular to a semiconductor structure and a method for manufacturing the same. Background Art

[0002] Memory is a memory component used to store programs and various data information. The random access memory (RAM) used in general computer systems can be divided into two types: dynamic random access memory (DRAM) and static random access memory (SRAM). Dynamic random access memory is a commonly used semiconductor memory device in computers, consisting of many repeated storage units.

[0003] A memory cell generally includes a capacitor and a transistor, wherein one of the source, drain or drain of the transistor is connected to a bit line structure, and the other of the source, drain or drain is connected to a capacitor, and the capacitor includes a capacitor contact structure and a capacitor. The word line structure of the memory cell can control the opening or closing of the channel region of the transistor, thereby reading the data information stored in the capacitor through the bit line structure, or writing the data information into the capacitor for storage through the bit line structure. Summary of the invention

[0004] The embodiments of the present disclosure provide a semiconductor structure and a method for manufacturing the same, which are at least beneficial to improving the stability of the semiconductor structure.

[0005] According to some embodiments of the present disclosure, on the one hand, an embodiment of the present disclosure provides a semiconductor structure, including: a word line, which extends along a third direction; a semiconductor layer, which surrounds the side wall of the word line along a first direction; a bit line, which is located on one side of the word line along the first direction, and the bit line extends along a second direction, the first direction is different from the second direction, and the bit line contacts a surface of the semiconductor layer away from the word line; a capacitor, which is located on the other side of the word line along the first direction, the capacitor includes a lower electrode layer, a dielectric layer and an upper electrode layer stacked in sequence, the lower electrode layer extends along the first direction, and a surface of the lower electrode layer away from the word line along the first direction is recessed in a direction pointing to the word line or convex in a direction away from the word line, the dielectric layer covers a portion of the surface of the lower electrode layer, and the upper electrode layer covers a surface of the dielectric layer away from the lower electrode layer.

[0006] In some embodiments, the semiconductor structure also includes: a supporting layer, the supporting layer extends along a third direction, the supporting layer is located on a side of the capacitor away from the word line along the first direction, along the first direction, a surface of the supporting layer facing the capacitor has a recessed portion, a surface of the lower electrode layer away from the word line protrudes in a direction away from the word line, and an end of the lower electrode layer away from the word line is located in the recessed portion.

[0007] In some embodiments, the semiconductor structure further includes: a supporting layer, the supporting layer extending along a third direction, the supporting layer being located on a side of the capacitor away from the word line along the first direction, along the first direction, a surface of the supporting layer on a side facing the capacitor having a protrusion, a surface of the lower electrode layer on a side away from the word line being recessed in a direction pointing to the word line, and the protrusion being located in the recess of the lower electrode layer.

[0008] In some embodiments, the word line includes a word line body and an extension surrounding the word line body, and the semiconductor layer surrounds a surface of the extension.

[0009] In some embodiments, the semiconductor structure also includes: an insulating layer, the insulating layer is located on opposite sides of the extension portion along the third direction, and covers two opposite surfaces of the semiconductor layer along the third direction, the insulating layer extends along a first direction, one end of the insulating layer is in contact with the word line body, and the other end extends in a direction away from the word line body, and a surface of the insulating layer on a side away from the word line is flush with a surface of the lower electrode layer on a side facing the word line, or is further away from the word line body than the surface of the lower electrode layer on a side facing the word line.

[0010] According to some embodiments of the present disclosure, the embodiments of the present disclosure also provide a method for manufacturing a semiconductor structure, comprising: providing a substrate; forming a stacked structure on the substrate, the stacked structure comprising a first sacrificial layer and a second sacrificial layer alternately stacked; patterning the stacked structure to form a word line groove; forming a semiconductor layer, the semiconductor layer covering the inner wall of the word line groove; filling the remaining word line groove to form a word line, the word line extending along a third direction, the semiconductor layer surrounding the side wall of the word line along the first direction; removing the second sacrificial layer located on one side of the word line groove along the first direction to form a bit line groove, the bit line groove extending along the second direction, the first direction and the second direction extending along the second direction. The second direction is different; filling the bit line groove to form a bit line, the bit line contacts the surface of the semiconductor layer away from the word line; removing the second sacrificial layer located on the other side of the word line groove along the first direction to form a lower electrode groove; filling the lower electrode groove to form a lower electrode layer, the lower electrode layer extends along the first direction, and the surface of the lower electrode layer away from the word line groove along the first direction is concave in the direction pointing to the word line groove or convex in the direction away from the word line groove; forming a dielectric layer, the dielectric layer covers part of the surface of the lower electrode layer; forming an upper electrode layer, the upper electrode layer covers the surface of the dielectric layer away from the lower electrode layer, and the lower electrode layer, the dielectric layer and the upper electrode layer constitute a capacitor.

[0011] In some embodiments, before removing the second sacrificial layer located on the other side of the word line groove along the first direction to form a lower electrode groove, it also includes: patterning the stacked structure to form a groove extending along the second direction; etching a portion of the first sacrificial layer along the first direction based on the groove; etching a portion of the first sacrificial layer to expose the second sacrificial layer; filling the groove to form a supporting layer.

[0012] In some embodiments, etching a portion of the first sacrificial layer along a first direction based on the groove includes: the first sacrificial layer exposes a portion of the second sacrificial layer, the width of the exposed second sacrificial layer along the first direction is a first width, the width of the second sacrificial layer along a third direction is a second width, and the first width is greater than the second width.

[0013] In some embodiments, the bit line and the lower electrode layer are formed in the same process step.

[0014] In some embodiments, after patterning the stacked structure to form a word line groove, the method further includes: removing a portion of the second sacrificial layer along the first direction and the second direction based on the word line groove; after forming the semiconductor layer, the method further includes: removing a portion of the semiconductor layer of the first sacrificial layer facing the surface of the word line groove.

[0015] The technical solution provided by the embodiments of the present disclosure has at least the following advantages:

[0016] In the semiconductor structure provided by the embodiment of the present disclosure, the word line extends along the third direction, and the semiconductor layer surrounds the side wall of the word line along the first direction, so as to form a structure in which the channel surrounds the word line, and the semiconductor layer on the two side walls of the word line along the first direction serves as a source region or a drain region, and the semiconductor layer on the two side walls of the word line along the second direction serves as a channel region. The bit line is located on one side of the word line along the first direction and is in electrical contact with the surface of the semiconductor layer, and the capacitor is located on the other side of the word line along the first direction, so as to form a storage unit, and the word line and the bit line are used to read and write the storage unit. In addition, the surface of the lower electrode layer of the capacitor on the side away from the word line along the first direction is concave in the direction pointing to the word line or convex in the direction away from the word line, that is, the surface of the lower electrode layer of the capacitor on the side away from the word line along the first direction is a non-planar structure, so that after forming the lower electrode layer of the capacitor, in the process of removing the material between the lower electrode layer to form the dielectric layer and the upper electrode layer, the lower electrode layer can be more firmly connected with other structures in the semiconductor structure. It can be understood that compared to a planar structure, a non-planar structure on the surface of the capacitor's lower electrode layer away from the word line along the first direction can help increase the friction between the lower electrode layer and the other structure, so as to avoid slippage between the end of the lower electrode layer away from the word line and the other structure after removing the material between the lower electrode layers, thereby improving the stability of the semiconductor structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] One or more embodiments are exemplarily illustrated by pictures in the corresponding drawings, and these exemplified descriptions do not constitute a limitation on the embodiments. Unless otherwise specified, the pictures in the drawings do not constitute a scale limitation. In order to more clearly illustrate the embodiments of the present disclosure or the technical solutions in the traditional technology, the drawings required for use in the embodiments are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0018] Figure 1 and Figure 2 Schematic diagram of various semiconductor structures provided by an embodiment of the present disclosure;

[0019] Figures 3 to 18 A schematic structural diagram corresponding to each step of a method for manufacturing a semiconductor structure provided in one embodiment of the present disclosure. DETAILED DESCRIPTION

[0020] According to some embodiments of the present disclosure, an embodiment of the present disclosure provides a semiconductor structure to improve the stability of the semiconductor structure.

[0021] The following will describe the various embodiments of the present disclosure in detail with reference to the accompanying drawings. However, it will be appreciated by those skilled in the art that in the various embodiments of the present disclosure, many technical details are provided in order to enable the reader to better understand the present disclosure. However, even without these technical details and various changes and modifications based on the following embodiments, the technical solutions claimed in the present disclosure can be implemented.

[0022] Figure 1 and Figure 2 The following is a schematic diagram of various semiconductor structures provided by an embodiment of the present disclosure. The semiconductor structure provided by the present embodiment will be described in detail in conjunction with the accompanying drawings, as follows:

[0023] refer to Figure 1 and Figure 2The semiconductor structure includes: a word line 300, the word line 300 extends along a third direction Z; a semiconductor layer 700, the semiconductor layer 700 surrounds the side wall of the word line 300 along a first direction X; a bit line 500, the bit line 500 is located on one side of the word line 300 along the first direction X, and the bit line 500 extends along a second direction Y, the first direction X is different from the second direction Y, the bit line 500 is in contact with a surface of the semiconductor layer 700 away from the word line 300; a capacitor 600, the capacitor 600 is located on the word line 300 along the On the other side of the first direction X, the capacitor 600 includes a lower electrode layer 601, a dielectric layer 602 and an upper electrode layer 603 stacked in sequence, the lower electrode layer 601 extends along the first direction X, and a surface of the lower electrode layer 601 along the first direction X away from the word line 300 is concave in the direction pointing to the word line 300 or convex in the direction away from the word line 300, the dielectric layer 602 covers a portion of the surface of the lower electrode layer 601, and the upper electrode layer 603 covers the surface of the dielectric layer 602 away from the lower electrode layer 601.

[0024] In the semiconductor structure provided by the embodiment of the present disclosure, the word line 300 extends along the third direction Z, and the semiconductor layer 700 surrounds the side wall of the word line 300 along the first direction X, so as to form a structure in which the channel surrounds the word line, and the semiconductor layer 700 on the two side walls of the word line 300 along the first direction X serves as a source region or a drain region, and the semiconductor layer 700 on the two side walls of the word line 300 along the second direction Y serves as a channel region. The bit line 500 is located on one side of the word line 300 along the first direction X and is in electrical contact with the surface of the semiconductor layer 700, and the capacitor 600 is located on the other side of the word line 300 along the first direction X, so as to form a storage unit, and the word line 300 and the bit line 500 are used to read and write the storage unit. In addition, the lower electrode layer 601 of the capacitor 600 is concave in the direction pointing to the word line 300 or convex in the direction away from the word line 300 on the side surface along the first direction X away from the word line 300, that is, the lower electrode layer 601 of the capacitor 600 is a non-planar structure on the side surface along the first direction X away from the word line 300, so that after forming the lower electrode layer 601 of the capacitor 600, in the process of removing the material between the lower electrode layer 601 to form the dielectric layer 602 and the upper electrode layer 603, the lower electrode layer 601 can be more firmly connected with other structures in the semiconductor structure. It can be understood that, compared with a planar structure, the non-planar structure of the side surface of the lower electrode layer 601 of the capacitor 600 away from the word line 300 along the first direction X can help increase the friction between the lower electrode layer 601 and other structures, so as to avoid slippage between the end of the lower electrode layer 601 away from the word line 300 and other structures after removing the material between the lower electrode layer 601, thereby improving the stability of the semiconductor structure.

[0025] In some embodiments, the semiconductor structure may further include a substrate 100 , and the word line 300 , the semiconductor layer 700 , the bit line 300 and the capacitor 600 are all located on the substrate 100 .

[0026] The material of the substrate 100 includes a basic semiconductor, a compound semiconductor or an alloy semiconductor. For example, the basic semiconductor includes germanium (Ge); the compound semiconductor includes silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, indium antimonide, and / or III-V semiconductor materials, etc.; the alloy semiconductor includes silicon germanium (SiGe), silicon germanium carbide, germanium tin, silicon germanium tin, gallium arsenic phosphide, gallium indium phosphide, gallium indium arsenide, indium gallium arsenide phosphide, aluminum indium arsenide, and / or aluminum gallium arsenide, etc. In some embodiments, the substrate 100 can also be a silicon-on-insulator structure, a silicon-germanium-on-insulator structure, a germanium-on-insulator structure, or a combination thereof.

[0027] The material of the word line 300 may include at least one of polysilicon, titanium nitride, titanium aluminide, tantalum nitride, nickel silicide, cobalt silicide, tantalum, aluminum, lanthanum, titanium, or tungsten.

[0028] In some embodiments, the sidewalls of the word lines may further include a gate dielectric layer, and the semiconductor layer surrounds the surface of the gate dielectric layer on the sidewalls of the word lines.

[0029] The material of the gate dielectric layer may include silicon oxide, silicon nitride, metal oxide, metal oxynitride, metal silicide, high-K material, ferroelectric material, anti-ferroelectric material or a combination thereof.

[0030] In some embodiments, reference Figure 1 and Figure 2 , the word line 300 may include a word line body 302 and an extension portion 303 surrounding the word line body 302, and the semiconductor layer 700 surrounds the surface of the extension portion 303, that is, the semiconductor layer 700 covers the sidewalls of the extension portion 303 and the two side surfaces of the extension portion 303 along the third direction Z. In other words, the extension portion 303 protrudes from the surface of the word line body 302, so that the extension portion 303 can further increase the surface area of ​​the word line 300, and the corresponding semiconductor layer 700 surrounds the surface of the extension portion 303, which can further increase the contact area between the semiconductor layer 700 and the word line 300, thereby improving the gate control ability of the word line 300. Reference Figure 1 The word line 300 may include a word line body 302 extending along a third direction Z and a plurality of extension portions 303 arranged along the third direction Z. The number of corresponding semiconductor layers 700 may be multiple, each semiconductor layer 700 surrounds the surface of an extension portion 303, and adjacent semiconductor layers 700 are spaced apart from each other. The plurality of semiconductor layers 700 may respectively constitute semiconductor channels of a plurality of transistors to increase the integration density of the semiconductor structure.

[0031] In some embodiments, the surface of the extension portion may further include a gate dielectric layer, and the semiconductor layer surrounds the surface of the gate dielectric layer.

[0032] In some embodiments, the semiconductor structure may further include: an insulating layer 211, the insulating layer 211 is located on opposite sides of the extension portion 303 along the third direction Z, and covers two opposite surfaces of the semiconductor layer 700 along the third direction Z, the insulating layer 211 extends along the first direction X, one end of the insulating layer 211 is in contact with the word line body 302, and the other end extends in a direction away from the word line body 302, and the surface of the insulating layer 211 on the side away from the word line 300 is flush with the surface of the lower electrode layer 601 on the side facing the word line 300, or is further away from the word line body 302 than the surface of the lower electrode layer 601 on the side facing the word line 300. Along the third direction Z, the insulating layer 211 can be used to isolate the semiconductor layer 700 from other structures in the semiconductor structure to prevent leakage between the semiconductor layer 700 and other structures. In addition, a surface of the insulating layer 211 away from the word line 300 is flush with a surface of the lower electrode layer 601 facing the word line 300, or is further away from the word line body 302 than the surface of the lower electrode layer 601 facing the word line 300. That is, the insulating layer 211 also covers a portion of the side wall of the lower electrode layer 601, so that the dielectric layer 602 can be isolated from the word line body 302 to avoid contamination of the dielectric layer 602 by the word line 300, and to prevent parasitic capacitance from being generated between the word line 300 and the lower electrode layer 601.

[0033] The material of the insulating layer 211 may include silicon oxide, silicon nitride, silicon oxynitride, or the like.

[0034] It should be noted that in Figure 1 In the example, the surface of the lower electrode layer 601 of the capacitor 600 facing the word line 300 is directly in contact with the semiconductor layer 700, which does not constitute a limitation on the positional relationship between the lower electrode layer 601 and the semiconductor layer 700. In some embodiments, a contact structure may be further included between the lower electrode layer and the semiconductor layer, and the contact structure is used to electrically connect the lower electrode layer and the semiconductor layer, and can reduce the contact resistance between the semiconductor layer and the lower electrode layer, and improve the electrical transmission performance between the lower electrode layer and the semiconductor layer.

[0035] The material of the contact structure includes one or more of tungsten, copper, aluminum or cobalt.

[0036] The material of the semiconductor layer 700 includes indium gallium zinc oxide, tungsten-doped indium oxide or indium tin oxide, etc. When the semiconductor channel is composed of the above materials, the carrier mobility of the semiconductor channel is lower than that of polysilicon, which can help reduce leakage current when the semiconductor structure is working, thereby reducing the power consumption of the semiconductor structure.

[0037] The material of the bit line 500 includes at least one of metal silicide, titanium nitride or tungsten. In some embodiments, the material of the bit line 500 may be a single metal, a metal compound or an alloy. The single metal may be aluminum, tungsten, gold or silver, etc. The metal compound may be tungsten nitride, tantalum nitride or titanium nitride; the alloy may be an alloy material composed of at least two of aluminum, tungsten, gold or silver.

[0038] In some embodiments, the semiconductor structure further includes: a support layer 411, the support layer 411 extends along the third direction Z, and the support layer 411 is located on a side of the capacitor 600 away from the word line 300 along the first direction X. The support layer 411 can serve as a support structure of the capacitor 600 on a side away from the word line 300 along the first direction X to improve the stability of the capacitor.

[0039] The material of the support layer 411 may be silicon oxide, silicon nitride, or silicon oxynitride.

[0040] In one example, refer to Figure 1 When the side surface of the lower electrode layer 601 away from the word line 300 bulges in the direction away from the word line 300, along the first direction X, the side surface of the support layer 411 facing the capacitor 600 may have a recessed portion 421, and the end of the lower electrode layer 601 away from the word line 300 is located in the recessed portion 421.

[0041] In another example, refer to Figure 2 When the side surface of the lower electrode layer 601 away from the word line 300 is recessed in the direction pointing to the word line 300, along the first direction X, the side surface of the support layer 411 facing the capacitor 600 may have a protrusion 431, and the protrusion 431 is located in the recess of the lower electrode layer 601.

[0042] In this way, the recessed portion 421 or the protruding portion 431 can improve the interfacial bonding force between the lower electrode layer 601 and the supporting layer 411, thereby improving the stability between the lower electrode layer 601 and the supporting layer 411, which is beneficial in the process of exposing the lower electrode layer 601 to form the dielectric layer 602 and the upper electrode layer 603. It is beneficial to improve the supporting role of the lower electrode layer 601, reduce the possibility of collapse of the lower electrode layer 601, and improve the stability of the semiconductor structure.

[0043] In the semiconductor structure provided by the embodiment of the present disclosure, the word line 300 extends along the third direction Z, and the semiconductor layer 700 surrounds the side wall of the word line 300 along the first direction X, so as to form a structure in which the channel surrounds the word line, and the semiconductor layer 700 on the two side walls of the word line 300 along the first direction X serves as a source region or a drain region, and the semiconductor layer 700 on the two side walls of the word line 300 along the second direction Y serves as a channel region. The bit line 500 is located on one side of the word line 300 along the first direction X and is in electrical contact with the surface of the semiconductor layer 700, and the capacitor 600 is located on the other side of the word line 300 along the first direction X, so as to form a storage unit, and the word line 300 and the bit line 500 are used to read and write the storage unit. In addition, the lower electrode layer 601 of the capacitor 600 is concave in the direction pointing to the word line 300 or convex in the direction away from the word line 300 on the side surface along the first direction X away from the word line 300, that is, the lower electrode layer 601 of the capacitor 600 is a non-planar structure on the side surface along the first direction X away from the word line 300, so that after forming the lower electrode layer 601 of the capacitor 600, in the process of removing the material between the lower electrode layer 601 to form the dielectric layer 602 and the upper electrode layer 603, the lower electrode layer 601 can be more firmly connected with other structures in the semiconductor structure. It can be understood that, compared with a planar structure, the non-planar structure of the side surface of the lower electrode layer 601 of the capacitor 600 away from the word line 300 along the first direction X can help increase the friction between the lower electrode layer 601 and other structures, so as to avoid slippage between the end of the lower electrode layer 601 away from the word line 300 and other structures after removing the material between the lower electrode layer 601, thereby improving the stability of the semiconductor structure.

[0044] According to some embodiments of the present disclosure, another embodiment of the present disclosure provides a method for manufacturing a semiconductor structure, which can be used to form the above-mentioned semiconductor structure to improve the performance of the formed semiconductor structure. It should be noted that the parts that are the same or corresponding to the above-mentioned embodiments can refer to the corresponding description of the above-mentioned embodiments, and will not be described in detail below.

[0045] Figures 3 to 18 A schematic structural diagram corresponding to each step of a method for manufacturing a semiconductor structure provided by an embodiment of the present disclosure, wherein: Figure 5 , Figures 7 to 15 , Fig.17 and Fig.18 for Figure 4 Schematic diagram of various cross-sectional structures along the AA1 direction, Figure 6 for Figure 4 Schematic diagram of the cross-sectional structure along the AA1 and BB1 directions, Fig.16 is a top view of a semiconductor structure. The semiconductor structure manufacturing method provided by this embodiment will be described in detail below in conjunction with the accompanying drawings, as follows:

[0046] refer to Figure 3 , providing a substrate 100; forming a stacked structure 200 on the substrate 100, the stacked structure 200 including a first sacrificial layer 201 and a second sacrificial layer 202 that are alternately stacked.

[0047] The material of the substrate 100 includes a basic semiconductor, a compound semiconductor or an alloy semiconductor. For example, the basic semiconductor includes germanium (Ge); the compound semiconductor includes silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, indium antimonide, and / or III-V semiconductor materials, etc.; the alloy semiconductor includes silicon germanium (SiGe), silicon germanium carbide, germanium tin, silicon germanium tin, gallium arsenic phosphide, gallium indium phosphide, gallium indium arsenide, indium gallium arsenide phosphide, aluminum indium arsenide, and / or aluminum gallium arsenide, etc. In some embodiments, the substrate 100 can also be a silicon-on-insulator structure, a silicon-germanium-on-insulator structure, a germanium-on-insulator structure, or a combination thereof.

[0048] The materials of the first sacrificial layer 201 and the second sacrificial layer 202 both include silicon oxide, silicon nitride or silicon oxynitride, etc. The first sacrificial layer 201 and the second sacrificial layer 202 are made of different materials, so that under the same etching environment, the first sacrificial layer 201 and the second sacrificial layer 202 may have different etching rates.

[0049] refer to Figure 4 , patterning the stacked structure 200 to form a word line trench 310 .

[0050] exist Figure 4 In the example, the number of word line slots 310 is three and arranged along the second direction Y, which does not constitute a limitation on the number of word line slots 310. In some embodiments, the number of word line slots may be 1, 5, or 10.

[0051] In some embodiments, a filling layer may be formed first to fill the word line groove, and after the bit line and capacitor are formed, the filling layer may be removed and the semiconductor layer and word line may be formed. Alternatively, a semiconductor layer and word line may be formed in the word line groove first, and then the bit line and capacitor may be formed. Secondly, the bit line may be formed first and then the capacitor may be formed, or the capacitor may be formed first and then the bit line may be formed. In other words, the formation order of the semiconductor layer and word line, bit line and capacitor may be changed, and this embodiment does not limit the formation order of the semiconductor layer and word line, bit line and capacitor.

[0052] The following description will be made by taking an example of first forming a filling layer to fill the word line groove, and then removing the filling layer and forming a semiconductor layer and a word line after forming the bit line and the capacitor.

[0053] refer to Figure 5 , forming a filling layer 301 , wherein the filling layer 301 fills the word line groove 310 .

[0054] The material of the filling layer 301 can be fluorinated polymer, low dielectric constant glass fiber, microporous mass polymer, fluorinated polyurethane, porous low dielectric constant fatty acid methyl ester, etc., such as SiON, SiCN, SiOC or SiOCN.

[0055] In some embodiments, reference Figure 6 After patterning the stacked structure 200 to form the wordline groove 310 and before forming the filling layer 301, the method further includes: removing a portion of the second sacrificial layer 202 along the first direction X and the second direction Y based on the wordline groove 310. This can facilitate the removal of a portion of the semiconductor layer of the first sacrificial layer facing the surface of the wordline groove in the subsequent process of forming the semiconductor layer to form a plurality of spaced semiconductor layers, thereby forming a plurality of semiconductor channels stacked along the third direction to improve the integration density of the semiconductor structure.

[0056] It should be noted that the method for manufacturing the semiconductor structure provided in this embodiment can form a plurality of transistor structures arranged along the second direction Y and the third direction Z. This does not constitute a limitation on the number of transistors, and in some embodiments, a single transistor structure can be formed based on the semiconductor structure provided in this embodiment.

[0057] In some embodiments, after forming the bit lines and capacitors, during the process of removing the filling layer and forming the word lines, part of the second sacrificial layer can be removed along the first direction and the second direction based on the word line groove to facilitate the subsequent removal of part of the semiconductor layer of the first sacrificial layer facing the surface of the word line groove.

[0058] In some embodiments, before forming the capacitor, the method further includes: referring to Figure 7 , patterning the stacked structure 200 to form a trench 410 extending along the second direction Y, the trench 410 being located on the other side of the word line trench 310 along the first direction X; etching a portion of the first sacrificial layer 201 along the first direction X based on the trench 410. Figure 8 , partially etching the first sacrificial layer 210 to expose the second sacrificial layer 202 ; filling the trench 410 to form a supporting layer 411 .

[0059] In some embodiments, reference Figure 7 , based on the groove 410, a portion of the first sacrificial layer 201 is etched along the first direction X, including: the first sacrificial layer 201 exposes a portion of the second sacrificial layer 202, the width of the exposed second sacrificial layer 202 along the first direction X is a first width L1, the width of the second sacrificial layer 202 along the third direction Z is a second width L2, and the first width L1 is greater than the second width L2. In this way, referring to Figure 8After etching part of the second sacrificial layer 202 , part of the second sacrificial layer 202 may still be retained protruding from the surface of the first sacrificial layer 201 facing the groove 410 , so that after the support layer 411 is subsequently formed, the end of the second sacrificial layer 202 can be embedded in the support layer 411 .

[0060] It should be noted that in Figure 8 In the embodiment, the shape of the end of the second sacrificial layer 202 embedded in the supporting layer 411 is a triangle, which does not constitute a limitation on the shape of the end of the second sacrificial layer 202 embedded in the supporting layer 411. It can be understood that the process of etching the second sacrificial layer exposed by the part of the first sacrificial layer can adopt a wet etching process, and the wet etching is non-directional. The shape of the second sacrificial layer after etching can also be an ellipse, a herringbone or other irregular shapes. This embodiment does not limit the shape of the end of the second sacrificial layer after etching.

[0061] In some embodiments, before forming the capacitor, the method further includes: referring to Fig. 9 , patterning the stacked structure 200 to form a trench 410 extending along the second direction Y, the trench 410 being located on the other side of the word line trench 310 along the first direction X; etching a portion of the second sacrificial layer 202 along the first direction X based on the trench 410. Fig.10 , filling the groove 410 to form a support layer 411. In this way, the second sacrificial layer can form a concave structure near the end of the support layer. When the second sacrificial layer is removed and the lower electrode layer is formed in the subsequent process, the shape of the lower electrode layer is the same as that of the second sacrificial layer, and part of the support layer can be embedded in the end of the lower electrode layer to improve the stability of the lower electrode layer and the support layer, and avoid the problem of collapse of the lower electrode layer after the first sacrificial layer is removed.

[0062] The material of the support layer 411 includes fluorinated polymer, low dielectric constant glass fiber, microporous mass polymer, fluorinated polyurethane, porous low dielectric constant fatty acid methyl ester, etc., such as SiON, SiCN, SiOC or SiOCN.

[0063] refer to Fig.11 , the second sacrificial layer 202 located on one side of the word line groove 310 along the first direction X is removed to form a bit line groove 510, the bit line groove 510 extends along the second direction Y, wherein the first direction X is different from the second direction Y, and the bit line groove 510 is connected to the word line groove 310. After a semiconductor layer and a word line are subsequently formed in the word line groove 310, the bit line can be electrically contacted with a surface of the semiconductor layer away from the word line. Fig.12 , filling the bit line trench 510 to form the bit line 500 .

[0064] In some embodiments, reference Fig.11, forming the bit line trench 510 may include: patterning the stacked structure 200 to form an initial bit line trench 520 extending along the second direction Y, the initial bit line trench 520 being located on one side of the word line trench 310 along the first direction X; removing the second sacrificial layer 202 along the first direction X based on the initial bit line trench 520 to form the bit line trench 510 extending along the second direction Y.

[0065] In some embodiments, reference Fig.12 After forming the bit line 500, an isolation layer 501 is formed to fill the initial bit line groove 520. The isolation layer 501 is located on a side of the bit line 500 away from the word line groove 310. The isolation layer 501 can insulate the bit line 500 from other structures in the semiconductor structure to prevent leakage between the bit line 500 and other structures.

[0066] The material of the isolation layer 501 includes silicon oxide, silicon nitride or silicon oxynitride.

[0067] refer to Fig.13 , remove the second sacrificial layer 202 located at the other side of the word line groove 310 along the first direction X to form a lower electrode groove 610. Fig.14 , fill the lower electrode groove 610 to form a lower electrode layer 601, the lower electrode layer 601 extends along the first direction X, and the side surface of the lower electrode layer 601 away from the word line groove 310 along the first direction X protrudes in a direction away from the word line groove 310. Fig.15 , remove part of the first sacrificial layer 201 between the lower electrode layers 601, and use the remaining first sacrificial layer 201 between the lower electrode layers 601 as an insulating layer; form a dielectric layer 602 and an upper electrode layer 603, wherein the dielectric layer 602 covers part of the surface of the lower electrode layer 601, and the upper electrode layer 603 covers the surface of the dielectric layer 602 away from the lower electrode layer 601, and the lower electrode layer 601, the dielectric layer 602 and the upper electrode layer 603 constitute a capacitor 600.

[0068] The material of the lower electrode layer 601 and the material of the upper electrode layer 603 include at least one of platinum nickel, titanium, tantalum, cobalt, polysilicon, copper, tungsten, tantalum nitride, titanium nitride or ruthenium.

[0069] The material of the dielectric layer 602 includes high dielectric constant materials such as silicon oxide, tantalum oxide, hafnium oxide, zirconium oxide, niobium oxide, titanium oxide, barium oxide, strontium oxide, yttrium oxide, lanthanum oxide, praseodymium oxide or barium strontium titanate.

[0070] It should be noted that in Figures 13 to 15In the figure, the side surface of the lower electrode layer 601 away from the word line groove 310 along the first direction X is convex in the direction away from the word line groove 310, which does not constitute a limitation on the shape of the lower electrode layer 601. Referring to the above steps of forming the groove 410 and the support layer 411, if a portion of the second sacrificial layer 202 is etched along the first direction X based on the groove 410, when the second sacrificial layer 202 is subsequently removed and the lower electrode layer 601 is formed, the side surface of the lower electrode layer 601 away from the word line groove 310 along the first direction X is concave in the direction pointing to the word line groove 310.

[0071] In some embodiments, the bit line 500 and the lower electrode layer 601 may be formed in the same process step, thereby improving the manufacturing efficiency of the semiconductor structure.

[0072] For example, refer to Fig.16 and Fig.17 , patterning the stacked structure 200, so as to form an initial bit line groove 520 extending along the second direction Y on one side of the word line groove 310 along the first direction X, and forming an isolation groove 530 extending along the first direction X between adjacent word line grooves 310; based on the initial bit line groove 520 and the isolation groove 530, the second sacrificial layer 202 located on both sides of the word line groove 310 along the first direction X is removed simultaneously. Return to reference Fig.14 , forming a bit line 500 and a lower electrode layer 601.

[0073] refer to Fig.18 , remove the filling layer 301 and form a semiconductor layer 700, the semiconductor layer 700 covers the inner wall of the word line groove 310; remove a portion of the semiconductor layer 700 facing the surface of the word line groove 310 of the first sacrificial layer 201; fill the remaining word line groove 310 to form a word line 300, the word line 300 extends along the third direction Z, and the semiconductor layer 700 surrounds the side wall of the word line 300 along the first direction X.

[0074] The material of the semiconductor layer 700 includes indium gallium zinc oxide, tungsten-doped indium oxide or indium tin oxide.

[0075] In some embodiments, filling the remaining word line grooves to form word lines includes: forming a gate dielectric layer, the gate dielectric layer at least covers the inner wall of the semiconductor layer; forming a word line, the word line fills the remaining word line grooves.

[0076] The material of the gate dielectric layer includes silicon oxide, silicon nitride, metal oxide, metal oxynitride, metal silicide, high-K material, ferroelectric material, anti-ferroelectric material or a combination thereof.

[0077] The material of the word line 300 includes at least one of polysilicon, titanium nitride, titanium aluminide, tantalum nitride, nickel silicide, cobalt silicide, tantalum, aluminum, lanthanum, titanium or tungsten.

[0078] In the method for manufacturing a semiconductor structure provided by the embodiment of the present disclosure, the word line 300 formed extends along the third direction Z, and the semiconductor layer 700 surrounds the side wall of the word line 300 along the first direction X, so as to form a structure in which a channel surrounds the word line, and the semiconductor layer 700 on the two side walls of the word line 300 along the first direction X is used as a source region or a drain region, and the semiconductor layer 700 on the two side walls of the word line 300 along the second direction Y is used as a channel region. The formed bit line 500 is located on one side of the word line 300 along the first direction X and is in electrical contact with the surface of the semiconductor layer 700, and the capacitor 600 is located on the other side of the word line 300 along the first direction X, so as to form a storage unit, and the word line 300 and the bit line 500 are used to read and write the storage unit. In addition, when forming the lower electrode layer 601, the surface of the lower electrode layer 601 on one side away from the word line 300 along the first direction X is concave in the direction pointing to the word line 300 or convex in the direction away from the word line 300, that is, the surface of the lower electrode layer 601 of the capacitor 600 on one side away from the word line 300 along the first direction X is a non-planar structure, so when the first sacrificial layer 201 between the lower electrode layer 601 is removed, the lower electrode layer 601 can be more firmly connected with the support layer 411. It can be understood that, compared with a planar structure, the non-planar structure of the surface of the lower electrode layer 601 of the capacitor 600 on one side away from the word line 300 along the first direction X can help increase the friction between the lower electrode layer 601 and the support layer 411, so as to avoid slippage between the end of the lower electrode layer 601 away from the word line 300 and the support layer 411 after removing the first sacrificial layer 201, thereby improving the stability of the semiconductor structure.

[0079] Those skilled in the art will appreciate that the above-mentioned embodiments are specific examples for implementing the present disclosure, and in actual applications, various changes may be made thereto in form and detail without departing from the spirit and scope of the present disclosure.

Claims

1. A semiconductor structure, characterized in that: include: a word line extending along a third direction; a semiconductor layer, the semiconductor layer surrounding the sidewall of the word line along a first direction; a bit line, the bit line being located at one side of the word line along the first direction and extending along a second direction, the first direction being different from the second direction, and the bit line being in contact with a surface of the semiconductor layer away from the word line; A capacitor, wherein the capacitor is located on the other side of the word line along the first direction, the capacitor comprises a lower electrode layer, a dielectric layer and an upper electrode layer stacked in sequence, the lower electrode layer extends along the first direction, a surface of the lower electrode layer along the first direction away from the word line is recessed in a direction pointing to the word line or protrudes in a direction away from the word line, the dielectric layer covers a portion of the surface of the lower electrode layer, and the upper electrode layer covers a surface of the dielectric layer away from the lower electrode layer.

2. The semiconductor structure according to claim 1, characterized in that: Also includes: A support layer, wherein the support layer extends along the third direction, the support layer is located on a side of the capacitor away from the word line along the first direction, and along the first direction, a surface of the support layer on a side facing the capacitor has a recessed portion, a surface of the lower electrode layer on a side away from the word line protrudes in a direction away from the word line, and an end of the lower electrode layer away from the word line is located in the recessed portion.

3. The semiconductor structure according to claim 1, characterized in that: Also includes: A support layer, wherein the support layer extends along the third direction, the support layer is located on a side of the capacitor away from the word line along the first direction, and along the first direction, a surface of the support layer on a side facing the capacitor has a protrusion, and a surface of the lower electrode layer on a side away from the word line is recessed in a direction pointing to the word line, and the protrusion is located in the recess of the lower electrode layer.

4. The semiconductor structure according to any one of claims 1 to 3, characterized in that: The word line includes a word line body and an extension surrounding the word line body, and the semiconductor layer surrounds a surface of the extension.

5. The semiconductor structure according to claim 4, characterized in that: Also includes: An insulating layer, wherein the insulating layer is located on opposite sides of the extension portion along the third direction and covers two opposite surfaces of the semiconductor layer along the third direction, the insulating layer extends along the first direction, one end of the insulating layer is in contact with the word line body, and the other end extends in a direction away from the word line body, and a surface of the insulating layer on a side away from the word line is flush with a surface of the lower electrode layer on a side facing the word line, or is further away from the word line body than the surface of the lower electrode layer on a side facing the word line.

6. A method for manufacturing a semiconductor structure, characterized in that: include: providing a substrate; forming a stacked structure on the substrate, the stacked structure comprising first sacrificial layers and second sacrificial layers that are alternately stacked; patterning the stacked structure to form word line trenches; forming a semiconductor layer, wherein the semiconductor layer covers an inner wall of the word line groove; Filling the remaining word line grooves to form word lines, wherein the word lines extend along a third direction, and the semiconductor layer surrounds sidewalls of the word lines along a first direction; Removing the second sacrificial layer located on one side of the word line groove along the first direction to form a bit line groove, wherein the bit line groove extends along a second direction, and the first direction is different from the second direction; Filling the bit line groove to form a bit line, the bit line is in contact with a surface of the semiconductor layer away from the word line; removing the second sacrificial layer located at the other side of the word line groove along the first direction to form a lower electrode groove; Filling the lower electrode groove to form a lower electrode layer, the lower electrode layer extending along the first direction, and a surface of the lower electrode layer along the first direction away from the word line groove is concave toward the direction pointing to the word line groove or convex toward the direction away from the word line groove; forming a dielectric layer, wherein the dielectric layer covers a portion of the surface of the lower electrode layer; An upper electrode layer is formed, wherein the upper electrode layer covers a surface of the dielectric layer away from the lower electrode layer, and the lower electrode layer, the dielectric layer and the upper electrode layer constitute a capacitor.

7. The method for manufacturing a semiconductor structure according to claim 6, characterized in that: Before removing the second sacrificial layer located at the other side of the word line groove along the first direction to form a lower electrode groove, the method further includes: patterning the stacked structure to form a groove extending along the second direction; Etching a portion of the first sacrificial layer along the first direction based on the groove; etching a portion of the first sacrificial layer to expose the second sacrificial layer; The trench is filled to form a supporting layer.

8. The method for manufacturing a semiconductor structure according to claim 7, characterized in that: The etching of part of the first sacrificial layer along the first direction based on the groove includes: the first sacrificial layer exposes part of the second sacrificial layer, the width of the exposed second sacrificial layer along the first direction is a first width, the width of the second sacrificial layer along the third direction is a second width, and the first width is greater than the second width.

9. The method for manufacturing a semiconductor structure according to claim 6, characterized in that: The bit line and the lower electrode layer are formed in the same process step.

10. The method for manufacturing a semiconductor structure according to claim 6, characterized in that: After patterning the stacked structure to form a word line trench, the method further includes: removing a portion of the second sacrificial layer along the first direction and the second direction based on the word line groove; After forming the semiconductor layer, the method further comprises: A portion of the semiconductor layer that is located on a surface of the first sacrificial layer and faces the word line groove is removed.

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