Preparation method of semiconductor structure and preparation method of semiconductor device structure

Abstract

The invention relates to a preparation method of a semiconductor structure and a preparation method of a semiconductor device structure. The preparation method of the semiconductor structure comprises the steps of providing a silicon structure layer; carrying out doping treatment on the silicon structure layer; forming a metal layer on the silicon structure layer; and carrying out annealing treatment on the obtained structure to enable the metal layer to react with the doped silicon structure layer so as to form a metal silicide structure. According to the preparation method of the semiconductor structure, the thermal stability of the embedded metal silicide bit line and the source end silicide can be improved, the problem of junction electric leakage of the bit line-drain end can be avoided, and performance degradation of the metal silicide structure in a subsequent high-temperature gate oxide process and a capacitor preparation process can be avoided.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a method for preparing a semiconductor structure and a method for preparing a semiconductor device structure. Background Art

[0002] In the field of semiconductor technology, metal silicide is widely used in various devices to reduce the parasitic resistance of the devices. At present, the method for forming metal silicide is generally to form a metal layer on the surface of the silicon structure and then perform annealing treatment so that the metal layer reacts with silicon to form metal silicide.

[0003] However, there are many high-temperature processing processes in semiconductor technology, such as high-temperature gate oxide process, etc. The metal silicide formed by the above method will experience thermal stability degradation in the high-temperature processing process, thereby affecting the performance of the device. Summary of the invention

[0004] Based on this, it is necessary to provide a method for preparing a semiconductor structure and a method for preparing a semiconductor device structure to address the above problems.

[0005] In one aspect, the present application provides a method for preparing a semiconductor structure, comprising:

[0006] providing a silicon structural layer;

[0007] Performing a doping process on the silicon structure layer;

[0008] forming a metal layer on the silicon structure layer;

[0009] The obtained structure is annealed so that the metal layer reacts with the silicon structure layer after the doping process to form a metal silicide structure.

[0010] In one embodiment, the step of performing doping treatment on the silicon structure layer includes:

[0011] Carbon impurities or nitrogen impurities are implanted into the silicon structure layer.

[0012] In one embodiment, during the doping process, the implantation energy is 10 keV to 20 keV, and the implantation dose is 5×10 14 cm -3 ~3×10 15 cm -3 .

[0013] The present application also provides a method for preparing a semiconductor device structure, comprising:

[0014] providing a substrate;

[0015] performing a doping process on the substrate;

[0016] Etching the substrate to form a plurality of bit line steps arranged at intervals;

[0017] forming a protective sidewall, wherein the protective sidewall covers the top of the bit line step and extends to the sidewall of the bit line step to cover a portion of the sidewall of the bit line step;

[0018] forming a first metal layer, wherein the first metal layer at least covers the exposed sidewalls of the bit line step;

[0019] The resulting structure is annealed to form a buried metal silicide bit line.

[0020] In one embodiment, before the substrate is doped, the method further comprises:

[0021] The substrate is subjected to bit line doping.

[0022] In one embodiment, before forming the protective sidewall, the method further includes: forming a first isolation dielectric layer between adjacent bit line steps and outside the bit line steps; the protective sidewall is located on the first isolation dielectric layer;

[0023] After forming the protective sidewall and before forming the first metal layer, the method further includes: etching back the first isolation dielectric layer to form a first isolation layer, wherein the first isolation layer is spaced apart from the protective sidewall to expose a portion of the sidewall of the bit line step.

[0024] In one embodiment, the substrate is subjected to a doping process, comprising:

[0025] Carbon impurities or nitrogen impurities are implanted into the substrate.

[0026] In one of the embodiments, a ratio of the thickness of the first metal layer to the width of the bit line step is greater than or equal to 0.6.

[0027] In one embodiment, after forming the buried metal silicide bit line, the method further comprises:

[0028] removing the protective side wall;

[0029] forming a second isolation layer between adjacent bit line steps and outside the bit line steps, wherein the upper surface of the second isolation layer is flush with the upper surface of the bit line step;

[0030] forming a dielectric stack, wherein the dielectric stack includes a sacrificial layer, and the sacrificial layer is spaced from an upper surface of the dielectric stack;

[0031] forming a plurality of channel holes in the dielectric stack, wherein the channel holes expose the upper surface of the bit line step;

[0032] forming an active pillar in the channel hole;

[0033] forming a release gap in the dielectric stack, wherein the release gap exposes the sacrificial layer;

[0034] removing the sacrificial layer based on the release gap to expose a portion of the sidewall of the active pillar;

[0035] Forming a gate word line, wherein the gate word line surrounds the exposed sidewall of the active pillar and extends along a first direction to connect in series a plurality of the active pillars spaced apart along the first direction;

[0036] Performing a doping process on the active pillar from the upper surface of the active pillar;

[0037] forming a second metal layer, wherein the second metal layer at least covers the upper surface of the active pillar;

[0038] The obtained structure is annealed to form a metal silicide layer on the upper surface of the active pillar.

[0039] In one embodiment, forming a gate word line includes: forming a gate dielectric layer, the gate dielectric layer surrounds the exposed sidewall of the active pillar; forming a gate conductive layer, the gate conductive layer covers the gate dielectric layer and extends along the first direction;

[0040] While forming the gate dielectric layer, a covering dielectric layer is also formed on the upper surface of the active pillar and the upper surface of the dielectric stack;

[0041] After forming the gate word line and before performing doping treatment on the active pillar from the upper surface of the active pillar, the method further includes: forming a word line isolation layer, wherein the word line isolation layer fills the release gap, and the upper surface of the word line isolation layer is flush with the upper surface of the covering dielectric layer;

[0042] An opening is formed in the cover dielectric layer, wherein the opening exposes the upper surface of the active pillar.

[0043] In one embodiment, after forming a metal silicide layer on the upper surface of the active pillar, the method further comprises:

[0044] forming a plurality of through-hole capacitor contact structures, wherein the through-hole capacitor contact structures are arranged in one-to-one correspondence with the active pillars, and the lower surfaces of the through-hole capacitor contact structures are in contact with the metal silicide layer;

[0045] A plurality of capacitors are formed, wherein the capacitors are arranged in one-to-one correspondence with the through-hole capacitor contact structures, and the lower electrodes of the capacitors are in contact with the upper surfaces of the through-hole capacitor contact structures.

[0046] In one embodiment, the active pillar is doped from the upper surface of the active pillar, comprising:

[0047] Carbon impurities or nitrogen impurities are implanted into the active pillar from the upper surface of the active pillar.

[0048] In one embodiment, after forming the source region and the drain region in the substrate, the method further comprises:

[0049] The obtained structure is subjected to annealing treatment.

[0050] The method for preparing a semiconductor structure of the present application performs a doping treatment on a silicon structure layer, forms a metal layer on the surface of the silicon structure layer, and then performs an annealing treatment on the obtained structure to obtain a metal silicide structure; by performing a doping treatment on the silicon structure layer, the grain size of the metal silicide formed by the annealing treatment to form the metal silicide structure can be reduced, and the film quality of the contact interface between the metal silicide and the silicon structure layer can be improved. The metal silicide structure can be a buried metal silicide bit line or a source end silicide, so the thermal stability of the buried metal silicide bit line and the source end silicide can be improved, and the junction leakage problem of the bit line-drain end can be avoided, and the performance degradation of the metal silicide structure in the subsequent high-temperature gate oxide process and capacitor preparation process can be avoided.

[0051] The method for preparing a semiconductor device structure of the present application performs doping treatment on a substrate, forms a plurality of spaced bit line steps on the substrate, forms a protective sidewall to cover the top of the bit line step and part of the side wall of the bit line step, forms a first metal layer to cover at least the exposed side wall of the bit line step, and forms a buried metal silicide bit line after annealing the obtained structure; by performing doping treatment on the substrate, the grain size of the metal silicide when the buried metal silicide bit line is formed by annealing can be reduced, and the film quality of the contact interface between the metal silicide and the substrate can be improved, so that the thermal stability of the buried metal silicide bit line can be improved and the junction leakage problem of the bit line-drain terminal can be avoided, and the performance degradation of the metal silicide structure in the subsequent high-temperature gate oxide process and capacitor preparation process can be avoided. BRIEF DESCRIPTION OF THE DRAWINGS

[0052] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the conventional technology, the drawings required for use in the embodiments or the conventional technology descriptions are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0053] Figure 1 is a flow chart of a method for preparing a semiconductor structure provided in an embodiment;

[0054] Figure 2 A schematic diagram of a cross-sectional structure of a structure obtained in step S101 in a method for preparing a semiconductor structure provided in an embodiment;

[0055] Figure 3 A schematic diagram of a cross-sectional structure of a structure obtained in step S102 in a method for preparing a semiconductor structure provided in an embodiment;

[0056] Figure 4 A schematic diagram of a cross-sectional structure of a structure obtained in step S103 in a method for preparing a semiconductor structure provided in an embodiment;

[0057] Figure 5 A schematic cross-sectional view of a structure obtained in step S103 of a method for preparing a semiconductor structure provided in another embodiment;

[0058] Figure 6 A schematic diagram of a cross-sectional structure of a structure obtained in step S104 in a method for preparing a semiconductor structure provided in an embodiment;

[0059] Figure 7 A schematic cross-sectional view of a structure obtained in step S104 in a method for preparing a semiconductor structure provided in another embodiment;

[0060] Figure 8 is a flow chart of a method for preparing a semiconductor device structure provided in an embodiment;

[0061] Fig. 9 is a schematic top view of a semiconductor device structure provided in an embodiment;

[0062] Fig.10 Figure (a) shows the structure obtained in step S801 provided in one embodiment. Fig. 9 FIG. 1 is a schematic diagram of a cross-sectional structure along the aa' direction, and FIG. (b) ... Fig. 9 A schematic diagram of the cross-sectional structure in the bb' direction is shown;

[0063] Fig.11 Figure (a) in the figure shows the structure obtained in step S802 provided in an embodiment. Fig. 9 FIG. 1 is a schematic diagram of a cross-sectional structure along the aa' direction, and FIG. (b) ... Fig. 9 A schematic diagram of the cross-sectional structure in the bb' direction is shown;

[0064] Fig.12 Figure (a) shows the structure obtained in step S803 provided in one embodiment. Fig. 9 FIG. 1 is a schematic diagram of a cross-sectional structure along the aa' direction, and FIG. (b) ... Fig. 9A schematic diagram of the cross-sectional structure in the bb' direction is shown;

[0065] Fig.13 FIG. (a) shows a structure obtained by forming a first isolation dielectric layer between adjacent bit line steps and outside the bit line steps in an embodiment. Fig. 9 FIG. 1 is a schematic diagram of a cross-sectional structure in the direction of aa′, and FIG. (b) is a schematic diagram of a structure obtained by forming a first isolation dielectric layer between adjacent bit line steps and outside the bit line steps in an embodiment. Fig. 9 A schematic diagram of the cross-sectional structure in the bb' direction is shown;

[0066] Fig.14 Figure (a) in the figure shows the structure obtained in step S804 provided in an embodiment. Fig. 9 FIG. 1 is a schematic diagram of a cross-sectional structure along the aa' direction, and FIG. (b) ... Fig. 9 A schematic diagram of the cross-sectional structure in the bb' direction is shown;

[0067] Fig.15 FIG. (a) in FIG. 1 shows a step of etching back the first isolation dielectric layer to form a first isolation layer provided in an embodiment. Fig. 9 FIG. 1 is a schematic diagram of a cross-sectional structure in the direction of aa', and FIG. (b) is a schematic diagram of a structure obtained by etching back the first isolation dielectric layer to form a first isolation layer in an embodiment. Fig. 9 A schematic diagram of the cross-sectional structure in the bb' direction is shown;

[0068] Fig.16 Figure (a) shows the structure obtained in step S805 provided in one embodiment. Fig. 9 FIG. 1 is a schematic diagram of a cross-sectional structure along the aa' direction, and FIG. (b) ... Fig. 9 A schematic diagram of the cross-sectional structure in the bb' direction is shown;

[0069] Fig.17 Figure (a) in the figure shows the structure obtained in step S806 provided in an embodiment. Fig. 9 FIG. 1 is a schematic diagram of a cross-sectional structure along the aa' direction, and FIG. (b) ... Fig. 9 A schematic diagram of the cross-sectional structure in the bb' direction is shown;

[0070] Fig.18 Figure (a) in the figure shows the structure obtained in step S808 provided in one embodiment. Fig. 9 FIG. 1 is a schematic diagram of a cross-sectional structure along the aa' direction, and FIG. (b) ... Fig. 9 A schematic diagram of the cross-sectional structure in the bb' direction is shown;

[0071] Fig.19 Figure (a) shows the structure obtained in step S809 provided in one embodiment. Fig. 9 FIG. 1 is a schematic diagram of a cross-sectional structure along the aa' direction, and FIG. (b) ... Fig. 9 A schematic diagram of the cross-sectional structure in the bb' direction is shown;

[0072] Fig. 20 Figure (a) shows the structure obtained in step S810 provided in one embodiment. Fig. 9 FIG. 1 is a schematic diagram of a cross-sectional structure along the aa' direction, and FIG. (b) ... Fig. 9 A schematic diagram of the cross-sectional structure in the bb' direction is shown;

[0073] Fig.21 Figure (a) in the figure shows the structure obtained in step S811 provided in an embodiment. Fig. 9 FIG. 1 is a schematic diagram of a cross-sectional structure along the aa' direction, and FIG. (b) is a schematic diagram of a structure obtained in step S811 provided in an embodiment. Fig. 9 A schematic diagram of the cross-sectional structure in the bb' direction is shown;

[0074] Fig. 22 Figure (a) shows the structure obtained in step S812 provided in one embodiment. Fig. 9 FIG. 1 is a schematic diagram of a cross-sectional structure along the aa' direction, and FIG. (b) ... Fig. 9 A schematic diagram of the cross-sectional structure in the bb' direction is shown;

[0075] Fig.23 Figure (a) in the figure shows the structure obtained in step S814 provided in one embodiment. Fig. 9 FIG. 1 is a schematic diagram of a cross-sectional structure along the aa' direction, and FIG. (b) ... Fig. 9 A schematic diagram of the cross-sectional structure in the bb' direction is shown;

[0076] Fig.24 FIG. (a) shows a structure obtained by forming a word line isolation layer in an embodiment. Fig. 9 FIG. 1 is a schematic diagram of a cross-sectional structure along the aa' direction, and FIG. (b) is a schematic diagram of a structure obtained by forming a word line isolation layer in an embodiment. Fig. 9 A schematic diagram of the cross-sectional structure in the bb' direction is shown;

[0077] Fig.25 FIG. (a) in FIG. 1 shows a structure obtained by forming an opening in a covering dielectric layer according to an embodiment. Fig. 9 FIG. 1 is a schematic diagram of a cross-sectional structure in the direction of aa', and FIG. (b) is a schematic diagram of a structure obtained by forming an opening in the covering dielectric layer in an embodiment. Fig. 9 A schematic diagram of the cross-sectional structure in the bb' direction is shown;

[0078] Fig.26 Figure (a) shows the structure obtained in step S815 provided in one embodiment. Fig. 9 FIG. 1 is a schematic diagram of a cross-sectional structure along the aa' direction, and FIG. (b) ... Fig. 9 A schematic diagram of the cross-sectional structure in the bb' direction is shown;

[0079] Fig. 27 Figure (a) shows the structure obtained in step S816 provided in one embodiment. Fig. 9 FIG. 1 is a schematic diagram of a cross-sectional structure along the aa' direction, and FIG. (b) ... Fig. 9 A schematic diagram of the cross-sectional structure in the bb' direction is shown;

[0080] Fig.28 Figure (a) in the figure shows the structure obtained in step S817 provided in one embodiment. Fig. 9 FIG. 1 is a schematic diagram of a cross-sectional structure along the aa' direction, and FIG. (b) ... Fig. 9 A schematic diagram of the cross-sectional structure in the bb' direction is shown;

[0081] Fig.29 Figure (a) shows the structure obtained in step S819 provided in one embodiment. Fig. 9 FIG. 1 is a schematic diagram of a cross-sectional structure along the aa' direction, and FIG. (b) ... Fig. 9 Schematic diagram of the cross-sectional structure in the bb' direction.

[0082] Description of reference numerals:

[0083] 1. Silicon structure layer; 2. Metal layer; 3. Metal silicide structure; 4. Isolation wall; 10. Substrate; 101. Bit line step; 102. Protective sidewall; 103. First metal layer; 104. Buried metal silicide bit line; 20. Isolation stack; 21. First isolation layer; 211. First isolation dielectric layer; 22. Second isolation layer; 30. Dielectric stack; 31. First dielectric layer; 32. Second dielectric layer; 33. Sacrificial layer; 34. Channel hole; 40. Source column; 401, opening; 41, second metal layer; 42, metal silicide layer; 50, gate word line; 501, release gap; 51, gate dielectric layer; 52, metal nitride layer; 53, gate conductive layer; 54, covering dielectric layer; 55, word line isolation layer; 56, filling dielectric layer; 60, through-hole capacitor contact structure; 61, contact dielectric layer; 62, contact conductive layer; 70, capacitor; 71, upper electrode; 72, capacitor dielectric layer; 73, lower electrode. DETAILED DESCRIPTION

[0084] In order to facilitate understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. The preferred embodiments of the present application are given in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.

[0085] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0086] It should be understood that when an element or layer is referred to as being "on, adjacent to, connected to or coupled to other elements or layers, it may be directly on, adjacent to, connected to or coupled to other elements or layers, or there may be intervening elements or layers. On the contrary, when an element is referred to as being "directly on, directly adjacent to, directly connected to or directly coupled to other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, doping types and / or parts, these elements, components, regions, layers, doping types and / or parts should not be limited by these terms. These terms are merely used to distinguish one element, component, region, layer, doping type or part from another element, component, region, layer, doping type or part.

[0087] Spatially relative terms such as "under," "beneath," "below," "under," "above," "above," and the like may be used herein to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that, in addition to the orientations shown in the figures, spatially relative terms also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is flipped, an element or feature described as "under other elements" or "under it" or "under it" will be oriented as being "above" the other elements or features. Thus, the exemplary terms "under" and "under" may include both upper and lower orientations. In addition, the device may also include additional orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein are interpreted accordingly.

[0088] When used herein, the singular forms "a", "an", and "said / the" may also include plural forms, unless the context clearly indicates otherwise. It should also be understood that when the terms "consisting of" and / or "comprising" are used in this specification, the presence of the features, integers, steps, operations, elements and / or parts can be determined, but the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups is not excluded. At the same time, when used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0089] With the development of memory technology, the miniaturization of memory devices has become a key point of current technology. In order to adapt to the development of miniaturization, a 4F device with a vertical transistor combined with a capacitor structure is 2 DRAM technology has become the main research and development direction ("F" stands for size factor, which is the smallest feature size in the manufacturing process. DRAM refers to dynamic random access memory. 4F 2 DRAM means each DRAM cell requires 4 transmission gates and 2 capacitors to store one bit).

[0090] In the manufacturing process of vertical transistors, if buried metal bit lines and source-drain silicides are not integrated, the parasitic resistance of the vertical transistors is large, resulting in a small transistor driving current. Therefore, buried metal bit lines and source-drain silicides need to be integrated.

[0091] However, there are problems with the integration of buried metal bit lines and source silicide. The buried metal bit lines and source silicide often suffer from thermal stability degradation in the subsequent high-temperature gate oxide process and capacitor preparation process, resulting in increased junction leakage between the bit line and the drain.

[0092] like Figure 1 As shown, the present application provides a method for preparing a semiconductor structure, which may include the following steps:

[0093] S101: providing a silicon structure layer.

[0094] S102: performing doping treatment on the silicon structure layer.

[0095] S103: forming a metal layer on the silicon structure layer.

[0096] S104: performing annealing treatment on the obtained structure, so that the metal layer reacts with the silicon structure layer after the doping treatment to form a metal silicide structure.

[0097] The metal silicide structure may be a buried metal silicide bit line or a source silicide.

[0098] The semiconductor structure obtained after steps S101-S104 can be referred to Figure 6 or Figure 7 Of course, in order to facilitate the understanding of the present invention, Figure 6 or Figure 7 Some examples of semiconductor structures prepared by the method for preparing a semiconductor structure of the present invention are given. There may be other suitable examples of semiconductor structures prepared by the method for preparing a semiconductor structure of the present invention, and the present invention is not limited thereto.

[0099] In the method for preparing the semiconductor structure in the above-mentioned embodiment, the silicon structure layer is doped to form a metal layer on the surface of the silicon structure layer, and then the obtained structure is annealed to obtain a metal silicide structure. By doping the silicon structure layer, the grain size of the metal silicide formed by annealing to form the metal silicide structure can be reduced, and the film quality of the contact interface between the metal silicide and the silicon structure layer can be improved. The metal silicide structure can be a buried metal silicide bit line or a source end silicide. Therefore, the thermal stability of the buried metal silicide bit line and the source end silicide can be improved, and the junction leakage problem of the bit line-drain end can be avoided, and the performance degradation of the metal silicide structure in the subsequent high-temperature gate oxide process and capacitor preparation process can be avoided.

[0100] In step S101, refer to Figure 1 Step S101 in Figure 2 , providing a silicon structure layer 1.

[0101] The silicon structure layer 1 may be a silicon-containing substrate, the substrate may include a doped substrate; the doped substrate may include an N-type doped substrate or a P-type doped substrate. The silicon structure layer 1 may also be a silicon-containing active column, the active column may include a doped active column; the doped active column may include an N-type doped active column or a P-type doped active column.

[0102] Exemplarily, when the silicon structure layer 1 is a silicon-containing substrate, the metal silicide structure 3 may be a buried metal silicide bit line. When the silicon structure layer 1 is a silicon-containing active pillar, the metal silicide structure 3 may be a source end silicide (a metal silicide layer located at the end of the active pillar).

[0103] In step S102, refer to Figure 1 Step S102 in Figure 3 , the silicon structure layer 1 is doped.

[0104] In one embodiment, the silicon structure layer 1 is doped, including: injecting carbon impurities or nitrogen impurities into the silicon structure layer 1 .

[0105] Among them, after carbon impurities or nitrogen impurities are injected into the silicon structure layer 1, during the subsequent heat treatment process, the carbon impurities or nitrogen impurities can improve the density of the silicon structure layer 1, so that the obtained metal silicide structure 3 has a dense structure, a small grain size, and improved thermal stability.

[0106] In one embodiment, when the metal silicide structure 3 is a buried metal silicide bit line, during the doping process of the silicon structure layer 1, the implantation energy is 10keV to 20keV, and the implantation dose of the doping element is 5×10 14 cm -3 ~3×10 15 cm -3 .

[0107] For example, the implantation energy may be 10keV, 12keV, 15keV, 18keV or 20keV, or other implantation energies between 10keV and 20keV, which are not limited in this embodiment. The implantation dose of the doping element is 5×10 14 cm -3 , 8×10 14 cm -3 , 1×10 15 cm -3 , 2×10 15 cm -3 or 3×10 15 cm -3 , or other 14 cm -3 ~3×10 15 cm -3 The injection dose between and is not limited in this embodiment.

[0108] In one embodiment, when the metal silicide structure 3 is a source-side silicide, during the doping process of the silicon structure layer 1, the injection energy is 1keV to 5keV, and the injection dose of the doping element is 5×10 14 cm -3 ~3×10 15 cm -3 .

[0109] For example, the implantation energy may be 1keV, 2keV, 3keV, 4keV or 5keV, or other implantation energies between 1keV and 5keV, which are not limited in this embodiment. The implantation dose of the doping element is 5×10 14 cm -3 , 8×10 14 cm -3 , 1×10 15 cm -3 , 2×1015 cm -3 or 3×10 15 cm -3 , or other 14 cm -3 ~3×10 15 cm -3 The injection dose between and is not limited in this embodiment.

[0110] The selection of the implantation energy and the implantation dose should ensure that the energy is sufficient to well incorporate the impurities into the silicon structure layer 1 , while not excessively damaging the silicon structure layer 1 .

[0111] In step S103, refer to Figure 1 Step S103 in Figure 4 and Figure 5 , a metal layer 2 is formed on the silicon structure layer 1.

[0112] The step of forming the metal layer 2 on the silicon structure layer 1 may include directly forming the metal layer 2 on the surface of the silicon structure layer 1. Figure 4 The metal layer 2 is formed on the silicon structure layer 1 and a separation wall 4 is formed between the silicon structure layer 1 and the metal layer 2. Figure 5 .

[0113] For example, the metal layer 2 may include but is not limited to a cobalt layer. The metal silicide structure 3 may include but is not limited to a cobalt silicide structure.

[0114] In step S104, refer to Figure 1 Step S104 in Figure 6 and Figure 7 The obtained structure is annealed so that the metal layer 2 reacts with the doped silicon structure layer 1 to form a metal silicide structure 3.

[0115] in, Figure 6 correspond Figure 4 The example shown is an example of forming a metal layer 2 on the surface of a silicon structure layer 1 and subjecting the resulting structure to a heat treatment. Figure 7 correspond Figure 5 The example shown is an example in which an isolation wall 4 is formed between the silicon structure layer 1 and the metal layer 2, and the resulting structure is then subjected to heat treatment.

[0116] The annealing temperature of the obtained structure can be 650°C to 950°C, and the annealing time of the obtained structure can be 20 seconds to 35 seconds. The selection of the annealing temperature and annealing time should not only promote the diffusion of the metal elements in the metal layer 2 into the silicon structure layer 1 to form the metal silicide structure 3, but also ensure that the silicon structure layer 1 will not be excessively damaged.

[0117] Exemplarily, the temperature for annealing the obtained structure may be 650°C, 700°C, 750°C, 800°C, 850°C or 950°C, or other annealing temperatures between 650°C and 950°C, which is not limited in this embodiment. The time for annealing the obtained structure may be 20 seconds, 25 seconds, 30 seconds or 35 seconds, or other annealing times between 20 seconds and 35 seconds, which is not limited in this embodiment.

[0118] Based on the same inventive concept, the present application also provides a method for preparing a semiconductor device structure, such as Figure 8 As shown, the method for preparing a semiconductor device structure may include the following steps:

[0119] S801: providing a substrate.

[0120] S802: performing doping treatment on the substrate.

[0121] S803: etching the substrate to form a plurality of bit line steps arranged at intervals.

[0122] S804: forming a protection sidewall, wherein the protection sidewall covers the top of the bit line step and extends to the sidewall of the bit line step to cover a portion of the sidewall of the bit line step.

[0123] S805: forming a first metal layer, wherein the first metal layer at least covers the exposed sidewalls of the bit line step.

[0124] S806: performing annealing treatment on the obtained structure to form a buried metal silicide bit line.

[0125] The semiconductor structure obtained after steps S801-S806 can be referred to Fig.17 Of course, in order to facilitate the understanding of the present invention, Fig.17 Some examples of semiconductor structures prepared by the method for preparing a semiconductor structure of the present invention are given. There may be other suitable examples of semiconductor structures prepared by the method for preparing a semiconductor structure of the present invention, and the present invention is not limited thereto.

[0126] In the method for preparing the semiconductor device structure in the above-mentioned embodiment, a substrate is doped to form a plurality of spaced-apart bit line steps on the substrate, a protective sidewall is formed to cover the top of the bit line step and part of the side wall of the bit line step, a first metal layer is formed to cover at least the exposed side wall of the bit line step, and a buried metal silicide bit line is formed after annealing the obtained structure; by doping the substrate, the grain size of the metal silicide when the buried metal silicide bit line is formed by annealing can be reduced, and the film quality of the contact interface between the metal silicide and the substrate can be improved, so that the thermal stability of the buried metal silicide bit line can be improved and the junction leakage problem of the bit line-drain terminal can be avoided, and the performance degradation of the metal silicide structure in the subsequent high-temperature gate oxide process and capacitor preparation process can be avoided.

[0127] See also Fig. 9 , Fig. 9 The aa' direction and the bb' direction of the semiconductor device structure in the present application are shown.

[0128] In step S801, refer to Figure 8 Step S801 in Fig.10 , providing a substrate 10.

[0129] Among them, the material of the substrate 10 can be any suitable material, for example, it can be at least one of the following materials: silicon (Si), silicon germanium (SiGe), silicon carbon (SiC), silicon germanium carbon (SiGeC), or silicon on insulator (SOI), stacked silicon on insulator (SSOI), stacked silicon germanium on insulator (S-SiGeOI), silicon germanium on insulator (SiGeOI) and germanium on insulator (GeOI), or it can also be double-sided polished silicon wafers (Double Side Polished Wafers, DSP), etc., which are not limited in this embodiment.

[0130] In one embodiment, before the substrate 10 is doped, the step of performing bit line doping on the substrate 10 is also included.

[0131] The substrate 10 may be subjected to bit line implantation, annealing and other processes to achieve bit line doping, so as to form an ohmic contact of the bit line, so as to subsequently reduce the contact resistance between the bit line and the drain terminal.

[0132] The bit line doping dose can be 0.8×10 20 cm -3 ~1.2×10 20 cm -3 For example, the bit line doping dose may be 0.8×10 20 cm -3 , 0.9×10 20 cm-3 , 1×10 20 cm -3 , 1.1×10 20 cm -3 or 1.2×10 20 cm -3 .

[0133] In step S802, refer to Figure 8 Step S802 in Fig.11 , the substrate 10 is doped.

[0134] In one embodiment, performing doping treatment on the substrate 10 may include: implanting carbon impurities or nitrogen impurities into the substrate 10 .

[0135] Among them, after carbon impurities or nitrogen impurities are injected into the substrate 10, during the subsequent heat treatment process, the carbon impurities or nitrogen impurities can improve the density of the substrate 10, so that the film layer of the obtained buried metal silicide bit line 104 is dense, the grain size is small, the film quality of the contact interface between the buried metal silicide bit line 104 and the substrate 10 is improved, and the thermal stability of the structure is improved.

[0136] In one embodiment, during the doping process of the substrate 10, the implantation energy is 10 keV to 20 keV, and the implantation dose of the doping element is 5×10 14 cm -3 ~3×10 15 cm -3 .

[0137] For example, the implantation energy may be 10keV, 12keV, 15keV, 18keV or 20keV, or other implantation energies between 10keV and 20keV, which are not limited in this embodiment. The implantation dose of the doping element is 5×10 14 cm -3 , 8×10 14 cm -3 , 1×10 15 cm -3 , 2×10 15 cm -3 or 3×10 15 cm -3 , or other 14 cm -3 ~3×10 15 cm -3 The injection dose between and is not limited in this embodiment.

[0138] The selection of the implantation energy and the implantation dose should ensure that the energy is sufficient to well incorporate the impurities into the substrate 10 , while not excessively damaging the substrate 10 .

[0139] In step S803, refer to Figure 8 Step S803 in Fig.12 , etching the substrate 10 to form a plurality of bit line steps 101 arranged at intervals.

[0140] Etching the substrate 10 to form a plurality of spaced bit line steps 101 may include the following steps: forming a mask layer on the upper surface of the substrate 10, the mask layer having a mask window, the mask window exposing the area to be etched; etching the area to be etched to form a plurality of spaced bit line steps 101 on the substrate 10. The mask layer may be formed on the upper surface of the substrate 10 by a physical vapor deposition process, a chemical vapor deposition process, or an atomic layer deposition process. The mask layer may include a silicon nitride layer or a photoresist layer.

[0141] The substrate 10 may be etched by a wet etching process or a dry etching process to form a plurality of bit line steps 101 arranged at intervals.

[0142] The method for preparing the semiconductor device structure provided in the present application does not specifically limit the manner of forming the bit line step 101 in step S803. As an example, a self-aligned double patterning (SADP) process or a self-aligned quadruple patterning (SAQP) process can be used to form a plurality of spaced bit line steps 101.

[0143] In one embodiment, before forming the protective spacer 102, the following steps may be further included: forming a first isolation dielectric layer 211 between adjacent bit line steps 101 and outside the bit line steps 101. The obtained structure is shown in FIG. Fig.13 ; The protective sidewall 102 is located on the first isolation dielectric layer 211.

[0144] The first isolation dielectric layer 211 may be formed between adjacent bit line steps 101 and outside the bit line steps 101 by using a physical vapor deposition process, a chemical vapor deposition process or an atomic layer deposition process. The first isolation dielectric layer 211 may include but is not limited to at least one of a silicon nitride layer and a silicon oxynitride layer, that is, the first isolation dielectric layer 211 may include a silicon nitride layer or a silicon oxynitride layer, or may include a stacked structure of a silicon nitride layer and a silicon oxynitride layer.

[0145] In step S804, refer to Figure 8 Step S804 in Fig.14, forming a protection spacer 102 , the protection spacer 102 covers the top of the bit line step 101 and extends to the side wall of the bit line step 101 , covering a portion of the side wall of the bit line step 101 .

[0146] The substrate 10 may be thermally oxidized by an in-situ steam generation (ISSG) process to consume part of the substrate 10, thereby forming a protective spacer 102, which can help control the position of the buried metal silicide bit line 104 during the subsequent annealing process, so that the formed buried metal silicide bit line 104 is located in the substrate 10; and the protective spacer 102 can protect the upper surface and sidewalls of the substrate 10 during the annealing process. The material of the protective spacer 102 may include oxide, and the oxide may include silicon dioxide.

[0147] In one embodiment, after forming the protective sidewall 102 and before forming the first metal layer 103, the following steps may be further included: etching back the first isolation dielectric layer 211 to form a first isolation layer 21, wherein the first isolation layer 21 is spaced apart from the protective sidewall 102 to expose a portion of the sidewall of the bit line step 101; the resulting structure is shown in FIG. Fig.15 .

[0148] The first isolation dielectric layer 211 may be etched back by a wet etching process or a dry etching process to form the first isolation layer 21 .

[0149] In step S805, refer to Figure 8 Step S805 in Fig.16 , forming a first metal layer 103 , wherein the first metal layer 103 at least covers the exposed sidewall of the bit line step 101 .

[0150] The first metal layer 103 may be formed by a physical vapor deposition process or an atomic layer deposition process. The first metal layer 103 at least covers the exposed sidewalls of the bit line step 101, which may mean that the first metal layer 103 covers the exposed sidewalls of the bit line step 101, the surface of the protective sidewall 102, and the surface of the first isolation layer 21 away from the substrate 10; or the first metal layer 103 covers the exposed sidewalls of the bit line step 101 and the surface of the protective sidewall 102; or the first metal layer 103 covers the exposed sidewalls of the bit line step 101 and the surface of the first isolation layer 21 away from the substrate 10; or the first metal layer 103 covers the exposed sidewalls of the bit line step 101.

[0151] In step S806, refer to Figure 8 Step S806 in Fig.17 The resulting structure is annealed to form a buried metal silicide bit line 104 .

[0152] For example, the first metal layer 103 may include but is not limited to a cobalt layer; the buried metal silicide bit line 104 may include but is not limited to a buried cobalt silicide bit line. The buried metal silicide bit line 104 can reduce the resistance of the bit line itself, which is beneficial to improving electrical performance and thermal stability.

[0153] The annealing temperature of the obtained structure may be 650° C. to 950° C., and the annealing time of the obtained structure may be 20 seconds to 35 seconds. The annealing temperature and annealing time are selected to promote the diffusion of metal elements in the metal layer into the substrate 10 to form the buried metal silicide bit line 104, while ensuring that the substrate 10 is not excessively damaged.

[0154] Exemplarily, the temperature for annealing the obtained structure may be 650°C, 700°C, 750°C, 800°C, 850°C or 950°C, or other annealing temperatures between 650°C and 950°C, which is not limited in this embodiment. The time for annealing the obtained structure may be 20 seconds, 25 seconds, 30 seconds or 35 seconds, or other annealing times between 20 seconds and 35 seconds, which is not limited in this embodiment.

[0155] In one embodiment, see Fig.16 As shown in FIG. b, the ratio of the thickness m of the first metal layer 103 to the width n of the bit line step 101 is greater than or equal to 0.6.

[0156] Among them, the ratio of the thickness m of the first metal layer 103 to the width n of the bit line step 101 can be greater than 0.6, or can be equal to 0.6, so that the exposed bit line step 101 can be completely metallized and transformed into a buried metal silicide bit line 104; while the unexposed bit line step 101 is almost unaffected; therefore, the position of the buried metal silicide bit line 104 can be precisely controlled.

[0157] Exemplarily, the upper surface of the buried metal silicide bit line 104 is lower than the upper surface of the bit line step 101 , that is, the upper surface of the buried metal silicide bit line 104 is lower than the upper surface of the substrate 10 , so the substrate 10 can better isolate and protect the buried metal silicide bit line 104 .

[0158] In one embodiment, after forming the buried metal silicide bit line 104, the method for preparing the semiconductor device structure may further include the following steps S807 to S817:

[0159] S807: removing the protective sidewall 102. The protective sidewall 102 may be removed by a wet etching process or a dry etching process.

[0160] S808: forming a second isolation layer 22 between adjacent bit line steps 101 and outside the bit line steps 101, wherein the upper surface of the second isolation layer 22 is flush with the upper surface of the bit line step 101. The second isolation layer 22 may be formed between adjacent bit line steps 101 and outside the bit line step 101 by a physical vapor deposition process, a chemical vapor deposition process, or an atomic layer deposition process. Fig.18 The first isolation layer 21 and the second isolation layer 22 together form an isolation stack 20 to protect the bit line step 101 and the buried metal silicide bit line 104 .

[0161] S809: forming a dielectric stack 30, wherein the dielectric stack 30 includes a sacrificial layer 33, and a distance is provided between the sacrificial layer 33 and the upper surface of the dielectric stack 30. The dielectric stack 30 may be formed by a physical vapor deposition process, a chemical vapor deposition process, or an atomic layer deposition process. Fig.19 The dielectric stack 30 includes a first dielectric layer 31 and a second dielectric layer 32. The first dielectric layer 31 is located on a surface of the second isolation layer 22 away from the substrate 10 and on a surface of the buried metal silicide bit line 104 away from the substrate 10. A sacrificial layer 33 is formed between the first dielectric layer 31 and the second dielectric layer 32.

[0162] Exemplarily, the first dielectric layer 31 and the second dielectric layer 32 may include an oxide layer, and the oxide may include a silicon dioxide layer. The sacrificial layer 33 may include but is not limited to at least one of a silicon nitride layer and a silicon oxynitride layer, that is, the sacrificial layer 33 may include a silicon nitride layer or a silicon oxynitride layer, or may include a stacked structure of a silicon nitride layer and a silicon oxynitride layer.

[0163] S810: forming a plurality of channel holes 34 in the dielectric stack 30, wherein the channel holes 34 expose the upper surface of the bit line step 101. Fig. 20 , wherein the method for forming the plurality of channel holes 34 in step S811 is not specifically limited. As an example, a self-aligned double imaging process or a self-aligned quadruple patterning process may be used to form the plurality of channel holes 34 in the dielectric stack 30 .

[0164] S811: forming an active pillar 40 in the channel hole 34. Fig.21 , an N-type doped silicon column can be formed as the active column 40 by using an epitaxial channel growth process; the doping concentration in the active column 40 is 5×10 18 cm -3 ~1×10 19 cm -3 For example, the doping concentration in the active pillar 40 may be 5×10 18 cm -3 , 6×10 18 cm -3 ,7×1018 cm -3 , 8×10 18 cm -3 ,9×10 18 cm -3 or 1×10 19 cm -3 , or other 18 cm -3 ~1×10 19 cm -3 The doping concentration between and is not limited in this embodiment.

[0165] Wherein, an N-type doped silicon column is formed as the active column 40 by adopting an epitaxial channel growth process, and the thermal stability of the active column 40 is further improved.

[0166] S812: forming a release gap 501 in the dielectric stack 30, wherein the release gap 501 exposes the sacrificial layer 33. Fig. 22 , a release gap 501 may be formed in the dielectric stack 30 using a self-aligned double imaging process or a self-aligned quadruple patterning process.

[0167] S813: removing the sacrificial layer 33 based on the release gap 501 to expose a portion of the sidewall of the active pillar 40. The sacrificial layer 33 may be removed by a wet etching process or a dry etching process.

[0168] S814: forming a gate word line 50, the gate word line 50 surrounds the exposed sidewall of the active pillar 40 and extends along the first direction to connect in series the plurality of active pillars 40 arranged at intervals along the first direction. Fig.23 .

[0169] It should be noted that the buried metal silicide bit line 104 extends along the second direction. The first direction and the second direction may intersect. Further, the first direction and the second direction may be perpendicular.

[0170] by Figures 9 to 23 For example, the second direction may be an example of the aa' direction, and the first direction may be an example of the bb' direction.

[0171] In one embodiment, the gate word line 50 includes a gate dielectric layer 51 and a gate conductive layer 53. Forming the gate word line 50 may include the following steps: forming a gate dielectric layer 51, wherein the gate dielectric layer 51 surrounds the exposed side wall of the active pillar 40; forming a gate conductive layer 53, wherein the gate conductive layer 53 covers the gate dielectric layer 51 and extends along the first direction.

[0172] See also Fig.23, wherein the gate dielectric layer 51 may be formed by an oxidation process. The gate conductive layer 53 may be formed by a physical vapor deposition process, a chemical vapor deposition process or an atomic layer deposition process.

[0173] Exemplarily, the gate dielectric layer 51 may include an oxide layer, and the oxide layer may include a silicon oxide layer. The gate conductive layer 53 may include at least one of a polysilicon layer, a cobalt layer, a molybdenum layer, or a tungsten layer, that is, the gate conductive layer 53 may be any one of a polysilicon layer, a cobalt layer, a molybdenum layer, or a tungsten layer, or may be a stacked structure formed by combining two or more of the cobalt layer, the molybdenum layer, or the tungsten layer.

[0174] Further, see Fig.23 The gate word line 50 may further include a metal nitride layer 52; the metal nitride layer 52 is formed between the gate dielectric layer 51 and the gate conductive layer 53. The metal nitride layer 52 may be formed by a physical vapor deposition process, a chemical vapor deposition process or an atomic layer deposition process; the metal nitride layer 52 may be, but is not limited to, a titanium nitride layer.

[0175] Still reading Fig.23 When the gate dielectric layer 51 is formed, a cover dielectric layer 54 is formed on the upper surface of the active pillar 40 and the upper surface of the dielectric stack 30. The cover dielectric layer 54 can be formed by a physical vapor deposition process, a chemical vapor deposition process or an atomic layer deposition process.

[0176] In one embodiment, after forming the gate word line 50, before performing doping treatment on the active pillar 40 from the upper surface of the active pillar 40, the following steps may be further included: forming a word line isolation layer 55, the word line isolation layer 55 fills the release gap 501, and the upper surface of the word line isolation layer 55 is flush with the upper surface of the covering dielectric layer 54, and the resulting structure is as shown in FIG. Fig.24 As shown; an opening 401 is formed in the cover dielectric layer 54, and the opening 401 exposes the upper surface of the active pillar 40, and the resulting structure is as shown Fig.25 shown.

[0177] The word line isolation layer 55 may be formed by a physical vapor deposition process, a chemical vapor deposition process or an atomic layer deposition process.

[0178] As an example, the opening 401 may be formed in the cover dielectric layer 54 by a self-aligned double imaging process or a self-aligned quadruple patterning process, or by other related processes, which are not specifically limited in this embodiment.

[0179] S815 : performing a doping process on the active pillar 40 from the upper surface of the active pillar 40 .

[0180] Among them, see Fig.26Performing a doping process on the active pillar 40 from the upper surface of the active pillar 40 may include: implanting carbon impurities or nitrogen impurities into the active pillar 40 from the upper surface of the active pillar 40 .

[0181] After carbon impurities or nitrogen impurities are injected into the active pillar 40, during the subsequent heat treatment process, the carbon impurities or nitrogen impurities can improve the density of the active pillar 40, so that the obtained metal silicide layer 42 has a dense film layer with a smaller grain size, the film quality of the contact interface between the metal silicide layer 42 and the active pillar 40 is improved, and the thermal stability of the structure is enhanced.

[0182] In one embodiment, during the process of doping the active pillar 40 from the upper surface of the active pillar 40, the implantation energy is 1keV to 5keV, and the implantation dose of the doping element is 5×10 14 cm -3 ~3×10 15 cm -3 .

[0183] For example, the implantation energy may be 1keV, 2keV, 3keV, 4keV or 5keV, or other implantation energies between 1keV and 5keV, which are not limited in this embodiment. The implantation dose of the doping element is 5×10 14 cm -3 , 8×10 14 cm -3 , 1×10 15 cm -3 , 2×10 15 cm -3 or 3×10 15 cm -3 , or other 14 cm -3 ~3×10 15 cm -3 The injection dose between and is not limited in this embodiment.

[0184] The selection of the implantation energy and the implantation dosage should ensure that the energy is sufficient to well dope the impurities into the active pillars 40 , while not excessively damaging the active pillars 40 .

[0185] S816 : forming a second metal layer 41 , wherein the second metal layer 41 at least covers the upper surface of the active pillar 40 .

[0186] Among them, Fig. 27 As shown, the second metal layer 41 may be formed by a physical vapor deposition process or an atomic layer deposition process.

[0187] S817 : performing annealing treatment on the obtained structure to form a metal silicide layer 42 on the upper surface of the active pillar 40 .

[0188] Among them, Fig.28 As shown, the metal silicide layer 42 on the upper surface of the active pillar 40 serves as the source end silicide. After the heat treatment process, the obtained metal silicide layer 42 has a dense film layer and a small grain size. The film quality of the contact interface between the metal silicide layer 42 and the active pillar 40 is improved, and the thermal stability of the structure is improved.

[0189] For example, the second metal layer 41 may include but is not limited to a cobalt layer. The metal silicide layer 42 may include but is not limited to a cobalt silicide layer.

[0190] In one embodiment, after forming the metal silicide layer 42 on the upper surface of the active pillar 40, the following steps may be further included:

[0191] S818: forming a plurality of through-hole capacitor contact structures 60, wherein the through-hole capacitor contact structures 60 are arranged one by one corresponding to the active pillars 40, and the lower surface of the through-hole capacitor contact structure 60 is in contact with the metal silicide layer 42. Fig.29 , a plurality of through-hole capacitor contact structures 60 may be formed by a damascene process.

[0192] S819: forming a plurality of capacitors 70, wherein the capacitors 70 are arranged in one-to-one correspondence with the through-hole capacitor contact structures 60, and the lower electrodes 73 of the capacitors 70 are in contact with the upper surfaces of the through-hole capacitor contact structures 60. Fig.29 The capacitor 70 is connected to the metal silicide layer 42 on the upper surface of the active pillar 40 through the through-hole capacitor contact structure 60 .

[0193] Among them, still refer to Fig.29 Before forming a plurality of through-hole capacitor contact structures 60, the method further includes: forming a filling dielectric layer 56 in the opening 401. The filling dielectric layer 56 fills the opening 401 to isolate and protect the active pillar 40 and the metal silicide layer 42. The filling dielectric layer 56 may include an oxide layer, and the oxide layer may include a silicon oxide layer.

[0194] For example, see Fig.29 The through-hole capacitor contact structure 60 may include a contact dielectric layer 61 and a contact conductive layer 62 .

[0195] The contact dielectric layer 61 may include at least one of a TiN (titanium nitride) layer and a TaN (tantalum nitride) layer, that is, the contact dielectric layer 61 may include any one of a TiN layer or a TaN layer, or may be a stacked structure composed of a TiN layer and a TaN layer.

[0196] Among them, the contact conductive layer 62 can include at least one of a cobalt layer, a molybdenum layer or a tungsten layer, that is, the contact conductive layer 62 can be any one of the cobalt layer, the molybdenum layer or the tungsten layer, or it can be a stacked structure composed of two or more of the cobalt layer, the molybdenum layer or the tungsten layer.

[0197] For example, see Fig.29 The capacitor 70 may include: an upper electrode 71 , a capacitor dielectric layer 72 and a lower electrode 73 .

[0198] The upper electrode 71 may include at least one of a TiN (titanium nitride) layer and a TaN (tantalum nitride) layer, that is, the upper electrode 71 may include any one of a TiN layer or a TaN layer, or may be a stacked structure composed of a TiN layer and a TaN layer.

[0199] Among them, the capacitor dielectric layer 72 includes a high-k dielectric material layer, and the high-k dielectric layer may include: at least one of an Al2O3 (aluminum oxide) layer, an HfO2 (hafnium dioxide) layer and a ZrO2 (zirconium dioxide) layer, that is, the capacitor dielectric layer 72 can be any one of the Al2O3 layer, the HfO2 layer and the ZrO2 layer, or it can be a stacked structure composed of two or more of the Al2O3 layer, the HfO2 layer and the ZrO2 layer.

[0200] The lower electrode 73 may include at least one of a TiN (titanium nitride) layer and a TaN (tantalum nitride) layer, that is, the lower electrode 73 may include any one of a TiN layer or a TaN layer, or may be a stacked structure composed of a TiN layer and a TaN layer.

[0201] It should be understood that, although each step in the flowchart of each embodiment is displayed in sequence according to the indication of the arrow, these steps are not necessarily executed in sequence according to the order indicated by the arrow. Unless there is a clear explanation in this article, the execution of these steps does not have a strict order restriction, and these steps can be executed in other orders. Moreover, at least a part of the steps in the flowchart of each embodiment may include multiple steps or multiple stages, and these steps or stages are not necessarily executed at the same time, but can be executed at different times, and the execution order of these steps or stages is not necessarily carried out in sequence, but can be executed in turn or alternately with other steps or at least a part of the steps or stages in other steps.

[0202] The technical features of the above-described embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features of the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0203] The above-described embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be construed as limiting the scope of the patent application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent application shall be subject to the attached claims.

Claims

1. A method for preparing a semiconductor structure, characterized in that: include: providing a silicon structural layer; Performing a doping process on the silicon structure layer; forming a metal layer on the silicon structure layer; The obtained structure is annealed so that the metal layer reacts with the silicon structure layer after the doping process to form a metal silicide structure.

2. The method for preparing a semiconductor structure according to claim 1, characterized in that: The step of performing doping treatment on the silicon structure layer comprises: Carbon impurities or nitrogen impurities are implanted into the silicon structure layer.

3. The method for preparing a semiconductor structure according to claim 2, characterized in that: In the process of doping the silicon structure layer, the implantation energy is 10keV to 20keV, and the implantation dose is 5×10 14 cm -3 ~3×10 15 cm -3 .

4. A method for preparing a semiconductor device structure, characterized in that: include: providing a substrate; performing a doping process on the substrate; Etching the substrate to form a plurality of bit line steps arranged at intervals; forming a protective sidewall, wherein the protective sidewall covers the top of the bit line step and extends to the sidewall of the bit line step to cover a portion of the sidewall of the bit line step; forming a first metal layer, wherein the first metal layer at least covers the exposed sidewalls of the bit line step; The resulting structure is annealed to form a buried metal silicide bit line.

5. The method for preparing a semiconductor device structure according to claim 4, characterized in that: Before the substrate is doped, the method further comprises: The substrate is subjected to bit line doping.

6. The method for preparing a semiconductor device structure according to claim 4, characterized in that: Before forming the protective sidewall, the method further includes: forming a first isolation dielectric layer between adjacent bit line steps and outside the bit line steps; the protective sidewall is located on the first isolation dielectric layer; After forming the protective sidewall and before forming the first metal layer, the method further includes: etching back the first isolation dielectric layer to form a first isolation layer, wherein the first isolation layer is spaced apart from the protective sidewall to expose a portion of the sidewall of the bit line step.

7. The method for preparing a semiconductor device structure according to claim 4, characterized in that: Performing a doping process on the substrate includes: Carbon impurities or nitrogen impurities are implanted into the substrate.

8. The method for preparing a semiconductor device structure according to claim 4, characterized in that: A ratio of the thickness of the first metal layer to the width of the bit line step is greater than or equal to 0.

6.

9. The method for preparing a semiconductor device structure according to any one of claims 4 to 8, characterized in that: After forming the buried metal silicide bit line, the method further includes: removing the protective side wall; forming a second isolation layer between adjacent bit line steps and outside the bit line steps, wherein the upper surface of the second isolation layer is flush with the upper surface of the bit line step; forming a dielectric stack, wherein the dielectric stack includes a sacrificial layer, and the sacrificial layer is spaced from an upper surface of the dielectric stack; forming a plurality of channel holes in the dielectric stack, wherein the channel holes expose the upper surface of the bit line step; forming an active pillar in the channel hole; forming a release gap in the dielectric stack, wherein the release gap exposes the sacrificial layer; removing the sacrificial layer based on the release gap to expose a portion of the sidewall of the active pillar; Forming a gate word line, wherein the gate word line surrounds the exposed sidewall of the active pillar and extends along a first direction to connect in series a plurality of the active pillars spaced apart along the first direction; Performing a doping process on the active pillar from the upper surface of the active pillar; forming a second metal layer, wherein the second metal layer at least covers the upper surface of the active pillar; The obtained structure is annealed to form a metal silicide layer on the upper surface of the active pillar.

10. The method for preparing a semiconductor device structure according to claim 9, characterized in that: Forming a gate word line, comprising: forming a gate dielectric layer, the gate dielectric layer surrounds the exposed sidewalls of the active pillar; forming a gate conductive layer, the gate conductive layer covers the gate dielectric layer and extends along the first direction; While forming the gate dielectric layer, a covering dielectric layer is also formed on the upper surface of the active pillar and the upper surface of the dielectric stack; After forming the gate word line and before performing doping treatment on the active pillar from the upper surface of the active pillar, the method further includes: forming a word line isolation layer, wherein the word line isolation layer fills the release gap, and the upper surface of the word line isolation layer is flush with the upper surface of the covering dielectric layer; An opening is formed in the cover dielectric layer, wherein the opening exposes the upper surface of the active pillar.

11. The method for preparing a semiconductor device structure according to claim 9, characterized in that: After forming a metal silicide layer on the upper surface of the active pillar, the method further comprises: forming a plurality of through-hole capacitor contact structures, wherein the through-hole capacitor contact structures are arranged in one-to-one correspondence with the active pillars, and the lower surfaces of the through-hole capacitor contact structures are in contact with the metal silicide layer; A plurality of capacitors are formed, wherein the capacitors are arranged in one-to-one correspondence with the through-hole capacitor contact structures, and the lower electrodes of the capacitors are in contact with the upper surfaces of the through-hole capacitor contact structures.

12. The method for preparing a semiconductor device structure according to claim 9, characterized in that: Performing a doping process on the active pillar from the upper surface of the active pillar comprises: Carbon impurities or nitrogen impurities are implanted into the active pillar from the upper surface of the active pillar.

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