Chip vertical stacking packaging structure and manufacturing method thereof
By adopting a vertical stacking structure and Fan-out process in flash memory chip packaging, the problems of large packaging volume and complex process in the existing technology are solved, and more efficient storage capacity and lower power consumption are achieved.
Patent Information
- Application Number
- CN202411435445.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-10-15
- Publication Date
- 2025-01-24
AI Technical Summary
In the existing flash chip packaging technology, misalignment stacking and gold wire bonding lead to an increase in the packaging area and thickness, and the process is complicated, which is prone to failure risk, affecting the packaging yield and storage capacity.
The chip is vertically stacked and packaged, and the PAD PAD of the chip is fanned to the silicon bridge through the FAN-OUT process to form a new PAD contact with TSV and form a welding ball on the bottom surface of the TSV to achieve the vertical interconnection of the chip.
Effectively reduce the packaging volume, reduce the cost of packaging, increase the quality and storage capacity, and reduce the signal transmission loss and power consumption.
Smart Images
Figure CN119364774A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of chip packaging, and in particular to a chip vertical stacking packaging structure and a manufacturing method thereof. Background Art
[0002] With the rapid development of data storage, the requirements for chip computing speed and storage capacity are getting higher and higher. Figure 1 and Figure 2 As shown, the flash memory chips in the industry currently use the process technology of "offset stacking-gold wire bonding-encapsulation" to achieve data storage and reading and writing. In order to increase storage capacity, the number of chip stacking layers is increasing (the number of stacking layers is from 2 layers to 4 layers to 8 layers to 16 layers or even 32 layers). However, in the existing technology, flash memory chips need to be staggered and stacked to make room for bonding PADs before gold wire bonding can be performed. This is bound to increase the packaging area and packaging thickness. At the same time, due to the limitation of the bonding process level, it will bring a series of failure risks such as "craters", "wire collapse" and "wire contact" due to excessive wire arcs, which will affect the entire packaging yield and storage capacity.
[0003] Therefore, how to effectively reduce the packaging volume is a problem that needs to be solved at present. Summary of the invention
[0004] The purpose of the present invention is to provide a chip vertical stacking packaging structure and a manufacturing method thereof, which can effectively reduce the packaging volume.
[0005] In order to achieve the above object, the present invention provides a chip vertical stacking packaging structure, comprising:
[0006] Carrier board;
[0007] A structure is integrated on the carrier; the structure is formed by vertically stacking multiple layers; each layer of the structure includes: a chip and a silicon bridge sheet arranged opposite to each other in a horizontal direction, and a through TSV is formed in the silicon bridge sheet; the PAD of the chip is fanned out to the silicon bridge sheet to form a new PAD, and the new PAD is in contact with the top surface of the TSV;
[0008] A solder ball is formed on the bottom surface of the TSV of the Nth layer (N>1) of the structure; the solder ball of the upper layer structure is in contact with the new PAD of the lower layer structure;
[0009] The first layer structure of the structural body is formed with a solder ball array electrically connected to the TSV through RDL, and the structural body is soldered to the carrier through the solder ball array.
[0010] In an optional solution, the carrier board includes a substrate and a functional chip integrated on the substrate;
[0011] The structure is integrated on the carrier board or on the functional chip.
[0012] In an optional solution, the chip of each layer structure of the structural body is a flash memory chip; a logic chip is integrated on the substrate, the structural body is integrated on the logic chip, and a cache chip is also integrated on the logic chip.
[0013] In an optional solution, the spacing of the PADs of the chip is equal to the spacing of the new PADs formed by fanning out to the silicon bridge wafer, and the electrical connection lines between each PAD of the chip and the corresponding new PAD are straight lines, and the multiple straight lines are parallel to each other.
[0014] In an optional solution, bottom filling glue is filled between the substrate and the structure and between the layers of the structure.
[0015] The present invention also provides a method for manufacturing a chip vertical stacking packaging structure, comprising:
[0016] Each layer structure of the structure is manufactured separately; wherein each layer structure includes: a chip and a silicon bridge sheet arranged opposite to each other in a horizontal direction, wherein a through TSV is formed in the silicon bridge sheet; the PAD of the chip is fanned out to the silicon bridge sheet to form a new PAD, wherein the new PAD contacts the top surface of the TSV;
[0017] When manufacturing the Nth layer (N>1) structure of the structure, solder balls are formed on the bottom surface of the TSV; when manufacturing the first layer structure of the structure, the new PAD of the silicon bridge wafer is reasonably distributed through RDL to form a solder ball array electrically connected to the bottom surface of the TVS;
[0018] Providing a carrier board, on which the solder ball array of the first layer structure is soldered to the carrier board by a flip chip process;
[0019] The second to N-th layer structures are stacked vertically on the first layer structure from bottom to top. During stacking, the solder balls of the upper layer structure are in contact with the new PAD of the silicon bridge wafer of the lower layer structure.
[0020] In an optional solution, the method for manufacturing the Nth layer (N>1) structure includes:
[0021] Provide temporary slides;
[0022] placing the chip and the silicon bridge wafer on the temporary wafer;
[0023] forming a plastic sealing layer on the temporary carrier to cover the chip and the silicon bridge wafer;
[0024] removing the temporary carrier to expose the top surface of the TSV;
[0025] By using a Fan-out process, the PAD of the chip is fanned out to the silicon bridge to produce a new PAD with the same spacing as that on the chip, wherein the new PAD is located on the top surface of the TSV;
[0026] Thinning the backside of the chip and the silicon bridge wafer to expose the bottom of the TSV;
[0027] A solder ball is formed at the bottom of the TSV of the silicon bridge wafer.
[0028] In an optional solution, the carrier includes a substrate and a functional chip integrated on the substrate; the structure is integrated on the substrate, or integrated on the functional chip.
[0029] In an optional solution, after welding the first layer structure on the substrate and stacking the upper layer structure on the lower layer structure, the method further includes:
[0030] The bottom filling glue is filled between the substrate and the first layer structure and between the two layers of structure.
[0031] In an optional solution, the chip of each layer structure of the structural body is a flash memory chip; a logic chip is integrated on the substrate, the structural body is integrated on the logic chip, and a cache chip is also integrated on the logic chip.
[0032] The beneficial effects of the present invention are:
[0033] The present invention abandons the traditional staggered stacking + WB (gold wire bonding) method of flash memory chips, and uses the Fan-out process to fan out the PAD of the flash memory chip to the silicon bridge through RDL. At the same time, on the silicon bridge, TSV + solder balls are used to realize vertical interconnection of the flash memory chips, which can effectively reduce the packaging volume. BRIEF DESCRIPTION OF THE DRAWINGS
[0034] The above and other objects, features and advantages of the present invention will become more apparent through a more detailed description of exemplary embodiments of the present invention in conjunction with the accompanying drawings, in which like reference numerals generally represent like components.
[0035] Figure 1 and Figure 2 The figure is a schematic diagram of a packaging structure of staggered chips in the prior art.
[0036] Figure 3 Schematic diagram of the structure of the chip obtained after cutting the wafer in one embodiment of the present invention.
[0037] Figure 4 It is a schematic structural diagram of a chip PAD being fanned out to a silicon bridge wafer to form a new PAD in one embodiment of the present invention.
[0038] Figure 5 Schematic diagram of a structure in one embodiment of the present invention.
[0039] Figure 6 Schematic diagram of a vertically stacked chip packaging structure in one embodiment of the present invention.
[0040] Figure 7 FIG. 4 is a process flow chart for manufacturing a silicon bridge wafer according to an embodiment of the present invention.
[0041] Figure 8 FIG. 1 is a flowchart of a process for manufacturing an N-th layer structure (N>1) of a structure in one embodiment of the present invention.
[0042] Fig. 9 It is a schematic structural diagram of the first layer structure (bottommost structure) of the structure in one embodiment of the present invention.
[0043] Fig.10 Schematic diagram of the front and cross-sectional structure of the Nth layer structure (N>1) of the structure in one embodiment of the present invention. DETAILED DESCRIPTION
[0044] The present invention is further described in detail below in conjunction with the accompanying drawings and specific embodiments. According to the following description and drawings, the advantages and features of the present invention will become clearer. However, it should be noted that the concept of the technical solution of the present invention can be implemented in a variety of different forms and is not limited to the specific embodiments described herein. The drawings are all in a very simplified form and are not in precise proportions, and are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention.
[0045] It should be understood that when an element or layer is referred to as being "on, adjacent to, connected to or coupled to other elements or layers, it may be directly on, adjacent to, connected to or coupled to other elements or layers, or there may be intervening elements or layers. In contrast, when an element is referred to as being "directly on, directly adjacent to, directly connected to or directly coupled to other elements or layers, there may be no intervening elements or layers. It should be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, without departing from the teachings of the present invention, the first element, component, region, layer or part discussed below may be represented as a second element, component, region, layer or part.
[0046] Spatially relative terms such as "under," "below," "below," "under," "above," "above," etc., may be used herein for ease of description to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that in addition to the orientations shown in the figures, the spatially relative terms are intended to include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is flipped, then the elements or features described as "under other elements" or "under" or "under" will be oriented as "on" the other elements or features. Therefore, the exemplary terms "under" and "under" may include both upper and lower orientations. The device may be oriented otherwise (rotated 90 degrees or other orientations) and the spatial descriptors used herein are interpreted accordingly.
[0047] The purpose of the terms used herein is only to describe specific embodiments and is not intended to be limiting of the present invention. When used herein, the singular forms "one", "an" and "said / the" are also intended to include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "consisting of" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.
[0048] Example 1
[0049] Reference Figures 3 to 10 , this embodiment provides a chip vertical stacking packaging structure, including:
[0050] Carrier board;
[0051] A structure is integrated on the carrier; the structure is formed by vertically stacking multiple layers; each layer of the structure includes: a chip and a silicon bridge sheet arranged opposite to each other in a horizontal direction, and a through TSV is formed in the silicon bridge sheet; the PAD of the chip is fanned out to the silicon bridge sheet to form a new PAD, and the new PAD is in contact with the top surface of the TSV;
[0052] A solder ball is formed on the bottom surface of the TSV of the Nth layer (N>1) of the structure;
[0053] The solder ball of the upper structure is in contact with the new PAD of the lower structure;
[0054] The first layer structure of the structural body is formed with a solder ball array through RDL, and the structural body is soldered to the carrier through the solder ball array.
[0055] Specifically, in the present embodiment, the carrier includes a substrate and a functional chip integrated on the substrate; the structure is integrated on the functional chip. In other embodiments, the structure may also be integrated on the carrier. In the present embodiment, the chip of each layer of the structure is a flash memory chip, and the flash memory chip has multiple PADs, and the multiple PADs are arranged in a row. The spacing of the PADs of the flash memory chip is equal to the spacing of the new PADs formed by fanning out to the silicon bridge chip, and the electrical connection lines between each PAD of the flash memory chip and the corresponding new PAD are straight lines. Since there are multiple PAD-new PAD groups, there are multiple electrical connection lines, and the multiple electrical connection lines are parallel to each other. A logic chip is integrated on the substrate, the structure is integrated on the logic chip, and a cache chip is also integrated on the logic chip.
[0056] In this embodiment, bottom filling glue is filled between the substrate and the structure and between the layers of the structure.
[0057] In this embodiment, the PAD of the flash memory chip is fanned out to the front of the silicon bridge through the Fan-out process to form a new PAD, which contacts the top surface of the TSV, and makes solder balls at the bottom of the TSV to achieve vertical interconnection of multiple flash memory chips without misaligned stacking, effectively reducing the package volume. It should be noted that the flash memory chip can also be made with TSV and solder balls directly on its back, but this process requires that the TSV position be designed in advance when the chip is designed and made in the wafer factory. This process will incur high design and production costs; in this embodiment, Fan-out rewiring is performed before packaging, which can be completed by a general packaging factory and the cost will be reduced by at least half.
[0058] This embodiment uses Fan-out+TSV+solder balls to thin the chip to 50μm thickness (if it is traditional gold wire bonding, the 50μm chip is very thin and it is easy to crack the chip), thereby increasing the number of stacking layers and expanding the storage capacity within a limited space.
[0059] Since the interconnect lines are stacked vertically, the path is the shortest, which can effectively reduce the loss of signal transmission, reduce signal delay and reduce power consumption.
[0060] The chip of each layer structure of the structure of this embodiment can be a different chip, which supports the integration of different types of circuit units and can realize more complex functions.
[0061] Example 2
[0062] This embodiment provides a method for manufacturing a chip vertical stacking packaging structure, comprising:
[0063] Each layer structure of the structure is manufactured separately; wherein each layer structure includes: a chip and a silicon bridge sheet arranged opposite to each other in a horizontal direction, wherein a through TSV is formed in the silicon bridge sheet; the PAD of the chip is fanned out to the silicon bridge sheet to form a new PAD, wherein the new PAD contacts the top surface of the TSV;
[0064] When manufacturing the Nth layer (N>1) structure of the structure, forming a solder ball on the bottom surface of the TSV;
[0065] When manufacturing the first layer structure of the structure, the new PAD of the silicon bridge wafer is reasonably distributed through RDL to form a solder ball array electrically connected to the bottom surface of the TVS;
[0066] Providing a carrier board, on which the solder ball array of the first layer structure is soldered to the carrier board by a flip chip process;
[0067] The second to N-th layer structures are stacked vertically on the first layer structure from bottom to top. During stacking, the solder balls of the upper layer structure are in contact with the new PAD of the silicon bridge wafer of the lower layer structure.
[0068] Specifically, Figure 3 As shown, the flash memory chip wafer is back-thinned (from 600 μm to 250 μm), and the flash memory chips are cut into individual pieces. Figure 7 As described above, a silicon bridge wafer is manufactured. On a bare silicon wafer, a hole with a depth of 50 μm is etched by TSV process, and the aspect ratio of the TSV hole is (10:1 or 5:1), and copper is electroplated to form a silicon bridge wafer.
[0069] Reference Figure 8 , the method for manufacturing the Nth layer (N>1) structure includes: providing a temporary carrier; arranging the chip and the silicon bridge chip on the temporary carrier. The chip and the silicon bridge chip can be bonded to the temporary carrier by thermal decomposition glue. A plastic encapsulation layer is formed on the temporary carrier to cover the chip and the silicon bridge chip. The material of the plastic encapsulation layer can be epoxy resin. By heating, the thermal decomposition glue is decomposed, and the flash memory chip and the silicon bridge chip are removed from the temporary carrier to expose the top surface of the TSV; by the Fan-out process, the PAD of the flash memory chip is fanned out to the silicon bridge through the RDL to produce a new PAD with the same spacing as that on the flash memory chip, wherein the new PAD is located on the top surface of the TSV. Except for the new PAD area on the silicon bridge chip, a PI layer is coated to protect the RDL metal line and the original PAD on the flash memory chip. On the new PAD of the silicon bridge chip, a nickel layer + a palladium layer + a gold layer are produced by a chemical plating process; the purpose of this step is for subsequent stacking bonding. The back sides of the flash memory chip and the silicon bridge wafer are thinned (approximately to 50 μm) to expose the bottom of the TSV; and solder balls are made at the bottom of the TSV of the silicon bridge wafer.
[0070] The method for manufacturing the first layer (lowest layer) structure includes: providing a temporary carrier; placing the chip and the silicon bridge on the temporary carrier; forming a plastic layer on the temporary carrier to cover the chip and the silicon bridge; removing the temporary carrier to expose the top surface of the TSV; fanning out the PAD of the chip to the silicon bridge through a Fan-out process to produce a new PAD with the same spacing as on the chip, wherein the new PAD is located on the top surface of the TSV; thinning the back of the chip and the silicon bridge to expose the bottom of the TSV. The above steps are the same as the relevant steps for manufacturing the Nth layer (N>1) structure, except that after exposing the bottom of the TSV, solder balls are not directly formed at the bottom of the TSV, but the new PAD of the silicon bridge is reasonably distributed through RDL to form a solder ball array. The purpose of this step is to redistribute the new PAD into an array so as to disperse the welding stress on the carrier, so that the force is more uniform and the heat flows more freely.
[0071] In this embodiment, the carrier includes a substrate and a functional chip integrated on the substrate; the structure is integrated on the functional chip. In other embodiments, the structure can also be integrated on the substrate. In this embodiment, the chip of each layer of the structure is a flash memory chip; the functional chip is a logic chip, the structure is integrated on the logic chip, and a cache chip is also integrated on the logic chip.
[0072] The assembly process of the functional chip is as follows: solder the logic chip to the substrate through FC and fill it with bottom filler (Underfill process). Solder the solder ball array of the first layer flash memory chip to the bottom logic chip through FC and fill it with bottom filler (Underfill process). Stack the second layer to the Nth layer flash memory chips vertically on top of the first layer flash memory chip from bottom to top and fill it with bottom filler (Underfill process). Integrate HBM (DDR or LPDDR) on the logic chip for cache.
[0073] It should be noted that through the Underfill process, a strong bonding layer and filling layer are formed to reduce the thermal stress mismatch between the chip and the substrate caused by the difference in thermal expansion coefficients, thereby improving the structural strength and reliability of the device and enhancing the drop resistance between the chip and the substrate.
[0074] Through the above steps, the packaging and production of the entire storage component are finally completed, and the reading, writing and storage of data are realized.
[0075] The above description is only a description of the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention. Any changes or modifications made by a person skilled in the art in the field of the present invention based on the above disclosure shall fall within the scope of protection of the claims.
Claims
1. A chip vertical stacking packaging structure, characterized in that: include: Carrier board; A structure, integrated on the carrier; The structure is formed by vertically stacking multiple layers; each layer of the structure includes: a chip and a silicon bridge sheet arranged opposite to each other in a horizontal direction, and a through TSV is formed in the silicon bridge sheet; the PAD of the chip is fanned out to the silicon bridge sheet to form a new PAD, and the new PAD is in contact with the top surface of the TSV; A solder ball is formed on the bottom surface of the TSV of the Nth layer (N>1) of the structure; the solder ball of the upper layer structure is in contact with the new PAD of the lower layer structure; The first layer structure of the structural body is formed with a solder ball array electrically connected to the TSV through RDL, and the structural body is soldered to the carrier through the solder ball array.
2. The chip vertical stacking packaging structure according to claim 1, characterized in that: The carrier board includes a substrate and a functional chip integrated on the substrate; The structure is integrated on the carrier board or on the functional chip.
3. The chip vertical stacking packaging structure according to claim 2, characterized in that: The chip of each layer structure of the structural body is a flash memory chip; a logic chip is integrated on the substrate, the structural body is integrated on the logic chip, and a cache chip is also integrated on the logic chip.
4. The chip vertical stacking packaging structure according to claim 1, characterized in that: The spacing of the PADs of the chip is equal to the spacing of the new PADs formed by fanning out to the silicon bridge wafer, and the electrical connection lines between each PAD of the chip and the corresponding new PAD are straight lines, and the multiple straight lines are parallel to each other.
5. The chip vertical stacking packaging structure according to claim 1, characterized in that: Bottom filling glue is filled between the substrate and the structure and between each layer structure of the structure.
6. A method for manufacturing a chip vertical stacking packaging structure, characterized in that: include: Each layer structure of the structure is manufactured separately; wherein each layer structure includes: a chip and a silicon bridge sheet arranged opposite to each other in a horizontal direction, wherein a through TSV is formed in the silicon bridge sheet; the PAD of the chip is fanned out to the silicon bridge sheet to form a new PAD, wherein the new PAD contacts the top surface of the TSV; When manufacturing the Nth layer (N>1) structure of the structure, solder balls are formed on the bottom surface of the TSV; when manufacturing the first layer structure of the structure, the new PAD of the silicon bridge wafer is reasonably distributed through RDL to form a solder ball array electrically connected to the bottom surface of the TVS; Providing a carrier board, on which the solder ball array of the first layer structure is soldered to the carrier board by a flip chip process; The second to N-th layer structures are stacked vertically on the first layer structure from bottom to top. During stacking, the solder balls of the upper layer structure are in contact with the new PAD of the silicon bridge wafer of the lower layer structure.
7. The method for manufacturing a vertically stacked chip packaging structure according to claim 6, characterized in that: The method of manufacturing the Nth layer (N>1) structure includes: Provide temporary slides; placing the chip and the silicon bridge wafer on the temporary wafer; forming a plastic sealing layer on the temporary carrier to cover the chip and the silicon bridge wafer; removing the temporary carrier to expose the top surface of the TSV; By using a Fan-out process, the PAD of the chip is fanned out to the silicon bridge to produce a new PAD with the same spacing as that on the chip, wherein the new PAD is located on the top surface of the TSV; Thinning the backside of the chip and the silicon bridge wafer to expose the bottom of the TSV; A solder ball is formed at the bottom of the TSV of the silicon bridge wafer.
8. The method for manufacturing a vertically stacked chip packaging structure according to claim 6, wherein: The carrier includes a substrate and a functional chip integrated on the substrate; the structure is integrated on the substrate, or integrated on the functional chip.
9. The method for manufacturing a vertically stacked chip packaging structure according to claim 6, wherein: After welding the first layer structure on the substrate and stacking the upper layer structure on the lower layer structure, the method further includes: The bottom filling glue is filled between the substrate and the first layer structure and between the two layers of structure.
10. The method for manufacturing a vertically stacked chip packaging structure according to claim 8, characterized in that: The chip of each layer structure of the structural body is a flash memory chip; a logic chip is integrated on the substrate, the structural body is integrated on the logic chip, and a cache chip is also integrated on the logic chip.