Display device and method for manufacturing display device

Abstract

The invention relates to a display device and a manufacturing method of the display device. The display device includes: a connection pattern and a dummy pattern spaced apart from each other on a substrate; the via hole layer is arranged on the substrate; a pixel electrode on the via layer and electrically connected to the connection pattern; a light emitting layer on the pixel electrode; a control layer on the light emitting layer; and a common electrode on the control layer. The dummy pattern may include a first dummy pattern and a second dummy pattern disposed on the first dummy pattern. The first dummy pattern may include a first layer, a second layer, and a third layer, each of the first layer, the second layer, and the third layer being made of a conductive material, and the first layer, the second layer, and the third layer being sequentially stacked. The second dummy pattern may include an organic pattern including a first portion and a second portion having different areas in a plan view.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to and the benefit of Korean Patent Application No. 10-2023-0096367 filed in the Korean Intellectual Property Office on July 24, 2023, the entire contents of which are incorporated herein by reference. Technical Field

[0003] The inventive concept relates to a display device and a method for manufacturing the display device. Background Art

[0004] Recently, as interest in information display has increased, research and development of display devices have been ongoing. Summary of the invention

[0005] The inventive concept may provide a display device having improved reliability and a method of manufacturing the display device.

[0006] The display device according to the embodiment includes: a connection pattern and a dummy pattern, which are spaced apart from each other on a substrate; a via layer, which is disposed on the substrate, and the via layer includes a contact portion exposing the connection pattern and a via hole exposing the dummy pattern; a pixel electrode, which is disposed on the via layer and electrically connected to the connection pattern through the contact portion; a light emitting layer, which is disposed on the pixel electrode; a control layer, which is disposed on the light emitting layer; and a common electrode, which is disposed on the control layer. The dummy pattern may include a first dummy pattern and a second dummy pattern disposed on the first dummy pattern. The first dummy pattern may include a first layer, a second layer, and a third layer, each of which is made of a conductive material, and the first layer, the second layer, and the third layer are stacked sequentially. The second dummy pattern may include an organic pattern, and the organic pattern includes a first part and a second part having different areas in a plan view.

[0007] In an embodiment, the second dummy pattern may include a negative photosensitive material. The control layer may be disconnected on the first portion.

[0008] In an embodiment, the first portion is disposed on the first dummy pattern, and the second portion is disposed on the first portion. The first portion may have an area smaller than that of the second portion. The second portion may have a reverse tapered shape in which the width narrows from the upper surface toward the lower surface.

[0009] In an embodiment, an inclination angle of a side surface connected to the lower surface in the second portion may be from 90° to 130°. In a plan view, a side surface of the first portion may be disposed inside the side surface of the second portion.

[0010] In an embodiment, the first portion may have an undercut portion recessed from the side surface of the second portion.

[0011] In an embodiment, the first layer and the third layer may include titanium (Ti), and the second layer may include aluminum (Al) having a greater thickness than the first layer and the third layer.

[0012] In an embodiment, the control layer may be disposed on each of the upper surface of the second portion, the side surface of the second portion, a portion of the upper surface of the third layer, a portion of the side surface of the second layer, and the side surface of the first layer. The common electrode may be disposed on each of the control layer, the side surface of the first portion, the upper surface and the side surface of the third layer, and the side surface of the second layer.

[0013] In an embodiment, the common electrode may be disconnected on the side surface of the first portion.

[0014] In an embodiment, a portion of the common electrode disposed on the second dummy pattern and a portion of the common electrode disposed on the first dummy pattern may be disconnected from each other.

[0015] In an embodiment, a portion of the common electrode disposed on the second dummy pattern and a portion of the common electrode disposed on the first dummy pattern may be connected to each other.

[0016] In an embodiment, the common electrode may fill an undercut portion surrounded by a lower surface of the second portion, the side surface of the first portion, and the upper surface of the third layer.

[0017] In an embodiment, the third layer may include an opening exposing a portion of the second layer. The common electrode may be disposed on the portion of the second layer exposed by the opening.

[0018] In an embodiment, the third layer may include a protrusion protruding in a direction toward the second dummy pattern.

[0019] In an embodiment, the display device may further include a conductive pattern disposed on the first dummy pattern and the second dummy pattern. The conductive pattern may include the same material as the pixel electrode.

[0020] In an embodiment, the second dummy pattern includes a plurality of second dummy patterns that may be disposed on the first dummy pattern.

[0021] In an embodiment, the connection pattern may include a first metal layer, a second metal layer disposed on the first metal layer, and a third metal layer disposed on the second metal layer. The first metal layer may include the same material as the first layer and the first metal layer may be disposed on the same layer as the first layer. The second metal layer may include the same material as the second layer and the second metal layer may be disposed on the same layer as the second layer. The third metal layer may include the same material as the third layer and the third metal layer may be disposed on the same layer as the third layer.

[0022] In an embodiment, the display device may further include at least one transistor disposed between the substrate and the connection pattern, and the at least one transistor is electrically connected to the pixel electrode through the connection pattern.

[0023] In an embodiment, the first dummy pattern may be electrically connected to the common electrode to receive a low potential voltage.

[0024] In an embodiment, the display device may further include a pixel defining layer exposing one region of the pixel electrode and a third dummy pattern disposed on the pixel defining layer.

[0025] The manufacturing method of the display device according to the embodiment includes: forming a connection pattern and a dummy pattern spaced apart from each other on a substrate; forming a via layer, the via layer including a contact portion exposing the connection pattern and a via hole exposing the dummy pattern, the via layer being disposed on the connection pattern; forming a pixel electrode electrically connected to the connection pattern through the contact portion on the via layer; forming a light emitting layer on the pixel electrode; forming a control layer on the light emitting layer; and forming a common electrode on the control layer. The dummy pattern may include a first dummy pattern and a second dummy pattern disposed on the first dummy pattern. The first dummy pattern may include a first layer, a second layer, and a third layer, each of the first layer, the second layer, and the third layer being made of a conductive material, and the first layer, the second layer, and the third layer being stacked sequentially. The second dummy pattern may include an organic pattern, the organic pattern including a first portion and a second portion having different areas in a plan view.

[0026] According to an embodiment, a second dummy pattern (or organic pattern) having a reverse tapered structure may be formed on a first dummy pattern (or electrode layer) electrically connected to a common electrode (or cathode electrode), thereby reducing an area in which a control layer is deposited on both side surfaces of the first dummy pattern.

[0027] According to the embodiment, a display device having improved reliability and a method of manufacturing the display device may be provided by further securing a contact area between the common electrode and the first dummy pattern to prevent a voltage drop of the common electrode.

[0028] The effects according to the embodiment are not limited to the contents exemplified above, and more various effects are included in this specification. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1 is a schematic plan view showing a display device according to an embodiment.

[0030] Figure 2 It is shown Figure 1 Schematic cross-sectional view of a display panel.

[0031] Figure 3 It is shown Figure 1 Schematic plan view of an example of a display area of ​​a display panel.

[0032] Figure 4 It is shown that the Figure 1 A schematic circuit diagram of the electrical connection relationship of the constituent elements in each of the pixels shown in FIG.

[0033] Figure 5 and Figure 6 is a schematic plan view showing a pixel according to the embodiment.

[0034] Figure 7 Only the included Figure 5 Schematic plan view of a transistor in a pixel, and constituent elements in a first conductive layer and a second conductive layer.

[0035] Figure 8 Only the included Figure 5 Schematic plan view of constituent elements in the fourth conductive layer in a pixel.

[0036] Fig. 9 It is along Figure 6 Schematic cross-sectional view taken along line II'.

[0037] Fig.10 , Fig.11 , Fig.12 , Fig.13 , Fig.14 , Fig.15 , Fig.16 and Fig.17 It is along Figure 6 Schematic cross-sectional view taken along line II-II'.

[0038] Fig.18 shows a pixel according to an embodiment and is Figure 6 Schematic cross-sectional view corresponding to line II'.

[0039] Fig.19A and Fig.19B It is shown that the Figure 1 A schematic plan view of a region of a display area in a display device.

[0040] Fig. 20 , Fig.21 , Fig. 22 , Fig.23 , Fig.24 , Fig.25 , Fig.26 , Fig. 27 , Fig.28 , Fig.29 and Fig.30 It is shown that the formation Fig. 9 The first sub-pixel and the second sub-pixel and Fig.10 Schematic cross-sectional view of a method for creating a dummy pattern. DETAILED DESCRIPTION

[0041] It is obvious to those skilled in the art that various modifications and variations may be made to the present disclosure without departing from the spirit or scope of the present disclosure, and specific embodiments are shown in the drawings and described in the detailed description. However, it should be understood that this is not intended to limit the inventive concept to the specific disclosed form, and includes all modifications, equivalents and substitutes included in the technical scope of the inventive concept.

[0042] Throughout the specification, the same reference numerals refer to the same elements. In the drawings, the size of the structure is exaggerated for clarity. The terms "first" and "second" and the like may be simply used to describe various constituent elements, but those meanings may not be limited to the restricted meanings. The above terms are only used to distinguish one constituent element from other constituent elements. For example, within the scope of the appended claims, a first constituent element may be referred to as a second constituent element, and similarly, a second constituent element may be referred to as a first constituent element.

[0043] In this specification, the words "including" or "having" are used to illustrate the presence of features, numbers, processes, operations, constituent elements, parts or combinations thereof, and it will be understood that the possibility of the presence or addition of one or more other features, numbers, processes, operations, constituent elements, parts or combinations thereof is not precluded. In addition, it will be understood that when an element such as a layer, film, region or substrate is referred to as being "on" another element, the element may be directly on the other element, or there may also be intervening elements. In this specification, it will be understood that when an element such as a layer, film, region or substrate is referred to as being "on" another element, the setting direction is not limited to the upper direction and includes a lateral direction or a lower direction. On the contrary, it will be understood that when an element such as a layer, film, region or substrate is referred to as being "below" another element, the element may be directly below the other element, or there may also be intervening elements.

[0044] In the present application, when a component (e.g., a "first component") is referred to as being "coupled (operably or communicatively) with" / "coupled (operably or communicatively) to" or "connected to" another component (e.g., a "second component"), it should be understood that the one component may be directly connected to the other component or may be connected through other components (e.g., a "third component"). On the other hand, when a component (e.g., a "first component") is referred to as being "directly coupled" or "directly connected" to another component (e.g., a "second component"), it should be understood that there are no other components (e.g., a "third component") between the one component and the other component.

[0045] Hereinafter, preferred embodiments and other embodiments of the inventive concept required for those skilled in the art to understand the contents of the inventive concept will be described in more detail with reference to the accompanying drawings. Unless otherwise described, terms in the singular form may include plural forms.

[0046] Figure 1 is a schematic plan view showing a display device DD according to the embodiment, and Figure 2 It is shown Figure 1 Schematic cross-sectional view of a display panel DP.

[0047] exist Figure 1 and Figure 2 , for convenience, the structure of the display device DD is briefly illustrated focusing on a display area DA that displays an image, for example, a display panel DP provided in the display device DD.

[0048] Reference Figure 1 and Figure 2, the display panel DP (or display device DD) according to the embodiment may be provided in various shapes. For example, the display panel DP may be provided in the shape of a rectangular plate having two pairs of parallel sides. However, the embodiment is not limited thereto. In the case where the display panel DP is provided in the shape of a rectangular plate, one of the two pairs of sides may be provided to be longer than the other pair of sides.

[0049] At least a portion of the display panel DP may have flexibility and may be folded at the portion having flexibility, but is not limited thereto.

[0050] The display panel DP can display an image. The display panel DP may include a display panel capable of self-emission, such as an organic light-emitting display panel (OLED panel) using an organic light-emitting diode as a light-emitting element, an ultra-small light-emitting diode display panel (micro-LED or nano-LED display panel) using an ultra-small light-emitting diode as a light-emitting element, and a quantum dot organic light-emitting display panel (QD OLED panel) using quantum dots and organic light-emitting diodes. In addition, the display panel DP may include a non-luminous display panel, such as a liquid crystal display panel (LCD panel), an electrophoretic display panel (EPD panel), and an electrowetting display panel (EWD panel). In the case of using a non-luminous display panel as the display panel DP, the display device DD may include a backlight unit that supplies light to the display panel DP. In an embodiment, the display panel DP may be an organic light-emitting display panel.

[0051] The display panel DP may include a substrate SUB and pixels PXL provided on the substrate SUB.

[0052] The substrate SUB may include a transparent insulating material and transmit light, but is not limited thereto. The substrate SUB may be a rigid substrate or a flexible substrate.

[0053] The rigid substrate may be, for example, one of a glass substrate, a quartz substrate, and a glass ceramic substrate (or a microcrystalline glass substrate).

[0054] The flexible substrate may be one of a film substrate and a plastic substrate including a polymeric organic material. For example, the flexible substrate may include at least one selected from the group consisting of polystyrene, polyvinyl alcohol, polymethyl methacrylate, polyether sulfone, polyacrylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyarylate, polyimide, polycarbonate, cellulose triacetate, and cellulose acetate propionate.

[0055] One area in the substrate SUB may be a display area DA such that the pixel PXL may be disposed therein, and the remaining area in the substrate SUB may be a non-display area NDA. For example, the substrate SUB may include a display area DA including a pixel area PXA in which each pixel PXL is disposed, and a non-display area NDA disposed around (or adjacent to) the display area DA.

[0056] The non-display area NDA may be disposed adjacent to the display area DA. The non-display area NDA may be provided on at least one side of the display area DA. For example, the non-display area NDA may surround the periphery (or edge) of the display area DA. A wiring unit electrically connected to each pixel PXL and a driving unit electrically connected to the wiring unit and for driving the pixel PXL may be provided in the non-display area NDA.

[0057] Each of the pixels PXL may be provided in a display area DA of a substrate SUB. The pixel PXL may include a light emitting element emitting white light and / or color light and a pixel circuit for driving the light emitting element. The pixel circuit may include at least one transistor electrically connected to the light emitting element. Each pixel PXL may emit light of one color among red, green and blue, but is not limited thereto. Each pixel PXL may emit light of one color among cyan, magenta, yellow and white.

[0058] The pixel PXL may be provided in plurality and arranged in a matrix form along a pixel row extending in a first direction DR1 and a pixel column extending in a second direction DR2 intersecting the first direction DR1. The arrangement of the pixel PXL is not particularly limited, and the pixel PXL may be arranged in various forms. According to an embodiment, the plurality of pixels PXL may have different areas (or sizes). For example, in the case where the pixels PXL have different colors of emitted light, the pixels PXL may have different areas (or sizes) or shapes different from each other.

[0059] The driver may control driving of the pixel PXL by providing a predetermined signal and a predetermined voltage to each pixel PXL through the wiring unit.

[0060] The display panel DP (or each of the pixels PXL) may include a pixel circuit layer PCL, a display element layer DPL, and an encapsulation layer TFE disposed on a substrate SUB.

[0061] The pixel circuit layer PCL may be provided on a substrate SUB and may include a transistor and a signal line connected to the transistor. For example, the transistor may have an active pattern (or semiconductor pattern), a gate electrode, a source electrode, and a drain electrode sequentially stacked on the substrate SUB, with an insulating layer between them. The semiconductor pattern may include amorphous silicon, polycrystalline silicon (e.g., low temperature polycrystalline silicon), an organic semiconductor, and / or an oxide semiconductor. The gate electrode, the source electrode, and the drain electrode may include one of aluminum (Al), copper (Cu), titanium (Ti), and molybdenum (Mo), but are not limited thereto. In addition, the pixel circuit layer PCL may include at least one insulating layer.

[0062] The display element layer DPL may be disposed on the pixel circuit layer PCL. The display element layer DPL may include a light emitting element that emits light. The light emitting element may be, for example, an organic light emitting diode, but is not limited thereto. According to an embodiment, the light emitting element may be an inorganic light emitting element including an inorganic light emitting material or a light emitting element that emits light by changing the wavelength of the emitted light using quantum dots.

[0063] The encapsulation layer TFE may be disposed on the display element layer DPL. The encapsulation layer TFE may include an encapsulation substrate or a multi-layer encapsulation film. In the case where the encapsulation layer TFE is in the form of an encapsulation film, the encapsulation layer TFE may include an inorganic layer and / or an organic layer. For example, the encapsulation layer TFE may include an inorganic layer, an organic layer, and an inorganic layer sequentially stacked on the display element layer DPL. The encapsulation layer TFE may prevent external air and moisture from penetrating into the display element layer DPL and the pixel circuit layer PCL.

[0064] Figure 3 It is shown Figure 1 Schematic plan view of an example of a display area DA of a display panel.

[0065] Reference Figures 1 to 3 , the pixel PXL may be disposed in the display area DA. The pixel PXL may be disposed in a pixel area PXA provided in the display area DA. The pixel area PXA may include an emission area EMA and a non-emission area NEA.

[0066] The pixel PXL may include a first sub-pixel SPX1, a second sub-pixel SPX2, and a third sub-pixel SPX3. The first sub-pixel SPX1 may emit light of a first color, the second sub-pixel SPX2 may emit light of a second color, and the third sub-pixel SPX3 may emit light of a third color. For example, the light of the first color may be light of a red wavelength band, the light of the second color may be light of a green wavelength band, and the light of the third color may be light of a blue wavelength band. However, it is not limited to the above examples.

[0067] The first subpixel SPX1 may include a first emission area EMA1 and a non-emission area NEA disposed adjacent to the first emission area EMA1 (or surrounding at least one side of the first emission area EMA1). The second subpixel SPX2 may include a second emission area EMA2 and a non-emission area NEA disposed adjacent to the second emission area EMA2 (or surrounding at least one side of the second emission area EMA2). The third subpixel SPX3 may include a third emission area EMA3 and a non-emission area NEA disposed adjacent to the third emission area EMA3 (or surrounding at least one side of the third emission area EMA3). The first emission area EMA1, the second emission area EMA2, and the third emission area EMA3 may constitute the emission area EMA of the pixel PXL.

[0068] Each of the first sub-pixel SPX1, the second sub-pixel SPX2, and the third sub-pixel SPX3 may include a light emitting element that emits light (refer to Figure 4 The first emission area EMA1 may be an area in which light is emitted from the light emitting element LD driven by the circuit element of the first sub-pixel SPX1. The second emission area EMA2 may be an area in which light is emitted from the light emitting element LD driven by the circuit element of the second sub-pixel SPX2. The third emission area EMA3 may be an area in which light is emitted from the light emitting element LD driven by the circuit element of the third sub-pixel SPX3.

[0069] The light emitting element LD provided in the first sub-pixel SPX1 may include a first pixel electrode PE1, a first light emitting layer EML1 provided on the first pixel electrode PE1, and a common electrode (refer to Fig. 9 The light emitting element LD disposed in the second sub-pixel SPX2 may include a second pixel electrode PE2, a second light emitting layer EML2 disposed on the second pixel electrode PE2, and a common electrode CE disposed on the second light emitting layer EML2. The light emitting element LD disposed in the third sub-pixel SPX3 may include a third pixel electrode PE3, a third light emitting layer EML3 disposed on the third pixel electrode PE3, and a common electrode CE disposed on the third light emitting layer EML3. The first pixel electrode PE1, the second pixel electrode PE2, and the third pixel electrode PE3 may constitute the pixel electrode PE of the pixel PXL.

[0070] In an embodiment, the first pixel electrode PE1 can be electrically connected to a circuit element set in the pixel circuit layer PCL of the first sub-pixel SPX1 through the first contact portion CNT1, and the second pixel electrode PE2 can be electrically connected to a circuit element set in the pixel circuit layer PCL of the second sub-pixel SPX2 through the second contact portion CNT2, and the third pixel electrode PE3 can be electrically connected to a circuit element set in the pixel circuit layer PCL of the third sub-pixel SPX3 through the third contact portion CNT3.

[0071] Figure 4 It is shown that the Figure 1 Schematic circuit diagram of the electrical connection relationship of the constituent elements in each of the pixels PXL shown in FIG. Figure 4 In the figure, for convenience of description, a pixel PXL (or a sub-pixel SPX) disposed in an i-th horizontal line (or an i-th pixel row) and connected to a j-th data line Dj is shown, and i and j are each a positive integer.

[0072] Reference Figures 1 to 4 The pixel PXL (or sub-pixel SPX) may include a pixel circuit PXC and a light emitting element LD. The pixel circuit PXC may include a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7 and a storage capacitor Cst.

[0073] A first electrode (or pixel electrode) of the light emitting element LD may be connected to a fourth node N4, and a second electrode (or common electrode) of the light emitting element LD may be connected to a fourth power line PL4. The light emitting element LD may generate light having a predetermined brightness in response to the amount of current (or drive current) supplied from the first transistor T1. In an embodiment, the light emitting element LD may be an organic light emitting diode including an organic light emitting layer. However, it is not limited thereto, and according to an embodiment, the light emitting element LD may be an inorganic light emitting element made of an inorganic material or a light emitting element composed of a combination of an inorganic material and an organic material.

[0074] The first transistor T1 (or driving transistor) may be electrically connected between the first power line PL1 and the first electrode of the light emitting element LD. The first transistor T1 may include a gate electrode electrically connected to the first node N1. The first transistor T1 may control the amount of current (or driving current) flowing from the first power line PL1 to the fourth power line PL4 via the light emitting element LD based on the voltage of the first node N1. The first power supply voltage VDD may be provided from the first power line PL1, the second power supply voltage VSS may be provided from the fourth power line PL4, and the first power supply voltage VDD may be higher than the second power supply voltage VSS.

[0075] The second transistor T2 may be electrically connected between the j-th data line Dj and the second node N2. The gate electrode of the second transistor T2 may be connected to the 1i-th scan line S1i (or the first scan line S1i). The second transistor T2 may be turned on in response to a first scan signal GW[i] (e.g., a low-level first scan signal) supplied from the 1i-th scan line S1i to electrically connect the j-th data line Dj and the second node N2. When the first transistor T1 is in the on state, the second transistor T2 may transmit the data signal of the j-th data line Dj to the second node N2 in response to the first scan signal GW[i].

[0076] The third transistor T3 may be electrically connected between the first node N1 and the third node N3. The gate electrode of the third transistor T3 may be electrically connected to the 1i-th scan line S1i. The third transistor T3 may be turned on in response to the first scan signal GW[i] supplied from the 1i-th scan line S1i. When the third transistor T3 is turned on, the first transistor T1 may have a diode connection form.

[0077] The fourth transistor T4 may be electrically connected between the first node N1 and the second power line PL2. The gate electrode of the fourth transistor T4 may be electrically connected to the 2i-th scan line S2i (or the second scan line S2i). The first initialization power supply voltage Vint1 may be applied from the second power line PL2. The fourth transistor T4 may be turned on in response to the second scan signal GI[i] supplied from the 2i-th scan line S2i. When the fourth transistor T4 is turned on, the first initialization power supply voltage Vint1 may be supplied to the first node N1 (i.e., the gate electrode of the first transistor T1).

[0078] The fifth transistor T5 may be electrically connected between the first power line PL1 and the second node N2. The gate electrode of the fifth transistor T5 may be electrically connected to the i-th emission control line Ei (or the emission control line Ei). The sixth transistor T6 may be electrically connected between the third node N3 and the light emitting element LD (or the fourth node N4). The gate electrode of the sixth transistor T6 may be electrically connected to the i-th emission control line Ei. The fifth transistor T5 and the sixth transistor T6 may be turned off in response to the i-th emission control signal EM[i] (e.g., the high-level emission control signal EM[i]) supplied from the i-th emission control line Ei, and may be turned on in other cases.

[0079] The seventh transistor T7 may be electrically connected between the first electrode (i.e., the fourth node N4) of the light emitting element LD and the third power line PL3. The gate electrode of the seventh transistor T7 may be electrically connected to the 3i-th scan line S3i (or the third scan line S3i). The second initialization power supply voltage Vint2 may be provided from the third power line PL3. According to an embodiment, the second initialization power supply voltage Vint2 may be the same as or different from the first initialization power supply voltage Vint1. The seventh transistor T7 may be turned on in response to the third scan signal GB[i] supplied from the 3i-th scan line S3i to supply the second initialization power supply voltage Vint2 to the first electrode of the light emitting element LD.

[0080] The storage capacitor Cst may be connected or formed between the first power line PL1 and the first node N1.

[0081] According to an embodiment, the pixel circuit PXC may further include an additional capacitor connected or formed between the first power line PL1 and the fourth transistor T4 (or the third transistor T3 ).

[0082] Figure 5 and Figure 6 is a schematic plan view showing a pixel PXL according to an embodiment, Figure 7 Only the included Figure 5 A schematic plan view of transistors T1 to T7 in a pixel, constituent elements in a first conductive layer CL1 and a second conductive layer CL2, and Figure 8 Only the included Figure 5 Schematic plan view of constituent elements in the fourth conductive layer CL4 in a pixel. For ease of description, Figures 5 to 8 Shown are a first subpixel SPX1 arranged in the i-th horizontal line (or i-th pixel row) and connected to the first data line D1, a second subpixel SPX2 arranged in the i-th horizontal line and connected to the second data line D2, and a third subpixel SPX3 arranged in the i-th horizontal line and connected to the third data line D3.

[0083] and Figure 5 Compared to the pixel PXL shown in Figure 6 The pixel PXL shown in FIG. 1 further includes a first pixel electrode PE1 of the first sub-pixel SPX1 , a second pixel electrode PE2 of the second sub-pixel SPX2 , and a third pixel electrode PE3 of the third sub-pixel SPX3 .

[0084] exist Figure 5 and Figure 6 In the figure, for convenience of description, the light emitting elements electrically connected to the transistors T1 to T7 are omitted.

[0085] Reference Figures 1 to 8The pixel PXL may be disposed in the pixel area PXA. The pixel PXL may include a first sub-pixel SPX1, a second sub-pixel SPX2, and a third sub-pixel SPX3.

[0086] The first sub-pixel SPX1 may include a first pixel circuit PXC1 and a light emitting element driven by the first pixel circuit PXC1 (refer to Figure 4 The second sub-pixel SPX2 may include a second pixel circuit PXC2 and a light emitting element LD driven by the second pixel circuit PXC2. The third sub-pixel SPX3 may include a third pixel circuit PXC3 and a light emitting element LD driven by the third pixel circuit PXC3.

[0087] Signal lines electrically connected to the first, second and third subpixels SPX1, SPX2 and SPX3 may be disposed in the pixel region PXA. For example, scan lines, emission control lines Ei, data lines D1, D2 and D3 and power lines PL1, PL2 and PL3 may be disposed in the pixel region PXA.

[0088] The scan lines may extend in the first direction DR1, and may include a first scan line S1i, a second scan line S2i, and a third scan line S3i that are spaced apart from each other.

[0089] The first scan line S1i, the second scan line S2i, and the third scan line S3i may include a second conductive layer CL2. The second conductive layer CL2 may be formed as a single layer or multiple layers, including molybdenum (Mo), copper (Cu), aluminum (Al), chromium (Cr), gold (Au), silver (Ag), titanium (Ti), nickel (Ni), neodymium (Nd), indium (In), tin (Sn), and oxides or alloys thereof.

[0090] The first scan line S1i may be integrally formed with the second gate electrode GE2 of the second transistor T2 of each of the first pixel circuit PXC1, the second pixel circuit PXC2, and the third pixel circuit PXC3. In this case, a portion of the first scan line S1i may be the second gate electrode GE2.

[0091] In addition, the first scan line S1i may be integrally formed with the 3a gate electrode GE3a of the 3a transistor T3a of each of the first pixel circuit PXC1, the second pixel circuit PXC2, and the third pixel circuit PXC3. In this case, another portion of the first scan line S1i may be the 3a gate electrode GE3a.

[0092] In addition, the first scan line S1i may be integrally formed with the 3b gate electrode GE3b of the 3b transistor T3b of each of the first pixel circuit PXC1, the second pixel circuit PXC2, and the third pixel circuit PXC3. In this case, another portion of the first scan line S1i may be the 3b gate electrode GE3b.

[0093] The second scan line S2i may be integrally formed with the 4a gate electrode GE4a of the 4a transistor T4a of each of the first pixel circuit PXC1, the second pixel circuit PXC2, and the third pixel circuit PXC3. In this case, a portion of the second scan line S2i may be the 4a gate electrode GE4a.

[0094] In addition, the second scan line S2i may be integrally formed with the 4bth gate electrode GE4b of the 4bth transistor T4b of each of the first pixel circuit PXC1, the second pixel circuit PXC2, and the third pixel circuit PXC3. In this case, another portion of the second scan line S2i may be the 4bth gate electrode GE4b.

[0095] The third scan line S3i may be integrally formed with the 7ath gate electrode GE7a of the 7ath transistor T7a of each of the first pixel circuit PXC1, the second pixel circuit PXC2, and the third pixel circuit PXC3. In this case, a portion of the third scan line S3i may be the 7ath gate electrode GE7a.

[0096] In addition, the third scan line S3i may be integrally formed with the 7bth gate electrode GE7b of the 7bth transistor T7b of each of the first pixel circuit PXC1, the second pixel circuit PXC2, and the third pixel circuit PXC3. In this case, another portion of the third scan line S3i may be the 7bth gate electrode GE7b.

[0097] The emission control line Ei may extend in the first direction DR1 and may be spaced apart from the first, second, and third scan lines S1i, S2i, and S3i. The emission control line Ei may include a second conductive layer CL2.

[0098] The emission control line Ei may be integrally formed with the fifth gate electrode GE5 of the fifth transistor T5 of each of the first pixel circuit PXC1, the second pixel circuit PXC2, and the third pixel circuit PXC3. In this case, a portion of the emission control line Ei may be the fifth gate electrode GE5.

[0099] In addition, the emission control line Ei may be integrally formed with the sixth gate electrode GE6 of the sixth transistor T6 of each of the first to third pixel circuits PXC1 to PXC2 and PXC3 . In this case, another portion of the emission control line Ei may be the sixth gate electrode GE6 .

[0100] The data lines may extend in the second direction DR2 and may include first, second, and third data lines D1, D2, and D3 spaced apart from each other. Each of the first, second, and third data lines D1, D2, and D3 may receive a data signal.

[0101] The first data line D1 may be electrically connected to the second transistor T2 of the first pixel circuit PXC1, the second data line D2 may be electrically connected to the second transistor T2 of the second pixel circuit PXC2, and the third data line D3 may be electrically connected to the second transistor T2 of the third pixel circuit PXC3. Each of the first data line D1, the second data line D2, and the third data line D3 may include a fourth conductive layer CL4. The fourth conductive layer CL4 may include the same material as the above-mentioned second conductive layer CL2, or may include one or more suitable (or selected) materials from the materials exemplified as the constituent materials of the second conductive layer CL2, but is not limited thereto. According to an embodiment, the fourth conductive layer CL4 may be formed of three layers.

[0102] The power lines PL1 , PL2 , and PL3 may include a first power line PL1 extending in the second direction DR2 , and second and third power lines PL2 and PL3 extending in the first direction DR1 .

[0103] The first power line PL1 may receive a first power voltage VDD. The first power line PL1 may be spaced apart from the data line in each sub-pixel. For example, the first power line PL1 in the first sub-pixel SPX1 may be arranged to be spaced apart from the first data line D1, the first power line PL1 in the second sub-pixel SPX2 may be arranged to be spaced apart from the second data line D2, and the first power line PL1 in the third sub-pixel SPX3 may be arranged to be spaced apart from the third data line D3. In an embodiment, the first power line PL1 may include a fourth conductive layer CL4, and may be formed by the same process and on the same plane as the first data line D1, the second data line D2, and the third data line D3.

[0104] The first power line PL1 may be electrically connected to the additional conductive pattern ACP through the corresponding contact hole CH. The additional conductive pattern ACP may include a second conductive layer CL2 and may overlap with the first power line PL1. The first power line PL1 may be electrically connected to the additional conductive pattern ACP disposed on a different layer through the corresponding contact hole CH to implement a double-layer structure. Therefore, the line resistance of the first power line PL1 may be reduced.

[0105] The first sub-pixel SPX1 and the second sub-pixel SPX2 may share the first power line PL1 , but are not limited thereto.

[0106] In each of the first sub-pixel SPX1 , the second sub-pixel SPX2 , and the third sub-pixel SPX3 , the first power line PL1 may be electrically connected to the fifth transistor T5 through the corresponding contact hole CH.

[0107] The second power line PL2 may receive a first initialization power voltage Vint1. The second power line PL2 may be disposed to be spaced apart from the second scan line S2i in the second direction DR2. The second power line PL2 may include a second conductive layer CL2. The second power line PL2 may be a common line commonly provided to the first sub-pixel SPX1, the second sub-pixel SPX2, and the third sub-pixel SPX3.

[0108] In the first sub-pixel SPX1 , the second power line PL2 may be electrically connected to the fourth transistor T4 through the second connection pattern CNP2 .

[0109] The second connection pattern CNP2 may include a fourth conductive layer CL4. One end of the second connection pattern CNP2 may be electrically connected to the second power line PL2 through a corresponding contact hole CH. The other end of the second connection pattern CNP2 may be electrically connected to the 4b transistor T4b of the fourth transistor T4 through a corresponding contact hole CH. The second connection pattern CNP2 may electrically connect the second power line PL2 and the 4b transistor T4b of the first sub-pixel SPX1 (or the first pixel circuit PXC1).

[0110] In the second sub-pixel SPX2 , the second power line PL2 may be electrically connected to the fourth transistor T4 through the sixth connection pattern CNP6 .

[0111] The sixth connection pattern CNP6 may include a fourth conductive layer CL4. One end of the sixth connection pattern CNP6 may be electrically connected to the second power line PL2 through a corresponding contact hole CH. The other end of the sixth connection pattern CNP6 may be electrically connected to the 4b transistor T4b of the fourth transistor T4 through a corresponding contact hole CH. The sixth connection pattern CNP6 may electrically connect the second power line PL2 to the 4b transistor T4b of the second sub-pixel SPX2 (or the second pixel circuit PXC2).

[0112] In the third sub-pixel SPX3 , the second power line PL2 may be electrically connected to the fourth transistor T4 through the tenth connection pattern CNP10 .

[0113] The tenth connection pattern CNP10 may include a fourth conductive layer CL4. One end of the tenth connection pattern CNP10 may be electrically connected to the second power line PL2 through a corresponding contact hole CH. The other end of the tenth connection pattern CNP10 may be electrically connected to the 4b transistor T4b of the fourth transistor T4 through a corresponding contact hole CH. The tenth connection pattern CNP10 may electrically connect the second power line PL2 and the 4b transistor T4b of the third sub-pixel SPX3 (or the third pixel circuit PXC3).

[0114] The third power line PL3 may receive a second initialization power voltage Vint2. The third power line PL3 may be spaced apart from the third scan line S3i in the second direction DR2. The third power line PL3 may include a second conductive layer CL2. The third power line PL2 may be a common line commonly provided to the first sub-pixel SPX1, the second sub-pixel SPX2, and the third sub-pixel SPX3.

[0115] In the first sub-pixel SPX1 , the third power line PL3 may be electrically connected to the seventh transistor T7 through the fourth connection pattern CNP4 .

[0116] The fourth connection pattern CNP4 may include a fourth conductive layer CL4. One end of the fourth connection pattern CNP4 may be electrically connected to the third power line PL3 through a corresponding contact hole CH. The other end of the fourth connection pattern CNP4 may be electrically connected to the 7b-th transistor T7b of the first sub-pixel SPX1 through a corresponding contact hole CH. The fourth connection pattern CNP4 may electrically connect the third power line PL3 and the 7b-th transistor T7b of the first sub-pixel SPX1 (or the first pixel circuit PXC1).

[0117] In the second sub-pixel SPX2 , the third power line PL3 may be electrically connected to the seventh transistor T7 through the eighth connection pattern CNP8 .

[0118] The eighth connection pattern CNP8 may include a fourth conductive layer CL4. One end of the eighth connection pattern CNP8 may be electrically connected to the third power line PL3 through a corresponding contact hole CH. The other end of the eighth connection pattern CNP8 may be electrically connected to the 7b-th transistor T7b of the second sub-pixel SPX2 through a corresponding contact hole CH. The eighth connection pattern CNP8 may electrically connect the third power line PL3 to the 7b-th transistor T7b of the second sub-pixel SPX2 (or the second pixel circuit PXC2).

[0119] In the third sub-pixel SPX3 , the third power line PL3 may be electrically connected to the seventh transistor T7 through the twelfth connection pattern CNP12 .

[0120] The twelfth connection pattern CNP12 may include a fourth conductive layer CL4. One end of the twelfth connection pattern CNP12 may be electrically connected to the third power line PL3 through a corresponding contact hole CH. The other end of the twelfth connection pattern CNP12 may be electrically connected to the 7b-th transistor T7b of the third sub-pixel SPX3 through a corresponding contact hole CH. The twelfth connection pattern CNP12 may electrically connect the third power line PL3 and the 7b-th transistor T7b of the third sub-pixel SPX3 (or the third pixel circuit PXC3).

[0121] The first pixel circuit PXC1 , the second pixel circuit PXC2 , and the third pixel circuit PXC3 may have substantially similar or identical structures. Hereinafter, the first pixel circuit PXC1 will be mainly described, and the second pixel circuit PXC2 and the third pixel circuit PXC3 will be briefly described.

[0122] The first pixel circuit PXC1 may include a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, and a seventh transistor T7 and a storage capacitor Cst.

[0123] The first transistor T1 may include a first active pattern ACT1 , a first gate electrode GE1 , a first source area SA1 , and a first drain area DA1 .

[0124] The first active pattern ACT1 may be a region of the semiconductor layer SCL overlapping the first gate electrode GE1. The first active pattern ACT1 may constitute a channel region of the first transistor T1 and may be a semiconductor pattern not doped with impurities. The first active pattern ACT1 may have a shape bent at least once.

[0125] The first source area SA1 may be connected to one end of the first active pattern ACT1 and may be a semiconductor pattern doped with impurities. The first source area SA1 may be connected to the second drain area DA2 of the second transistor T2 and the fifth drain area DA5 of the fifth transistor T5.

[0126] The first drain area DA1 may be connected to the other end of the first active pattern ACT1 and may be a semiconductor pattern doped with impurities. The first drain area DA1 may be connected to the 3ath source area SA3a of the 3ath transistor T3a and the sixth source area SA6 of the sixth transistor T6.

[0127] The first gate electrode GE1 may be disposed on the first active pattern ACT1 and may overlap the first active pattern ACT1 in a plan view. The first gate electrode GE1 may have an island-shaped conductive pattern. The first gate electrode GE1 may include a second conductive layer CL2. The first gate electrode GE1 may be electrically connected to the third transistor T3 and the fourth transistor T4 through the first connection pattern CNP1.

[0128] The first connection pattern CNP1 may include a fourth conductive layer CL4. One end of the first connection pattern CNP1 may be electrically connected to the first gate electrode GE1 through a corresponding contact hole CH. The other end of the first connection pattern CNP1 may be electrically connected to a portion of the semiconductor layer SCL shared by the 3b-th transistor T3b and the 4a-th transistor T4a through a corresponding contact hole CH. For example, a portion of the semiconductor layer SCL may include a 3b-th drain area DA3b of the 3b-th transistor T3b and a 4a-th source area SA4a of the 4a-th transistor T4a. In an embodiment, the first connection pattern CNP1 may electrically connect the first gate electrode GE1, the 3b-th drain area DA3b of the 3b-th transistor T3b, and the 4a-th source area SA4a of the 4a-th transistor T4a.

[0129] The first gate electrode GE1 may overlap with the first lower metal pattern BML1. The first lower metal pattern BML1 may shield the first gate electrode GE1 and the first active pattern ACT1 from the lower side. The first lower metal pattern BML1 may include a first conductive layer CL1. The first conductive layer CL1 may include copper (Cu), molybdenum (Mo), tungsten (W), neodymium (Nd), titanium (Ti), aluminum (Al), silver (Ag), and alloys thereof (e.g., aluminum neodymium (AlNd)). The first lower metal pattern BML1 may be provided in an island shape. The first lower metal pattern BML1 may be electrically connected to the first gate electrode GE1 through a corresponding contact hole CH, but is not limited thereto.

[0130] The second transistor T2 may include a second active pattern ACT2 , a second source area SA2 , a second drain area DA2 , and a second gate electrode GE2 .

[0131] The second active pattern ACT2 may be a region of the semiconductor layer SCL overlapping the second gate electrode GE2. The second active pattern ACT2 may constitute a channel region of the second transistor T2 and may be a semiconductor pattern that is not doped with impurities.

[0132] The second source area SA2 may be connected to one end of the second active pattern ACT2 and may be a semiconductor pattern doped with impurities. The second source area SA2 may be electrically connected to the first data line D1 through the corresponding contact hole CH.

[0133] The second drain area DA2 may be connected to the other end of the second active pattern ACT2 and may be a semiconductor pattern doped with impurities. The second drain area DA2 may be connected to the first source area SA1.

[0134] The second gate electrode GE2 may overlap the second active pattern ACT2 in a plan view. The second gate electrode GE2 may be a portion of the first scan line S1i.

[0135] The second gate electrode GE2 may overlap with the second lower metal pattern BML2. The second lower metal pattern BML2 may shield the second gate electrode GE2 and the second active pattern ACT2 from the lower side. The second lower metal pattern BML2 may include a first conductive layer CL1. The second lower metal pattern BML2 may be provided in an island shape. The second lower metal pattern BML2 may be electrically connected to the second gate electrode GE2 (or the first scan line S1i) through a corresponding contact hole CH, but is not limited thereto. The second lower metal pattern BML2 may be disposed to be spaced apart from the first lower metal pattern BML1.

[0136] The third transistor T3 may have a double gate structure in which sub-transistors are connected in series to prevent leakage current. In this case, the third transistor T3 may include a 3a-th transistor T3a and a 3b-th transistor T3b.

[0137] The 3a-th transistor T3a may include a 3a-th active pattern ACT3a, a 3a-th source area SA3a, a 3a-th drain area DA3a, and a 3a-th gate electrode GE3a.

[0138] The 3a-th active pattern ACT3a may be a region of the semiconductor layer SCL overlapping the 3a-th gate electrode GE3a. The 3a-th active pattern ACT3a may constitute a channel region of the 3a-th transistor T3a and may be a semiconductor pattern not doped with impurities.

[0139] The 3a-th source area SA3a may be connected to one end of the 3a-th active pattern ACT3a and may be a semiconductor pattern doped with impurities. The 3a-th source area SA3a may be electrically connected to the first drain area DA1.

[0140] The 3a-th drain area DA3a may be connected to the other end of the 3a-th active pattern ACT3a and may be a semiconductor pattern doped with impurities. The 3a-th drain area DA3a may be connected to the 3b-th source area SA3b of the 3b-th transistor T3b.

[0141] In a plan view, the 3a-th gate electrode GE3a may overlap the 3a-th active pattern ACT3a. The 3a-th gate electrode GE3a may be a portion of the first scan line S1i.

[0142] The 3b-th transistor T3b may include a 3b-th active pattern ACT3b, a 3b-th source area SA3b, a 3b-th drain area DA3b, and a 3b-th gate electrode GE3b.

[0143] The 3b-th active pattern ACT3b may be a region of the semiconductor layer SCL overlapping the 3b-th gate electrode GE3b. The 3b-th active pattern ACT3b may constitute a channel region of the 3b-th transistor T3b and may be a semiconductor pattern not doped with impurities.

[0144] The 3b-th source area SA3b may be connected to one end of the 3b-th active pattern ACT3b and may be a semiconductor pattern doped with impurities. The 3b-th source area SA3b may be electrically connected to the 3a-th drain area DA3a.

[0145] The 3b-th drain area DA3b may be connected to the other end of the 3b-th active pattern ACT3b and may be a semiconductor pattern doped with impurities. The 3b-th drain area DA3b may be connected to the 4a-th source area SA4a of the 4a-th transistor T4a.

[0146] The 3b-th gate electrode GE3b may overlap the 3b-th active pattern ACT3b in a plan view. The 3b-th gate electrode GE3b may be a portion of the first scan line S1i.

[0147] In an embodiment, the 3a gate electrode GE3a and the 3b gate electrode GE3b may overlap with the third lower metal pattern BML3. The third lower metal pattern BML3 may shield the 3a gate electrode GE3a, the 3a active pattern ACT3a, the 3b gate electrode GE3b, and the 3b active pattern ACT3b from the lower side. The third lower metal pattern BML3 may include a first conductive layer CL1. The third lower metal pattern BML3 may be provided in an island shape. The third lower metal pattern BML3 may be electrically connected to the first scan line S1i through a corresponding contact hole CH, but is not limited thereto. The third lower metal pattern BML3 may be spaced apart from the first lower metal pattern BML1 and the second lower metal pattern BML2.

[0148] The fourth transistor T4 may have a dual gate structure in which sub-transistors are connected in series to prevent leakage current. In this case, the fourth transistor T4 may include a 4a-th transistor T4a and a 4b-th transistor T4b.

[0149] The 4a-th transistor T4a may include a 4a-th active pattern ACT4a, a 4a-th source area SA4a, a 4a-th drain area DA4a, and a 4a-th gate electrode GE4a.

[0150] The 4a-th active pattern ACT4a may be a region of the semiconductor layer SCL overlapping the 4a-th gate electrode GE4a. The 4a-th active pattern ACT4a may constitute a channel region of the 4a-th transistor T4a and may be a semiconductor pattern not doped with impurities.

[0151] The 4a-th source area SA4a may be connected to one end of the 4a-th active pattern ACT4a and may be a semiconductor pattern doped with impurities. The 4a-th source area SA4a may be connected to the 3b-th drain area DA3b.

[0152] The 4a-th drain area DA4a may be connected to the other end of the 4a-th active pattern ACT4a and may be a semiconductor pattern doped with impurities. The 4a-th drain area DA4a may be connected to the 4b-th source area SA4b of the 4b-th transistor T4b.

[0153] The 4a-th gate electrode GE4a may overlap the 4a-th active pattern ACT4a. The 4a-th gate electrode GE4a may be a portion of the second scan line S2i.

[0154] The 4b-th transistor T4b may include a 4b-th active pattern ACT4b, a 4b-th source area SA4b, a 4b-th drain area DA4b, and a 4b-th gate electrode GE4b.

[0155] The 4b-th active pattern ACT4b may be a region of the semiconductor layer SCL overlapping the 4b-th gate electrode GE4b. The 4b-th active pattern ACT4b may constitute a channel region of the 4b-th transistor T4b and may be a semiconductor pattern not doped with impurities.

[0156] The 4b-th source area SA4b may be connected to one end of the 4b-th active pattern ACT4b and may be a semiconductor pattern doped with impurities. The 4b-th source area SA4b may be connected to the 4a-th drain area DA4a.

[0157] The 4b-th drain area DA4b may be connected to the other end of the 4b-th active pattern ACT4b and may be a semiconductor pattern doped with impurities. The 4b-th drain area DA4b may be electrically connected to the second connection pattern CNP2 through the corresponding contact hole CH.

[0158] The 4b-th gate electrode GE4b may overlap the 4b-th active pattern ACT4b in a plan view. The 4b-th gate electrode GE4b may be a portion of the second scan line S2i.

[0159] In an embodiment, the 4a gate electrode GE4a and the 4b gate electrode GE4b may overlap with the fourth lower metal pattern BML4. The fourth lower metal pattern BML4 may shield the 4a gate electrode GE4a, the 4a active pattern ACT4a, the 4b gate electrode GE4b, and the 4b active pattern ACT4b from the lower side. The fourth lower metal pattern BML4 may include a first conductive layer CL1. The fourth lower metal pattern BML4 may be provided in an island shape. The fourth lower metal pattern BML4 may be electrically connected to the second scan line S2i through a corresponding contact hole CH, but is not limited thereto. The fourth lower metal pattern BML4 may be spaced apart from the first lower metal pattern BML1, the second lower metal pattern BML2, and the third lower metal pattern BML3.

[0160] The fifth transistor T5 may include a fifth active pattern ACT5 , a fifth source area SA5 , a fifth drain area DA5 , and a fifth gate electrode GE5 .

[0161] The fifth active pattern ACT5 may be a region of the semiconductor layer SCL overlapping the fifth gate electrode GE5. The fifth active pattern ACT5 may constitute a channel region of the fifth transistor T5 and may be a semiconductor pattern that is not doped with impurities.

[0162] The fifth source area SA5 may be connected to one end of the fifth active pattern ACT5 and may be a semiconductor pattern doped with impurities. The fifth source area SA5 may be electrically connected to the first power line PL1 through a corresponding contact hole CH.

[0163] The fifth drain area DA5 may be connected to the other end of the fifth active pattern ACT5 and may be a semiconductor pattern doped with impurities. The fifth drain area DA5 may be connected to the first source area SA1.

[0164] The fifth gate electrode GE5 may overlap the fifth active pattern ACT5 in a plan view. The fifth gate electrode GE5 may be a portion of the emission control line Ei.

[0165] The fifth gate electrode GE5 may overlap with the fifth lower metal pattern BML5. The fifth lower metal pattern BML5 may shield the fifth gate electrode GE5 and the fifth active pattern ACT5 from the lower side. The fifth lower metal pattern BML5 may include a first conductive layer CL1. The fifth lower metal pattern BML5 may be provided in an island shape. The fifth lower metal pattern BML5 may be electrically connected to the fifth gate electrode GE5 (or the emission control line Ei) through a corresponding contact hole CH, but is not limited thereto. The fifth lower metal pattern BML5 may be spaced apart from the first lower metal pattern BML1, the second lower metal pattern BML2, the third lower metal pattern BML3, and the fourth lower metal pattern BML4.

[0166] The sixth transistor T6 may include a sixth active pattern ACT6 , a sixth source area SA6 , a sixth drain area DA6 , and a sixth gate electrode GE6 .

[0167] The sixth active pattern ACT6 may be a region of the semiconductor layer SCL overlapping the sixth gate electrode GE6. The sixth active pattern ACT6 may constitute a channel region of the sixth transistor T6 and may be a semiconductor pattern that is not doped with impurities.

[0168] The sixth source area SA6 may be connected to one end of the sixth active pattern ACT6 and may be a semiconductor pattern doped with impurities. The sixth source area SA6 may be connected to the first drain area DA1.

[0169] The sixth drain area DA6 may be connected to the other end of the sixth active pattern ACT6 and may be a semiconductor pattern doped with impurities. The sixth drain area DA6 may be electrically connected to the third connection pattern CNP3 through the corresponding contact hole CH.

[0170] The third connection pattern CNP3 may include a fourth conductive layer CL4. The third connection pattern CNP3 may be electrically connected to the sixth drain area DA6 through a corresponding contact hole CH. The third connection pattern CNP3 may be electrically connected to the first pixel electrode PE1 through a first contact portion CNT1. The third connection pattern CNP3 may electrically connect the first pixel electrode PE1 and the sixth transistor T6.

[0171] The sixth gate electrode GE6 may overlap the sixth active pattern ACT6. The sixth gate electrode GE6 may be a portion of the emission control line Ei.

[0172] The sixth gate electrode GE6 may overlap with the sixth lower metal pattern BML6. The sixth lower metal pattern BML6 may shield the sixth gate electrode GE6 and the sixth active pattern ACT6 from the lower side. The sixth lower metal pattern BML6 may include a first conductive layer CL1. The sixth lower metal pattern BML6 may be provided in an island shape. The sixth lower metal pattern BML6 may be electrically connected to the sixth gate electrode GE6 (or the emission control line Ei) through a corresponding contact hole CH, but is not limited thereto. The sixth lower metal pattern BML6 may be spaced apart from the first lower metal pattern BML1, the second lower metal pattern BML2, the third lower metal pattern BML3, the fourth lower metal pattern BML4, and the fifth lower metal pattern BML5.

[0173] The seventh transistor T7 may have a double gate structure in which sub-transistors are connected in series to prevent leakage current. In this case, the seventh transistor T7 may include a 7a-th transistor T7a and a 7b-th transistor T7b.

[0174] The 7a-th transistor T7a may include a 7a-th active pattern ACT7a, a 7a-th source area SA7a, a 7a-th drain area DA7a, and a 7a-th gate electrode GE7a.

[0175] The 7a-th active pattern ACT7a may be a region of the semiconductor layer SCL overlapped with the 7a-th gate electrode GE7a. The 7a-th active pattern ACT7a may constitute a channel region of the 7a-th transistor T7a and may be a semiconductor pattern not doped with impurities.

[0176] The 7a-th source area SA7a may be connected to one end of the 7a-th active pattern ACT7a and may be a semiconductor pattern doped with impurities. The 7a-th source area SA7a may be connected to the sixth drain area DA6.

[0177] The 7a-th drain area DA7a may be connected to the other end of the 7a-th active pattern ACT7a and may be a semiconductor pattern doped with impurities. The 7a-th drain area DA7a may be connected to the 7b-th source area SA7b of the 7b-th transistor T7b.

[0178] The 7a-th gate electrode GE7a may overlap the 7a-th active pattern ACT7a. The 7a-th gate electrode GE7a may be a portion of the third scan line S3i.

[0179] The 7b-th transistor T7b may include a 7b-th active pattern ACT7b, a 7b-th source area SA7b, a 7b-th drain area DA7b, and a 7b-th gate electrode GE7b.

[0180] The 7b-th active pattern ACT7b may be a region of the semiconductor layer SCL overlapping the 7b-th gate electrode GE7b. The 7b-th active pattern ACT7b may constitute a channel region of the 7b-th transistor T7b and may be a semiconductor pattern that is not doped with impurities.

[0181] The 7b-th source area SA7b may be connected to one end of the 7b-th active pattern ACT7b and may be a semiconductor pattern doped with impurities. The 7b-th source area SA7b may be electrically connected to the 7a-th drain area DA7a.

[0182] The 7b-th drain area DA7b may be connected to the other end of the 7b-th active pattern ACT7b and may be a semiconductor pattern doped with impurities. The 7b-th drain area DA7b may be electrically connected to the fourth connection pattern CNP4 through the corresponding contact hole CH.

[0183] The 7b-th gate electrode GE7b may overlap the 7b-th active pattern ACT7b. The 7b-th gate electrode GE7b may be a portion of the third scan line S3i.

[0184] In an embodiment, the 7a gate electrode GE7a and the 7b gate electrode GE7b may overlap with the seventh lower metal pattern BML7. The seventh lower metal pattern BML7 may shield the 7a gate electrode GE7a, the 7a active pattern ACT7a, the 7b gate electrode GE7b, and the 7b active pattern ACT7b from the lower side. The seventh lower metal pattern BML7 may include a first conductive layer CL1. The seventh lower metal pattern BML7 may be provided in an island shape. The seventh lower metal pattern BML7 may be electrically connected to the third scan line S3i through a corresponding contact hole CH, but is not limited thereto. The seventh lower metal pattern BML7 may be disposed to be spaced apart from the first lower metal pattern BML1, the second lower metal pattern BML2, the third lower metal pattern BML3, the fourth lower metal pattern BML4, the fifth lower metal pattern BML5, and the sixth lower metal pattern BML6.

[0185] The storage capacitor Cst may include a first lower electrode LE1 and a first upper electrode UE1. The first lower electrode LE1 may be integrally formed with the first gate electrode GE1 of the first transistor T1. In this case, the first lower electrode LE1 may be the first gate electrode GE1.

[0186] The first upper electrode UE1 may overlap with the first lower electrode LE1 in a plan view. The capacitance of the storage capacitor Cst may be increased by increasing the overlapping area between the first upper electrode UE1 and the first lower electrode LE1. The first upper electrode UE1 may extend in the first direction DR1. The first upper electrode UE1 may include a third conductive layer CL3. The third conductive layer CL3 may include the same material as the above-mentioned second conductive layer CL2, or may include one or more suitable (or selected) materials from the materials exemplified as the constituent materials of the second conductive layer CL2, but is not limited thereto. The first upper electrode UE1 may be electrically connected to the first power line PL1 through the corresponding contact hole CH. The first upper electrode UE1 may have an opening in a region in which a contact hole CH connecting the first gate electrode GE1 and the first connection pattern CNP1 is formed.

[0187] The first pixel circuit PXC1 may further include an additional capacitor Cad. The additional capacitor Cad may include a second lower electrode LE2 and a second upper electrode UE2.

[0188] The second lower electrode LE2 may include a third conductive layer CL3 and may be provided in an island shape. The second lower electrode LE2 may be connected to the 4a-th drain area DA4a and the 4b-th source area SA4b through corresponding contact holes CH.

[0189] The second upper electrode UE2 may overlap the second lower electrode LE2 in a plan view. The second upper electrode UE2 may be formed integrally with the first power line PL1. In this case, the second upper electrode UE2 may be a part of the first power line PL1.

[0190] The second pixel circuit PXC2 may include a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, and a seventh transistor T7, and a storage capacitor Cst.

[0191] The gate electrode of the first transistor T1 may be electrically connected to the third transistor T3 and the fourth transistor T4 through the fifth connection pattern CNP5 .

[0192] The fifth connection pattern CNP5 may include a fourth conductive layer CL4. One end of the fifth connection pattern CNP5 may be electrically connected to the gate electrode of the first transistor T1 through a corresponding contact hole CH. The other end of the fifth connection pattern CNP5 may be electrically connected to a portion of the semiconductor layer SCL shared by the 3b-th transistor T3b and the 4a-th transistor T4a through a corresponding contact hole CH.

[0193] The sixth transistor T6 may be electrically connected to the seventh connection pattern CNP7 through the corresponding contact hole CH.

[0194] The seventh connection pattern CNP7 may include a fourth conductive layer CL4. The seventh connection pattern CNP7 may be electrically connected to the drain region of the sixth transistor T6 through the corresponding contact hole CH. The seventh connection pattern CNP7 may be electrically connected to the second pixel electrode PE2 through the second contact portion CNT2. The seventh connection pattern CNP7 may electrically connect the second pixel electrode PE2 and the sixth transistor T6.

[0195] The third pixel circuit PXC3 may include a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, and a seventh transistor T7, and a storage capacitor Cst.

[0196] The gate electrode of the first transistor T1 may be electrically connected to the third transistor T3 and the fourth transistor T4 through a ninth connection pattern CNP9 .

[0197] The ninth connection pattern CNP9 may include a fourth conductive layer CL4. One end of the ninth connection pattern CNP9 may be electrically connected to the gate electrode of the first transistor T1 through a corresponding contact hole CH. The other end of the ninth connection pattern CNP9 may be electrically connected to a portion of the semiconductor layer SCL shared by the 3b-th transistor T3b and the 4a-th transistor T4a through a corresponding contact hole CH.

[0198] The sixth transistor T6 may be electrically connected to the eleventh connection pattern CNP11 through the corresponding contact hole CH.

[0199] The eleventh connection pattern CNP11 may include a fourth conductive layer CL4. The eleventh connection pattern CNP11 may be electrically connected to the drain region of the sixth transistor T6 through the corresponding contact hole CH. The eleventh connection pattern CNP11 may be electrically connected to the third pixel electrode PE3 through the third contact portion CNT3. The eleventh connection pattern CNP11 may electrically connect the third pixel electrode PE3 and the sixth transistor T6.

[0200] Each of the first pixel circuit PXC1, the second pixel circuit PXC2, and the third pixel circuit PXC3 may be electrically connected to the pixel electrode PE through a corresponding contact portion CNT. For example, the first pixel circuit PXC1 may be electrically connected to the first pixel electrode PE1 through the first contact portion CNT1, the second pixel circuit PXC2 may be electrically connected to the second pixel electrode PE2 through the second contact portion CNT2, and the third pixel circuit PXC3 may be electrically connected to the third pixel electrode PE3 through the third contact portion CNT3.

[0201] The first pixel electrode PE1 , the second pixel electrode PE2 , and the third pixel electrode PE3 may include a fifth conductive layer CL5 .

[0202] The first pixel electrode PE1 may correspond to the anode electrode of the light emitting element LD provided in the first sub-pixel SPX1, and may overlap with a portion of the first pixel circuit PXC1. The second pixel electrode PE2 may correspond to the anode electrode of the light emitting element LD provided in the second sub-pixel SPX2, and may overlap with a portion of the second pixel circuit PXC2. The third pixel electrode PE3 may correspond to the anode electrode of the light emitting element LD provided in the third sub-pixel SPX3, and may overlap with a portion of the third pixel circuit PXC3.

[0203] The pixel region PXA may include a dummy region DMA. For example, the dummy region DMA may be disposed between a region of the pixel region PXA where the second pixel circuit PXC2 is disposed and a region of the pixel region PXA where the third pixel circuit PXC3 is disposed, but is not limited thereto.

[0204] The dummy lines DML and the dummy patterns DMP may be disposed in the dummy area DMA.

[0205] The dummy line DML may extend in the second direction DR2 and may be disposed between the second data line D2 and the third data line D3. The dummy line DML may be spaced apart from each of the second data line D2 and the third data line D3. A plurality of dummy lines DML may be provided in the display area DA. The dummy line DML may be electrically connected to a fourth power line (refer to Figure 4 The fourth power line PL4 in FIG. 1 ). Therefore, the second power voltage VSS may be applied to the dummy line DML. The dummy line DML may include a fourth conductive layer CL4. For example, the dummy line DML may be formed of a three-layer conductive pattern.

[0206] The dummy pattern DMP may be disposed in a region of the dummy line DML. The dummy pattern DMP may include a first dummy pattern DMP1 and a second dummy pattern DMP2. The first dummy pattern DMP1 may be formed integrally with the dummy line DML. In this case, the first dummy pattern DMP1 may be formed by a conductive pattern of three layers in which a first layer, a second layer, and a third layer including a conductive material are sequentially stacked. In an embodiment, the first dummy pattern DMP1 may have a width greater than that of the dummy line DML in the first direction DR1. For example, the dummy line DML may have a first width W1 of approximately 3 μm in the first direction DR1, and the first dummy pattern DMP1 may have a second width W2 of approximately 9.5 μm in the first direction DR1, but is not limited thereto.

[0207] The second dummy pattern DMP2 may overlap the first dummy pattern DMP1. The second dummy pattern DMP2 may include a material different from that of the first dummy pattern DMP1. For example, the second dummy pattern DMP2 may include an organic pattern including an organic material. The second dummy pattern DMP2 may have a width in the first direction DR1 that is the same as or similar to that of the first dummy pattern DMP1, but is not limited thereto. According to an embodiment, the second dummy pattern DMP2 may have a width in the first direction DR1 that is greater than or less than that of the first dummy pattern DMP1.

[0208] The dummy pattern DMP including the first dummy pattern DMP1 and the second dummy pattern DMP2 may be exposed to the outside through the via hole VIH. The dummy pattern DMP may be electrically connected to the common electrode (refer to Fig. 9 and Fig.10 The common electrode CE in the pixel PXL is used to prevent a voltage drop that may occur at the common electrode CE, thereby improving the reliability of each pixel PXL.

[0209] Will refer to later Figures 10 to 17 A detailed description of the aforementioned dummy pattern DMP is described.

[0210] In the following, reference will be made to Fig. 9The stacked structure (or cross-sectional structure) of the above-mentioned pixel PXL is mainly described.

[0211] Fig. 9 It is along Figure 6 Schematic cross-sectional view taken along line II'.

[0212] To avoid Fig. 9 The repeated description of the embodiment will mainly describe the differences from the above-mentioned embodiment.

[0213] Reference Figures 1 to 9 , the pixel PXL may include a first sub-pixel SPX1 , a second sub-pixel SPX2 , and a third sub-pixel SPX3 that are adjacent to each other.

[0214] Each of the first sub-pixel SPX1 , the second sub-pixel SPX2 , and the third sub-pixel SPX3 may include a substrate SUB, a pixel circuit layer PCL, a display element layer DPL, and an encapsulation layer TFE.

[0215] The substrate SUB may include a transparent insulating material and transmit light. The substrate SUB may be a rigid substrate or a flexible substrate.

[0216] The first pixel circuit PXC1, the second pixel circuit PXC2, and the third pixel circuit PXC3 and the signal line may be provided in the pixel circuit layer PCL. The light emitting element (refer to Figure 4 The light emitting element LD) may be provided in the display element layer DPL.

[0217] At least one insulating layer may be disposed on the substrate SUB. For example, a first insulating layer INS1, a second insulating layer INS2, a third insulating layer INS3, a fourth insulating layer INS4, a fifth insulating layer INS5, and a via layer VIA sequentially stacked in the third direction DR3 may be disposed on the substrate SUB. In addition, at least one conductive layer may be disposed on the substrate SUB. For example, the conductive layer may include a first conductive layer CL1, a second conductive layer CL2, a third conductive layer CL3, a fourth conductive layer CL4, and a fifth conductive layer CL5. The first conductive layer CL1 may be disposed between the substrate SUB and the first insulating layer INS1, the second conductive layer CL2 may be disposed on the second insulating layer INS2, the third conductive layer CL3 may be disposed on the third insulating layer INS3, the fourth conductive layer CL4 may be disposed on the fourth insulating layer INS4, and the fifth conductive layer CL5 may be disposed on the via layer VIA.

[0218] The first conductive layer CL1 may include a first lower metal pattern BML1, a second lower metal pattern BML2, a third lower metal pattern BML3, a fourth lower metal pattern BML4, a fifth lower metal pattern BML5, a sixth lower metal pattern BML6, and a seventh lower metal pattern BML7. The second conductive layer CL2 may include a second power line PL2, a first scan line S1i, a second scan line S2i, a third scan line S3i, an emission control line Ei, a third power line PL3, a first gate electrode GE1, a first lower electrode LE1, and an additional conductive pattern ACP. The third conductive layer CL3 may include a first upper electrode UE1 and a second lower electrode LE2. The fourth conductive layer CL4 may include first to twelfth connection patterns CNP1 to CNP12, first to third data lines D1, D2, and D3, a first power line PL1, a second upper electrode UE2, a dummy line DML, and a first dummy pattern DMP1. The fifth conductive layer CL5 may include a first pixel electrode PE1, a second pixel electrode PE2, and a third pixel electrode (refer to Figure 6 The third pixel electrode PE3 in the image).

[0219] In an embodiment, the fourth conductive layer CL4 may be formed of three layers including a conductive material. For example, each of the third connection pattern CNP3 and the seventh connection pattern CNP7 formed by the fourth conductive layer CL4 may include a first metal layer ML1, a second metal layer ML2, and a third metal layer ML3 sequentially stacked. The first metal layer ML1 and the third metal layer ML3 may include the same conductive material, and the second metal layer ML2 may include a conductive material having material properties different from those of the first metal layer ML1 and the third metal layer ML3. For example, each of the first metal layer ML1 and the third metal layer ML3 may include titanium, and the second metal layer ML2 may include aluminum. The first metal layer ML1 may be disposed on the fourth insulating layer INS4, the second metal layer ML2 may be disposed on the first metal layer ML1, and the third metal layer ML3 may be disposed on the second metal layer ML2.

[0220] The first metal layer ML1 of each of the third connection pattern CNP3 and the seventh connection pattern CNP7 may be electrically connected to the sixth drain area DA6 of the sixth transistor T6 through a contact hole CH formed through the second insulating layer INS2, the third insulating layer INS3, and the fourth insulating layer INS4. The third metal layer ML3 of the third connection pattern CNP3 may be electrically connected to the first pixel electrode PE1 through the first contact portion CNT1 of the via layer VIA, and the third metal layer ML3 of the seventh connection pattern CNP7 may be electrically connected to the second pixel electrode PE2 through the second contact portion CNT2 of the via layer VIA.

[0221] In an embodiment, the second metal layer ML2 may be disposed between the first metal layer ML1 and the third metal layer ML3, and may have a side surface recessed from a side surface of each of the first metal layer ML1 and the third metal layer ML3. In this case, each of the first metal layer ML1 and the third metal layer ML3 may protrude from a side surface of the second metal layer ML2. When viewed in a cross section, the width of the second metal layer ML2 may be smaller than the width of the first metal layer ML1 and the width of the third metal layer ML3.

[0222] The pixel circuit layer PCL may be disposed on the substrate SUB. The first insulating layer INS1, the second insulating layer INS2, the third insulating layer INS3, the fourth insulating layer INS4, and the fifth insulating layer INS5 may be disposed in the pixel circuit layer PCL.

[0223] The first insulating layer INS1 (or buffer layer) may be completely disposed on the substrate SUB. The first insulating layer INS1 may prevent impurities from diffusing into the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 included in the first pixel circuit PXC1, the second pixel circuit PXC2, and the third pixel circuit PXC3. The first insulating layer INS1 may be an inorganic insulating layer including an inorganic material. For example, the first insulating layer INS1 may include silicon nitride (SiN x ), silicon oxide (SiO x ) and silicon oxynitride (SiO x N y ) or may include at least one of aluminum oxide (Al x O y ). The first insulating layer INS1 may be provided as a single layer, but may also be provided as a multilayer of at least two layers. In the case where the first insulating layer INS1 is provided as a multilayer, each layer may be formed of the same material or a different material. Depending on the material of the substrate SUB and process conditions, the first insulating layer INS1 may be omitted.

[0224] The second insulating layer INS2 (or the first gate insulating layer) may be completely disposed on the first insulating layer INS1. The second insulating layer INS2 may include the same material as the above-mentioned first insulating layer INS1, or may include a suitable (or selected) material from the materials exemplified as the constituent materials of the first insulating layer INS1. For example, the second insulating layer INS2 may include an inorganic insulating layer including an inorganic material. According to an embodiment, the second insulating layer INS2 may be partially disposed on the first insulating layer INS1. For example, the second insulating layer INS2 may be etched together with the base material of the second conductive layer CL2 during the manufacturing process of the second conductive layer CL2, so that the second insulating layer INS2 is disposed only below the second conductive layer CL2. In this case, the second insulating layer INS2 may have the same width as the second conductive layer CL2 disposed on the second insulating layer INS2, but is not limited thereto.

[0225] The third insulating layer INS3 (or the second gate insulating layer) may be completely provided and / or formed on the second insulating layer INS2. The third insulating layer INS3 may include the same material as the first insulating layer INS1, or may include one or more suitable (or selected) materials from the materials exemplified as the constituent materials of the first insulating layer INS1. For example, the third insulating layer INS3 may be an inorganic insulating layer including an inorganic material.

[0226] The fourth insulating layer INS4 (or interlayer insulating layer) may be entirely provided and / or formed on the third insulating layer INS3. The fourth insulating layer INS4 may include the same material as that of the first insulating layer INS1, or may include one or more suitable (or selected) materials from among the materials exemplified as constituent materials of the first insulating layer INS1.

[0227] The fifth insulating layer INS5 (or passivation layer) may be completely provided and / or formed on the fourth insulating layer INS4. The fifth insulating layer INS5 may be an inorganic insulating layer including an inorganic material. The fifth insulating layer INS5 may include an opening corresponding to each of the contact portions CNT of the via layer VIA to expose a portion of the fourth conductive layer CL4 disposed below the fifth insulating layer INS5.

[0228] The via layer VIA may be completely provided and / or formed on the fifth insulating layer INS5. The via layer VIA may be formed of a single layer or a multilayer including an organic layer. According to an embodiment, the via layer VIA may be provided in the form of an inorganic layer and an organic layer disposed on the inorganic layer. In the case where the via layer VIA is a multilayer including an organic layer, the inorganic layer may be provided as the uppermost layer. The via layer VIA may include at least one selected from the group consisting of a polyacrylate resin, an epoxy resin, a phenolic resin, a polyamide resin, a polyimide resin, an unsaturated polyester resin, a polyphenylene ether resin, a polyphenylene sulfide resin, and a benzocyclobutene resin.

[0229] In an embodiment, the via layer VIA may include a contact portion CNT exposing some circuit elements disposed in the pixel circuit layer PCL. For example, the via layer VIA may include a first contact portion CNT1, a second contact portion CNT2, and a third contact portion CNT3. The first contact portion CNT1 may expose a region of the third connection pattern CNP3, the second contact portion CNT2 may expose a region of the seventh connection pattern CNP7, and the third contact portion CNT3 may expose a region of the eleventh connection pattern CNP11. In an embodiment, the via layer VIA may include a via VIH exposing a dummy pattern DMP.

[0230] The pixel circuit layer PCL of each of the first to third subpixels SPX1 , SPX2 , and SPX3 may include first to seventh transistors T1 to T7 , a storage capacitor Cst, and an additional capacitor Cad disposed on the first insulating layer INS1 .

[0231] The first transistor T1 may include a first active pattern ACT1, a first source area SA1, and a first drain area DA1 disposed on the first insulating layer INS1, and may include a first gate electrode GE1 disposed on the second insulating layer INS2. The first lower metal pattern BML1 may be disposed under the first gate electrode GE1 and the first active pattern ACT1, with the first insulating layer INS1 interposed therebetween.

[0232] The second transistor T2 may include a second active pattern ACT2, a second source area SA2, and a second drain area DA2 disposed on the first insulating layer INS1, and may include a second gate electrode GE2 disposed on the second insulating layer INS2. The second lower metal pattern BML2 may be disposed below the second gate electrode GE2 (or the first scan line S1i) and the second active pattern ACT2, and the first insulating layer INS1 is interposed between the second lower metal pattern BML2 and the second gate electrode GE2 (or the first scan line S1i) and the second active pattern ACT2.

[0233] The 3a transistor T3a may include a 3a active pattern ACT3a, a 3a source area SA3a, and a 3a drain area DA3a disposed on the first insulating layer INS1, and may include a 3a gate electrode GE3a disposed on the second insulating layer INS2. The 3b transistor T3b may include a 3b active pattern ACT3b, a 3b source area SA3b, and a 3b drain area DA3b disposed on the first insulating layer INS1, and may include a 3b gate electrode GE3b disposed on the second insulating layer INS2. The third lower metal pattern BML3 may be disposed under the 3a gate electrode GE3a and the 3b gate electrode GE3b (or the first scan line S1i) and the 3a active pattern ACT3a and the 3b active pattern ACT3b, and the first insulating layer INS1 is interposed between the third lower metal pattern BML3 and the 3a gate electrode GE3a and the 3b gate electrode GE3b (or the first scan line S1i) and the 3a active pattern ACT3a and the 3b active pattern ACT3b.

[0234] The 4a-th transistor T4a may include a 4a-th active pattern ACT3a, a 4a-th source area SA4a, and a 4a-th drain area DA4a disposed on the first insulating layer INS1, and may include a 4a-th gate electrode GE4a disposed on the second insulating layer INS2. The 4b-th transistor T4b may include a 4b-th active pattern ACT4b, a 4b-th source area SA4b, and a 4b-th drain area DA4b disposed on the first insulating layer INS1, and may include a 4b-th gate electrode GE4b disposed on the second insulating layer INS2. The fourth lower metal pattern BML4 can be set below the 4a gate electrode GE4a and the 4b gate electrode GE4b (or the second scan line S2i) and the 4a active pattern ACT4a and the 4b active pattern ACT4b, and the first insulating layer INS1 is interposed between the fourth lower metal pattern BML4 and the 4a gate electrode GE4a and the 4b gate electrode GE4b (or the second scan line S2i) and the 4a active pattern ACT4a and the 4b active pattern ACT4b.

[0235] The fifth transistor T5 may include a fifth active pattern ACT5, a fifth source area SA5, and a fifth drain area DA5 disposed on the first insulating layer INS1, and may include a fifth gate electrode GE5 disposed on the second insulating layer INS2. The fifth lower metal pattern BML5 may be disposed under the fifth gate electrode GE5 (or the emission control line Ei) and the fifth active pattern ACT5, and the first insulating layer INS1 is interposed between the fifth lower metal pattern BML5 and the fifth gate electrode GE5 (or the emission control line Ei) and the fifth active pattern ACT5.

[0236] The sixth transistor T6 may include a sixth active pattern ACT6, a sixth source area SA6, and a sixth drain area DA6 disposed on the first insulating layer INS1, and may include a sixth gate electrode GE6 disposed on the second insulating layer INS2. The sixth lower metal pattern BML6 may be disposed below the sixth gate electrode GE6 (or the emission control line Ei) and the sixth active pattern ACT6, and the first insulating layer INS1 is interposed between the sixth lower metal pattern BML6 and the sixth gate electrode GE6 (or the emission control line Ei) and the sixth active pattern ACT6. In the first sub-pixel SPX1, the sixth drain area DA6 may be electrically connected to the third connection pattern CNP3 through a contact hole CH formed through the second insulating layer INS2, the third insulating layer INS3, and the fourth insulating layer INS4. In the second sub-pixel SPX2, the sixth drain area DA6 may be electrically connected to the seventh connection pattern CNP7 through a contact hole CH formed through the second insulating layer INS2, the third insulating layer INS3, and the fourth insulating layer INS4.

[0237] The 7a-th transistor T7a may include a 7a-th active pattern ACT7a, a 7a-th source area SA7a, and a 7a-th drain area DA7a disposed on the first insulating layer INS1, and may include a 7a-th gate electrode GE7a disposed on the second insulating layer INS2. The 7b-th transistor T7b may include a 7b-th active pattern ACT7b, a 7b-th source area SA7b, and a 7b-th drain area DA7b disposed on the first insulating layer INS1, and may include a 7b-th gate electrode GE7b disposed on the second insulating layer INS2. The seventh lower metal pattern BML7 can be set under the 7a gate electrode GE7a and the 7b gate electrode GE7b (or the third scan line S3i) and the 7a active pattern ACT7a and the 7b active pattern ACT7b, and the first insulating layer INS1 is interposed between the seventh lower metal pattern BML7 and the 7a gate electrode GE7a and the 7b gate electrode GE7b (or the third scan line S3i) and the 7a active pattern ACT7a and the 7b active pattern ACT7b.

[0238] The storage capacitor Cst may include a first lower electrode LE1 disposed on the second insulating layer INS2 , and may include a first upper electrode UE1 disposed on the third insulating layer INS3 and overlapping the first lower electrode LE1 in a plan view.

[0239] The additional capacitor Cad may include a second lower electrode LE2 disposed on the third insulating layer INS3 , and may include a second upper electrode UE2 disposed on the fourth insulating layer INS4 and overlapping the second lower electrode LE2 in a plan view.

[0240] The display element layer DPL may be disposed on the pixel circuit layer PCL. The display element layer DPL may include a light emitting element LD and a pixel defining layer PDL. For example, the light emitting element LD may include a first light emitting element LD1 electrically connected to the first pixel circuit PXC1, a second light emitting element LD2 electrically connected to the second pixel circuit PXC2, and a third light emitting element electrically connected to the third pixel circuit PXC3. The first light emitting element LD1 may be disposed in the display element layer DPL of the first sub-pixel SPX1, the second light emitting element LD2 may be disposed in the display element layer DPL of the second sub-pixel SPX2, and the third light emitting element may be disposed in the display element layer DPL of the third sub-pixel SPX3.

[0241] The first light emitting element LD1 may include a first pixel electrode PE1 (anode electrode or first electrode), a first light emitting layer EML1 and a common electrode CE (cathode electrode or second electrode). The second light emitting element LD2 may include a second pixel electrode PE2 (anode electrode or first electrode), a second light emitting layer EML2 and a common electrode CE (cathode electrode or second electrode). The third light emitting element may include a third pixel electrode PE3 (anode electrode or first electrode), a third light emitting layer (refer to Figure 3 A third light emitting layer EML3) and a common electrode CE (cathode electrode or second electrode).

[0242] The first pixel electrode PE1 may be electrically connected to the third connection pattern CNP3 through the first contact portion CNT1. The second pixel electrode PE2 may be electrically connected to the seventh connection pattern CNP7 through the second contact portion CNT2.

[0243] Each of the first pixel electrode PE1, the second pixel electrode PE2 and the third pixel electrode PE3 may be made of a conductive material (or conductive substance). The conductive material may include an opaque metal. For example, the opaque metal may include metals such as silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), titanium (Ti) and their alloys. However, the material of each of the first pixel electrode PE1, the second pixel electrode PE2 and the third pixel electrode PE3 is not limited to the above-mentioned embodiment. According to an embodiment, the first pixel electrode PE1, the second pixel electrode PE2 and the third pixel electrode PE3 may include a transparent conductive material (or a transparent conductive substance). The transparent conductive material (or a transparent conductive substance) may include conductive oxides such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium gallium zinc oxide (IGZO) and indium tin zinc oxide (ITZO) and conductive polymers such as poly (3,4-ethylenedioxythiophene) (PEDOT). In the case where the first pixel electrode PE1, the second pixel electrode PE2, and the third pixel electrode PE3 include a transparent conductive material (or a transparent conductive substance), a separate conductive layer made of an opaque metal may be added to reflect light emitted from the first light emitting layer EML1, the second light emitting layer EML2, and the third light emitting layer EML3 in the image display direction of the display device DD (or the upper direction of the encapsulation layer TFE). For example, each of the first pixel electrode PE1, the second pixel electrode PE2, and the third pixel electrode PE3 may be formed of three layers made of ITO / Ti / ITO.

[0244] The first pixel electrode PE1 may be disposed at least in the first emission area EMA1, the second pixel electrode PE2 may be disposed at least in the second emission area EMA2, and the third pixel electrode PE3 may be disposed at least in the third emission area (refer to Figure 3 In the third emission area EMA3).

[0245] The pixel defining layer PDL may be provided on the pixel circuit layer PCL in the non-emission area NEA, and may define (or divide) the first emission area EMA1, the second emission area EMA2, and the third emission area EMA3. The pixel defining layer PDL may include an organic insulating layer formed of an organic material. The organic material may include acrylic resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, and the like. According to an embodiment, the pixel defining layer PDL may include a light absorbing material or may be coated with a light absorbing material to absorb light introduced from the outside. For example, the pixel defining layer PDL may include a carbon-based black pigment, but is not limited thereto.

[0246] The pixel defining layer PDL may include an opening exposing an area of ​​each of the first pixel electrode PE1, the second pixel electrode PE2, and the third pixel electrode PE3, and may protrude from the via layer VIA in the third direction DR3 along the periphery of each of the first emission area EMA1, the second emission area EMA2, and the third emission area EMA3.

[0247] The first light-emitting layer EML1 may be disposed on the first pixel electrode PE1 exposed by one opening of the pixel defining layer PDL, the second light-emitting layer EML2 may be disposed on the second pixel electrode PE2 exposed by another opening of the pixel defining layer PDL, and the third light-emitting layer EML3 may be disposed on the third pixel electrode PE3 exposed by other openings of the pixel defining layer PDL.

[0248] The first light emitting layer EML1 may be disposed on the first pixel electrode PE1 only in one opening of the pixel defining layer PDL, the second light emitting layer EML2 may be disposed on the second pixel electrode PE2 only in another opening of the pixel defining layer PDL, and the third light emitting layer EML3 may be disposed on the third pixel electrode PE3 only in the other opening of the pixel defining layer PDL. Each of the first light emitting layer EML1, the second light emitting layer EML2, and the third light emitting layer EML3 may be disposed in a target region of a corresponding sub-pixel (e.g., on a pixel electrode exposed by an opening of the pixel defining layer PDL) by an inkjet printing method or the like, but is not limited thereto.

[0249] Each of the first light-emitting layer EML1, the second light-emitting layer EML2, and the third light-emitting layer EML3 may include a light-generating layer that generates light. For example, the first light-emitting layer EML1 may include a light-generating layer that generates and emits red light, the second light-emitting layer EML2 may include a light-generating layer that generates and emits green light, and the third light-emitting layer EML3 may include a light-generating layer that generates and emits blue light, but is not limited thereto. According to an embodiment, each of the first light-emitting layer EML1, the second light-emitting layer EML2, and the third light-emitting layer EML3 may include a light-generating layer that generates and emits white light or blue light, and in this case, a color conversion layer for converting white light or blue light (e.g., first color light) into a specific color light (e.g., second color light) may be provided.

[0250] The control layer COL and the common electrode CE may be disposed on the first and second light emitting layers EML1 and EML2 and the pixel defining layer PDL.

[0251] The control layer COL may be disposed between each of the first pixel electrode PE1 and the second pixel electrode PE2 and the common electrode CE. The control layer COL may be disposed above and / or below each of the first light emitting layer EML1 and the second light emitting layer EML2. The control layer COL may improve the light emitting efficiency and life of the first light emitting element LD1 and the second light emitting element LD2 by controlling the movement of charges. The control layer COL may include at least one of a hole transport material, a hole injection material, an electron transport material, and an electron injection material. Fig. 9 , the control layer COL is shown as being disposed between each of the first light-emitting layer EML1 and the second light-emitting layer EML2 and the common electrode CE, but is not limited thereto. According to an embodiment, the control layer COL may also be disposed between the first light-emitting layer EML1 and the first pixel electrode PE1 and between the second light-emitting layer EML2 and the second pixel electrode PE2. The control layer COL may be provided as a plurality of layers stacked in the third direction DR3, with the first light-emitting layer EML1 and the second light-emitting layer EML2 interposed between the plurality of layers. The control layer COL may be provided in common to the first sub-pixel SPX1, the second sub-pixel SPX2, and the third sub-pixel SPX3.

[0252] The common electrode CE may be disposed on the first light emitting layer EML1 and the second light emitting layer EML2. The common electrode CE may be provided in common to the first sub-pixel SPX1, the second sub-pixel SPX2, and the third sub-pixel SPX3. The common electrode CE may be provided in a plate shape throughout the entire area of ​​the display area DA (e.g., provided in the entire area of ​​the display area DA), but is not limited thereto. The common electrode CE may be a thin metal layer having a thickness sufficient to transmit light emitted from the first light emitting layer EML1 and the second light emitting layer EML2. The common electrode CE may be formed of a metal material or a transparent conductive material to have a relatively thin thickness. For example, the common electrode CE may include at least one of various transparent conductive materials including indium tin oxide, indium zinc oxide, indium tin zinc oxide, aluminum zinc oxide, gallium zinc oxide, zinc tin oxide, or gallium tin oxide, and the common electrode CE may be implemented as substantially transparent or translucent to meet a predetermined transmittance. Therefore, light emitted from each of the first light emitting layer EML1 and the second light emitting layer EML2 disposed below the common electrode CE may pass through the common electrode CE and be emitted in the upper direction of the encapsulation layer TFE.

[0253] Although not directly shown in the drawings, the common electrode CE may be electrically connected to a fourth power line (refer to Figure 4 Therefore, the common electrode CE may receive the same voltage as that of the dummy line DML and the dummy pattern DMP, for example, the second power supply voltage VSS (or a low potential voltage).

[0254] The encapsulation layer TFE may include a first encapsulation layer ENC1, a second encapsulation layer ENC2, and a third encapsulation layer ENC3 sequentially disposed on the common electrode CE. The first encapsulation layer ENC1 may be formed on the display element layer DPL (or the common electrode CE), and may be disposed over at least a portion of the display area DA and the non-display area NDA. The second encapsulation layer ENC2 may be formed on the first encapsulation layer ENC1, and may be disposed over at least a portion of the display area DA and the non-display area NDA. The third encapsulation layer ENC3 may be formed on the second encapsulation layer ENC2, and may be disposed over at least a portion of the display area DA and the non-display area NDA. According to an embodiment, the third encapsulation layer ENC3 may be disposed over the entire display area DA and the non-display area NDA.

[0255] Each of the first encapsulation layer ENC1 and the third encapsulation layer ENC3 may be formed of an inorganic layer including an inorganic material, and the second encapsulation layer ENC2 may be formed of an organic layer including an organic material. The inorganic layer may include, for example, silicon nitride (SiN x ), silicon oxide (SiO x ) or silicon oxynitride (SiO x N y ). The organic layer may include an organic insulating material such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, unsaturated polyester resin, polyphenylene ether resin, polyphenylene sulfide resin, or benzocyclobutene (BCB).

[0256] According to an embodiment, a color filter layer and / or a color conversion layer for emitting light emitted from the first and second light emitting elements LD1 and LD2 as light with excellent color reproducibility may be selectively provided and / or formed on the encapsulation layer TFE.

[0257] In the following, reference will be made to Figures 10 to 17 The dummy pattern DMP provided in the dummy area DMA is described in detail.

[0258] Figures 10 to 17 It is along Figure 6 Schematic cross-sectional view taken along line II-II'.

[0259] Figures 11 to 17 The shape of the dummy pattern DMP is shown. Fig.10 's modified example.

[0260] To avoid Figures 10 to 17 The repeated description of the embodiment will mainly describe the differences from the above-mentioned embodiment.

[0261] Reference Figures 5 to 17, the dummy pattern DMP may be disposed on the fourth insulating layer INS4 in the dummy area DMA (or the non-emission area NEA).

[0262] The dummy pattern DMP may include a first dummy pattern DMP1 and a second dummy pattern DMP2 disposed on the first dummy pattern DMP1. The first dummy pattern DMP1 and the second dummy pattern DMP2 may include different materials. For example, the first dummy pattern DMP1 may be a conductive pattern including a conductive material, and the second dummy pattern DMP2 may be an organic pattern including an organic material.

[0263] In an embodiment, the first dummy pattern DMP1 may include a fourth conductive layer CL4. The first dummy pattern DMP1 may include a first layer FL, a second layer SL, and a third layer TL sequentially stacked in the third direction DR3. The first layer FL may be disposed on the fourth insulating layer INS4, the second layer SL may be disposed on the first layer FL, and the third layer TL may be disposed on the second layer SL.

[0264] The first layer FL and the third layer TL may include the same material as each other. For example, the first layer FL and the third layer TL may include titanium. The first layer FL may include the same material as the first metal layer ML1 of each of the third connection pattern CNP3 and the seventh connection pattern CNP7 and may be disposed on the same layer. The third layer TL may include the same material as the third metal layer ML3 of each of the third connection pattern CNP3 and the seventh connection pattern CNP7 and may be disposed on the same layer. The second layer SL may include a conductive material having material properties different from those of the first layer FL and the third layer TL. For example, the second layer SL may include aluminum. The second layer SL may include the same material as the second metal layer ML2 of each of the third connection pattern CNP3 and the seventh connection pattern CNP7 and may be disposed on the same layer.

[0265] The first layer FL may have a first thickness d1 (or first height) in the third direction DR3 , the second layer SL may have a second thickness d2 (or second height) in the third direction DR3 , and the third layer TL may have a third thickness d3 (or third height) in the third direction DR3 .

[0266] The first thickness d1, the second thickness d2, and the third thickness d3 may be different from each other. The second thickness d2 may be thicker than the first thickness d1 and the third thickness d3. For example, the first thickness d1 may be about 700 angstroms, the second thickness d2 may be about 6000 angstroms, and the third thickness d3 may be about 300 angstroms, but is not limited thereto.

[0267] The second layer SL may include a lower surface directly contacting the first layer FL and an upper surface directly contacting the third layer TL. The second layer SL may have a polygonal shape, for example, a trapezoidal shape whose width decreases from the lower surface toward the upper surface. The width W3 of the lower surface of the second layer SL may be about 10μm to about 13μm, and the width W4 of the upper surface of the second layer SL may be about 9μm, but is not limited thereto. The side surface of the second layer SL may be recessed from the side surface of each of the first layer FL and the third layer TL. In this case, each of the first layer FL and the third layer TL may protrude from the side surface of the second layer SL. Specifically, the second layer SL may have an undercut portion recessed from the side surfaces of the first layer FL and the third layer TL in a cross-sectional view.

[0268] The second dummy pattern DMP2 may be disposed on the first dummy pattern DMP1. For example, the second dummy pattern DMP2 may be disposed on the third layer TL of the first dummy pattern DMP1.

[0269] The second dummy pattern DMP2 may include a lower surface S6 and an upper surface S3 facing each other in the third direction DR3 The lower surface S6 may be disposed on the third layer TL of the first dummy pattern DMP1 and may directly contact the third layer TL.

[0270] In an embodiment, the second dummy pattern DMP2 may include a first portion A1 and a second portion A2.

[0271] The first portion A1 may have an area (or size) smaller than that of the second portion A2 and may have a square shape, but is not limited thereto. The first portion A1 may include a first side surface SS1 and a second side surface SS2 facing each other and a lower surface S6 connected to the first side surface SS1 and the second side surface SS2 in a cross-sectional view. The lower surface S6 may be a lower surface S6 of the second dummy pattern DMP2.

[0272] The second portion A2 may have an area (or size) larger than that of the first portion A1, and may have a polygonal shape. For example, the second portion A2 may have a reverse tapered shape (or an inverted trapezoidal shape) whose width increases toward the top in the third direction DR3. The second portion A2 may have a height in the third direction DR3 that is larger than the height of the first portion A1 in the third direction DR3. Therefore, the second dummy pattern DMP2 may have an overhanging structure. The height h of the second portion A2 in the third direction DR3 may be about 1 μm to about 1.5 μm, but is not limited thereto.

[0273] The second portion A2 may include a third side surface S4 and a fourth side surface S5 facing each other and an upper surface S3 connected to the third side surface S4 and the fourth side surface S5. The upper surface S3 may be the upper surface S3 of the second dummy pattern DMP2. In addition, the second portion A2 may include a first lower surface S1 and a second lower surface S2. The first lower surface S1 may face the upper surface S3 and may connect the third side surface S4 and the first side surface SS1 of the first portion A1. The second lower surface S2 may face the upper surface S3 and may connect the fourth side surface S5 and the second side surface SS2 of the first portion A1. The second portion A2 may be provided in a polygonal shape including straight lines, but is not limited thereto. According to an embodiment, as Fig.11 As shown in , the second portion A2 may be provided in a shape including at least one curved surface (eg, a mushroom shape). Fig.11 As shown in , the first portion A1 disposed below the second portion A2 may have a shape including at least one curved surface.

[0274] The inclination angle θ between the third side surface S4 and the first lower surface S1 (hereinafter referred to as "first inclination angle θ") may be from about 90° to about 130°, but is not limited thereto. For example, the first inclination angle θ may be 120°. The inclination angle between the fourth side surface S5 and the second lower surface S2 may be the same as the first inclination angle θ, but is not limited thereto.

[0275] In an embodiment, in a plan view, the first side surface SS1 of the first portion A1 may be disposed inside the third side surface S4 of the second portion A2, and in a plan view, the second side surface SS2 of the first portion A1 may be disposed inside the fourth side surface S5 of the second portion A2. In other words, the second portion A2 may protrude from each of the first side surface SS1 and the second side surface SS2 of the first portion A1. For example, in the case of observing from the first side surface SS1 and the second side surface SS2 of the first portion A1, the first portion A1 may have an undercut portion or the second portion A2 may have a protruding edge. In this case, when the second portion A2 relatively protrudes from the side surface of the first portion A1, an undercut portion SP (or a recessed portion) may be formed in the side surface of the second dummy pattern DMP2. The undercut portion SP may be surrounded by the first lower surface S1 of the second portion A2, the first side surface SS1 of the first portion A1, and the third layer TL of the first dummy pattern DMP1. In addition, the undercut portion SP may be surrounded by the second lower surface S2 of the second portion A2 , the second side surface SS2 of the first portion A1 , and the third layer TL of the first dummy pattern DMP1 .

[0276] In an embodiment, the second dummy pattern DMP2 may include an organic material. For example, the second dummy pattern DMP2 may include a negative photosensitive material. In this case, in the process of forming the second dummy pattern DMP2 on the first dummy pattern DMP1 made of a conductive material, according to the material properties of each of the first dummy pattern DMP1 and the second dummy pattern DMP2, the adhesion between the first dummy pattern DMP1 and the second dummy pattern DMP2 may be weakened, so the second dummy pattern DMP2 may have a reverse tapered shape. Therefore, the second dummy pattern DMP2 may have an overhanging structure in which the second portion A2 having a relatively large area is disposed on the first portion A1 having a relatively small area. That is, the first side surface SS1 of the first portion A1 may be disposed inside the third side surface S4 of the second portion A2, and the second side surface SS2 of the first portion A1 in a plan view may be disposed inside the fourth side surface S5 of the second portion A2. In this case, the second portion A2 may protrude from the first side surface SS1 and the second side surface SS2 of the first portion A1.

[0277] The first dummy pattern DMP1 may be exposed to the outside through the via hole VIH of the via layer VIA.

[0278] The control layer COL may be disposed on the dummy pattern DMP. The control layer COL may be a reference Fig. 9 Describes the control layer COL.

[0279] A portion of the control layer COL commonly provided to the first subpixel SPX1, the second subpixel SPX2, and the third subpixel SPX3 may be disconnected in a region corresponding to the undercut portion SP of the dummy pattern DMP, for example, the undercut portion of the first dummy pattern DMP1 and the undercut portion of the second dummy pattern DMP2. The disconnected portion may be a portion where the control layer COL is not continuously formed in the via hole VIH due to the undercut portion SP.

[0280] The control layer COL may be formed on the dummy pattern DMP by an inkjet printing method. Since the second portion A2 protrudes from the first portion A1 and has a reverse tapered shape, the control layer COL may be formed only on the upper surface S3, the third side surface S4, and the fourth side surface S5 of the second portion A2, and may not be formed on the first portion A1. That is, since the first portion A1 and the undercut portion SP are covered by the second portion A2, the control layer COL may be formed only on the upper surface S3, the third side surface S4, and the fourth side surface S5 of the exposed second portion A2.

[0281] In the first dummy pattern DMP1, when the third layer TL protrudes from the second layer SL, the control layer COL may be formed only on a portion of the upper surface of the third layer TL, the lower side surface of the second layer SL, and the first layer FL, and may not be formed on the region of the upper surface of the third layer TL in contact with the first portion A1 and the upper side surface of the second layer SL. That is, a portion of the third layer TL may be covered by the second dummy pattern DMP2, and a portion of the second layer SL may be covered by the third layer TL, so that the control layer COL may be formed only on a portion of the upper surface of the third layer TL, the lower side surface of the second layer SL, and the exposed first layer FL.

[0282] Therefore, the control layer COL may be separated (or disconnected) by the undercut portions of the first and second dummy patterns DMP1 and DMP2 in the via holes VIH.

[0283] The common electrode CE may be disposed on the control layer COL. The common electrode CE may be a reference Fig. 9 Described common electrode CE.

[0284] A common electrode CE commonly provided to the first sub-pixel SPX1, the second sub-pixel SPX2, and the third sub-pixel SPX3 may be formed on the control layer COL by a sputtering method. In addition, the common electrode CE may be formed on the first side surface SS1 and the second side surface SS2 of the first portion A1, on the upper surface of the third layer TL, and on the upper side surface of the second layer SL on which the control layer COL is not formed. In this case, a portion of the common electrode CE formed on the second portion A2 and a portion of the common electrode CE formed on the first portion A1 may be disconnected (or separated) from each other.

[0285] Since the common electrode CE is formed by a sputtering method, the moving direction of particles can be randomized according to process conditions. Therefore, compared with the control layer COL formed by an inkjet method, the common electrode CE can be formed with relatively less influence on the pixel PXL (or display panel DP (refer to FIG. Figure 1 )) is formed without the influence of the difference in the incident angle of the arrangement and / or the process deviation. Therefore, the common electrode CE may also be formed on the area of ​​the first dummy pattern DMP1 exposed to the outside by the disconnected portion of the control layer COL. In this case, the contact area between the conductive first dummy pattern DMP1 and the common electrode CE may be increased. Since the contact area between the first dummy pattern DMP1 and the common electrode CE is increased, the contact resistance of the common electrode CE is improved, thereby improving the display device (refer to Figure 1 The reliability of the display device DD) in the display device.

[0286] In addition, in the above-described embodiment, a process such as laser drilling for electrically connecting the cathode electrode and the driving power line may be omitted, and the common electrode CE and the first dummy pattern DMP1 may be electrically connected, thereby improving manufacturing efficiency of the display device DD.

[0287] The encapsulation layer TFE may be disposed on the dummy pattern DMP. The encapsulation layer TFE may be a reference Fig. 9 The encapsulation layer TFE is described.

[0288] According to an embodiment, the common electrode CE may also be formed in the undercut portion SP without being disconnected in the undercut portion SP. Fig.12 As shown in , the common electrode CE may be formed on the first side surface SS1 and the second side surface SS2 of the first portion A1 to entirely surround the second dummy pattern DMP2. In this case, the common electrode CE formed on the second dummy pattern DMP2 may be connected to the common electrode CE disposed on the first dummy pattern DMP1 without being separated (or disconnected). Therefore, the contact resistance of the common electrode CE may be further improved.

[0289] According to an embodiment, the common electrode CE may be provided in a form of completely filling the undercut portion SP. Fig.13 As shown in , the common electrode CE may be provided in the form of completely filling the undercut portion SP surrounded by the first side surface SS1 of the first portion A1, the first lower surface S1 of the second portion A2, and the upper surface of the third layer TL, and the undercut portion surrounded by the second side surface SS2 of the first portion A1, the second lower surface S2 of the second portion A2, and the upper surface of the third layer TL. In this case, the common electrode CE formed on the second dummy pattern DMP2 may be connected to the common electrode CE provided on the first dummy pattern DMP1 without being separated. In addition, since the common electrode CE is provided in the form of completely filling the undercut portion SP of the dummy pattern DMP, the area of ​​the common electrode CE in contact with the first dummy pattern DMP1 may be further increased, so that the contact resistance of the common electrode CE may be further improved.

[0290] An embodiment of further improving the contact resistance of the common electrode CE by further ensuring the contact area between the common electrode CE and the second layer SL of the first dummy pattern DMP1 may be considered. Fig.14As shown in , since the third layer TL of the first dummy pattern DMP1 includes the opening OP, the third layer TL may expose the upper surface of the second layer SL disposed below the third layer TL to the outside. In this case, in the process of forming the common electrode CE, the common electrode CE may directly contact the second layer SL exposed through the opening OP of the third layer TL. Since the second layer SL made of aluminum has a relatively smaller resistivity than the third layer TL made of titanium, in the case where the second layer SL is in direct contact with the common electrode CE, the contact resistance of the common electrode CE may be further improved.

[0291] According to an embodiment, the third layer TL of the first dummy pattern DMP1 may include a first protrusion PRT1 and a second protrusion PRT2. Fig.15 As shown in . The first protrusion PRT1 and the second protrusion PRT2 can be formed by wet etching the second layer SL after etching the first layer FL, the second layer SL and the third layer TL at the same time. For example, in wet etching, when the over-etching is performed for more than 100 seconds using a phosphate-based aluminum etchant, the first protrusion PRT1 and the second protrusion PRT2 can be formed. The first protrusion PRT1 and the second protrusion PRT2 can protrude in a direction toward the second dummy pattern DMP2. For example, the first protrusion PRT1 and the second protrusion PRT2 can protrude toward the second dummy pattern DMP2 in a direction inclined to the third direction DR3. Since the third layer TL includes the first protrusion PRT1 and the second protrusion PRT2, the undercut shape of the third layer TL can be further maximized. In this case, the area of ​​the disconnected portion of the control layer COL formed on the first dummy pattern DMP1 can be further increased, so that the exposed area of ​​the first dummy pattern DMP1 can be increased. Therefore, the contact area between the common electrode CE and the first dummy pattern DMP1 can be further ensured to prevent the voltage drop of the common electrode CE.

[0292] According to an embodiment, a separate conductive layer may be disposed on the first dummy pattern DMP1 and the second dummy pattern DMP2. Fig.16 As shown in FIG. 1 , the conductive pattern CP may be disposed on the first dummy pattern DMP1 and the second dummy pattern DMP2. The conductive pattern CP may be Fig. 9 The described first pixel electrode PE1 and second pixel electrode PE2 are formed by the same process and may include the same material. For example, the conductive pattern CP may be made of a transparent conductive oxide.

[0293] The conductive pattern CP may be formed on the second portion A2 of the second dummy pattern DMP2 to completely surround the second portion A2, and may be formed on the upper and lower ends of the first side surface SS1 and the second side surface SS2 of the first portion A1 of the second dummy pattern DMP2. The conductive pattern CP may not be formed on the middle portion of each of the first side surface SS1 and the second side surface SS2 of the first portion A1 covered by the second portion A2, but is not limited thereto. According to an embodiment, the conductive pattern CP may also be formed on the middle portion of each of the first side surface SS1 and the second side surface SS2 of the first portion A1.

[0294] The conductive pattern CP may be formed on the first dummy pattern DMP1. For example, the conductive pattern CP may be formed on the upper surface of the third layer TL, the lower side surface of the second layer SL, and the side surface of the first layer FL. The conductive pattern CP made of a transparent conductive oxide may be disposed on the first layer FL and the third layer TL made of titanium and the second layer SL made of aluminum so as to cover the first layer FL, the second layer SL, and the third layer TL to prevent oxidation that may occur due to the material characteristics of each layer. In addition, the conductive pattern CP may be disposed between the common electrode CE and the first dummy pattern DMP1, and may be electrically connected to the common electrode CE and the first dummy pattern DMP1. Therefore, the contact resistance of the common electrode CE may be further improved.

[0295] According to an embodiment, a plurality of second dummy patterns DMP2 may be provided. Fig.17 As shown in FIG. 1 , the second dummy pattern DMP2 may include a 2-1st dummy pattern DMP2_1, a 2-2nd dummy pattern DMP2_2, and a 2-3rd dummy pattern DMP2_3 disposed on the third layer TL of the first dummy pattern DMP1. Each of the 2-1st dummy pattern DMP2_1, the 2-2nd dummy pattern DMP2_2, and the 2-3rd dummy pattern DMP2_3 may include a first portion A1 and a second portion A2.

[0296] The 2-1st dummy pattern DMP2_1, the 2-2nd dummy pattern DMP2_2, and the 2-3rd dummy pattern DMP2_3 may be spaced apart from each other on the third layer TL. In this case, the control layer COL may include disconnected portions between the 2-1st dummy pattern DMP2_1 and the 2-2nd dummy pattern DMP2_2 and between the 2-2nd dummy pattern DMP2_2 and the 2-3rd dummy pattern DMP2_3. That is, the control layer COL may be formed on a portion of the upper surface of the third layer TL disposed between the 2-1st dummy pattern DMP2_1 and the 2-2nd dummy pattern DMP2_2, and may be formed on a portion of the upper surface of the third layer TL disposed between the 2-2nd dummy pattern DMP2_2 and the 2-3rd dummy pattern DMP2_3. The common electrode CE may be formed on the control layer COL to cover the control layer COL, and may also be formed on the upper surface of the third layer TL of the first dummy pattern DMP1 that is exposed to the outside because the control layer COL is not formed. Therefore, the contact area between the common electrode CE and the first dummy pattern DMP1 may be further ensured to prevent a voltage drop of the common electrode CE, thereby further improving the reliability of the display device DD.

[0297] In the above-described embodiment, it has been described that the second dummy pattern DMP2 is formed on the first dummy pattern DMP1 and is disposed only in the dummy area DMA, but is not limited thereto. Fig.18 Describe it.

[0298] Fig.18 shows a pixel according to an embodiment and is Figure 6 Schematic cross-sectional view corresponding to line II'.

[0299] To avoid Fig.18 The repeated description of the embodiment will mainly describe the differences from the above-mentioned embodiment.

[0300] Reference Figures 1 to 5 and Fig.18 , the second dummy pattern DMP2 may be disposed in the non-emission area NEA disposed between the first sub-pixel SPX1 and the second sub-pixel SPX2.

[0301] The second dummy pattern DMP2 may be disposed on the pixel defining layer PDL. The second dummy pattern DMP2 may include a first portion A1 and a second portion A2. The second dummy pattern DMP2 may have an overhang structure in which the second portion A2 has an area relatively larger than that of the first portion A1. Moreover, since the second portion A2 protrudes beyond the first portion A1, the first portion A1 may have an undercut portion.

[0302] The control layer COL and the common electrode CE may be disposed on the second dummy pattern DMP2 .

[0303] Since the first portion A1 has an undercut portion, the control layer COL may not be formed on the side surface of the first portion A1 disposed below the second portion A2. Therefore, the control layer COL may have a disconnected portion (or an opening portion) disposed between the first sub-pixel SPX1 and the second sub-pixel SPX2. Since the control layer COL is disconnected between the first sub-pixel SPX1 and the second sub-pixel SPX2, the leakage current of each sub-pixel through the control layer COL can be further reduced or further minimized so as not to be transmitted to an adjacent sub-pixel, thereby further improving the reliability of each sub-pixel.

[0304] The common electrode CE may be disposed on the control layer COL. The common electrode CE may be formed on the control layer COL and the pixel defining layer PDL exposed by the disconnected portion of the control layer COL.

[0305] An encapsulation layer TFE may be formed on the common electrode CE and the second dummy pattern DMP2 .

[0306] Fig.19A and Fig.19B It is shown that the Figure 1 Schematic plan view of a region of the display area DA in the display device DD. Specifically, Fig.19A and Fig.19B Various embodiments of arrangement structures of pixel circuits and dummy patterns DMP are shown.

[0307] Reference Figure 1 , Fig.19A and Fig.19B , a plurality of pixel circuits and a dummy pattern DMP may be disposed in a display area DA of a display device DD.

[0308] The display area DA may include pixel rows R1 to R4. Each of the pixel rows R1 to R4 may extend in a first direction DR1, and the pixel rows R1 to R4 may be arranged in a second direction DR2. Each of the pixel rows R1 to R4 may include a pixel circuit.

[0309] The eleventh pixel circuit PXC11, the twelfth pixel circuit PXC12, the thirteenth pixel circuit PXC13, and the fourteenth pixel circuit PXC14 may be arranged in the first pixel row R1 (or the first horizontal line). The eleventh pixel circuit PXC11 may be a pixel circuit of a first sub-pixel arranged in the first pixel row R1, the twelfth pixel circuit PXC12 may be a pixel circuit of a second sub-pixel arranged in the first pixel row R1, the thirteenth pixel circuit PXC13 may be a pixel circuit of a third sub-pixel arranged in the first pixel row R1, and the fourteenth pixel circuit PXC14 may be a pixel circuit of a fourth sub-pixel arranged in the first pixel row R1.

[0310] The twenty-first pixel circuit PXC21, the twenty-second pixel circuit PXC22, the twenty-third pixel circuit PXC23, and the twenty-fourth pixel circuit PXC24 may be disposed in the second pixel row R2 (or the second horizontal line). The twenty-first pixel circuit PXC21 may be a pixel circuit of a first sub-pixel disposed in the second pixel row R2, the twenty-second pixel circuit PXC22 may be a pixel circuit of a second sub-pixel disposed in the second pixel row R2, the twenty-third pixel circuit PXC23 may be a pixel circuit of a third sub-pixel disposed in the second pixel row R2, and the twenty-fourth pixel circuit PXC24 may be a pixel circuit of a fourth sub-pixel disposed in the second pixel row R2.

[0311] The thirty-first pixel circuit PXC31, the thirty-second pixel circuit PXC32, the thirty-third pixel circuit PXC33, and the thirty-fourth pixel circuit PXC34 may be disposed in the third pixel row R3 (or the third horizontal line). The thirty-first pixel circuit PXC31 may be a pixel circuit of a first sub-pixel disposed in the third pixel row R3, the thirty-second pixel circuit PXC32 may be a pixel circuit of a second sub-pixel disposed in the third pixel row R3, the thirty-third pixel circuit PXC33 may be a pixel circuit of a third sub-pixel disposed in the third pixel row R3, and the thirty-fourth pixel circuit PXC34 may be a pixel circuit of a fourth sub-pixel disposed in the third pixel row R3.

[0312] The forty-first pixel circuit PXC41, the forty-second pixel circuit PXC42, the forty-third pixel circuit PXC43, and the forty-fourth pixel circuit PXC44 may be disposed in the fourth pixel row R4 (or the fourth horizontal line). The forty-first pixel circuit PXC41 may be a pixel circuit of a first sub-pixel disposed in the fourth pixel row R4, the forty-second pixel circuit PXC42 may be a pixel circuit of a second sub-pixel disposed in the fourth pixel row R4, the forty-third pixel circuit PXC43 may be a pixel circuit of a third sub-pixel disposed in the fourth pixel row R4, and the forty-fourth pixel circuit PXC44 may be a pixel circuit of a fourth sub-pixel disposed in the fourth pixel row R4.

[0313] In the display area DA, the dummy patterns DMP may be arranged at a density different from that of the pixel circuits. Fig.19A As shown in , one dummy pattern DMP may be provided for each unit pixel block UPX. The unit pixel block UPX may be a dummy unit block having a predetermined area, including two pixel circuits disposed adjacent to each other in a first direction DR1 and two pixel circuits disposed adjacent to the two pixel circuits in a second direction DR2 intersecting the first direction DR1. The unit pixel block UPX may include, for example, an eleventh pixel circuit PXC11, a twelfth pixel circuit PXC12, a twenty-first pixel circuit PXC21, and a twenty-second pixel circuit PXC22. In the display area DA, one dummy pattern DMP may be provided for each unit pixel block UPX including 2×2 pixel circuits, and the dummy pattern DMP may be provided in a number less than the number of pixel circuits.

[0314] In the above-mentioned embodiment, it has been described that the unit pixel block UPX includes 2×2 pixel circuits, but is not limited thereto. According to an embodiment, the unit pixel block UPX may include 3×3 pixel circuits or 4×4 pixel circuits.

[0315] According to an embodiment, in the display area DA, the dummy patterns DMP may be arranged at the same density as the density of the pixel circuits. Fig.19B As shown in , the number of dummy patterns DMP may be the same as the number of pixel circuits. In this case, the dummy patterns DMP may be arranged to be formed in one-to-one correspondence with the pixel circuits.

[0316] The arrangement structure of the pixel circuits and the dummy pattern DMP is not limited to the above-described embodiment. That is, the density, number, and size of the pixel circuits and the dummy pattern DMP in the display area DA may be variously modified within the scope consistent with the concept of the present embodiment.

[0317] In the following, reference will be made to Figures 20 to 30 A method of manufacturing a display device according to an embodiment is described.

[0318] Figures 20 to 30 It is shown that the formation Fig. 9 The first sub-pixel SPX1 and the second sub-pixel SPX2 and Fig.10 Schematic cross-sectional view of a dummy pattern DMP method.

[0319] exist Figures 20 to 30 In the embodiment of the present invention, the manufacturing steps of the display device are described as being performed sequentially according to the cross-sectional views, but unless the scope of the inventive concept is changed, it is obvious that the steps shown as being performed sequentially may be performed simultaneously, the order of the steps may be changed, some steps may be omitted, or other steps may be included between each step.

[0320] exist Figures 20 to 30 In order to avoid redundant description, the differences from the above-mentioned embodiment will be mainly described.

[0321] Reference Figures 1 to 10 and Fig. 20 , a first base conductive layer BSL1, a second base conductive layer BSL2, and a third base conductive layer BSL3 may be formed on the substrate (or the fourth insulating layer INS4) of the display area DA.

[0322] The first base conductive layer BSL1 may correspond to a base material of the first metal layer ML1 and the first layer FL, and may include a conductive material. For example, the first base conductive layer BSL1 may include titanium.

[0323] The first base conductive layer BSL1 may be formed on the fourth insulating layer INS4 and may be connected to the sixth drain area DA6 of the sixth transistor T6 of each of the first pixel circuit PXC1 and the second pixel circuit PXC2 through a contact hole CH formed through the fourth insulating layer INS4 and the third insulating layer INS3 and the second insulating layer INS2 disposed under the fourth insulating layer INS4.

[0324] The second base conductive layer BSL2 may be formed on the first base conductive layer BSL1. The second base conductive layer BSL2 may correspond to the base material of the second metal layer ML2 and the second layer SL, and may include a conductive material. For example, the second base conductive layer BSL2 may include aluminum.

[0325] The third base conductive layer BSL3 may be formed on the second base conductive layer BSL2. The third base conductive layer BSL3 may correspond to the base material of the third metal layer ML3 and the third layer TL and may include a conductive material. For example, the third base conductive layer BSL3 may include titanium.

[0326] The first base conductive layer BSL1, the second base conductive layer BSL2, and the third base conductive layer BSL3 may be sequentially formed in the same chamber without breaking the vacuum.

[0327] Reference Figures 1 to 10 , Fig. 20 and Fig.21 , the third connection patterns CNP3 , the seventh connection patterns CNP7 , and the first dummy patterns DMP1 may be formed by collectively patterning the first to third base conductive layers BSL1 , BSL2 , and BSL3 by performing a photolithography process using a mask.

[0328] Each of the third connection pattern CNP3 and the seventh connection pattern CNP7 may include a first metal layer ML1, a second metal layer ML2, and a third metal layer ML3 sequentially stacked in the third direction DR3. The third connection pattern CNP3 may be disposed in a region of the first pixel circuit PXC1 in which the first subpixel SPX1 is disposed, and the seventh connection pattern CNP7 may be disposed in a region of the second pixel circuit PXC2 in which the second subpixel SPX2 is disposed.

[0329] The first dummy pattern DMP1 may include a first layer FL, a second layer SL, and a third layer TL sequentially stacked in the third direction DR3 . The first dummy pattern DMP1 may be disposed in the dummy area DMA.

[0330] The first metal layer ML1 and the first layer FL may be formed by the same process, may include the same material, and may be provided on the same layer. The second metal layer ML2 and the second layer SL may be formed by the same process, may include the same material, and may be provided on the same layer. The third metal layer ML3 and the third layer TL may be formed by the same process, may include the same material, and may be provided on the same layer.

[0331] Reference Figures 1 to 10 and Figure 20 to Figure 22 , a wet etching process may be performed to selectively etch the second metal layer ML2 and the second layer SL.

[0332] Due to the above-mentioned wet etching process, the side surface of the second metal layer ML2 may be recessed from each of the side surfaces of the first metal layer ML1 and the third metal layer ML3. Therefore, the second metal layer ML2 may have an undercut portion disposed below the third layer TL and recessed from each of the side surfaces of the first metal layer ML1 and the third metal layer ML3.

[0333] In the above embodiments, selective etching of the second metal layer ML2 is performed together with the second layer SL, but is not limited thereto. According to embodiments, the second metal layer ML2 may be covered by a separate mask (eg, an etching mask), and thus only the second layer SL may be etched during the wet etching process.

[0334] Reference Figures 1 to 10 as well as Figure 20 to Figure 23 , the fifth insulating layer INS5 may be formed on the third connection pattern CNP3 and the seventh connection pattern CNP7. By removing a portion of the fifth insulating layer INS5 in the dummy area DMA, the fifth insulating layer INS5 may expose the first dummy pattern DMP1 without being formed on the first dummy pattern DMP1. In other words, the fifth insulating layer INS5 may not be formed on the first dummy pattern DMP1.

[0335] The fifth insulating layer INS5 may expose a portion of each of the third and seventh connection patterns CNP3 and CNP7 by removing portions of the fifth insulating layer INS5 on the third and seventh connection patterns CNP3 and CNP7 .

[0336] Reference Figures 1 to 10 and Figure 20 to Figure 24 , a via layer VIA is formed on the fifth insulating layer INS5.

[0337] The via layer VIA may include a first contact portion CNT1 exposing a portion of the third connection pattern CNP3 and a second contact portion CNT2 exposing a portion of the seventh connection pattern CNP7 .

[0338] The via layer VIA may include a via hole VIH exposing the first dummy pattern DMP1 in the dummy area DMA. In the dummy area DMA, the via layer VIA may be directly formed on the fourth insulating layer INS4, but is not limited thereto. For example, in the case where the fifth insulating layer INS5 is provided in the dummy area DMA in the form of including an opening completely exposing the first dummy pattern DMP1, the via layer VIA may be formed on the fifth insulating layer INS5.

[0339] Reference Figures 1 to 10 as well as Figure 20 to Figure 25 The first pixel electrode PE1 and the second pixel electrode PE2 may be formed on the via layer VIA. The first pixel electrode PE1 may be electrically connected to the third connection pattern CNP3 through the first contact portion CNT1, and the second pixel electrode PE2 may be electrically connected to the seventh connection pattern CNP7 through the second contact portion CNT2.

[0340] According to the embodiment, as shown in FIG. Fig.17As described above, the conductive pattern CP may be formed on the first dummy pattern DMP1. In this case, the conductive pattern CP may be formed through the same process as the first pixel electrode PE1 and the second pixel electrode PE2 and may include the same material.

[0341] Reference Figures 1 to 10 as well as Figure 20 to Figure 26 , a pixel defining layer PDL may be formed on the first pixel electrode PE1 and the second pixel electrode PE2. The pixel defining layer PDL may include an opening exposing a region of each of the first pixel electrode PE1 and the second pixel electrode PE2.

[0342] By removing a portion of the pixel defining layer PDL in the dummy area DMA, the pixel defining layer PDL may expose the first dummy pattern DMP1 without being formed on the first dummy pattern DMP1. In other words, the pixel defining layer PDL may not be formed on the first dummy pattern DMP1.

[0343] Reference Figures 1 to 10 and Figures 20 to 27 , after coating an organic material layer on the first dummy pattern DMP1, a photolithography process is performed using a mask to form a second dummy pattern DMP2.

[0344] The second dummy pattern DMP2 may be formed on the first dummy pattern DMP1 in the dummy area DMA. The second dummy pattern DMP2 may be made of, for example, a negative photosensitive material. Due to the material properties of the second dummy pattern DMP2 and the material properties of the first dummy pattern DMP1 (or the third layer TL), the adhesion between the first dummy pattern DMP1 and the second dummy pattern DMP2 may be weakened, so that the second dummy pattern DMP2 may have a reverse tapered shape (or an overhanging structure).

[0345] The second dummy pattern DMP2 may include a first portion A1 and a second portion A2. The second portion A2 may have an area (or size) relatively larger than that of the first portion A1.

[0346] The first dummy pattern DMP1 and the second dummy pattern DMP2 may constitute a dummy pattern DMP.

[0347] Reference Figures 1 to 10 and Figures 20 to 28 , a first light emitting layer EML1 may be formed on the first pixel electrode PE1 exposed through the opening of the pixel defining layer PDL, and a second light emitting layer EML2 may be formed on the second pixel electrode PE2 exposed through another opening of the pixel defining layer PDL.

[0348] Reference Figures 1 to 10 as well as Figures 20 to 29, the control layer COL may be formed on the first light emitting layer EML1, the second light emitting layer EML2, and the dummy pattern DMP.

[0349] The control layer COL may be provided in common to the first sub-pixel SPX1 and the second sub-pixel SPX2. The control layer COL may be disposed in the dummy area DMA and may be formed on the dummy pattern DMP. In this case, in the dummy area DMA, the control layer COL may have a disconnected portion in an area corresponding to the undercut portion formed in the first dummy pattern DMP1 and the second dummy pattern DMP2. The control layer COL may be formed on the upper surface S3 and the third and fourth side surfaces S4 and S5 of the second portion A2 of the second dummy pattern DMP2, and may not be formed in the first portion A1 covered by the second portion A2. In addition, the control layer COL may be formed only on a portion of each of the third layer TL, the second layer SL, and the first layer FL of the first dummy pattern DMP1.

[0350] Reference Figures 1 to 10 as well as Figures 20 to 30 , the common electrode CE may be formed on the control layer COL.

[0351] The common electrode CE may be commonly provided to the first sub-pixel SPX1 and the second sub-pixel SPX2. The common electrode CE may be disposed in the dummy area DMA and may be formed on the control layer COL and the first dummy pattern DMP1 exposed by the disconnected portion of the control layer COL. In this case, the contact area between the first dummy pattern DMP1 and the common electrode CE may be increased, thereby improving the contact resistance of the common electrode CE.

[0352] An encapsulation layer TFE may be formed on the common electrode CE.

[0353] While the inventive concept has been shown and described with reference to particular embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made thereto without departing from the scope of the inventive concept as defined by the appended claims and their equivalents.

[0354] Therefore, the technical scope of the present disclosure can be determined by the technical scope of the appended claims.

Claims

1. A display device, wherein: The display device comprises: The connection pattern and the dummy pattern are spaced apart from each other on the substrate; A via layer is disposed on the substrate, and the via layer includes a contact portion exposing the connection pattern and a via hole exposing the dummy pattern; a pixel electrode disposed on the via layer and electrically connected to the connection pattern through the contact portion; A light-emitting layer is disposed on the pixel electrode; a control layer, disposed on the light-emitting layer; and A common electrode is arranged on the control layer, The dummy pattern includes a first dummy pattern and a second dummy pattern arranged on the first dummy pattern, the first dummy pattern includes a first layer, a second layer and a third layer, each of the first layer, the second layer and the third layer is made of a conductive material, and the first layer, the second layer and the third layer are stacked sequentially, and the second dummy pattern includes an organic pattern, and the organic pattern includes a first part and a second part having different areas in a plan view.

2. The display device according to claim 1, wherein: The second dummy pattern includes a negative photosensitive material, and the control layer is disconnected on the first portion.

3. The display device according to claim 2, wherein: The first portion is disposed on the first dummy pattern, the second portion is disposed on the first portion, the first portion has an area smaller than that of the second portion, and the second portion has a reverse tapered shape in which a width becomes narrower from an upper surface toward a lower surface.

4. The display device according to claim 3, wherein: An inclination angle of a side surface connected to the lower surface in the second portion is from 90° to 130°, and in a plan view, a side surface of the first portion is disposed inside the side surface of the second portion.

5. The display device according to claim 4, wherein: The first portion has an undercut portion recessed from the side surface of the second portion.

6. The display device according to claim 1, wherein: The first layer and the third layer include titanium, and the second layer includes aluminum having a greater thickness than the first layer and the third layer.

7. The display device according to claim 6, wherein: The control layer is disposed on each of an upper surface of the second portion, a side surface of the second portion, a portion of an upper surface of the third layer, a portion of a side surface of the second layer, and a side surface of the first layer, and The common electrode is disposed on each of the control layer, the side surface of the first portion, the upper surface and the side surface of the third layer, and the side surface of the second layer.

8. The display device according to claim 7, wherein: The common electrode is disconnected on the side surface of the first portion.

9. The display device according to claim 8, wherein: A portion of the common electrode disposed on the second dummy pattern and a portion of the common electrode disposed on the first dummy pattern are disconnected from each other.

10. The display device according to claim 7, wherein: A portion of the common electrode disposed on the second dummy pattern and a portion of the common electrode disposed on the first dummy pattern are connected to each other.

11. The display device according to claim 10, wherein: The common electrode fills an undercut portion surrounded by a lower surface of the second portion, the side surface of the first portion, and the upper surface of the third layer.

12. The display device according to claim 10, wherein: The third layer includes an opening exposing a portion of the second layer, and the common electrode is disposed on the portion of the second layer exposed by the opening.

13. The display device according to claim 7, wherein: The third layer includes a protrusion protruding in a direction toward the second dummy pattern.

14. The display device according to claim 7, wherein: The display device further includes: a conductive pattern disposed on the first dummy pattern and the second dummy pattern, and The conductive pattern and the pixel electrode include the same material.

15. The display device according to claim 7, wherein: The second dummy pattern includes a plurality of second dummy patterns disposed on the first dummy pattern.

16. The display device according to claim 1, wherein: The connection pattern includes a first metal layer, a second metal layer disposed on the first metal layer, and a third metal layer disposed on the second metal layer, and Among them, the first metal layer and the first layer include the same material and the first metal layer and the first layer are arranged on the same layer, the second metal layer and the second layer include the same material and the second metal layer and the second layer are arranged on the same layer, and the third metal layer and the third layer include the same material and the third metal layer and the third layer are arranged on the same layer.

17. The display device according to claim 1, wherein: The display device further includes: At least one transistor is disposed between the substrate and the connection pattern, and the at least one transistor is electrically connected to the pixel electrode through the connection pattern.

18. The display device according to claim 1, wherein: The first dummy pattern is electrically connected to the common electrode to receive a low potential voltage.

19. The display device according to claim 1, wherein: The display device further includes a pixel defining layer exposing a region of the pixel electrode and a third dummy pattern disposed on the pixel defining layer.

20. A method for manufacturing a display device, wherein: The manufacturing method comprises: forming a connection pattern and a dummy pattern spaced apart from each other on a substrate; forming a via layer, the via layer comprising a contact portion exposing the connection pattern and a via hole exposing the dummy pattern, the via layer being disposed on the connection pattern; forming a pixel electrode on the via layer, the pixel electrode being electrically connected to the connection pattern through the contact portion; forming a light-emitting layer on the pixel electrode; forming a control layer on the light emitting layer; and forming a common electrode on the control layer, The dummy pattern includes a first dummy pattern and a second dummy pattern arranged on the first dummy pattern, the first dummy pattern includes a first layer, a second layer and a third layer, each of the first layer, the second layer and the third layer is made of a conductive material, and the first layer, the second layer and the third layer are stacked sequentially, and the second dummy pattern includes an organic pattern, and the organic pattern includes a first part and a second part having different areas in a plan view.

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