Comparator with hysteresis and electronic equipment
By introducing the configuration of the current mirror and the anti -phase device in the comparator circuit, the closerness is realized, and the problem of being easily affected by noise in the fast signal processing of the existing comparator is solved, and the signal stability and adaptability are improved.
Patent Information
- Application Number
- CN202380051041.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Priority Date
- 2022-07-29
- Filing Date
- 2023-07-26
- Publication Date
- 2025-01-24
AI Technical Summary
Existing comparator circuits are susceptible to noise when processing fast signals, resulting in undesired rapid changes between output states, affecting signal stability.
A comparator including an input stage, an output stage and a gain stage is designed, and hysteresis is achieved through the configuration of current mirror and inverter. Specifically, the second inverter output in the gain stage controls the on or off state of the third transistor, thereby adjusting the current mirror load and adjusting the speed of the switching phase.
This design can effectively resist the noise in the input signal, reduce the unwilling changes between the output state, improve the stability of the signal, and apply to the fast signal application.
Smart Images
Figure CN119366111A_ABST
Abstract
Description
[0001] Comparators are commonly used to distinguish between two different signal levels. They do this by comparing two voltages or currents and outputting a digital signal indicating which is greater. Comparators are commonly used components or circuit elements, for example, in analog-to-digital converters (ADCs), two-point or three-point controllers, and switching power supplies.
[0002] In more detail, a common comparator circuit includes a circuit for receiving an input signal (e.g., V - 、V + ) and two analog input terminals for outputting digital output signals (for example, V out ) is a binary digital output terminal. If V + Greater than V - , then V out is 1 (logic high). If V + Less than V - , then V out However, one disadvantage of this configuration is that since noise is always present on the input signal V + 、V - The small voltage fluctuation caused by this may cause two output states V out Unexpected rapid changes occur between.
[0003] To prevent such output oscillations, a small hysteresis of a few millivolts is integrated into many common comparator circuits. For example, such a comparator can be operated by applying positive feedback to it. The high and low output signals V out The potential difference between the feedback resistor and the input signal V - The comparison reference voltage.
[0004] For example, hysteresis can be achieved by using two different threshold voltages (e.g., V thL 、V thH ), to avoid multiple conversions. In one exemplary configuration, the input signal V - may exceed the upper threshold V thH Make V out becomes low, or falls below the lower threshold V thL Make V out Since the threshold V thH A margin is set between the low-to-high threshold, so even if the input signal V - The voltage is close to the threshold voltage V thL 、V thH , V out will not be affected (i.e., no jitter will occur).
[0005] However, for applications requiring fast signals, adaptation is required to provide sufficient robustness against noise in the input signal.
[0006] It is therefore an object of the present invention to provide an improved comparator. Summary of the invention
[0007] According to an embodiment, the comparator includes an input stage, an output stage, and a gain stage, wherein the input stage is configured to receive a pair of input signals to generate at least one differential current signal; the output stage is configured to generate an output signal according to the differential current signal, the output stage includes a current mirror and a node electrically connected to the current mirror, the current mirror includes a first transistor, a second transistor, and a third transistor, the second transistor and the third transistor are connected in parallel; the gain stage includes a first inverter and a second inverter, wherein the output of the first inverter is input to the second inverter. In more detail, the output of the second inverter is configured to control the third transistor to be in a floating state or a conducting state.
[0008] In other words, the third transistor acts as a switch that is turned on and off according to the output of the second inverter. This switch configuration achieves hysteresis by regulating the current mirror load.
[0009] For example, if the output of the second inverter is high, the third transistor can be controlled to be turned on. In this case, a larger current may flow through the output stage, thereby increasing the upper threshold voltage.
[0010] On the other hand, if the output of the second inverter is low, the third transistor can be controlled to float. In this case, a smaller current may flow through the output stage, thereby reducing the lower threshold voltage.
[0011] In this way, hysteresis can be achieved. This configuration allows the speed of the switching phase to be adjusted, allowing the comparator to be used for fast signals.
[0012] The input stage may include a first input transistor and a second input transistor, the first input transistor being different from the second input transistor. In other words, in one configuration of the comparator, an asymmetric pair of input transistors may be implemented. For example, the second input transistor may be smaller than the first input transistor, and the second input transistor may be connected to the switch input. The first transistor may be connected to a reference terminal. This allows faster switching and may provide more headroom for a current source (e.g., a bias transistor), thereby producing a constant and stable current source in a saturated state.
[0013] The comparator may further include an inverter and a control transistor. The output of the second inverter may be fed to a gate terminal of the control transistor via the inverter. The control transistor may control the conduction or cutoff of the third transistor according to the output of the second inverter.
[0014] The control transistor can be implemented by using an NMOS transistor. BRIEF DESCRIPTION OF THE DRAWINGS
[0015] The accompanying drawings are incorporated into this specification and are a part of this specification, and the accompanying drawings are included to further understand the embodiments of the present invention. These drawings illustrate embodiments of the present invention and are used to explain the relevant principles together with the contents of the specification. Other embodiments of the present invention and many expected advantages will become easier to understand through the detailed description below. The elements in the accompanying drawings are not necessarily proportional to each other. The same reference numerals designate corresponding similar parts.
[0016] Figure 1 is a schematic diagram showing components of a comparator according to an embodiment.
[0017] Figure 2 Examples of input signals and output signals of a comparator according to an embodiment are shown.
[0018] Figure 3 An example of an electronic device according to an embodiment is shown. DETAILED DESCRIPTION
[0019] In the detailed description below, reference is made to the accompanying drawings, which form a part of this specification and illustrate by way of illustration specific embodiments in which the invention may be implemented. In this regard, directional terms such as "top", "bottom", "front", "rear", "above", "on", "above", "head", "tail", etc. are used with reference to the orientation of the drawings being described. Since the components of the embodiments of the invention can be placed in many different orientations, the directional terms are for illustrative purposes only and are not intended to be limiting. It should be understood that other embodiments may be employed and structural or logical changes may be made without departing from the scope defined by the claims.
[0020] The description of these embodiments is non-limiting. In particular, elements of the embodiments described below may be combined with elements of different embodiments.
[0021] The terms "coupled" and / or "electrically coupled" used in this specification do not mean that all elements are directly coupled together, but intermediate elements may be provided between the "coupled" or "electrically coupled" elements. The term "electrically connected" is intended to describe a low-ohmic electrical connection between electrically connected elements.
[0022] As used herein, the terms "having", "containing", "including", "comprising" and the like are open terms, used to indicate the presence of stated elements or features, but do not exclude the presence of other elements or features. Unless the context clearly indicates otherwise, the articles "a", "an" and "the" are intended to include plural as well as singular forms.
[0023] Figure 1 is a schematic diagram showing components of a comparator 10 according to an embodiment. Figure 1 As indicated by corresponding arrows in , the comparator 10 includes an input stage IS, an output stage OS and a gain stage GS.
[0024] The input stage IS may include a bias transistor 34 and input transistors 26, 28. The bias transistor 34 may be configured to operate as a tail current source of a differential input circuit formed by the input transistors 26, 28. The gate terminal of the bias transistor 34 may receive a bias voltage. The source terminal of the bias transistor 34 may be electrically connected to a reference potential, which is typically Vss or GND.
[0025] The gate terminal of input transistor 26 may form the non-inverting input of comparator 10 , while the gate terminal of transistor 28 may form the inverting input of comparator circuit 10 .
[0026] The input stage IS can also include Figure 1 The load circuit formed by multiple transistors shown in the upper part. In this circuit, a pair of cross-coupled transistors can be coupled between the differential input circuit and the positive power supply node Vdd. In this case, there are many possible configurations. Figure 1 The load circuit shown is by way of example only, and many alternative implementations and modifications are possible.
[0027] The input stage IS receives a pair of input signals S1, S2 via transistors 26, 28, which will be described in detail below. The input stage IS then generates a differential current signal S3 which is transmitted to the output stage OS.
[0028] The output stage OS generates an output signal S4 according to the differential current signal S3. The output stage OS includes a current mirror 12 and a node 14 electrically connected to the current mirror 12. In more detail, the current mirror 12 may include a first transistor 16, a second transistor 18, and a third transistor 20. Figure 1 As shown, the second transistor 18 and the third transistor 20 are connected in parallel.
[0029] In addition, the gain stage GS includes a first inverter 22 and a second inverter 24, wherein the output of the first inverter 22 is input to the second inverter 24. Figure 1As shown, the gain stage GS may further include other inverters. Then, the output of the second inverter 24 is fed back to the current mirror 12.
[0030] In more detail, the output of the second inverter 24 controls the third transistor 20 to be in a floating or turned-on state.
[0031] That is, the third transistor 20 operates as a switch, which is turned on or off depending on the output of the second inverter 24. Hysteresis is achieved by this configuration.
[0032] For example, if the output of the second inverter 24 is high, the third transistor 20 can be controlled to be turned on or turned on. In the first phase, a larger current can pass or flow through the output stage OS. Then, the current mirror 12 can have a coefficient of 2 that can be enabled in the output stage OS.
[0033] If the output of the second inverter 24 is low, the third transistor 20 can be controlled to float or turn off. In the second phase, a smaller current can pass or flow through the output stage OS. Then, the current mirror 12 can have a coefficient of 1 that can be enabled in the output stage OS.
[0034] In other words, in the first phase, the coefficient 2 of the current mirror 12 is enabled, and in the second phase, the coefficient 1 of the current mirror 12 is enabled. Hysteresis is achieved by this switching. In one example, the circuit can have an offset value of about 22 mV.
[0035] This configuration can make the comparator 10 robust against noise and undesired switching. In addition, the above configuration can increase the switching speed between the first phase and the second phase.
[0036] Furthermore, according to an embodiment, the input stage IS may include the first input transistor 26 and the second input transistor 28 as described above. The first input transistor 26 may be different from the second input transistor 28. For example, the term “the first input transistor may be different from the second input transistor” may mean that the channel width of the first input transistor 26 is different from, for example, greater than, the channel width of the second input transistor. The conductivity type of the first input transistor 26 may be the same as the conductivity type of the second input transistor 28, for example, both are NMOS.
[0037] For example, the second input transistor 28 can be smaller than the first transistor 26. The second input transistor 28 can be connected to the switch input. This can increase the switching speed. The first transistor 26 can be connected to the reference terminal because the threshold voltage can be lower and therefore, more operating space can be available for the bias transistor 34. This can keep the current source constant and stable in the saturation state. Both effects can achieve fast switching.
[0038] The comparator 10 may include a Figure 1 A control inverter 30 and a control transistor 32 are shown. These elements may be included in the output stage OS. The output of the second inverter 24 may be fed to the gate terminal of the control transistor 32 via the control inverter 30. The control transistor 32 may control the switching of the third transistor 30 according to the output of the second converter 24.
[0039] The control transistor 32 may be implemented as an NMOS transistor. A source terminal of the control transistor 32 may be connected to Vss (eg, GND).
[0040] In addition, the bias transistor 34, the first input transistor 26, the second input transistor 28, the first transistor 16, the second transistor 18, the third transistor 20 and the control transistor 32 may also be implemented as NMOS transistors. According to another example, these transistors may also be implemented as PMOS transistors.
[0041] Figure 2 An example of the voltage characteristic of a comparator is shown. Figure 2 Reference signal S1, switch input signal S2, and output signal S4 are shown. At about the moment when S2 and S1 intersect, output S4 switches from high (HIGH) to low (LOW), or from low to high. Due to the hysteresis of the specific configuration discussed in this article, this means that the switch to high is delayed after S2 is greater than S1. On the other hand, S4 is switched to low before S2 is less than S1. The voltage difference between S2 and S1 that causes the switch to occur is called the offset voltage ΔV. For example, ΔV can be less than 50 mV and greater than 5 mV. For example, ΔV can be approximately 15 to 25 mV (e.g., 22 mV).
[0042] As described above, due to the hysteresis of the comparator described herein, noise can be suppressed. The comparator can operate at high speed. The comparator can be implemented at low voltage, thereby reducing energy consumption. The comparator can have a smaller size. Therefore, the comparator can be used in mobile devices. Figure 3 An example of an electronic device 11 is shown that includes the comparator 10. The electronic device may be implemented with a laser driver, smart glasses, or a mobile device.
[0043] Although multiple embodiments of the present invention have been described above, it is clear that there are more embodiments that can be implemented. For example, other embodiments may include any sub-combination of the features described in the claims, or any sub-combination of the elements described in the examples above. Therefore, the spirit and scope of the appended claims should not be limited to the description of the embodiments contained herein.
[0044] Reference numerals list
[0045] 10. Comparator
[0046] 11 Electronic devices
[0047] 12 Current mirror
[0048] 14 nodes
[0049] 16. First transistor
[0050] 18 Second transistor
[0051] 20Third transistor
[0052] 22 First Inverter
[0053] 24 Second inverter
[0054] 26 First input transistor
[0055] 28 Second input transistor
[0056] 30 Control inverter
[0057] 32 control transistor
[0058] 34 Bias transistor
[0059] IS Input Stage
[0060] OS output stage
[0061] GS Gain Stage
[0062] S1 input signal
[0063] S2 input signal
[0064] S3 differential current signal
[0065] S4 output signal.
Claims
1. A comparator (10), comprising: an input stage (IS) configured to receive a pair of input signals (S1, S2) to generate at least one differential current signal (S3); an output stage (OS) configured to generate an output signal (S4) according to a differential current signal (S3), the output stage (OS) comprising a current mirror (12) and a node (14) electrically connected to the current mirror (12), the current mirror (12) comprising a first transistor (16), a second transistor (18) and a third transistor (20), the second transistor (18) and the third transistor (20) being connected in parallel; and a gain stage (GS) comprising a first inverter (22) and a second inverter (24), wherein the output of the first inverter (22) is input to the second inverter (24), The output of the second inverter (24) is configured to control the third transistor (20) to be in a floating state or a conducting state.
2. The comparator (10) according to claim 1, wherein: If the output of the second inverter (24) is high, the third transistor (20) is controlled to be turned on.
3. The comparator (10) according to claim 1 or 2, wherein: If the output of the second inverter (24) is low, the third transistor (20) is controlled to float.
4. The comparator (10) according to any one of the preceding claims, wherein: The input stage (IS) comprises a first input transistor (26) and a second input transistor (28), the first input transistor (26) being different from the second input transistor (28).
5. The comparator (10) according to any one of the preceding claims, further comprising a control inverter (30) and a control transistor (32), wherein: The output of the second inverter (24) is fed to the gate terminal of the control transistor (32) via the control inverter (30).
6. The comparator (10) according to claim 5, wherein: The control transistor (32) is implemented as an NMOS transistor.
7. An electronic device (11) comprising a comparator (10) according to any one of the preceding claims.
8. The electronic device (11) according to claim 7, which is implemented as a laser driver, smart glasses or a mobile device.