IO expansion circuit

Abstract

The invention provides an IO expansion circuit, which is suitable for being connected between an MCU and an interface chip, is used for expanding IO for the MCU, and comprises a signal pin, a channel input and output management module, a signal channel, a register configuration interface, an interrupt interface and a DMA interface, the signal pin is used for connecting the interface chip with the channel input / output management module and driving the interface chip to perform information interaction with the MCU; the channel input and output management module is used for managing input and output signals of the signal channel, transmitting the signals output by the signal channel to the signal pin, and transmitting the signals input by the signal pin to the signal channel; the signal channel is used for controlling sending and receiving of data. According to the IO expansion circuit, a CPU or a communication port does not need to participate in driving an interface chip to send data and compare received data, CPU resources are saved, and data missing or data sending timeout cannot occur.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and in particular to an IO expansion circuit. Background Art

[0002] As the electrification and unmanned driving of automobiles become increasingly popular, the application systems of automotive microprocessors (MCUs) are becoming increasingly complex. This has led to a significant increase in the demand for input and output port (IO) resources on the MCU chip. At the same time, the MCU itself is unable to provide abundant IO resources for all applications due to reasons such as area, power consumption, cost, and product positioning. Therefore, expanding IO has become an indispensable means. The main purpose of expanding IO is to strengthen the control of external input and output when the IO resources on the MCU chip are scarce, such as input comparison of external parallel IO, parallel output control of external IO, etc. At present, the common means of expanding IO resources is to add an interface chip to the MCU, such as parallel interface chips, serial interface chips, I2C bus chips, SPI bus chips, and interrupt controller chips.

[0003] There are usually two solutions for the interaction between MCU and interface chip. One is that the CPU in MCU directly intervenes, driving the on-chip GPIO to periodically send data to the interface chip to drive the external circuit, receive the IO data of the interface chip and store the received data in its own memory, and trigger corresponding actions according to the received data or data changes. In this solution, a large amount of CPU resources will be occupied, and due to the limitation of other tasks of the CPU, the interface chip will be driven slowly and the time interval is too long, resulting in missing data or timeout of sending IO data. Secondly, in this solution, if the double data rate mode (DDR) is to be implemented to transmit data, the differential mode is generally used to reduce electromagnetic interference (EMI). If the single data rate mode (SDR) is used to transmit data, the spread spectrum clock (SSC) method is generally used to reduce the electromagnetic interference (EMI) generated by the signal. Considering the influence of EMC, these two ways of transmitting data will increase CPU resource consumption and may cause problems such as limited clock rate and poor accuracy. The second is to use communication ports such as SPI and I2C to receive IO data from the interface chip. Although this solution reduces CPU intervention, the communication rate of the communication port cannot be changed in real time, the received data is limited, and the data cannot be compared in real time. After receiving a certain amount of IO data, the CPU is still required to participate in detecting and comparing the data, and determine whether to start the communication port again to obtain IO data based on the comparison results. Therefore, this solution may still miss IO data and occupy some CPU resources. In addition, communication ports such as I2C generally only have SDR mode, do not support DDR mode, and cannot adapt to interface chips that support DDR mode. Secondly, this type of communication port generally cannot achieve the ability to spread the clock spectrum, and the generated clock signal is easily affected by electromagnetic interference, which reduces the stability of the system. Summary of the invention

[0004] The object of the present invention is to provide an IO expansion circuit, which does not require a CPU or a communication port to drive an interface chip to send and receive data, thereby saving CPU resources and preventing data omission or data transmission timeout.

[0005] To achieve the above object, the present invention provides the following technical solutions: The present invention provides an IO expansion circuit, which is suitable for being connected between an MCU and an interface chip and is used for expanding the IO of the MCU. The IO expansion circuit comprises a signal pin, a channel input and output management module, a signal channel, a register configuration interface, an interrupt interface, and a DMA interface. The signal pin, the channel input and output management module, and the signal channel are connected in sequence. The signal channel is connected to the register configuration interface, the interrupt interface, and the DMA interface, and the register configuration interface, the interrupt interface, and the DMA interface are all connected in pairs. The signal pin is used to connect the interface chip to the channel input and output management module to drive the interface chip to perform information exchange with the MCU. The channel input and output management module is used to connect the interface chip to the channel input and output management module to drive the interface chip to perform information exchange with the MCU. The device is used to manage the input and output signals of the signal channel, transmit the signal output by the signal channel to the signal pin, and also transmit the signal input by the signal pin to the signal channel; the signal channel is used to control the sending and receiving of data; the register configuration interface is used to accept user configuration parameters, conditions, and functions, send the user's configuration to the signal channel and start the signal channel, and receive the status flag and data of the signal channel for user query; the interrupt interface is used to determine whether the interrupt trigger condition is met according to the interrupt trigger condition configured by the user and generate an interrupt request to send to the MCU, and the DMA interface is used to determine whether the DMA trigger condition is met according to the DMA trigger condition configured by the user and generate a DMA request to send to the MCU.

[0006] In one embodiment, the signal pins have multiple groups, which are respectively connected to different types of interface chips; the signal channels have multiple groups, which correspond one-to-one to the groups of signal pins.

[0007] In one embodiment, each group of signal pins includes a clock signal, a control signal, and multiple data signals. Each data signal is connected to an interface chip of the same type, and multiple interface chips of the same type share the clock signal and the control signal.

[0008] In one embodiment, the signal channel includes a synchronizer, a shift position control generating module, a clock generating module, a control logic module, a receiving FIFO, a transmitting FIFO, a shifter and a comparator. The synchronizer is connected to the register configuration interface, the shift position control generating module, the clock generating module and the control logic module. The shift position control generating module and the clock generating module are also connected to the channel input and output management module. The control logic module is connected to the shift position control generating module, the clock generating module, the shifter and the comparator. The shifter is also connected to the receiving FIFO, the transmitting FIFO, the clock generating module, the comparator and the channel input and output management module. The synchronizer is used to synchronize the signal sent by the register configuration interface to the clock domain inside the signal channel, and also The signal inside the signal channel is synchronized to the register configuration interface; the shift position control generation module is used to generate a control signal under the management of the control logic module, and the control signal can drive the interface chip to latch the data on the external IO connected to the interface chip into the interface chip, or drive the interface chip to send the data sent by the MCU to the external IO connected to the interface chip; the clock generation module is used to generate a clock signal to drive the interface chip under the management of the control logic module; the shifter module cooperates with the sending FIFO and the receiving FIFO, and sends and receives data under the clock signal generated by the clock generation module and the management of the control logic module, and has two modes: SDR and DDR; the comparator is used to receive the data transmitted by the shifter, and compares it under the management of the control logic module to generate a corresponding interrupt request or DMA request.

[0009] In one embodiment, the comparator includes a converter, a cache unit, a comparison unit, a rising edge detection unit, a falling edge detection unit, an OR gate, a logic and judgment unit, a logic or judgment unit, a first selector, a second selector, and a third selector. The converter is connected to the shifter, the control logic module, the cache unit, and the comparison unit, receives data sent by the shifter, converts the data according to the length of the data to be compared and the data bit to be compared sent by the control logic module, outputs the converted data, and sends it to the cache unit and the comparison unit; the comparison unit is also connected to the third selector. , compare the converted data with the preset value, generate an intermediate comparison result and send it to the third selector; the cache unit is connected to both the rising edge detection unit and the falling edge detection unit, receives the converted data, and outputs the first data to be compared, the second data to be compared, and the edge detection enable signal after receiving the two sets of converted data, and sends them to the rising edge detection unit and the falling edge detection unit; the rising edge detection unit is also connected to the OR gate and the first selector, and generates a rising edge detection result according to the first data to be compared, the second data to be compared, and the edge detection enable signal and sends it to the rising edge detection unit and the falling edge detection unit. to the OR gate and the first selector; the falling edge detection unit is also connected to the OR gate and the first selector, and generates a falling edge detection result according to the first data to be compared, the second data to be compared, and the edge detection enable signal, and sends it to the OR gate and the first selector; the first selector is also connected to the logic and judgment unit and the logic or judgment unit, and generates an edge detection result according to the rising edge detection result, the falling edge detection result, the output of the OR gate and the edge detection type signal, and outputs it to the logic and judgment unit and the logic or judgment unit; the logic and judgment unit is also connected to the second selector, and generates a logic and judgment result according to the edge detection result and sends it to the second selector; the logic or judgment unit is also connected to the second selector, and generates a logic or judgment result according to the edge detection result and sends it to the second selector; the second selector is also connected to the third selector, and generates a logic judgment result according to the logic and judgment result, the logic or judgment result and the logic judgment type signal and sends it to the third selector; the third selector generates a final comparison result according to the intermediate comparison result, the logic judgment result and the comparison type signal.

[0010] In one embodiment, the clock generation module has two working modes: a global clock mode and a real-time clock mode. The global clock mode generates a clock according to the period and duty cycle information of the global clock configured by the user in the global clock configuration register. The real-time clock mode generates a clock according to the period and duty cycle information of the global clock configured by the user in the global clock configuration register and the period, duty cycle, and clock sequence number information of the real-time clock configured in the real-time clock configuration register. The global clock configuration register and the real-time clock configuration register are both located in the register configuration interface.

[0011] In one implementation, the clock generation module has a clock spreading function unit, and the clock spreading function unit provides three types of spreading: intermediate spreading, downward spreading, and upward spreading.

[0012] In one embodiment, the clock spreading function unit has a spreading rate, and the spreading rate can be configured as a fixed value or a random value.

[0013] In one implementation, the IO expansion circuit is integrated into the MCU; or the IO expansion circuit is independent and self-contained.

[0014] In one implementation, the interface chip includes a parallel interface chip, a serial interface chip, an I2C bus chip, an SPI bus chip, or an interrupt controller chip.

[0015] Compared with the prior art, the technical solution of the present invention has the following beneficial effects: The IO expansion circuit of the present invention does not require the CPU or the communication port to drive the interface chip to send data and compare received data, thus saving CPU resources and preventing data omission or data sending timeout. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative work.

[0017] Figure 1 A structural block diagram of an IO expansion circuit provided in a first embodiment of the present invention; Figure 2 for Figure 1 The internal circuit diagram of the comparator in FIG. Figure 3 This is a timing diagram of an interface chip in one embodiment of the present invention; Figure 4 This is a timing diagram of a driving interface chip according to an embodiment of the present invention; Figure 5 A timing diagram for configuring a driving interval according to an embodiment of the present invention; Figure 6 A timing diagram for adjusting the clock period and duty cycle in real time according to an embodiment of the present invention; Figure 7 This is a timing diagram of enabling the clock spread spectrum function according to an embodiment of the present invention; Figure 8 A timing diagram of supporting DDR mode according to an embodiment of the present invention; Fig. 9 A timing diagram for selecting a specific IO for comparing data according to an embodiment of the present invention; Fig.10 A timing diagram showing comparison data to an expected value according to an embodiment of the present invention; Fig.11 A timing diagram for comparing full data edge matching according to an embodiment of the present invention; Fig.12 FIG. 1 is a timing diagram for comparing arbitrary matching of data edges according to an embodiment of the present invention. DETAILED DESCRIPTION

[0018] The technical solutions in the embodiments of the present invention will be described clearly and completely below. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments in the present invention, all other embodiments obtained by those skilled in the art without creative work belong to the scope of protection of the present invention. It should be noted that the description order of the following embodiments is not used as a limitation on the preferred order of the embodiments of the present invention. In the following embodiments, the description of each embodiment has its own emphasis. For the parts that are not described in detail in a certain embodiment, please refer to the relevant description of other embodiments.

[0019] See also Figure 1As shown, the first embodiment of the present invention provides an IO expansion circuit, which is suitable for being connected between an MCU and an interface chip, and is used to expand the IO of the MCU. The IO expansion circuit includes a signal pin 10, a channel input and output management module 20, a signal channel 30, a register configuration interface 40, an interrupt interface 50, and a DMA interface 60. The signal pin 10, the channel input and output management module 20, and the signal channel 30 are connected in sequence, and the signal channel 30 is connected to the register configuration interface 40, the interrupt interface 50, and the DMA interface 60, and the register configuration interface 40, the interrupt interface 50, and the DMA interface 60 are connected in pairs; the signal pin 10 is used to connect the interface chip to the channel input and output management module to drive the interface chip to exchange information with the MCU; the channel The input and output management module 20 is used to manage the input and output signals of the signal channel 30, transmit the signal output by the signal channel 30 to the signal pin 10, and also transmit the signal input by the signal pin 10 to the signal channel 30; the signal channel 30 is used to control the sending and receiving of data; the register configuration interface 40 is used to accept user configuration parameters, conditions, and functions, send the user's configuration to the signal channel 30 and start the signal channel 30, receive the status flag and data of the signal channel 30 for user query; the interrupt interface 50 is used to determine whether the interrupt trigger condition is met according to the interrupt trigger condition configured by the user and generate an interrupt request to send to the MCU, and the DMA interface 60 is used to determine whether the DMA trigger condition is met according to the DMA trigger condition configured by the user and generate a DMA request to send to the MCU.

[0020] The IO expansion circuit of the present invention controls the sending and receiving of data through its own signal channel 30, and does not need the CPU or communication port to drive the interface chip to send and receive data, thereby saving CPU resources and preventing data omission or data sending timeout.

[0021] The IO expansion circuit of the present invention can be integrated into the MCU or can be independently integrated, and the selection can be made according to actual needs.

[0022] The interface chip may include any one or more of a parallel interface chip, a serial interface chip, an I2C bus chip, an SPI bus chip or an interrupt controller chip.

[0023] In one embodiment, the signal pins 10 have multiple groups, which are respectively connected to different types of interface chips; the signal channels 30 have multiple groups, which correspond one to one with the groups of the signal pins 10. That is, the signal pin 10 group 0 can be connected to the interface chip 0, the signal pin 10 group 1 can be connected to the driver interface chip 1, and so on. This application scenario can improve the utilization rate of the IO expansion system and enhance the performance of the application system. In one embodiment, each group of signal pins 10 includes a clock signal, a control signal, and multiple data signals. Each data signal is connected to an interface chip of the same type, and multiple interface chips of the same type share the clock signal and the control signal. The user can select the corresponding number of signal pin 10 groups and the number of data signals in the signal pin 10 through configuration (register configuration interface 40) according to the type and number of interface chips to be connected.

[0024] The channel input and output management module 20 is used to manage the input and output signals of all signal channels 30 in the device, send the output signals of all signal channels 30 in the device to the signal pins 10, and also receive the signals input from the signal pins 10 and distribute them to the corresponding signal channels 30.

[0025] The register configuration interface 40 is used to allow the user to configure various parameters, conditions, functions, etc. of the device (IO expansion circuit of the present invention), such as output clock frequency, duty cycle, control signal establishment time, hold time, data comparison size, type, etc. The register configuration interface 40 interacts with the signal channel 30 to send the user's configuration to the corresponding signal channel 30 and start the signal channel 30, and at the same time receive the status flags and received data of all signal channels 30, so as to facilitate user query.

[0026] The interrupt interface 50 determines whether the interrupt trigger condition is met according to the interrupt trigger condition configured by the user, wherein the interrupt trigger condition includes, for example: transmission completion trigger interrupt, reception completion trigger interrupt, transmission FIFO 37 of signal channel 30 is empty, reception FIFO 38 of signal channel 30 is full, etc. The interrupt interface 50 obtains the status flag of the device from the register configuration interface 40, and determines whether the interrupt trigger condition is met, thereby determining whether to generate an interrupt request.

[0027] The DMA interface 60 determines whether the DMA trigger condition is met according to the DMA trigger condition configured by the user, wherein the DMA trigger condition includes, for example, the sending FIFO 37 of the signal channel 30 is empty, the receiving FIFO 38 of the signal channel 30 is full, etc. The DMA interface 60 obtains the status flag of the device from the register configuration interface 40, and determines whether the DMA trigger condition is met, thereby determining whether to generate a DMA request to send to the DMA controller of the MCU.

[0028] The signal channels 30 are described in detail below. There are multiple signal channels 30, corresponding to the number of groups of signal pins 10, that is, one signal channel 30 corresponds to one group of signal pins 10. All signal channels 30 have the same structure, and any signal channel 30 is used as an example below. In one embodiment, the signal channel 30 includes a synchronizer 31, a shift position control generation module 32, a clock generation module 33, a control logic module 34, a receiving FIFO 38, a transmitting FIFO 37, a shifter 36 and a comparator 35. The synchronizer 31 is connected to the register configuration interface 40, the shift position control generation module 32, the clock generation module 33, and the control logic module 34. The shift position control generation module 32 and the clock generation module 33 are also connected to the channel input and output management module 20. The control logic module 34 is connected to the shift position control generation module 32, the clock generation module 33, the shifter 36, and the comparator 35. The shifter 36 is also connected to the receiving FIFO 38, the transmitting FIFO 37, the clock generation module 33, the comparator 35, and the channel input and output management module 20. The synchronizer 31 is used to synchronize the signal sent by the register configuration interface 40. to the clock domain inside the signal channel 30, and also synchronizes the signal inside the signal channel 30 to the register configuration interface 40; the shift position control generating module 32 is used to generate a control signal under the management of the control logic module 34, and the control signal can drive the interface chip to latch the data on the external IO connected to the interface chip into the interface chip, or drive the interface chip to send the data sent by the MCU to the external IO connected to the interface chip; the clock generating module 33 is used to generate a clock signal to drive the interface chip under the management of the control logic module 34; the shifter 36 module cooperates with the sending FIFO 37 and the receiving FIFO 38, and sends and receives data under the clock signal generated by the clock generating module 33 and the management of the control logic module 34, with two modes of SDR and DDR; the comparator 35 is used to receive the data transmitted by the shifter 36, and compare it under the management of the control logic module 34 to generate a corresponding interrupt request or DMA request.

[0029] The synchronizer 31 is used to synchronize the control signal sent from the register configuration interface 40 to the clock domain inside the signal channel 30, and also synchronize the signal inside the signal channel 30 to the register configuration interface 40 to avoid signal metastable propagation.

[0030] The shift position control generation module 32 is used to generate a control signal, which can drive the interface chip to latch the external IO data connected to it into the interface chip, or drive the interface chip to send the data sent by the device to the external IO connected to it. The generation process of the control signal is that the shift position control generation module 32 first obtains the relevant configuration from the register configuration interface 40, and then generates the control signal required by the user under the management of the control logic module 34. The polarity of the control signal is user-configurable, that is, the user can configure the initial level of the control signal to be high level, and low level is valid. Or the initial level is low level, and high level is valid. Secondly, the user can configure the time when the control signal is generated, for example: 1. The control signal needs to be generated before the clock, 2. The control signal needs to be generated after all current clocks end, 3, The control signal needs to be generated after a certain clock at the current time. At the same time, when configuring the generation time of the control signal, the user can configure the interval between the control signal and the clock signal to meet the establishment time and holding time of the interface chip. In addition, the user can configure the width of the control signal generation, that is, if the initial level is configured to be high level and low level is valid, the user can configure the width of the low level. These configurations are all stored in the register configuration interface 40 .

[0031] The clock generation module 33 is used to generate a clock signal to drive the external interface chip. The module obtains relevant configurations from the register configuration interface 40, and generates the required clock signal under the management of the control logic module 34. At the same time, the module generates the corresponding clock signal for the shifter 36 to receive and send data. The device provides a global clock configuration register for configuring the cycle and duty cycle of the global clock. In addition, the device provides a series of real-time clock configuration registers, which support up to 8, for real-time adjustment of the cycle and duty cycle of a specific clock. Each real-time clock configuration register contains information such as cycle, duty cycle, clock sequence number, etc., which is used to configure the cycle and duty cycle of a specific clock. The clock generation module 33 has two working modes: 1. The clock real-time adjustment function is turned off (i.e., global clock mode), the user configures the global clock configuration, and the clock generation module 33 generates the clock according to the cycle and duty cycle information of the global clock configuration. 2. The clock real-time adjustment function is turned on (i.e., real-time clock mode), the user configures the global clock configuration and the real-time clock configuration, and the clock generation module 33 selects a specific cycle and duty cycle configuration according to these configurations to generate the clock. In addition, the clock polarity can also be configured, and the user can configure the clock to be high effective or low effective. These configuration registers are also located in the register configuration interface 40.

[0032] In one implementation, the clock generation module 33 has a clock spreading function unit (SSC), which provides three types of spreading: intermediate spreading, downward spreading, and upward spreading.

[0033] The clock spread spectrum function unit provides a clock spread spectrum function, which can effectively reduce the EMI of the clock signal and reduce the EMC impact to cope with complex application systems. It should be noted that it is recommended to turn off the real-time clock adjustment function when using this function.

[0034] The clock spread function supports three types of intermediate spread, downward spread and upward spread, and its spread rate is δ. The spread rate can be generated in the following two ways: 1. The user writes (fixed value) through the register configuration interface 40, which is a linear spread; 2. The user writes the spread rate through the register configuration interface 40 and turns on the spread rate random generation function (random value). The device uses a pseudo-random number to randomly generate a value within the spread range for generating a clock signal. It should be noted that in the second method, the period and duty cycle of each clock signal are randomly generated (within the spread rate range), and the spread rate is applicable to both the period and the duty cycle. The intermediate spread means that after the device obtains information such as the frequency fc (i.e., clock period information), the duty cycle ŋ, the spread rate and the number of clocks in the driving period, it will generate a set of clock signals with a frequency between (1-δ)fc—(1+δ)fc and a duty cycle between (1-δ) ŋ—(1+δ) ŋ. The downward spread spectrum means that after the device obtains information such as frequency fc, duty cycle ŋ, spread ratio and the number of clocks in the driving cycle, it will generate a set of clock signals with frequencies between (1-δ)fc-fc and duty cycles between (1-δ) ŋ- ŋ. The upward spread spectrum means that after the device obtains information such as frequency fc, duty cycle ŋ, spread ratio and the number of clocks in the driving cycle, it will generate a set of clock signals with frequencies between fc-(1+δ)fc and duty cycles between ŋ- (1+δ)ŋ.

[0035] The control logic module 34 is the main core control unit inside the signal channel 30. The control logic module 34 cooperates with the shift position generating module, clock generating module 33, shifter 36 and comparator 35 inside the signal channel 30 to generate specific clock signals and control signals to realize data sending, receiving and comparison, etc.

[0036] The shifter 36 cooperates with the transmission FIFO 37, the reception FIFO 38, the clock generation module 33 and the control logic module 34 to realize the transmission and reception of data, and supports SDR and DDR modes. The number of shift registers inside the shifter 36 corresponds to the number of data signals in the signal channel 30. The number of data signals in the signal channel 30 is configurable, for example, the data signal is 3. The user can configure any combination of the input and output of the three data signals, for example, data signal 0 is the transmission data, and data signals 1 and 2 are the reception data. The transmission FIFO 37 and the reception FIFO 38 are carriers for storing data, and their storage content is data and data signal identifiers. The data signal identifier is used to distinguish which data signal the data belongs to.

[0037] The following example illustrates the data transmission and reception process. The number of bits of data in the example is 32. The process of signal channel 30 sending data is as follows: the user writes the data to be sent sequentially into the sending FIFO37 through the register configuration interface 40. The size of the data written at a time is 1-32 bits, and the high bits less than 32 bits are padded with zeros. The shifter 36 reads the transmission data in sequence according to the number of signals of the transmission data and saves it to the corresponding shift register. The clock generation module 33 sends the clock signal into the shifter 36. The control logic module 34 drives the shifter 36 to output the data to the data signal bit by bit at the rising edge, falling edge, and double edge (DDR mode) of the clock according to the user configuration.

[0038] The process of signal channel 30 receiving data is as follows: the clock generation module 33 sends the clock signal into the shifter 36, and the control logic module 34 latches the data signal to the corresponding shifter 36 at the rising edge, falling edge, and both edges (DDR mode) of the clock according to the user configuration. If the write function of the receiving FIFO 38 is turned on and the received data has reached 32 bits, the shifter 36 will write the data plus the data signal identifier into the receiving FIFO 38 in sequence.

[0039] The comparator 35 is mainly used to compare the changes of the received data and generate a corresponding interrupt request or DMA request. The comparator 35 receives the data input by the shifter 36, and obtains the size and type of the data from the control logic module 34, and compares the received data.

[0040] See also Figure 2As shown, in one embodiment, the comparator 35 includes a converter 351, a cache unit 353, a comparison unit 352, a rising edge detection unit 354, a falling edge detection unit 355, an OR gate 356, a logic and judgment unit 358, a logic or judgment unit 359, a first selector 357, a second selector 361, and a third selector 362. The converter 351 is connected to the shifter 36, the control logic module 34, the cache unit 353, and the comparison unit 352, receives the data sent by the shifter 36, converts the data according to the length of the data to be compared and the data bit to be compared sent by the control logic module 34, outputs the converted data, and sends it to the cache unit The comparison unit 352 is connected to the third selector 362, compares the converted data with the preset value, generates an intermediate comparison result and sends it to the third selector 362; the cache unit 353 is connected to the rising edge detection unit 354 and the falling edge detection unit 355, receives the converted data, and outputs the first data to be compared, the second data to be compared, and the edge detection enable signal to the rising edge detection unit 354 and the falling edge detection unit 355 after receiving the two sets of converted data; the rising edge detection unit 354 is also connected to the OR gate 356 and the first selector 357, and generates an intermediate comparison result according to the first set of data to be compared. The comparison data, the second data to be compared, and the edge detection enable signal generate a rising edge detection result and send it to the OR gate 356 and the first selector 357; the falling edge detection unit 355 is also connected to the OR gate 356 and the first selector 357, and generates a falling edge detection result according to the first data to be compared, the second data to be compared, and the edge detection enable signal and sends it to the OR gate 356 and the first selector 357; the first selector 357 is also connected to the logic and judgment unit 358 and the logic or judgment unit 359, and generates a falling edge detection result according to the rising edge detection result, the falling edge detection result, the output of the OR gate 356, and the edge detection type. The edge detection result generated by the type signal is output to the logic and judgment unit 358 and the logic or judgment unit 359; the logic and judgment unit 358 is also connected to the second selector 361, and generates a logic and judgment result according to the edge detection result and sends it to the second selector 361; the logic or judgment unit 359 is also connected to the second selector 361, and generates a logic or judgment result according to the edge detection result and sends it to the second selector 361; the second selector 361 is also connected to the third selector 362, and generates a logic judgment result according to the logic and judgment result, the logic or judgment result and the logic judgment type signal and sends it to the third selector 362;The third selector 362 generates a final comparison result (hereinafter also referred to as a matching signal) and outputs it according to the intermediate comparison result, the logic judgment result and the comparison type signal. ;

[0041] The comparator 35 can compare various data sizes, not limited to 8 / 16 / 32 bits, and supports comparison of specific data. For example, if the data comparison size is 8 bits, the user can configure any combination of the 8 bits to be compared, such as bit0 / bit3 or bit1 / bit3 / bit7.

[0042] The comparator 35 supports two types of comparison: 1. Whether the data is an expected value; 2. Whether there is a change before and after the data. The second type can be divided into three types of changes: 1. Rising edge change (0->1); 2. Falling edge change (1->0); 3. Any edge change. For the second type, the user can set the specific change of each bit, such as bit0 has a falling edge change, bit3 has a rising edge change, and bit7 has an arbitrary edge change. The comparator 35 will detect whether there is a corresponding change before and after the received data. In addition, the comparator 35 also supports two data comparison requirements: 1. All bits are compared to meet the change; 2. Any bit in the comparison bit meets the change. For example, the data comparison size is 8 bits, and the comparison bit is bit0 / bit3 / bit7. The user can configure bit0 / 3 / 7 to meet the change or any one or more of bit0 / bit3 / bit7 meet the change, and the comparison is successful. At the same time, the comparator 35 updates the data comparison status in real time, and finally sends the status to the register configuration interface 40.

[0043] The signal channel 30 supports the functions of automatically driving the interface chip and comparing the received data in real time, and these two functions can be used at the same time. After both functions are turned on, the signal channel 30 will compare the received data (the comparison conditions are configured by the user). That is, the signal channel 30 drives the interface chip in the first drive cycle, obtains the received data and sends it to the comparator 35. One of the drive cycles refers to the signal channel 30 generating a control signal, a number of clock signals, and receiving all the data latched inside the interface chip. After receiving the data in a drive cycle, the shifter 36 will send the received data to the comparator 35 for real-time comparison. It should be noted that if the user configures the comparison condition to determine whether the received data is an expected value, the comparator 35 will compare every time. When the user configures the comparison condition to determine whether the data changes before and after, the comparator 35 needs to start comparing after receiving the two batches of data before and after. And the comparator 35 only compares the latest two batches of data before and after, that is, compares the changes in the data of the two most recent batches. In addition, after the data meets the comparison conditions, the device will generate an interrupt request or a DMA request report to the system. It should be noted that when the data meets the comparison conditions, since the function of the automatic driving interface chip is turned on, the device will continue to drive the interface chip, obtain real-time data and send it to the comparator 35 for real-time comparison. The data comparison state will be updated in real time without losing the previous comparison state. In addition, the user can set the interval between two driving cycles, that is, after the first driving cycle ends, the signal channel 30 will delay a certain time interval (user configuration, control logic module 34 implementation) before starting the next driving cycle. When the automatic driving interface chip is not turned on, and the real-time comparison data function is turned on, the device will stop driving the interface chip after the data meets the expected conditions.

[0044] The following will take a mainstream interface chip as a specific embodiment, and combine Figure 3-Figure 12 The function of the IO expansion circuit of the present invention is described in detail. The interface chip is an interface chip that supports 8 IO parallel inputs / serial inputs and one serial output. The timing diagram of the interface chip is Figure 3 .exist Figure 3It can be seen that the interface chip latches the IO data on the interface chip when the sh / ld signal (control signal) is low, and shifts the internal latched data to the device at the rising edge of the clock. The io_data in the figure is the io data connected to the interface chip, and the data change is related to the external io; q in the figure is the output of the interface chip. The io_data data change and change speed in the figure are only for the convenience of understanding and display, and do not represent the real change of the actual IO. In theory, the change frequency of the external IO should be slower than the internal clock frequency (clk). The application scenario of this interface chip is to connect 8 external IOs in parallel to the interface chip, and the MCU regularly controls the interface chip to latch the level status of 8 IOs, and generates a clock to send these 8 IO level statuses to the internal storage of the MCU. When the MCU detects that there is a difference in the level status of the 8 IOs between two times or that the IO data is the expected value once, the MCU will perform the corresponding action. At present, the commonly used driving interface chip solutions are mainly: 1. CPU drives GPIO to control the interface chip, 2. Control the interface chip through communication ports such as SPI. For the first solution, a large amount of CPU resources will be occupied to drive GPIO, and the MCU performance will be sharply reduced. For the second solution, it does not support automatic comparison of IO level status, clock spread spectrum function and DDR mode, and requires CPU intervention after receiving. The circuit of this device can better drive the interface chip, flexibly configure, and does not need to occupy CPU resources.

[0045] In this embodiment, the user configures the device to generate the required clock frequency and SH / LD control signal to meet the setup time and hold time of the interface chip. At the same time, the comparison function and the automatic interface chip drive function are turned on, and the comparison size and type of the IO data are configured. After the configuration is completed, the circuit of the device will automatically drive the interface chip in a loop, receive the IO data and compare it. When the comparison conditions are met, the interface chip will stop being driven and the CPU or DMA will be notified. When the comparison conditions are not met, the device circuit will drive the interface chip again to obtain the latest IO data status in real time and compare it. Figure 4 .

[0046] Figure 4 Only two complete processes of obtaining IO data are shown. Later, the device will automatically drive the interface chip again, compare the received data in real time, and notify the CPU or DMA when the data meets the comparison conditions. Figure 4 The automatic drive interface chip function is turned on in , that is, the device will repeatedly drive the interface chip until the device is turned off or the configuration is changed, compare the data in real time, and save the comparison status. In these two drive cycles, the clock frequency and duty cycle are fixed. Figure 4 In each complete cycle, the device obtains 8 IO data. The data obtained for the first time is 00010001, and the data obtained for the second time is 01010101. Figure 4 The second drive cycle starts after the first drive cycle ends, and the time interval is 0. This interval depends on the application requirements and can be configured by the user.

[0047] The user can configure the interval between the two drive cycles, such as Figure 5 The second driving cycle starts after the first driving cycle ends with a delay of 3 clock signals.

[0048] Users can also flexibly change the period and duty cycle of each clock in each drive cycle, supporting up to 8 clocks. Figure 6 As shown in the figure, the third clock cycle and duty cycle in the first driving cycle are specially configured by the user and are different from the other six clock cycles. In the second driving cycle, the cycle and duty cycle of the second clock are specially configured by the user, and the cycle and duty cycle are also different from the third clock cycle of the first driving cycle.

[0049] Users can also enable the clock spread spectrum function, such as Figure 7 In the first driving cycle, the clock spread spectrum function is turned on, and the spread spectrum value of each clock is randomly generated by the device (within the user configuration range). Figure 7 It can be seen that within a driving cycle, the period and duty cycle of the clock signal change randomly.

[0050] Since the interface chip does not support double data rate mode, the above figure only shows that one IO data is received in one clock cycle. However, the circuit of this device supports DDR mode, and its possible received data is as follows Figure 8 As shown. Figure 8 In SPI, data changes occur on both the rising and falling edges of the clock.

[0051] The user can configure the configuration of the comparator 35, such as configuring the specific serial number of the IO data to be compared. Since the interface chip supports a maximum of 8 IO inputs (i.e., 8-bit IO data), and when the user only wants to compare IO0 / IO3 / IO7 (i.e., bit0 / bit3 / bit7), the number of IO data comparisons can be configured as 8, and the mask value can be configured as 0x89 to compare only IO0 / IO3 / IO7. Fig. 9 As shown, in the first driving cycle, the device receives 8-bit data of 00010001. Since only IO0 / IO3 / IO7 are compared, the comparison data is 00000001. Only the comparison data bit is retained, and the remaining bits are 0, even if there is data on IO4.

[0052] In addition, users can configure two types of comparison: 1. Compare whether the IO data is the expected value; 2. Compare whether the IO data has changed compared to the previous time.

[0053] To compare whether the IO data is the expected value, the user only needs to write the expected value in advance and start the device. The circuit of this device will periodically obtain the IO data through the interface chip and compare it. When it is the same as the expected value, it will notify the CPU. Fig.10 .exist Fig.10 In the example, the expected value set by the user is 0x88, and the comparison IO is the value of all 8 IOs. Fig.10 It can be seen that when the second received IO data is 0x88, the device will generate a match signal match and report it to the CPU or DMA.

[0054] For the second case, the IO data changes can be divided into: 1. rising edge change (0->1); 2. falling edge change; 3. arbitrary edge change. Each IO data can be configured with a specific edge change. For example, IO0 needs to meet the rising edge change, and IO5 meets the falling edge change. When the comparator 35 detects that the level state of IO0 / IO5 in the two previous and subsequent data meets the above requirements, it will generate a match signal to notify the CPU or DMA.

[0055] In addition, when comparing multiple IO data, it can be divided into all IOs being satisfied or any one or more of the IOs being satisfied. For example, the interface chip supports a maximum of 8 IO parallel inputs, and the user only wants to compare IO0 / IO4 / IO7. At this time, the user can configure the change requirements of these three IO data (rising edge / falling edge / any edge), and at the same time can configure the satisfaction conditions to be that these three IO data changes are established at the same time or that one or more of these three IO data meet the conditions. After the circuit of this device detects the change of IO data, it compares it with the comparison conditions. If it meets the conditions, it notifies the CPU or DMA processing. Otherwise, it will continue to drive the interface chip to obtain real-time IO data. When the IO size is set to 8bit, the comparison IO is IO1 / IO3 / IO6, and the comparison type is to compare IO data changes and meet IO1 is a rising edge, IO3 is a falling edge, IO6 is a falling edge, and IO1 / IO3 / IO6 need to be met at the same time. Such as Fig.11 As shown in the figure, the data received by the device for the first time is 01001101, and the data received for the second time is 00110111. Since only IO1 / IO3 / IO6 are compared, and the rising edge of IO1 and the falling edge of IO3 / IO6 are satisfied at the same time, and other IO data are ignored, a match signal is generated to notify the CPU or DMA after the second data reception is completed and the comparison is successful. When the user configuration only requires any one of IO1 / IO3 / IO6 to meet the change, such as Fig.12The data received by this device for the first time is 01001101, and the data received for the second time is 01110101. It can be seen that only IO3 meets the falling edge change condition, and IO1 / IO6 do not meet the condition. However, since match_typ is 0, as long as any one of IO1 / 3 / 6 meets the condition, a match signal is generated to the CPU or DMA after the second data reception is completed and the comparison is successful.

[0056] Therefore, the IO expansion circuit of the present invention can be configured flexibly by the user to meet the requirements of IO expansion for different interface chips.

[0057] Compared with the prior art, the technical solution of the present invention has the following beneficial effects: The IO expansion circuit of the present invention does not require the CPU or communication port to drive the interface chip to send data and compare received data, which saves CPU resources and does not cause missing data or timeout in sending data. Moreover, the IO expansion circuit of the present invention supports clock spread spectrum function, supports DDR mode, supports automatic driving of interface chips, obtains IO real-time data, and compares whether the data meets the requirements according to the user-configured comparison type. The comparison conditions of the circuit of this device are diverse, basically covering the mainstream application requirements, and shortening the time interval of sampling data, reducing the probability of missing data. Compared with the current mainstream IO expansion solution, the circuit of this device has high flexibility, strong anti-interference ability, automation ability and higher efficiency.

[0058] The above is only a specific implementation of the present invention, but the protection scope of the present invention is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed by the present invention, which should be covered within the protection scope of the present invention. Therefore, the protection scope of the present invention shall be based on the protection scope of the claims. In addition, the specification uses specific examples to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only used to help understand the method of the present invention and its core idea. The content of this specification should not be understood as a limitation on the present invention.

Claims

1. An IO expansion circuit, suitable for connecting between an MCU and an interface chip, for expanding the IO of the MCU, characterized in that: The IO expansion circuit includes a signal pin, a channel input and output management module, a signal channel, a register configuration interface, an interrupt interface, and a DMA interface. The signal pin, the channel input and output management module, and the signal channel are connected in sequence. The signal channel is connected to the register configuration interface, the interrupt interface, and the DMA interface, and the register configuration interface, the interrupt interface, and the DMA interface are connected in pairs; the signal pin is used to connect the interface chip to the channel input and output management module to drive the interface chip to exchange information with the MCU; the channel input and output management module is used to manage the input and output signals of the signal channel, transmit the signal output from the signal channel to the signal pin, and also transmit the signal input from the signal pin to the signal channel; the signal channel is used to control the sending and receiving of data; the register configuration interface is used to accept user configuration parameters, conditions, and functions, send the user's configuration to the signal channel and start the signal channel, and receive the status flag and data of the signal channel for user query; The interrupt interface is used to determine whether the interrupt trigger condition is met according to the interrupt trigger condition configured by the user and generate an interrupt request to send to the MCU. The DMA interface is used to determine whether the DMA trigger condition is met according to the DMA trigger condition configured by the user and generate a DMA request to send to the MCU.

2. The IO expansion circuit according to claim 1, characterized in that: The signal pins have multiple groups, which are respectively connected to different types of interface chips; the signal channels have multiple groups, which correspond one to one to the groups of signal pins.

3. The IO expansion circuit according to claim 2, characterized in that: Each group of signal pins includes a clock signal, a control signal, and multiple data signals. Each data signal is connected to an interface chip of the same type, and multiple interface chips of the same type share the clock signal and the control signal.

4. The IO expansion circuit according to claim 2, characterized in that: The signal channel includes a synchronizer, a shift position control generating module, a clock generating module, a control logic module, a receiving FIFO, a transmitting FIFO, a shifter and a comparator. The synchronizer is connected to the register configuration interface, the shift position control generating module, the clock generating module and the control logic module. The shift position control generating module and the clock generating module are also connected to the channel input and output management module. The control logic module is connected to the shift position control generating module, the clock generating module, the shifter and the comparator. The shifter is also connected to the receiving FIFO, the transmitting FIFO, the clock generating module, the comparator and the channel input and output management module. The synchronizer is used to synchronize the signal sent from the register configuration interface to the clock domain inside the signal channel, and also synchronize the signal inside the signal channel to the register configuration interface. The shift position control generation module is used to generate a control signal under the management of the control logic module, and the control signal can drive the interface chip to latch the data on the external IO connected to the interface chip into the interface chip, or drive the interface chip to send the data sent by the MCU to the external IO connected to the interface chip; the clock generation module is used to generate a clock signal to drive the interface chip under the management of the control logic module; The shifter module cooperates with the sending FIFO and the receiving FIFO to send and receive data under the clock signal generated by the clock generation module and the management of the control logic module, and has two modes: SDR and DDR; the comparator is used to receive the data transmitted by the shifter, and compares it under the management of the control logic module to generate a corresponding interrupt request or DMA request.

5. The IO expansion circuit according to claim 4, characterized in that: The comparator includes a converter, a cache unit, a comparison unit, a rising edge detection unit, a falling edge detection unit, an OR gate, a logic and judgment unit, a logic or judgment unit, a first selector, a second selector, and a third selector. The converter is connected to the shifter, the control logic module, the cache unit, and the comparison unit, receives the data sent by the shifter, converts the data according to the length of the data to be compared and the data bit to be compared sent by the control logic module, outputs the converted data, and sends it to the cache unit and the comparison unit; the comparison unit is also connected to the third selector, compares the converted data with a preset value, generates an intermediate comparison result and sends it to the third selector; the cache unit is connected to the rising edge detection unit and the falling edge detection unit, receives the converted data, and after receiving the two sets of converted data, outputs the first data to be compared, the second data to be compared, and the edge detection enable signal and sends them to the rising edge detection unit and the comparison unit. A falling edge detection unit; the rising edge detection unit is also connected to the OR gate and the first selector, and generates a rising edge detection result according to the first data to be compared, the second data to be compared, and the edge detection enable signal, and sends it to the OR gate and the first selector; the falling edge detection unit is also connected to the OR gate and the first selector, and generates a falling edge detection result according to the first data to be compared, the second data to be compared, and the edge detection enable signal, and sends it to the OR gate and the first selector; the first selector is also connected to the logic and judgment unit and the logic or judgment unit, and generates an edge detection result according to the rising edge detection result, the falling edge detection result, the output of the OR gate, and the edge detection type signal, and outputs it to the logic and judgment unit and the logic or judgment unit; the logic and judgment unit is also connected to the second selector, and generates a logic and judgment result according to the edge detection result and sends it to the second selector; The logic or judgment unit is also connected to the second selector, and generates a logic or judgment result according to the edge detection result and sends it to the second selector; the second selector is also connected to the third selector, and generates a logic judgment result according to the logic and judgment result, the logic or judgment result and the logic judgment type signal and sends it to the third selector; The third selector generates a final comparison result output according to the intermediate comparison result, the logic judgment result and the comparison type signal.

6. The IO expansion circuit according to claim 4, characterized in that: The clock generation module has two working modes: a global clock mode and a real-time clock mode. The global clock mode generates a clock according to the period and duty cycle information of the global clock configured by the user in the global clock configuration register. The real-time clock mode generates a clock according to the period and duty cycle information of the global clock configured by the user in the global clock configuration register and the period, duty cycle, and clock sequence number information of the real-time clock configured in the real-time clock configuration register. The global clock configuration register and the real-time clock configuration register are both located in the register configuration interface.

7. The IO expansion circuit according to claim 4, characterized in that: The clock generation module has a clock spread spectrum function unit, and the clock spread spectrum function unit provides three types of spread spectrum: intermediate spread spectrum, downward spread spectrum, and upward spread spectrum.

8. The IO expansion circuit according to claim 7, characterized in that: The clock spreading function unit has a spreading rate, and the spreading rate can be configured as a fixed value or a random value.

9. The IO expansion circuit according to claim 1, characterized in that: The IO expansion circuit is integrated into the MCU; or the IO expansion circuit is independent and self-contained.

10. The IO expansion circuit according to claim 1, characterized in that: The interface chip includes a parallel interface chip, a serial interface chip, an I2C bus chip, an SPI bus chip or an interrupt controller chip.

Images