Integrated circuit layout generation method and device and storage medium

Abstract

The embodiment of the invention provides an integrated circuit layout generation method and device and a storage medium, and belongs to the technical field of integrated circuits. The method comprises the following steps: receiving a circuit layout design request; acquiring circuit layout design parameters in a preset layout design parameter library according to the circuit layout design request; wherein the circuit layout design parameters comprise silicon substrate well design parameters and connection line design parameters; screening out a target programming toolkit from preset candidate programming toolkits according to the silicon substrate well design parameters and the connection line design parameters; drawing the silicon substrate well on a preset circuit layout template through the target programming toolkit and the silicon substrate well design parameters to obtain a selected circuit layout; and performing metal wiring on the selected circuit layout through the target programming toolkit and the wiring design parameters to obtain a target circuit layout. According to the embodiment of the invention, time and manpower for integrated circuit layout design are saved, and errors of layout design are reduced.

Description

Technical Field

[0001] The present application relates to the field of integrated circuit technology, and in particular to an integrated circuit layout generation method and device, and a storage medium. Background Art

[0002] The integrated circuit layout is the specific manifestation of the circuit, which contains relevant physical information such as the device type, device size, relative position between devices, and connection relationship between each device. Therefore, integrated circuit layout design is an indispensable design link for realizing integrated circuit manufacturing. Traditionally, integrated circuit layout design is mainly drawn manually by layout engineers on circuit drawing software, which not only takes a lot of time and manpower, but is also prone to errors, affecting the production efficiency of integrated circuits.

[0003] Therefore, how to save time and manpower in integrated circuit layout design and reduce layout design errors has become a technical problem that needs to be solved urgently. Summary of the invention

[0004] The main purpose of the embodiments of the present application is to propose an integrated circuit layout generation method and device, and a storage medium, aiming to save time and manpower in integrated circuit layout design and reduce layout design errors.

[0005] To achieve the above-mentioned purpose, a first aspect of an embodiment of the present application provides a method for generating an integrated circuit layout, the method comprising:

[0006] receiving a circuit layout design request;

[0007] Obtaining circuit layout design parameters from a preset layout design parameter library according to the circuit layout design request; wherein the circuit layout design parameters include: silicon substrate well design parameters and connection design parameters;

[0008] Screening out a target programming toolkit from preset candidate programming toolkits according to the silicon substrate well design parameters and the connection design parameters;

[0009] Drawing a silicon substrate well on a preset circuit layout template using the target programming toolkit and the silicon substrate well design parameters to obtain a selected circuit layout;

[0010] Metal wiring is performed on the selected circuit layout using the target programming toolkit and the wiring design parameters to obtain a target circuit layout.

[0011] In some embodiments, the silicon substrate well design parameters include: transistor design parameters and transistor connection parameters, and the transistor connection parameters include: body connection parameters and pin connection parameters;

[0012] The step of drawing a silicon substrate well on a preset circuit layout template using the target programming toolkit and the silicon substrate well design parameters to obtain a selected circuit layout includes:

[0013] Drawing transistors on the circuit layout template using the target programming toolkit and the transistor design parameters to obtain a preliminary circuit layout;

[0014] Performing main connection on the transistors on the preliminary circuit layout by using the target programming toolkit and the main connection parameters to obtain a candidate circuit layout;

[0015] The transistors on the candidate circuit layout are pin-connected using the target programming toolkit and the pin connection parameters to obtain the selected circuit layout.

[0016] In some embodiments, the transistor design parameters include: silicon body spacing, pin width value and silicon body connection parameters;

[0017] The step of drawing transistors on the circuit layout template using the target programming toolkit and the transistor design parameters to obtain a preliminary circuit layout includes:

[0018] Performing silicon drawing on the circuit layout template using the target programming toolkit, the silicon body spacing and the pin width value to obtain a first circuit layout;

[0019] The target programming toolkit and the silicon body connection parameters are used to perform punching settings on the first metal layer of the first circuit layout, and the silicon body on the first circuit layout is connected by punching to obtain the preliminary circuit layout.

[0020] In some embodiments, the step of performing pin connection on the transistors on the candidate circuit layout using the target programming toolkit and the pin connection parameters to obtain the selected circuit layout includes:

[0021] Acquiring pin position information of transistors on the candidate circuit layout through the target coding toolkit;

[0022] Performing punching setting on the first metal layer of the candidate circuit layout by using the target coding toolkit, the pin position information and the pin connection parameters, obtaining a first through hole;

[0023] The pins of the transistors on the candidate circuit layout are connected through the first through-hole and the second metal layer to obtain the selected circuit layout.

[0024] In some embodiments, performing metal wiring on the selected circuit layout using the target programming toolkit and the wiring design parameters to obtain a target circuit layout includes:

[0025] Drawing an intermediate metal layer on the selected circuit layout by using the target programming toolkit to obtain a fourth circuit layout;

[0026] Performing doping area setting on the fourth circuit layout by using the target programming toolkit to obtain a fifth circuit layout;

[0027] Adjusting the layout of components of the fifth circuit layout by using the target programming toolkit and the wiring design parameters to obtain a sixth circuit layout;

[0028] The target circuit layout is obtained by drawing the top metal layer of the sixth circuit layout using the target programming toolkit.

[0029] In some embodiments, the step of drawing an intermediate metal layer on the selected circuit layout by the target programming toolkit to obtain a fourth circuit layout includes:

[0030] The target metal layer drawing method is selected from preset candidate metal layer drawing methods by the target programming toolkit; wherein the target metal layer drawing method is a horizontal drawing method;

[0031] An intermediate metal layer is drawn on the selected circuit layout according to the target metal layer drawing method to obtain the fourth circuit layout.

[0032] In some embodiments, after performing metal wiring on the selected circuit layout using the target programming toolkit and the wiring design parameters to obtain a target circuit layout, the method further includes:

[0033] Drawing an electrical isolation layer on the target circuit layout to obtain an updated circuit layout;

[0034] The updated circuit layout is packaged by the target programming toolkit to obtain a layout packaging file.

[0035] In some embodiments, before acquiring the circuit layout design parameters from a preset layout design parameter library according to the circuit layout design request, the method further includes:

[0036] Constructing the layout design parameter library specifically includes:

[0037] Obtain semiconductor manufacturing process documents from external semiconductor manufacturing platforms;

[0038] Parsing the semiconductor manufacturing process file to obtain file parsing data;

[0039] Extracting semiconductor attribute data from the file parsed data;

[0040] The semiconductor property data is input into a preset parameter library to obtain the layout design parameter library.

[0041] To achieve the above-mentioned purpose, a second aspect of an embodiment of the present application provides an integrated circuit layout generation device, the device comprising:

[0042] A request receiving module, used for receiving a circuit layout design request;

[0043] A parameter acquisition module, used to acquire circuit layout design parameters from a preset layout design parameter library according to the circuit layout design request; wherein the circuit layout design parameters include: silicon substrate well design parameters and connection design parameters;

[0044] A tool screening module, used for screening out a target programming tool kit from preset candidate programming tool kits according to the silicon substrate well design parameters and the connection design parameters;

[0045] A silicon substrate well drawing module, used to draw a silicon substrate well on a preset circuit layout template using the target programming toolkit and the silicon substrate well design parameters to obtain a selected circuit layout;

[0046] The metal wiring module is used to perform metal wiring on the selected circuit layout through the target programming toolkit and the wiring design parameters to obtain the target circuit layout.

[0047] To achieve the above-mentioned purpose, a third aspect of an embodiment of the present application proposes a computer-readable storage medium, wherein the computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the method described in the first aspect is implemented.

[0048] The integrated circuit layout generation method, device and storage medium proposed in the present application extract the circuit layout design parameters used for layout design from the layout design parameter library according to the circuit layout design request, and the circuit layout design parameters include: silicon substrate well design parameters and connection design parameters, firstly select the target programming toolkit from the candidate programming toolkit according to the silicon substrate well design parameters and the connection design parameters, so as to draw the silicon substrate well on the circuit layout template through the target programming toolkit and the silicon substrate well design parameters, and then make metal connections according to the connection design parameters to output the target circuit layout. Therefore, the user only needs to input the parameters required for the circuit layout to automatically generate the circuit layout, and the circuit layout generation process is implemented by the target programming toolkit without manual intervention, which saves manpower and time for circuit layout generation, improves the generation efficiency of the circuit layout, and reduces errors in the circuit layout design process. BRIEF DESCRIPTION OF THE DRAWINGS

[0049] Figure 1is a flow chart of the integrated circuit layout generation method provided in an embodiment of the present application;

[0050] Figure 2 is a flow chart of an integrated circuit layout generation method provided by another embodiment of the present application;

[0051] Figure 3 It is a system architecture diagram of the integrated circuit layout generation method provided in an embodiment of the present application;

[0052] Figure 4 yes Figure 1 Flow chart of step S103 in FIG.

[0053] Figure 5 yes Figure 4 Flow chart of step S401 in FIG.

[0054] Figure 6 It is a schematic diagram of a preliminary circuit layout in the integrated circuit layout generation method provided in an embodiment of the present application;

[0055] Figure 7 yes Figure 4 Flow chart of step S403 in FIG.

[0056] Figure 8 It is a schematic diagram of cross-punching of a first metal layer and a second metal layer in the integrated circuit layout generation method provided in an embodiment of the present application;

[0057] Fig. 9 yes Figure 1 Flow chart of step S104 in FIG.

[0058] Fig.10 yes Fig. 9 Flow chart of step S901 in FIG.

[0059] Fig.11 It is a schematic diagram of vertical cross metal punching in the prior art;

[0060] Fig.12 It is a schematic diagram of a metal layer after horizontal drilling in the integrated circuit layout generation method provided in an embodiment of the present application;

[0061] Fig.13 is a flow chart of an integrated circuit layout generation method provided by another embodiment of the present application;

[0062] Fig.14 It is a schematic diagram of updating a circuit layout in the integrated circuit layout generation method provided in an embodiment of the present application;

[0063] Fig.15 It is a structural schematic diagram of an integrated circuit layout generation device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0064] In order to make the purpose, technical solution and advantages of the present application more clearly understood, the present application is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0065] It should be noted that, although the functional modules are divided in the device schematic diagram and the logical order is shown in the flowchart, in some cases, the steps shown or described may be performed in a different order than the module division in the device or the order in the flowchart. The terms "first", "second", etc. in the specification, claims and the above drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence.

[0066] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein are only for the purpose of describing the embodiments of this application and are not intended to limit this application.

[0067] First, some nouns involved in this application are analyzed:

[0068] Python: is a high-level cross-platform programming language originally designed for rapid development and prototyping. Python is widely used in various fields due to its wide applicability and strong portability.

[0069] PDK (Process Design Kit): also known as process design kit or process design kit, is a toolbox for designing and verifying digital circuits. It provides a complete design process, including logic design, layout design, verification and testing steps.

[0070] GDS: also known as GDSII stream format, commonly abbreviated as GDSII, is a database file format used for data conversion of integrated circuit layouts and has become a de facto industry standard.

[0071] Gdstk: It is a Python library used to create and process GDSII (Generated Digital System Interface) files, and can also be used as a Python module.

[0072] N-Metal-Oxide-Semiconductor (NMOS): Also known as NMOS transistor. MOS transistors are divided into P-type MOS tubes and N-type MOS tubes. In n-type MOSFET, the majority carriers are electrons; in p-type MOSFET, the majority carriers are holes.

[0073] Power Unit, Power MosFet: In the field of power management in analog integrated circuits, large current is usually required, which requires a large-sized Mosfet, called Power MosFet, and the constituent unit of Power MosFet becomes Power Unit.

[0074] Technology file: It is an important input file type for semiconductor manufacturing plants and designs, including the name, number and different data types of the factory mask.

[0075] Source, Drain, Body, Gate: These are the four ports of a MOS tube. Source is the terminal where electrons enter the transistor and is usually connected to a low potential (such as ground). Drain is the terminal where electrons leave the transistor. It is usually connected to a high potential (such as a power supply). Current flows from the drain to the source (for n-type MOSFET) or from the source to the drain (for p-type MOSFET). Body is the semiconductor substrate of the MOSFET, also known as the base or substrate. During chip manufacturing, the body is usually an independent terminal, but in most circuits, it is connected to the source. The potential of the body can affect the threshold voltage and performance of the MOSFET. Gate is the terminal that controls the switching state of the MOSFET. By applying a voltage between the gate and the body, the current between the source and the drain can be controlled. There is an oxide insulating layer between the gate and the body, which makes the gate current very small. The voltage applied to the gate determines whether the MOSFET is turned on (allowing current to flow) or turned off (preventing current from flowing).

[0076] Rdson: The on-resistance, the resistance between the source and drain of the MOSFET in the on state, usually measured in milliohms (mΩ). Lower Rdson means lower conduction losses and higher efficiency.

[0077] Diff, Cont, Poly: Diff (diffusion region): refers to the region in the semiconductor that is doped to form the source and drain. Cont (contact hole): refers to the conductive hole used to connect different layers in chip manufacturing. Poly (polysilicon): refers to the polysilicon layer used as the gate material of MOSFET.

[0078] Meta l 1~Meta l6: These are different metal layers used for wiring in integrated circuits. Each layer of metal can be superimposed on each other and connected through contact holes to achieve complex circuit interconnection. The metal of adjacent layers is connected through Via.

[0079] Design Rules Check (DRC): Check whether the IC layout complies with the design rules of the manufacturing process.

[0080] Layout VS Schmat ic, LVS: Verify whether the IC layout is consistent with the circuit schematic to ensure the correct implementation of the design.

[0081] NBL: Refers to the N-type doped region formed on the semiconductor substrate during the manufacturing process, usually used to form the body or drain / source region of an N-type MOSFET.

[0082] Pick up: Ground and power pickup refers to the pickup points used for grounding or power in IC design, which are used to ensure electrical connection and stable power supply to various parts of the chip.

[0083] isoring: In chip design, a ring-shaped structure used for electrical isolation, usually to isolate different voltage domains or sensitive circuit parts.

[0084] Parameter cell (Pcell): refers to the standard cell automatically generated according to parameters in IC layout design to improve design efficiency and consistency.

[0085] In analog integrated circuit design, integrated circuit layout design and drawing largely determine the difference between chip simulation performance and actual test performance, and are the top priority for analog circuit design implementation. Integrated circuit layout is the specific manifestation of the circuit, which contains relevant physical information such as the device type, device size, relative position between devices, and connection relationship between various devices. In the field of integrated circuit manufacturing, integrated circuit layout design is an indispensable design link for realizing integrated circuit manufacturing. It is not only related to the correctness of the integrated circuit function, but also greatly affects the performance, cost and power consumption of the integrated circuit. Traditionally, integrated circuit layout designers are mainly layout designers who use EDA software to draw integrated circuit layouts, which not only takes a lot of time and energy, but also is prone to errors in manual drawing. Even a small drawing error can cause serious performance problems of the integrated circuit and even cause the IC chip to fail.

[0086] Based on this, the embodiments of the present application provide an integrated circuit layout generation method and device, and a storage medium, which aim to save time and manpower in integrated circuit layout design and reduce layout design errors.

[0087] The integrated circuit layout generation method, device, and storage medium provided in the embodiments of the present application are specifically illustrated through the following embodiments. First, the integrated circuit layout generation method in the embodiments of the present application is described.

[0088] The integrated circuit layout generation method provided in the embodiment of the present application relates to the field of integrated circuit technology. The integrated circuit layout generation method provided in the embodiment of the present application can be applied to a terminal, can also be applied to a server side, and can also be software running in a terminal or a server side. In some embodiments, the terminal can be a smart phone, a tablet computer, a laptop computer, a desktop computer, etc.; the server side can be configured as an independent physical server, or a server cluster or distributed system composed of multiple physical servers, and can also be configured as a cloud server that provides basic cloud computing services such as cloud services, cloud databases, cloud computing, cloud functions, cloud storage, network services, cloud communications, middleware services, domain name services, security services, CDN, and big data and artificial intelligence platforms; the software can be an application that implements the integrated circuit layout generation method, etc., but is not limited to the above forms.

[0089] The present application can be used in many general or special computer system environments or configurations. For example: personal computers, server computers, handheld or portable devices, tablet devices, multiprocessor systems, microprocessor-based systems, set-top boxes, programmable consumer electronics, network PCs, minicomputers, mainframe computers, distributed computing environments including any of the above systems or devices, etc. The present application can be described in the general context of computer-executable instructions executed by a computer, such as program modules. Generally, program modules include routines, programs, objects, components, data structures, etc. that perform specific tasks or implement specific abstract data types. The present application can also be practiced in distributed computing environments, in which tasks are performed by remote processing devices connected through a communication network. In a distributed computing environment, program modules can be located in local and remote computer storage media including storage devices.

[0090] Figure 1 is an optional flowchart of the integrated circuit layout generation method provided in an embodiment of the present application, Figure 1 The method may include but is not limited to steps S101 to S105.

[0091] Step S101, receiving a circuit layout design request;

[0092] Step S102, obtaining circuit layout design parameters from a preset layout design parameter library according to the circuit layout design request; wherein the circuit layout design parameters include: silicon substrate well design parameters and connection design parameters;

[0093] Step S103, selecting a target programming toolkit from preset candidate programming toolkits according to silicon substrate well design parameters and connection design parameters;

[0094] Step S104, drawing a silicon substrate well on a preset circuit layout template using a target programming toolkit and silicon substrate well design parameters to obtain a selected circuit layout;

[0095] Step S105, performing metal wiring on the selected circuit layout using the target programming toolkit and wiring design parameters to obtain the target circuit layout.

[0096] Steps S101 to S105 shown in the embodiment of the present application are to extract the circuit layout design parameters used for layout design from the layout design parameter library according to the circuit layout design request, and the circuit layout design parameters include: silicon substrate well design parameters and connection design parameters, firstly select the target programming toolkit from the candidate programming toolkits according to the silicon substrate well design parameters and the connection design parameters, so as to draw the silicon substrate well on the circuit layout template through the target programming toolkit and the silicon substrate well design parameters, and then make metal connections according to the connection design parameters to output the target circuit layout. Therefore, the user only needs to input the parameters required for the circuit layout to automatically generate the circuit layout, and the circuit layout generation process is implemented by the target programming toolkit without manual intervention, which saves manpower and time for circuit layout generation, improves the generation efficiency of the circuit layout, and reduces errors in the circuit layout design process.

[0097] In step S101 of some embodiments, when a user needs to perform circuit layout design, a circuit layout design request is initiated on the user side, and the circuit layout design request is generated by the user selecting parameters on the circuit layout design interface, or the user customizes the parameters of the required layout on the circuit layout design interface to generate the request. This embodiment does not impose specific restrictions on the method of generating the circuit layout design request.

[0098] In some embodiments, before step S102, the integrated circuit layout generation method further includes: constructing a layout design parameter library. It should be noted that the layout design parameter library stores relevant process data of circuit layout design, specifically including different layer numbers and transistors used in the integrated circuit process, etc.

[0099] See also Figure 2 In some embodiments, constructing a layout design parameter library may include but is not limited to steps S201 to S204:

[0100] Step S201, obtaining semiconductor manufacturing process files of an external semiconductor manufacturing platform;

[0101] Step S202, parsing the semiconductor manufacturing process file to obtain file parsing data;

[0102] Step S203, extracting semiconductor attribute data from the file parsing data;

[0103] Step S204, inputting the semiconductor property data into a preset parameter library to obtain a layout design parameter library.

[0104] It should be noted that existing integrated circuit layout automatic generation tools directly call the semiconductor devices in the PDK in the analog integrated circuit design to achieve unlimited layout, and no secondary design is required. In addition, existing integrated circuit layout automatic generation tools cannot generate across processes, which means that the same set of tools cannot be used to generate integrated circuit layouts on different process platforms. Based on this, in order to adapt to the process requirements of different process platforms, this embodiment summarizes the requirements of different semiconductor manufacturers' different size processes as circuit layout design parameters during circuit layout design.

[0105] In step S201 of some embodiments, the external semiconductor manufacturing platform is a platform created by an external semiconductor manufacturer, and the process information of the semiconductor is regularly updated on the external semiconductor manufacturing platform. The semiconductor manufacturing process file stores the process information of the semiconductor manufacturing process and semiconductor-related parameters. In this embodiment, in order to realize the cross-process generation of integrated circuit layouts, the semiconductor manufacturing process files of multiple external semiconductor manufacturing platforms are collected to adapt to the process requirements of different process platforms.

[0106] In steps S202 to S203 of some embodiments, the semiconductor preparation process file is in the format of ini. After parsing the semiconductor preparation process file into file parsing data, parameters related to semiconductor preparation are extracted from the file parsing data as semiconductor attribute data. Specifically, the semiconductor attribute data includes: layer number, layer number attributes, different tube types, electrical isolation ring structure parameters (iso ringing) and parameters used by design rule checking (DRC), etc. Among them, the layer number and the different attributes of the layer number constitute various elements in the final GDS layout. Different tube types determine the tubes used in the pre-simulation design and layout generation. Usually one of the biggest differences is the voltage resistance of the tube. The electrical isolation ring structure parameters refer to the means of voltage isolation of the generated layout, which can effectively protect the components inside the protected area. The parameters used in the design rule check are used to indicate which design rule checks need to be done after the circuit layout is generated, reduce the circuit problems existing in the circuit layout, greatly improve the production efficiency of the integrated circuit layout, and shorten the development cycle.

[0107] In step S204 of some embodiments, the semiconductor attribute data of the integrated circuit layout generation process is extracted, and then the semiconductor attribute data is stored in a preset parameter library to generate a layout design parameter library that can realize the generation of integrated circuit layouts across process platforms. It should be noted that the layout design parameter library not only stores the semiconductor attribute parameters obtained by the external semiconductor manufacturing platform, but also stores the custom design parameters preset by the user, and the semiconductor attribute parameters are not modifiable, while the custom design parameters can be modified, and the custom design parameters are divided into two categories, one is the pre-set layout parameters, mainly including the spacing between layers, grounding and power pickup related parameters, the spacing can be customized by the user under the condition of meeting the design rule check, and grounding and power pickup are very important concepts in the integrated circuit layout, which can be considered that when a large current needs to be passed in the power tube, some digital ground terminals need to be inserted therein to achieve the purpose of separating the current and protecting the power tube. The other type requires the user to input parameters related to the size and layout of the power tube, that is, the width and length of the semiconductor channel, the number of polysilicon in the tube in parallel, etc., as well as electrical isolation ring structure parameters, grounding and power pickup related parameters and layout parameters. The parameters related to grounding and power pickup can be the number of grounds that need to be inserted and the number of rows and columns required for the final layout.

[0108] In steps S201 to S204 shown in this embodiment, semiconductor preparation process files of multiple different external semiconductor manufacturing platforms are obtained, and semiconductor attribute data is extracted through the semiconductor preparation process files, so that the semiconductor attribute data is stored in a preset parameter library to form a layout design parameter library, thereby achieving support for cross-process integrated circuit layout generation. The same tool can be used on different process platforms to generate circuit integration layouts, reducing the complexity of design conversion and improving the efficiency of integrated circuit layout design.

[0109] In step S102 of some embodiments, as disclosed above, the constructed layout design parameters include not only semiconductor attribute data extracted from an external semiconductor manufacturing platform, but also custom design parameters pre-set by the user, so semiconductor attribute data and / or custom design parameters are extracted from the layout design parameter library as circuit layout design parameters according to the circuit layout design request, making the integrated circuit layout generation operation more efficient.

[0110] Specifically, the circuit layout design parameters may include parameters used by design rule checks of different semiconductor manufacturers, and the more advanced the semiconductor process, the more complex the parameters used by the design rule check. The traditional circuit layout generation process is to generate the circuit layout and then check it according to the parameters used by the design rule check to check for problems on the circuit layout. However, the embodiment of the present application obtains the parameters used by the design rule check in advance as the circuit layout design parameters, and generates the circuit layout according to the parameters used by the design rule check, so that the generated circuit layout will also meet the design rule check, reduce the design problems existing in the circuit layout, and do not need to consume a lot of time to solve the design problems.

[0111] It should be noted that the target programming toolkit of this embodiment is the open source library gdstk in Python. Specifically, Figure 3 As shown, the integrated circuit layout generation method is implemented by the main function. After the circuit layout design parameters are input into the main function, the main function calls the already written related classes and functions to draw the power tube. Specifically, the integrated circuit layout generation is mainly divided into two stages, namely the front-end process and the back-end process. The front-end process is mainly to manufacture the silicon substrate well, where the N tube is directly made in the P-type substrate, and the P tube needs to make the N well in the P-type substrate to be manufactured. Usually, it is necessary to manufacture the three terminals of the required single transistor, namely the source, drain, gate, and body, and arrange them in a certain order to form an overall power unit (Power unit), and the front-end process is generally the first metal layer for metal routing, and other layers do not need metal routing. The back-end process is to perform metal routing, which is mainly to connect the terminals made by the silicon substrate to the top metal layer through metal and vias Via, so as to connect with other circuit components in the circuit layout.

[0112] The specific contents of the front-end process and the back-end process are described in detail below.

[0113] In some embodiments, the silicon substrate well design parameters include transistor design parameters and transistor connection parameters, and the transistor connection parameters include body connection parameters and pin connection parameters. It should be noted that the body connection parameters are parameters for setting the transistor body, and the pin connection parameters are parameters for setting the transistor pins.

[0114] See also Figure 4 In some embodiments, step S103 may include but is not limited to steps S401 to S403:

[0115] Step S401, drawing transistors on a circuit layout template using a target programming toolkit and transistor design parameters to obtain a preliminary circuit layout;

[0116] Step S402, main-connecting the transistors on the preliminary circuit layout by using the target programming toolkit and main-connection parameters to obtain a candidate circuit layout;

[0117] Step S403, pin-connecting the transistors on the candidate circuit layout using the target programming toolkit and pin connection parameters to obtain a selected circuit layout.

[0118] It should be noted that the front-end process is mainly divided into three steps, namely transistor drawing, transistor main connection and transistor pin connection. Therefore, first draw the transistor on the circuit layout template through the target programming toolkit and transistor design, then connect the drawn transistor according to the main connection parameters, and then connect the transistor pins according to the pin connection parameters to complete the transistor drawing process and obtain the selected circuit layout. It should be noted that the selected circuit layout is a circuit layout that includes transistors and transistor connection structures.

[0119] In step S401 of some embodiments, the present embodiment calls related classes and functions in an open source library toolkit in Python, and draws the most basic transistor structure according to transistor design parameters, so that the preliminary circuit layout includes the most basic transistors that have been drawn.

[0120] In steps S402 to S403 of some embodiments, the preliminary circuit layout has drawn basic transistors, and the transistors are made on a silicon substrate, including different regions such as source, drain, gate and body, wherein the source, drain and body are formed by a first metal layer, and the gate is formed by polysilicon (Poly), so it is necessary to first connect the body of the transistor according to the body connection parameters as the ground and power pickup terminal of the outermost ring, and then connect the source, drain and gate of the transistor according to the pin connection parameters to obtain a selected circuit layout containing a complete transistor structure.

[0121] It should be noted that transistor drawing is mainly implemented by using related classes and functions in the open source library gdstk, and various elements of the transistor drawing process are included in the files of the open source library gdstk. When calling the gdstk library, a certain format and method are required. In essence, it transforms the traditional drawing method based on visual graphics in EDA tools into the drawing method based on code and coordinates in python, but the target circuit layout they constitute is consistent, including libraries, rectangular boxes, connections, text, references, etc.; compared to the traditional call to Pce ll for layout design, the use of pyhton, a new drawing method, can arbitrarily change the elements inside Pce ll and adjust it to the best performance.

[0122] See also Figure 5In some embodiments, the transistor design parameters include: silicon body spacing, pin width value and silicon body connection parameters; step S401 may include but is not limited to steps S501 to S502:

[0123] Step S501, performing silicon drawing on a circuit layout template by using a target programming toolkit, silicon body spacing and pin width values ​​to obtain a first circuit layout;

[0124] Step S502, drilling is performed on the first metal layer of the first circuit layout using the target programming toolkit and silicon body connection parameters, and the silicon body on the first circuit layout is connected by drilling to obtain a preliminary circuit layout.

[0125] In step S501 of some embodiments, it should be noted that the traditional transistor drawing cannot change the internal elements, and the traditional drawing method makes it difficult to achieve the grounding and power pickup of the main body. In this embodiment, the silicon body is drawn on the circuit layout template through the target programming toolkit, the silicon body spacing and the pin width value to achieve the customized generation of the transistor body. Specifically, the traditional transistor drawing is directly called and connected by clicking the mouse, which lacks flexibility. In this embodiment, the target programming toolkit is used to gradually draw the transistor body according to the silicon body spacing and the pin width value through code implementation to achieve personalized customization of the transistor body.

[0126] In step S502 of some embodiments, after the silicon body drawing is completed, it is necessary to punch holes in the first metal layer on the first circuit layout according to the silicon body connection parameters, so as to connect the silicon body on the first circuit layout through the holes in the first metal layer to generate a preliminary circuit layout. It should be noted that, through the target programming toolkit, that is, in a code manner, according to the silicon body connection parameters, the first circuit layout is punched and the silicon body is connected to obtain a preliminary circuit layout including a transistor structure.

[0127] It should be noted that due to the antenna effect, the main body of the gate should not be too long, most of the time it is within 50um, and then after drawing 4-5 polysilicon (Poly), use the main body (Body) to ground and pick up the power (Pick up) once, and finally connect the polysilicon at both ends through the holes in the first metal layer.

[0128] In steps S501 to S502 shown in this embodiment, a silicon body is drawn on a circuit layout template through a target programming toolkit, silicon body spacing and pin width values, and then holes are punched on the first metal layer according to the silicon body connection parameters and then connected through the holes, so that the silicon body drawing is gradually realized by using codes and silicon body related parameters, which not only improves the flexibility of silicon body setting, but also can quickly and accurately generate a silicon body that meets the requirements, thereby reducing errors in the circuit layout.

[0129] like Figure 6 As shown, Figure 6 A schematic diagram of a preliminary circuit layout, that is, a circuit layout containing a basic transistor structure.

[0130] See also Figure 7 In some embodiments, step S403 may include but is not limited to steps S701 to S703:

[0131] Step S701, obtaining the pin position information of the transistor on the candidate circuit layout through the target coding toolkit;

[0132] Step S702, performing punching setting on the first metal layer of the candidate circuit layout by using the target coding toolkit, the pin position information and the pin connection parameters to obtain a first through hole;

[0133] Step S703, connecting the pins of the transistors on the candidate circuit layout through the first through-hole and the second metal layer to obtain a selected circuit layout.

[0134] In steps S701 to S702 of some embodiments, the pin position information of the transistor on the candidate circuit layout is first obtained, and the pin position information includes source pin position information, drain pin position information and gate pin position information, and the punching position in the candidate circuit layout is determined according to the source pin position information, drain pin position information, gate pin position information and pin connection parameters, and the first through hole is punched on the candidate circuit layout according to the punching position. It should be noted that the first through hole is used to realize the pin connection of the transistor.

[0135] In step S703 of some embodiments, the pins of the transistors on the candidate circuit layout are connected through the first through hole, that is, the pins located on the first metal layer and the second metal layer are connected through the first through hole. Specifically, this embodiment uses the intersection area and the punching to realize the pin connection, such as Figure 8 Cross-punching of the first and second metal layers is shown.

[0136] Furthermore, the second metal layer of the source and drain should be as wide as possible to reduce the on-resistance.

[0137] In steps S701 to S703 shown in this embodiment, the pin position information of the transistor on the candidate circuit layout is first determined, and then a first through hole is punched on the first metal layer of the candidate circuit layout according to the pin position information and the pin connection parameters, so that the transistor pins on the candidate circuit layout are connected through the first through hole to obtain a selected circuit layout, so as to realize automatic connection of transistor pins and improve the efficiency of circuit layout generation.

[0138] See also Fig. 9In some embodiments, step S104 includes but is not limited to steps S901 to S904:

[0139] Step S901, drawing an intermediate metal layer on the selected circuit layout by using a target programming toolkit to obtain a fourth circuit layout;

[0140] Step S902, performing doping area setting on the fourth circuit layout by using a target programming toolkit to obtain a fifth circuit layout;

[0141] Step S903, adjusting the layout of components of the fifth circuit layout by using the target programming toolkit and wiring design parameters to obtain a sixth circuit layout;

[0142] Step S904, drawing the top metal layer of the sixth circuit layout by using a target programming toolkit to obtain a target circuit layout.

[0143] It should be noted that the back-end process is mainly divided into four steps. The first step is to set up the middle metal layer. The second step is to add the N-type doped area and the grounding or power pickup end of the N-type doped area to the drawn power unit. The third step is to layout the power unit, grounding and power pickup end of the N-type doped area. The fourth step is to generate the topmost metal layer to complete the circuit layout design.

[0144] In step S901 of some embodiments, only the first metal layer and the second metal layer are selected on the circuit layout, and the first metal layer and the second metal layer are used for the setting of transistors and the pin connection of the transistors themselves. In order to connect the pins between transistors or the connection between transistors and other components, it is necessary to draw an intermediate metal layer on the selected circuit layout. Specifically, in this embodiment, three intermediate metal layers are set, and the three intermediate metal layers are defined as the third metal layer, the fourth metal layer and the fifth metal layer.

[0145] In step S902 of some embodiments, the second step of the back-end process is to set the N-type doped region and the grounding and power pickup terminals, so it is implemented through the target programming toolkit, and the N-type doped region (NBL) and the grounding and power pickup terminals of the N-type doped region (NBL) are added to the power supply unit on the fourth circuit layout by code programming. Specifically, the N-type doped region (NBL) is widely used in the layout design related to it as a high-voltage technology in analog integrated circuits. The main step is to use the open source library gdstk to draw the N-type doped region (NBL) in the fourth circuit layout, and connect it to the substrate through Cont and the first metal layer (Metal l 1). It should be noted that in the second step, 1-3 power supply units are usually placed in the same N-type doped region (NBL), and then Pick up again.

[0146] In step S903 of some embodiments, in the third step of the back-end process, the fifth circuit layout is laid out using the target programming toolkit and the wiring design parameters, that is, the power supply unit, grounding, and power pickup terminal in the N-type doped region (NBL) are laid out according to the wiring design parameters. For example, if the wiring design parameter is that a row and b column have a total of m tubes in parallel, then the tubes on the fifth circuit layout are set in parallel according to the wiring design parameter to obtain a neatly arranged sixth circuit layout.

[0147] In step S904 of some embodiments, after completing the internal setting of the transistor, a top metal layer is set on the sixth circuit layout to obtain a target circuit layout. It should be noted that when setting the top metal layer, the top metal layer is adjusted according to the current direction information to generate a cross-type or box-type top metal layer, which can achieve a lower on-resistance value compared to the traditional drawing method.

[0148] In steps S901 to S904 shown in this embodiment, in the back-end process of circuit layout generation, the intermediate metal layer setting, N-type doping area setting, power supply unit, grounding and power pickup terminal layout setting in the N-type doping area are performed through the target coding tool, and finally the top metal layer is set, so as to gradually complete the back-end process of the circuit layout in the form of code, which not only realizes the automatic completion of the back-end process, but also realizes the setting of the detailed part of the circuit layout, and outputs a more accurate target circuit layout.

[0149] See also Fig.10 In some embodiments, step S901 may include but is not limited to steps S1001 to S1002:

[0150] Step S1001, selecting a target metal layer drawing mode from preset candidate metal layer drawing modes through a target programming toolkit; wherein the target metal layer drawing mode is a horizontal drawing mode;

[0151] Step S1002, drawing an intermediate metal layer on the selected circuit layout according to the target metal layer drawing method to obtain a fourth circuit layout.

[0152] In some embodiments, from step S1001 to step S1002, this embodiment adopts a horizontal drawing method to draw the intermediate metal layer, which can increase the density of drilling holes and greatly improve the utilization rate of holes. It should be noted that in the design of integrated circuit layout, the three-dimensional interconnection of metal is achieved through via, that is, if the vertical cross metal, such as Fig.11As shown in the figure, it is a plane diagram. The blue and pink are metal Meta l. If you want to connect them accordingly, you can see that the area of ​​the holes is at most 50% if you don't consider the spacing between the metals. You should know that not all metals are connected together, but they must have the same potential, that is, the source (Source) and the drain (Drain). So if the first horizontal pink is D and the second is S, then the first pink cannot be connected to the first metal S of the next layer of blue metal. Similarly, the second pink S and the second blue metal D cannot be connected. Here, a very large waste of vias is generated. The more via holes there are, the stronger the ability to pass current, and the smaller the resistance will be. If the horizontal drawing reaches 100%, as shown in Figure 12, the source S and the drain D are divided into only two horizontal metals, the upper and the lower, and then the next layer of metal is still constructed in this way, so that all the holes between the metals can be filled, and the effect of 100% can be achieved, which can significantly reduce the on-resistance.

[0153] In step S1001 to step S1002 shown in this embodiment, the drawing of the intermediate metal layer is completed by adopting a horizontal drawing method, so that the drilling density can be increased and the utilization rate of the holes can be improved.

[0154] See also Fig.13 In some embodiments, after step S105, the integrated circuit layout generation method may further include but is not limited to steps S1301 to S1302:

[0155] Step S1301, drawing an electrical isolation layer on the target circuit layout to obtain an updated circuit layout;

[0156] Step S1302, packaging the updated circuit layout through the target programming toolkit to obtain a layout packaging file.

[0157] In step S1301 of some embodiments, a circle of electrical isolation layer is drawn on the periphery of the target circuit layout to achieve high voltage isolation through the electrical isolation layer, thereby obtaining an updated circuit layout with high voltage isolation effect. Specifically, the electrical isolation layer used in this embodiment is an isolation ring of different levels such as 8V, 29V, and 70V, and this embodiment does not limit the specific isolation ring used for the electrical isolation layer.

[0158] In step S1302 of some embodiments, the updated circuit layout is packaged into a layout package file using the open source library gdstk in Python, and the layout package file is a gds file, so that users can produce circuit boards through the layout package file.

[0159] In step S1301 to step S1302 shown in this embodiment, an electrical isolation layer is set for the target circuit layout that has been laid out, and then the circuit layout is output in the form of a file to facilitate subsequent use of the circuit layout.

[0160] For example, an 8V electrical isolation layer (iso_ring) is set on the target circuit layout to obtain the following Fig.14 The updated circuit layout is shown.

[0161] In summary, by combining traditional analog integrated circuit layout design with Python tools, a breakthrough with great practical value has been achieved for the design and optimization of Power fet in the power supply field of analog integrated circuit layout design. As disclosed above, by inputting the circuit layout design parameters, the final optimized target circuit layout can be achieved through targeted related designs in the front-end process and the back-end process. While realizing the target circuit layout design at the same time, a smaller on-resistance (Rdson) can be achieved, reducing the parasitic loss on the target circuit layout. Not only that, the Power tube generated by the code design does not need to be modified in the subsequent DRC and LVS processes. In addition, by modifying the circuit layout design parameters, design across different processes can be achieved, which greatly promotes the efficiency and accuracy of layout designers.

[0162] See also Fig.15 The embodiment of the present application further provides an integrated circuit layout generation device, which can implement the above integrated circuit layout generation method, and the device includes:

[0163] A request receiving module 1501 is used to receive a circuit layout design request;

[0164] The parameter acquisition module 1502 is used to acquire circuit layout design parameters from a preset layout design parameter library according to the circuit layout design request; wherein the circuit layout design parameters include: silicon substrate well design parameters and connection design parameters;

[0165] A tool screening module 1503 is used to screen out a target programming tool kit from preset candidate programming tool kits according to silicon substrate well design parameters and connection design parameters;

[0166] A silicon substrate well drawing module 1504 is used to draw a silicon substrate well on a preset circuit layout template using a target programming toolkit and silicon substrate well design parameters to obtain a selected circuit layout;

[0167] The metal wiring module 1505 is used to perform metal wiring on the selected circuit layout through the target programming toolkit and wiring design parameters to obtain the target circuit layout.

[0168] The specific implementation of the integrated circuit layout generation device is basically the same as the specific implementation of the integrated circuit layout generation method mentioned above, and will not be repeated here.

[0169] An embodiment of the present application also provides a computer-readable storage medium, which stores a computer program. When the computer program is executed by a processor, the above-mentioned integrated circuit layout generation method is implemented.

[0170] The memory, as a non-transient computer-readable storage medium, can be used to store non-transient software programs and non-transient computer executable programs. In addition, the memory may include a high-speed random access memory, and may also include a non-transient memory, such as at least one disk storage device, a flash memory device, or other non-transient solid-state storage device. In some embodiments, the memory may optionally include a memory remotely disposed relative to the processor, and these remote memories may be connected to the processor via a network. Examples of the above-mentioned network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.

[0171] The embodiments described in the embodiments of the present application are intended to more clearly illustrate the technical solutions of the embodiments of the present application and do not constitute a limitation on the technical solutions provided in the embodiments of the present application. Those skilled in the art will appreciate that with the evolution of technology and the emergence of new application scenarios, the technical solutions provided in the embodiments of the present application are also applicable to similar technical problems.

[0172] Those skilled in the art will appreciate that the technical solutions shown in the figures do not constitute a limitation on the embodiments of the present application, and may include more or fewer steps than shown in the figures, or a combination of certain steps, or different steps.

[0173] The device embodiments described above are merely illustrative, and the units described as separate components may or may not be physically separated, that is, they may be located in one place or distributed on multiple network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0174] Those skilled in the art will appreciate that all or some of the steps in the methods disclosed above, and the functional modules / units in the systems and devices may be implemented as software, firmware, hardware, or a suitable combination thereof.

[0175] The terms "first", "second", "third", "fourth", etc. (if any) in the specification of the present application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchangeable where appropriate, so that the embodiments of the present application described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device comprising a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0176] It should be understood that in the present application, "at least one (item)" means one or more, and "plurality" means two or more. "And / or" is used to describe the association relationship of associated objects, indicating that three relationships may exist. For example, "A and / or B" can mean: only A exists, only B exists, and A and B exist at the same time, where A and B can be singular or plural. The character " / " generally indicates that the objects associated before and after are in an "or" relationship. "At least one of the following" or similar expressions refers to any combination of these items, including any combination of single or plural items. For example, at least one of a, b or c can mean: a, b, c, "a and b", "a and c", "b and c", or "a and b and c", where a, b, c can be single or multiple.

[0177] In the several embodiments provided in the present application, it should be understood that the disclosed devices and methods can be implemented in other ways. For example, the device embodiments described above are only schematic. For example, the division of the above units is only a logical function division. There may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0178] The units described above as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0179] In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit. The above-mentioned integrated unit may be implemented in the form of hardware or in the form of software functional units.

[0180] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application is essentially or the part that contributes to the prior art or all or part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a storage medium, including multiple instructions to enable a computer device (which can be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods of various embodiments of the present application. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (Read-Only Memory, referred to as ROM), random access memory (Random Access Memory, referred to as RAM), disk or optical disk and other media that can store programs.

[0181] The preferred embodiments of the present application are described above with reference to the accompanying drawings, but the scope of the rights of the present application is not limited thereto. Any modification, equivalent substitution and improvement made by a person skilled in the art without departing from the scope and essence of the present application should be within the scope of the rights of the present application.

Claims

1. A method for generating an integrated circuit layout, characterized in that: The method comprises: receiving a circuit layout design request; Obtaining circuit layout design parameters from a preset layout design parameter library according to the circuit layout design request; wherein the circuit layout design parameters include: silicon substrate well design parameters and connection design parameters; Screening out a target programming toolkit from preset candidate programming toolkits according to the silicon substrate well design parameters and the connection design parameters; Drawing a silicon substrate well on a preset circuit layout template using the target programming toolkit and the silicon substrate well design parameters to obtain a selected circuit layout; Metal wiring is performed on the selected circuit layout using the target programming toolkit and the wiring design parameters to obtain a target circuit layout.

2. The method according to claim 1, characterized in that The silicon substrate well design parameters include: transistor design parameters and transistor connection parameters, and the transistor connection parameters include: body connection parameters and pin connection parameters; The step of drawing a silicon substrate well on a preset circuit layout template using the target programming toolkit and the silicon substrate well design parameters to obtain a selected circuit layout includes: Drawing transistors on the circuit layout template using the target programming toolkit and the transistor design parameters to obtain a preliminary circuit layout; Performing main connection on the transistors on the preliminary circuit layout by using the target programming toolkit and the main connection parameters to obtain a candidate circuit layout; The transistors on the candidate circuit layout are pin-connected using the target programming toolkit and the pin connection parameters to obtain the selected circuit layout.

3. The method according to claim 2, characterized in that The transistor design parameters include: silicon body spacing, pin width value and silicon body connection parameters; The step of drawing transistors on the circuit layout template using the target programming toolkit and the transistor design parameters to obtain a preliminary circuit layout includes: Performing silicon drawing on the circuit layout template using the target programming toolkit, the silicon body spacing and the pin width value to obtain a first circuit layout; The target programming toolkit and the silicon body connection parameters are used to perform punching settings on the first metal layer of the first circuit layout, and the silicon body on the first circuit layout is connected by punching to obtain the preliminary circuit layout.

4. The method according to claim 3, characterized in that The step of performing pin connection on the transistors on the candidate circuit layout by using the target programming toolkit and the pin connection parameters to obtain the selected circuit layout comprises: Acquiring pin position information of transistors on the candidate circuit layout through the target coding toolkit; Performing punching setting on the first metal layer of the candidate circuit layout by using the target coding toolkit, the pin position information and the pin connection parameters, obtaining a first through hole; The pins of the transistors on the candidate circuit layout are connected through the first through-hole and the second metal layer to obtain the selected circuit layout.

5. The method according to claim 1, characterized in that The step of performing metal wiring on the selected circuit layout using the target programming toolkit and the wiring design parameters to obtain a target circuit layout includes: Drawing an intermediate metal layer on the selected circuit layout by using the target programming toolkit to obtain a fourth circuit layout; Performing doping area setting on the fourth circuit layout by using the target programming toolkit to obtain a fifth circuit layout; Adjusting the layout of components of the fifth circuit layout by using the target programming toolkit and the wiring design parameters to obtain a sixth circuit layout; The target circuit layout is obtained by drawing the top metal layer of the sixth circuit layout using the target programming toolkit.

6. The method according to claim 5, characterized in that The step of drawing an intermediate metal layer on the selected circuit layout by the target programming toolkit to obtain a fourth circuit layout comprises: The target metal layer drawing method is selected from preset candidate metal layer drawing methods by the target programming toolkit; wherein the target metal layer drawing method is a horizontal drawing method; An intermediate metal layer is drawn on the selected circuit layout according to the target metal layer drawing method to obtain the fourth circuit layout.

7. The method according to any one of claims 1 to 6, characterized in that: After performing metal wiring on the selected circuit layout using the target programming toolkit and the wiring design parameters to obtain the target circuit layout, the method further includes: Drawing an electrical isolation layer on the target circuit layout to obtain an updated circuit layout; The updated circuit layout is packaged by the target programming toolkit to obtain a layout packaging file.

8. The method according to any one of claims 1 to 6, characterized in that: Before acquiring the circuit layout design parameters from a preset layout design parameter library according to the circuit layout design request, the method further includes: Constructing the layout design parameter library specifically includes: Obtain semiconductor manufacturing process documents from external semiconductor manufacturing platforms; Parsing the semiconductor manufacturing process file to obtain file parsing data; Extracting semiconductor attribute data from the file parsed data; The semiconductor property data is input into a preset parameter library to obtain the layout design parameter library.

9. An integrated circuit layout generation device, characterized in that: The device comprises: A request receiving module, used for receiving a circuit layout design request; A parameter acquisition module, used to acquire circuit layout design parameters from a preset layout design parameter library according to the circuit layout design request; wherein the circuit layout design parameters include: silicon substrate well design parameters and connection design parameters; A tool screening module, used for screening out a target programming tool kit from preset candidate programming tool kits according to the silicon substrate well design parameters and the connection design parameters; A silicon substrate well drawing module, used to draw a silicon substrate well on a preset circuit layout template using the target programming toolkit and the silicon substrate well design parameters to obtain a selected circuit layout; The metal wiring module is used to perform metal wiring on the selected circuit layout through the target programming toolkit and the wiring design parameters to obtain the target circuit layout.

10. A computer-readable storage medium storing a computer program, characterized in that: When the computer program is executed by a processor, the method according to any one of claims 1 to 8 is implemented.

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