Manufacturing method of power device with groove type grid electrode

Abstract

According to the manufacturing method of the power device with the groove type grid electrode, in the etching process of the grid electrode groove, the oxide layer which is originally thick and serves as a hard mask is split into the three-layer structure of the oxide layer, the nitride layer and the oxide layer, the time for etching the oxide layer in the groove etching process is effectively shortened, and the yield of the power device is improved. And polymer residues in the trench are reduced, so that silicon spikes are reduced or even avoided, and breakdown voltage failure caused by generation of a gate oxide layer with poor quality is avoided.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a method for manufacturing a power device with a trench-type gate. Background Art

[0002] VDMOS (Vertical Double-diffused Metal Oxide Semiconductor) is a vertical double-diffused metal oxide semiconductor device, which is a type of power MOSFET (Metal Oxide Semiconductor Field Effect Transistor). Trench VDMOS device is a new type of vertical structure device, which is developed on the basis of VDMOS. Compared with VDMOS, Trench VDMOS has lower on-resistance and gate-drain charge density, so it has lower conduction and switching losses and faster switching speed. At the same time, because the channel of Trench VDMOS device is vertical, its channel density can be further improved and the chip size can be reduced.

[0003] Figure 1 The schematic diagram of the structure of a Trench VDMOS device is shown in FIG. In the manufacturing process of such power devices, the deep trench process is widely used, and the deep trench is obtained by dry etching. For the dry etching of the deep trench, because a deeper trench is required for etching, the etching time is long, the thickness of the hard mask layer and the photoresist are relatively thick, especially the thickness of the hard mask layer can reach several microns, the etching time of the hard mask layer is long, and after the trench etching, the photolithography, hard mask, etc. remain, and polymer residue (Polymer Residue) particles appear in the trench. The polymer residue is easy to form a block etching (BlockET), and then after the trench silicon etching (Trench Si ET), silicon spikes (Si Grass) are formed at the bottom of the trench. In addition, because there are more polymer residues, cleaning cannot be completely cleaned, resulting in a poor morphology (Profile) of the gate oxide layer (Gate Oxide) grown in the trench, and the breakdown voltage fails. Summary of the invention

[0004] The object of the present invention is to provide a method for manufacturing a power device with a trench-type gate, which is used to reduce polymer residue in the trench during the etching process of the gate trench, thereby reducing or even avoiding silicon spikes, thereby avoiding breakdown voltage failure caused by a poor quality gate oxide layer.

[0005] To achieve the above object, the present invention provides a method for manufacturing a power device having a trench gate, comprising:

[0006] Providing a substrate, forming a hard mask layer on the substrate, wherein the hard mask layer includes a first oxide layer, an intermediate nitride layer and a second oxide layer in sequence from the substrate upward;

[0007] performing patterning on the hard mask layer;

[0008] The substrate is etched using the patterned hard mask layer as a mask to form a gate trench.

[0009] Optionally, the first oxide layer and the second oxide layer both include TEOS, and the intermediate nitride layer includes silicon nitride.

[0010] Optionally, the thickness of the second oxide layer is greater than the thickness of the first oxide layer.

[0011] Optionally, the thickness of the second oxide layer is 1.8um to 2.2um, the thickness of the nitride layer is 0.2um to 0.8um, and the thickness of the first oxide layer is 0.2um to 0.5um.

[0012] Optionally, patterning the hard mask layer includes:

[0013] forming a patterned photoresist on the second oxide layer;

[0014] The patterned photoresist is used as a mask to sequentially etch the second oxide layer, the middle nitride layer and the first oxide layer until a portion of the substrate is exposed.

[0015] Optionally, after the hard mask layer is patterned and before the substrate is etched using the patterned hard mask layer as a mask, the method further includes: removing the patterned photoresist.

[0016] Optionally, after forming the gate trench, the method further includes:

[0017] removing the mask layer and cleaning the gate trench;

[0018] The surface of the gate trench is repaired by depositing a sacrificial oxide layer.

[0019] Optionally, after repairing the surface of the gate trench by depositing a sacrificial oxide layer, the method further comprises:

[0020] forming a gate oxide layer on the sidewalls and bottom of the gate trench;

[0021] Polysilicon is deposited in the trench gate groove to form a trench gate.

[0022] Optionally, the substrate includes a semiconductor substrate and an epitaxial layer located on the semiconductor substrate, and the semiconductor substrate and the epitaxial layer have the same conductivity type.

[0023] Optionally, the power device includes Trench IGBT, Trench VDMOS, or Trench super junction VDMOS.

[0024] In summary, the present invention provides a method for manufacturing a power device with a trench-type gate. During the etching process of the gate groove, the originally relatively thick oxide layer serving as a hard mask is split into a three-layer structure of oxide layer-nitride layer-oxide layer, which effectively reduces the time for etching the oxide layer in the trench etching process, reduces the polymer residue in the trench, and further reduces or even avoids silicon spikes, thereby avoiding the breakdown voltage failure caused by the poor quality gate oxide layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 It is a schematic diagram of the structure of a Trench VDMOS device;

[0026] Figure 2 is the SEM image of silicon spike A;

[0027] FIG. 3A to FIG. 3C A schematic diagram of a structure formed by corresponding steps of a method for manufacturing a Trench VDMOS device;

[0028] Figure 4 A schematic flow chart of a method for manufacturing a power device with a trench gate provided by an embodiment of the present invention;

[0029] FIG. 5A to FIG. 5E A schematic diagram of a structure formed by corresponding steps of a method for manufacturing a power device with a trench gate in one embodiment of the present invention;

[0030] The reference numerals are described as follows:

[0031] 10, 100 - substrate; 11, 110 - gate trench; 20 - oxide layer; 30, 300 - patterned photoresist; 210 - first oxide layer; 220 - middle nitride layer; 230 - second oxide layer. DETAILED DESCRIPTION

[0032] To make the content of the present invention more clear and understandable, the content of the present invention is further described below in conjunction with the accompanying drawings. Of course, the present invention is not limited to this specific embodiment, and general replacements known to those skilled in the art are also covered within the protection scope of the present invention.

[0033] Secondly, the present invention is described in detail using schematic diagrams. When describing the examples of the present invention in detail, for the sake of convenience, the schematic diagrams are not partially enlarged according to general proportions, and this should not be used as a limitation of the present invention.

[0034] For ease of description, some embodiments of the present invention may use spatially relative terms such as "above", "below", "top", "below", etc. to describe the relationship between one element or component and another (or other) elements or components as shown in the various figures of the embodiments. It should be understood that in addition to the orientations described in the drawings, the spatially relative terms are also intended to include different orientations of the device in use or operation. For example, if the device in the drawings is turned over, the elements or components described as being "below" or "beneath" other elements or components will subsequently be positioned as being "above" or "above" the other elements or components. The terms "first", "second", etc., hereinafter, are used to distinguish between similar elements and are not necessarily used to describe a specific order or time sequence.

[0035] Figure 3A-3C FIG. 1 is a schematic diagram of a structure formed by corresponding steps of a method for manufacturing a Trench VDMOS device. FIG. 3A to FIG. 3C As shown, the process includes the following steps: forming an oxide layer 20 on a substrate 10, forming a patterned photoresist 30 on the oxide layer 20, and defining an etching process window for a gate trench, such as Figure 3A Then, the oxide layer 20 is subjected to a photolithography process to form a patterned oxide layer 20, as shown in FIG. Figure 3B Then, the substrate 10 is etched using the patterned oxide layer 20 as a mask to form a gate trench 11, as shown in FIG. Figure 3C As shown. In the above gate trench etching process, the oxide layer as a hard mask is relatively thick (up to 3um), the etching time is long, and the etching residue polymer A' is likely to appear in the gate trench, hindering the etching. After the gate trench is etched, silicon spikes (Si Grass) A are formed at the bottom of the trench. In addition, because there are many polymer residues, cleaning cannot completely clean them, and the number of silicon spikes A increases, resulting in a poor morphology (Profile) of the gate oxide layer (Gate OX) grown in the gate trench, and a breakdown voltage failure.

[0036] Specifically, silicon spikes (Si Grass), also known as silicon grass, are produced because the flow rate of fluorocarbons is too high during the etching step, causing the deposition rate of the protective film to be greater than the removal rate, causing the protective film to accumulate at the bottom of the etching area. The deposits of these protective films will form carbon clusters, which act as nanomasks to hinder the etching of silicon, thereby forming nanoscale protrusions on the silicon surface, namely silicon grass. The formation of silicon grass is also affected by other etching parameters, such as power, temperature and time. Silicon grass will cause the roughness of the device surface to increase, thereby increasing friction, wear and stress. Silicon grass will also reduce the etching rate and uniformity of the device, thereby affecting the dimensional accuracy and consistency of the device, and then affecting the performance of the device.

[0037] In view of this, the present invention provides a method for manufacturing a power device with a trench-type gate. During the etching process of the gate trench, the originally relatively thick oxide layer serving as a hard mask is split into a three-layer structure of oxide layer-nitride layer-oxide layer, thereby effectively reducing the time for etching the oxide layer in the trench etching process, reducing polymer residue, and further reducing or even avoiding silicon spikes, thereby avoiding breakdown voltage failure caused by poor quality gate oxide layer.

[0038] Figure 4 A schematic diagram of a process for manufacturing a power device with a trench gate provided by an embodiment of the present invention is shown in FIG. Figure 4 As shown, the method for manufacturing a power device with a trench gate provided in this embodiment includes the following steps:

[0039] Step S01: providing a substrate, and forming a hard mask layer on the substrate, wherein the hard mask layer includes a first oxide layer, an intermediate nitride layer, and a second oxide layer in sequence from the substrate upward;

[0040] Step S02: performing patterning on the hard mask layer; and,

[0041] Step S03: etching the substrate using the patterned hard mask layer as a mask to form a gate trench.

[0042] FIG. 5A to FIG. 5E Schematic diagram of the structure formed by the corresponding steps of the method for manufacturing a power device with a trench gate in one embodiment of the present invention. Figure 4 As shown, combined with FIG. 5A to FIG. 5E , a method for manufacturing a power device with a trench gate provided by the present invention is described in detail.

[0043] First, refer to Figure 5A As shown, step S01 is performed to provide a substrate 100 and form a hard mask layer on the substrate. The hard mask layer includes a first oxide layer 210 , an intermediate nitride layer 220 and a second oxide layer 230 in sequence from the substrate 100 upwards.

[0044] The substrate 100 may be any suitable base material known in the art, for example, it may be at least one of the following materials: silicon (Si), germanium (Ge), silicon germanium (SiGe), carbon silicon (SiC), carbon germanium silicon (SiGeC), indium arsenide (InAs), gallium arsenide (GaAs), indium phosphide (InP) or other III / V compound semiconductors. The substrate may be a substrate with a certain degree of doping, the substrate comprising a semiconductor substrate and an epitaxial layer located on the semiconductor substrate, the semiconductor substrate and the epitaxial layer having the same conductivity type. For example, the substrate may be a silicon substrate doped with N-type ions (N-type doped silicon substrate), and an N-type doped epitaxial layer is also formed on its surface, and annealing treatment may be performed after each doping, such as a rapid annealing process, but is not limited thereto. For example, as Figure 1 As shown, the substrate includes an N-type doped silicon substrate (N+Substrate) and an N-type doped epitaxial layer (N epi) located on the N-type doped silicon substrate.

[0045] It should be understood that the ion implantation type of the epitaxial layer in the embodiment of the present invention needs to be the same as the ion implantation type of the substrate, and it can specifically be an N-type doped epitaxial layer or a P-type doped epitaxial layer. The specific doping type of the epitaxial layer can be determined according to the type of the trench VDMOS device, and the well region, source and drain formed subsequently are different from the type of the trench VDMOS device. In the embodiment of the present invention, only an N-type doped silicon substrate is used as an example.

[0046] Furthermore, after the N-type doped epitaxial layer is formed on the N-type doped silicon substrate, at least one ion implantation process may be performed again to form a P-type well region in the N-type doped epitaxial layer, and after forming the P-type well, annealing treatment may be performed, such as a rapid annealing process, but is not limited to this.

[0047] Furthermore, after forming the P-type well, photolithography and etching, such as dry etching, can be further used to form multiple isolation trenches in the N-type doped epitaxial layer, and deposition processes, such as chemical vapor deposition, physical vapor deposition and other processes, can be used to fill insulating materials, such as silicon dioxide, silicon nitride and other materials, in each of the isolation trenches. Thereafter, a chemical mechanical polishing process is used to flatten the insulating material filled in the isolation trenches, thereby forming an active area for defining the formation of a trench VDMOS device, wherein the trench isolation can be a shallow trench isolation STI structure or a field oxide structure, but is not limited to this.

[0048] Furthermore, after the active area is formed, a gate trench can be formed in the N-type doped epitaxial layer corresponding to the active area by etching, such as dry etching, wet etching or a mixed process of dry etching and wet etching, and a gate oxide layer and a polysilicon material covering the gate oxide layer and filling the gate trench, i.e., gate polysilicon, can be formed on the inner wall of the gate trench.

[0049] Specifically, in the etching process of the gate trench, a hard mask layer is formed on the substrate 100, and the hard mask layer includes a first oxide layer 210, an intermediate nitride layer 220 and a second oxide layer 230 in order from the substrate 100 upwards, the first oxide layer 210 and the second oxide layer 230 both include tetraethoxysilane (TEOS) or silicon dioxide (SiO2), and the intermediate nitride layer 220 includes silicon nitride (SiN) or silicon oxynitride (SiON). In this embodiment, the material of the first oxide layer 210 and the second oxide layer 230 is the same, for example, it can be TEOS, and TEOS can be deposited by PECVD (Plasma Enhanced Chemical Vapor Deposition) process. In other embodiments of the present invention, the materials of the first oxide layer 210 and the second oxide layer 230 may also be different.

[0050] The thickness of the second oxide layer 230 is greater than that of the first oxide layer 210 , the thickness of the second oxide layer is 1.8 um to 2.2 um, the thickness of the nitride layer is 0.2 um to 0.8 um, and the thickness of the first oxide layer is 0.2 um to 0.5 um.

[0051] Next, refer to FIG. 5A to FIG. 5D As shown, step S02 is performed to pattern the hard mask layer. Patterning the hard mask layer includes: forming a patterned photoresist 300 on the second oxide layer 230, such as Figure 5A As shown, a groove pattern is formed on the surface of the substrate by a photolithography process; then, the second oxide layer 230, the intermediate nitride layer 220 and the first oxide layer 210 are sequentially etched using the patterned photoresist 300 as a mask until a portion of the substrate 100 is exposed, and the groove pattern on the groove mask is copied to the substrate surface, as shown in FIG. FIG. 5B to FIG. 5D As shown in the figure, the longer the etching time of the oxide layer is, the more etched polymer residues there are. In this embodiment, the thicker oxide layer is split into a stack of oxide layer-nitride layer-oxide layer as an etching hard mask layer, thereby reducing the polymer residue A' and avoiding silicon spikes generated by trench etching.

[0052] Next, refer to Figure 5EAs shown, step S03 is performed to etch the substrate 100 using the patterned hard mask layer as a mask to form a groove 110. Specifically, before the groove is etched, the patterned photoresist 300 is removed, and then the substrate 100 is etched using the patterned hard mask layer as a mask to form the groove 110, and then the hard mask layer is removed. Further, after removing the hard mask layer, the groove is cleaned, and the surface of the groove is repaired by depositing a sacrificial oxide layer.

[0053] In addition, the method for manufacturing a power device with a trench-type gate further includes: forming a gate oxide layer on the sidewall and bottom of the trench; and depositing polysilicon in the gate trench to form a trench-type gate. Through the above steps S01 and S02, the hard mask layer structure of the gate trench etching is adjusted, which effectively reduces the time for etching the oxide layer in the gate trench etching process, reduces the polymer residue, and greatly reduces the generation of silicon spikes in the process of etching the gate trench. In this way, after subsequent cleaning and sacrificial layer repair, a flat and clean silicon surface can be obtained, thereby forming a flat gate oxide layer.

[0054] The method for manufacturing a power device with a trench gate provided in this embodiment is applicable to the manufacture of devices such as Trench IGBT, Trench VDMOS, Trench super junction VDMOS, etc.

[0055] In summary, the present invention provides a method for manufacturing a power device with a trench-type gate. During the etching process of the gate groove, the originally relatively thick oxide layer serving as a hard mask is split into a three-layer structure of oxide layer-nitride layer-oxide layer, which effectively reduces the time for etching the oxide layer in the trench etching process, reduces polymer residue, and further reduces or even avoids silicon spikes, thereby avoiding breakdown voltage failure caused by poor quality gate oxide layer.

[0056] The above description is only a description of the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention. Any changes or modifications made by a person skilled in the art in the field of the present invention based on the above disclosure shall fall within the scope of protection of the claims.

Claims

1. A method for manufacturing a power device having a trench gate, characterized in that: include: Providing a substrate, forming a hard mask layer on the substrate, wherein the hard mask layer includes a first oxide layer, an intermediate nitride layer and a second oxide layer in sequence from the substrate upward; performing patterning on the hard mask layer; The substrate is etched using the patterned hard mask layer as a mask to form a gate trench.

2. The method for manufacturing a power device having a trench gate according to claim 1, characterized in that: The first oxide layer and the second oxide layer both include TEOS, and the intermediate nitride layer includes silicon nitride.

3. The method for manufacturing a power device having a trench gate according to claim 2, characterized in that: The thickness of the second oxide layer is greater than the thickness of the first oxide layer.

4. The method for manufacturing a power device having a trench gate according to claim 3, characterized in that: The thickness of the second oxide layer is 1.8um to 2.2um, the thickness of the nitride layer is 0.2um to 0.8um, and the thickness of the first oxide layer is 0.2um to 0.5um.

5. The method for manufacturing a power device having a trench gate according to claim 1, characterized in that: The patterning process of the hard mask layer includes: forming a patterned photoresist on the second oxide layer; The patterned photoresist is used as a mask to sequentially etch the second oxide layer, the middle nitride layer and the first oxide layer until a portion of the substrate is exposed.

6. The method for manufacturing a power device with a trench gate according to claim 5, characterized in that: After the hard mask layer is patterned, and before the substrate is etched using the patterned hard mask layer as a mask, the method further includes: removing the patterned photoresist.

7. The method for manufacturing a power device with a trench gate according to claim 6, characterized in that: After forming the gate trench, the method further includes: removing the mask layer and cleaning the gate trench; The surface of the gate trench is repaired by depositing a sacrificial oxide layer.

8. The method for manufacturing a power device with a trench gate according to claim 7, characterized in that: After repairing the surface of the gate trench by depositing a sacrificial oxide layer, the method further comprises: forming a gate oxide layer on the sidewalls and bottom of the gate trench; Polysilicon is deposited in the gate trench to form a trench-type gate.

9. The method for manufacturing a power device having a trench gate according to claim 1, characterized in that: The substrate comprises a semiconductor substrate and an epitaxial layer located on the semiconductor substrate, and the semiconductor substrate and the epitaxial layer have the same conductivity type.

10. The method for manufacturing a power device having a trench gate according to claim 1, characterized in that: The power devices include Trench IGBT, Trench VDMOS, and Trench super junction VDMOS.

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