Common mode current removal scheme for digital-to-analog converter

Abstract

Methods and apparatus for common mode current removal in a digital-to-analog converter (DAC). An example DAC circuit generally includes a plurality of current steering units; a resistor ladder circuit coupled to the plurality of current steering units; a first current sink coupled between a shunt branch of the resistor step circuit and a reference potential node of the DAC circuit; and a second current sink coupled between the first output of the DAC circuit and the reference potential node.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to U.S. patent application serial number 17 / 810,100, filed on June 30, 2022, which is hereby incorporated by reference into this application. Technical Field

[0003] Certain aspects of the present disclosure relate generally to electronic circuits, and more particularly to techniques and apparatus for common-mode current removal in digital-to-analog converters (DACs). Background Art

[0004] Wireless communication devices are widely deployed to provide various communication services, such as telephony, video, data, messaging, broadcast, etc. Such wireless communication devices may send and / or receive radio frequency (RF) signals via any of a variety of suitable radio access technologies (RATs), including but not limited to 5G New Radio (NR), Long Term Evolution (LTE), Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Wideband CDMA (WCDMA), Global System for Mobile (GSM), Bluetooth, Bluetooth Low Energy (BLE), ZigBee, Wireless Local Area Network (WLAN) RATs (e.g., WiFi), etc.

[0005] A wireless communication network may include multiple base stations that can support communications for multiple mobile stations. A mobile station (MS) may communicate with a base station (BS) via a downlink and an uplink. A downlink (or forward link) refers to a communication link from a base station to a mobile station, while an uplink (or reverse link) refers to a communication link from a mobile station to a base station. A base station may send data and control information to a mobile station on a downlink, and / or may receive data and control information from a mobile station on an uplink. A base station and / or a mobile station may include a transmit digital-to-analog converter (TX DAC), which may be used, for example, to convert a digital signal into an analog signal for signal processing (e.g., filtering, up-conversion, and amplification) before being transmitted by one or more antennas. Summary of the invention

[0006] The systems, methods, and devices of the present disclosure each have several aspects, no single aspect of which is solely responsible for its desired characteristics. Without limiting the scope of the present disclosure as expressed by the claims that follow, some features will now be briefly discussed. After considering this discussion, and particularly after reading the section entitled "Detailed Description of the Invention," it will be understood how the features of the present disclosure provide advantages including lower common-mode current variations with variations in process, voltage, and / or temperature (PVT) without affecting digital signal performance and without significantly increasing noise, offset, area, or power consumption of a digital-to-analog converter (DAC).

[0007] Certain aspects of the present disclosure provide a DAC. The DAC generally includes a plurality of current steering units; a resistor ladder circuit coupled to the plurality of current steering units; a first current sink coupled between a shunt branch of the resistor ladder circuit and a reference potential node of the DAC circuit; and a second current sink coupled between a first output of the DAC circuit and the reference potential node.

[0008] Certain aspects of the present disclosure provide a method for operating a DAC. The DAC generally includes a plurality of current steering units and a resistor ladder circuit coupled to the plurality of current steering units. The method generally involves absorbing a first portion of a common-mode current of the DAC circuit from a shunt branch of the resistor ladder circuit and absorbing a second portion of the common-mode current of the DAC circuit from a first output of the DAC circuit.

[0009] To achieve the foregoing and related ends, one or more aspects include the features fully described below and particularly pointed out in the claims. The following description and the accompanying drawings set forth in detail some illustrative features of one or more aspects. However, these features are merely indicative of some of the various ways in which the principles of the various aspects may be employed, and this specification is intended to include all such aspects and their equivalents. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] In order to be able to understand in detail the manner in which the above-mentioned features of the present disclosure are achieved, a more specific description briefly summarized above may be obtained by reference to various aspects, some of which are illustrated in the accompanying drawings. However, it should be noted that the accompanying drawings illustrate only certain typical aspects of the present disclosure and are therefore not to be considered as limiting the scope thereof, as the specification may admit to other equally effective aspects.

[0011] Figure 1 is an illustration of an example wireless communication network in which aspects of the present disclosure may be practiced.

[0012] Figure 2 is a block diagram conceptually illustrating designs of example base stations (BSs) and user equipment (UEs) in which aspects of the present disclosure may be practiced.

[0013] Figure 3 is a block diagram of an example radio frequency (RF) transceiver in which aspects of the present disclosure may be practiced.

[0014] Figure 4 An example digital-to-analog converter (DAC) is illustrated in which aspects of the present disclosure may be practiced.

[0015] Figure 5 is a block diagram of an example DAC circuit with common-mode current removal circuitry in accordance with certain aspects of the present disclosure.

[0016] Figure 6 According to certain aspects of the present disclosure Figure 5 Schematic diagram of an example implementation of one or more current sinks in a common-mode current removal scheme.

[0017] Figure 7 is a flow chart of example operations for digital-to-analog conversion with common-mode current removal in accordance with certain aspects of the present disclosure.

[0018] To facilitate understanding, identical reference numerals have been used, where possible, to designate identical elements that are common to the figures. It is contemplated that elements disclosed in one aspect may be beneficially utilized on other aspects without specific recitation. DETAILED DESCRIPTION

[0019] Certain aspects of the present disclosure relate to techniques and apparatus for common-mode current removal in a digital-to-analog converter (DAC), such as a current-steering DAC having a resistor ladder circuit. The common-mode current removal scheme may be implemented with a first current sinking circuit coupled to the center of a shunt branch of the resistor ladder circuit and a second current sinking circuit coupled to an output (e.g., a differential output) of the DAC. The first current sinking circuit and the second current sinking circuit may be designed to remove (or at least substantially reduce) common-mode current from the DAC. The second current sinking circuit may be designed to offset variations due to process, voltage, and / or temperature (PVT) in the first current sinking circuit, such that the common-mode current removal scheme will be independent of PVT or at least have low variations.

[0020] The various aspects of the present disclosure are described more fully below with reference to the accompanying drawings. However, the present disclosure can be embodied in many different forms, and should not be interpreted as being limited to any specific structure or function presented throughout the present disclosure. Instead, these aspects are provided so that the present disclosure will be thorough and complete, and the protection scope of the present disclosure will be fully conveyed to those skilled in the art. Based on the teachings of this article, it should be understood by those skilled in the art that the scope of the present disclosure is intended to cover any aspect of the disclosure disclosed herein, whether it is implemented independently or in combination with any other aspect of the present disclosure. For example, any number of aspects set forth herein can be used to implement a device or practice method. In addition, the scope of the present disclosure is intended to cover such devices or methods that are practiced using other structures, functionality, or structures and functionality in addition to the various aspects of the present disclosure set forth herein or different from the various aspects of the present disclosure set forth herein. It should be understood that any aspect of the present disclosure disclosed herein can be embodied by one or more elements of the present invention.

[0021] The word “exemplary” is used herein to mean “serving as an example, instance, or illustration.” Any aspect described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other aspects.

[0022] As used herein, the term "connected with" in various tenses of the verb "connect" may mean that element A is directly connected to element B or that other elements may be connected between element A and element B (i.e., element A is indirectly connected to element B). In the context of electronic components, the term "connected with" may also be used herein to mean that wires, traces, or other conductive materials are used to electrically connect element A and element B (and any components electrically connected therebetween).

[0023] Example Wireless System

[0024] Figure 1 An example wireless communication network 100 in which aspects of the present disclosure may be practiced is illustrated. For example, the wireless communication network 100 may be a New Radio (NR) system (e.g., a fifth generation (5G) NR network), an Evolved Universal Terrestrial Radio Access (E-UTRA) system (e.g., a fourth generation (4G) network), a Universal Mobile Telecommunications System (UMTS) (e.g., a second generation / third generation (2G / 3G) network), or a Code Division Multiple Access (CDMA) system (e.g., a 2G / 3G network), or may be configured for communication according to IEEE standards such as one or more of the 802.11 standards.

[0025] like Figure 1As illustrated in FIG. 1 , the wireless communication network 100 may include several base stations (BSs) 110 a to 110 z (each of which is also individually referred to as BS 110 or collectively referred to as BS 110 herein) and other network entities. A BS may also be referred to as an access point (AP), an evolved Node B (eNodeB or eNB), a next generation Node B (gNodeB or gNB), or some other terminology.

[0026] BS 110 may provide communication coverage for a particular geographic area (sometimes referred to as a "cell"), which may be stationary or may move depending on the location of mobile BS 110. In some examples, BS 110 may be interconnected with each other and / or connected to one or more other BSs or network nodes (not shown) in wireless communication network 100 through various types of backhaul interfaces (e.g., direct physical connections, wireless connections, virtual networks, etc.) using any suitable transport network. Figure 1 In the example shown, BSs 110a, 110b, and 110c may be macro BSs for macro cells 102a, 102b, and 102c, respectively. BS 110x may be a pico BS for pico cell 102x. BSs 110y and 110z may be femto BSs for femto cells 102y and 102z, respectively. A BS may support one or more cells.

[0027] The BS 110 communicates with one or more user equipment (UE) 120a to 120y (each also individually or collectively referred to herein as UE 120) in the wireless communication network 100. A UE may be fixed or mobile, and may also be referred to as a user terminal (UT), a mobile station (MS), an access terminal, a station (STA), a client, a wireless device, a mobile device, or some other terminology. A user terminal may be a wireless device such as a cellular phone, a smart phone, a personal digital assistant (PDA), a handheld device, a wearable device, a wireless modem, a laptop computer, a tablet computer, a personal computer, etc.

[0028] BS 110 is considered a transmitting entity for downlink and a receiving entity for uplink. UE 120 is considered a transmitting entity for uplink and a receiving entity for downlink. As used herein, a "transmitting entity" is an independently operated device or apparatus capable of transmitting data via a frequency channel, and a "receiving entity" is an independently operated device or apparatus capable of receiving data via a frequency channel. In the following description, the subscript "dn" indicates a downlink, and the subscript "up" indicates an uplink. N may be selected. up UEs are used for simultaneous transmission on the uplink, N dn UEs are used for simultaneous transmission on the downlink. up May or may not be equal to Ndn , and N up and N dn It may be a static value or may change for each scheduling interval.Beam steering or some other spatial processing technique may be used at the BS 110 and / or the UE 120.

[0029] UEs 120 (e.g., 120x, 120y, etc.) may be dispersed throughout the wireless communication network 100, and each UE 120 may be stationary or mobile. The wireless communication network 100 may also include a relay station (e.g., relay station 110r) (also referred to as a repeater, etc.) that receives transmissions of data and / or other information from an upstream station (e.g., BS 110a or UE 120r) and transmits transmissions of data and / or other information to a downstream station (e.g., UE 120 or BS 110), or relays transmissions between UEs 120 to facilitate communication between devices.

[0030] BS 110 may communicate on the downlink and uplink with one or more UEs 120 at any given moment. The downlink (i.e., forward link) is the communication link from BS 110 to UE 120, while the uplink (i.e., reverse link) is the communication link from UE 120 to BS 110. A UE 120 may also communicate peer-to-peer with another UE 120.

[0031] The wireless communication network 100 may use multiple transmit antennas and multiple receive antennas to transmit data on the downlink and uplink. The BS 110 may be equipped with several (N ap A group of (N) antennas can be used to implement transmit diversity for downlink transmission and / or receive diversity for uplink transmission. u Each UE 120 may receive downlink transmissions and send uplink transmissions. Each UE 120 may send user-specific data to and / or receive user-specific data from the BS 110. Typically, each UE 120 may be equipped with one or more antennas. u The UEs 120 may have the same or different numbers of antennas.

[0032] The wireless communication network 100 may be a time division duplex (TDD) system or a frequency division duplex (FDD) system. For a TDD system, the downlink and uplink share the same frequency band. For an FDD system, the downlink and uplink use different frequency bands. The wireless communication network 100 may also utilize a single carrier or multiple carriers for transmission. Each UE 120 may be equipped with a single antenna (e.g., to reduce costs) or multiple antennas (e.g., where additional costs can be supported).

[0033] The network controller 130 (sometimes also referred to as a "system controller") may communicate with a set of BSs 110 and provide coordination and control (e.g., via backhaul) for these BSs 110. In some cases (e.g., in a 5G NR system), the network controller 130 may include a centralized unit (CU) and / or a distributed unit (DU). In some aspects, the network controller 130 may communicate with a core network 132 (e.g., a 5G core network (5GC)), which provides various network functions such as access and mobility management, session management, user plane functions, policy control functions, authentication server functions, unified data management, application functions, network open functions, network repository functions, network slice selection functions, etc.

[0034] In certain aspects of the present disclosure, BS 110 and / or UE 120 may include a digital-to-analog converter (DAC) circuit that implements a common-mode current removal scheme, as described in more detail herein.

[0035] Figure 2 1 and 120a (eg, from a BS 110a) in which various aspects of the present disclosure may be implemented. Figure 1 Example components of a wireless communication network 100).

[0036] On the downlink, at BS 110a, the transmit processor 220 may receive data from the data source 212, control information from the controller / processor 240, and / or possibly other data (e.g., from the scheduler 244). Various types of data may be transmitted on different transport channels. For example, control information may be designated for a physical broadcast channel (PBCH), a physical control format indicator channel (PCFICH), a physical hybrid automatic repeat request (HARQ) indicator channel (PHICH), a physical downlink control channel (PDCCH), a group common PDCCH (GC PDCCH), etc. Data may be designated for a physical downlink shared channel (PDSCH), etc. A medium access control (MAC)-control element (MAC-CE) is a MAC layer communication structure that may be used for the exchange of control commands between wireless nodes. The MAC-CE may be carried in a shared channel such as a PDSCH, a physical uplink shared channel (PUSCH), or a physical sidelink shared channel (PSSCH).

[0037] The processor 220 may process (e.g., encode and symbol map) data and control information to obtain data symbols and control symbols, respectively. The transmit processor 220 may also generate reference symbols such as for a primary synchronization signal (PSS), a secondary synchronization signal (SSS), a PBCH demodulation reference signal (DMRS), and a channel state information reference signal (CSI-RS).

[0038] The transmit (TX) multiple-input multiple-output (MIMO) processor 230 may perform spatial processing (e.g., pre-decoding) on ​​data symbols, control symbols, and / or reference symbols where applicable, and may provide an output symbol stream to a modulator (MOD) in a transceiver 232a-232t. Each modulator 232a-232t in the transceiver may process a respective output symbol stream (e.g., for orthogonal frequency division multiplexing (OFDM) or the like) to obtain an output sample stream. Each transceiver 232a-232t may further process (e.g., convert to analog, amplify, filter, and up-convert) the output sample stream to obtain a downlink signal. The downlink signals from the transceivers 232a-232t may be transmitted via antennas 234a-234t, respectively.

[0039] At UE 120a, antennas 252a-252r may receive downlink signals from BS110a and may provide received signals to transceivers 254a-254r, respectively. Transceivers 254a-254r may condition (e.g., filter, amplify, downconvert, and digitize) the corresponding received signals to obtain input samples. Each demodulator (DEMOD) in transceivers 232a-232t may further process the input samples (e.g., for OFDM, etc.) to obtain received symbols. MIMO detector 256 may obtain received symbols from all demodulators in transceivers 254a-254r, perform MIMO detection on the received symbols (where applicable), and provide detected symbols. Receive processor 258 may process (e.g., demodulate, deinterleave, and decode) the detected symbols, provide decoded data for UE 120a to data sink 260, and provide decoded control information to controller / processor 280.

[0040] On the uplink, at the UE 120a, a transmit processor 264 may receive and process data from a data source 262 (e.g., for a physical uplink shared channel (PUSCH)) and control information from a controller / processor 280 (e.g., for a physical uplink control channel (PUCCH)). The transmit processor 264 may also generate reference symbols for reference signals (e.g., for a sounding reference signal (SRS)). The symbols from the transmit processor 264 may be pre-decoded by a TX MIMO processor 266 (where applicable), further processed by a modulator (MOD) in the transceivers 254a to 254r (e.g., for single carrier frequency division multiplexing (SC-FDM), etc.), and transmitted to the BS 110a. At BS 110a, the uplink signal from UE 120a may be received by antenna 234, processed by demodulators in transceivers 232a-232t, detected by MIMO detector 236 (if applicable), and further processed by receive processor 238 to obtain decoded data and control information transmitted by UE 120a. Receive processor 238 may provide the decoded data to a data sink 239 and the decoded control information to controller / processor 240.

[0041] Memories 242 and 282 may store data and program codes for BS 110a and UE 120a, respectively. Memories 242 and 282 may also interface with controllers / processors 240 and 280, respectively. Scheduler 244 may schedule UEs to transmit data on the downlink and / or uplink.

[0042] The antennas 252, processors 258, 264, 266 and / or controller / processor 280 of the UE 120a and / or the antennas 234, processors 220, 230, 238 and / or controller / processor 240 of the BS 110a may be used to perform the various techniques and methods described herein.

[0043] In certain aspects of the present disclosure, transceiver 232 and / or transceiver 254 may include digital-to-analog converter (DAC) circuitry that implements a common-mode current removal scheme, as described in greater detail herein.

[0044] NR can use orthogonal frequency division multiplexing (OFDM) with a cyclic prefix (CP) on the uplink and downlink. NR can use time division duplex (TDD) to support half-duplex operation. OFDM and single carrier frequency division multiplexing (SC-FDM) divide the system bandwidth into multiple orthogonal subcarriers, which are also commonly referred to as tones, frequency bands, etc. Each subcarrier can be modulated with data. Modulation symbols can be transmitted in the frequency domain using OFDM and in the time domain using SC-FDM. The spacing between adjacent subcarriers can be fixed, and the total number of subcarriers can depend on the system bandwidth. The system bandwidth can also be divided into subbands. For example, one subband can cover multiple resource blocks (RBs).

[0045] Example RF Transceiver

[0046] Figure 3 is a block diagram of an example radio frequency (RF) transceiver circuit 300 according to certain aspects of the present disclosure. The RF transceiver circuit 300 includes at least one transmit (TX) path 302 (also referred to as a “transmit chain”) for transmitting signals via one or more antennas 306 and at least one receive (RX) path 304 (also referred to as a “receive chain”) for receiving signals via antenna 306. When TX path 302 and RX path 304 share antenna 306, these paths can be connected to the antenna via interface 308, which can include any of a variety of suitable RF devices, such as switches, duplexers, diplexers, multiplexers, etc.

[0047] Receiving in-phase (I) and / or quadrature (Q) baseband analog signals from a digital-to-analog converter (DAC) 310, the TX path 302 may include a baseband filter (BBF) 312, a mixer 314, a driver amplifier (DA) 316, and a power amplifier (PA) 318. The BBF 312, the mixer 314, the DA 316, and the PA 318 may be included in a radio frequency integrated circuit (RFIC). For certain aspects, the PA 318 may be external to the RFIC.

[0048] For certain aspects, DAC 310 can be implemented by any of a variety of suitable high-speed DAC topologies, such as a current-steering DAC. For certain aspects, DAC 310 can be implemented with a common-mode current removal scheme for removing common-mode current from the DAC, as described in more detail below.

[0049] The BBF 312 filters the baseband signal received from the DAC 310, and the mixer 314 mixes the filtered baseband signal with a transmit local oscillator (LO) signal to convert the baseband signal of interest to a different frequency (e.g., upconvert from baseband to radio frequency). This frequency conversion process produces sum and difference frequencies between the LO frequency and the frequency of the baseband signal of interest. The sum and difference frequencies are referred to as "beat frequencies." The beat frequencies are typically in the RF range, so that the signal output by the mixer 314 is typically an RF signal, which may be amplified by the DA 316 and / or by the PA 318 before being transmitted by the antenna 306. Although one mixer 314 is illustrated, multiple mixers may be used to upconvert the filtered baseband signal to one or more intermediate frequencies, and thereafter upconvert the intermediate frequency (IF) signal to a frequency for transmission.

[0050] The RX path 304 may include a low noise amplifier (LNA) 324, a mixer 326, and a baseband filter (BBF) 328. The LNA 324, the mixer 326, and the BBF 328 may be included in one or more RFICs, which may be the same RFIC as the RFIC that includes the TX path components, or may be a different RFIC. The RF signal received via the antenna 306 may be amplified by the LNA 324, and the mixer 326 mixes the amplified RF signal with a receive local oscillator (LO) signal to convert the RF signal of interest to a different baseband frequency (e.g., down-convert). The baseband signal output by the mixer 326 may be filtered by the BBF 328 before being converted to a digital I and / or Q signal by an analog-to-digital converter (ADC) 330 for digital signal processing.

[0051] Some transceivers may employ a frequency synthesizer with a variable frequency oscillator (e.g., a voltage controlled oscillator (VCO) or a digitally controlled oscillator (DCO)) to generate a stable, tunable LO with a specific tuning range. Thus, the transmit LO may be generated by the TX frequency synthesizer 320, which may be buffered or amplified by the amplifier 322 before being mixed with the baseband signal in the mixer 314. Similarly, the receive LO may be generated by the RX frequency synthesizer 332, which may be buffered or amplified by the amplifier 334 before being mixed with the RF signal in the mixer 326. For certain aspects, a single frequency synthesizer may be used for both the TX path 302 and the RX path 304. In certain aspects, the TX frequency synthesizer 320 and / or the RX frequency synthesizer 332 may include a frequency multiplier (such as a doubler) driven by an oscillator (e.g., a VCO) in the frequency synthesizer.

[0052] Controller 336 (eg, Figure 2Controller / processor 280 in the RF transceiver circuit 300A may direct the operation of the RF transceiver circuit 300A, such as transmitting signals via TX path 302 and / or receiving signals via RX path 304. Controller 336 may be a processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic device (PLD), discrete gate or transistor logic, discrete hardware components, or any combination thereof. Memory 338 (e.g., Figure 2 The memory 282 in the controller 336 may store data and / or program codes for operating the RF transceiver circuit 300. The controller 336 and / or the memory 338 may include control logic (eg, complementary metal oxide semiconductor (CMOS) logic).

[0053] Although Figures 1 to 3 Wireless communications are provided as an example application in which certain aspects of the present disclosure may be implemented to facilitate understanding, but certain aspects described herein may be used for digital-to-analog conversion in any of a variety of other suitable systems (e.g., audio systems or other electronic systems).

[0054] Introduction to Digital-to-Analog Conversion Using Current Steering

[0055] A current-steering digital-to-analog converter (DAC) is an example architecture used for high-performance digital-to-analog conversion in many wireless transmitters. A current-steering DAC provides design versatility, high-speed operation, and high performance (such as relatively high linearity). Although a current-steering DAC is described as an example type of DAC that can implement aspects of the present disclosure, it should be understood that aspects of the present disclosure may also be applied to other suitable types of DACs.

[0056] Figure 4 An example current steering DAC 400 (eg, which may implement Figure 3 DAC 310). As shown, the current steering DAC 400 includes a current steering unit 401 and a resistor ladder circuit 402. The resistor ladder circuit 402 can be implemented as an R-2R type ladder circuit, as explained below. For example, the resistor ladder circuit 402 may include a plurality of segments (e.g., segments 490, 492), each of which includes a positive ladder node R2Rp <0> to R2Rp <k>and negative step node R2Rn <0> To R2Rn <k>. Between the positive ladder node and the negative ladder node of each segment may be a resistance element (e.g., resistance elements 440, 442 or resistance elements 450, 452). In addition, a resistance element (e.g., resistance element 444 or 454) may be coupled between the positive nodes of adjacent segments of the resistor ladder circuit 402, and a resistance element (e.g., resistance element 446 or 456) may be coupled between the negative nodes of adjacent segments of the resistor ladder circuit 402. In an R-2R ladder circuit, the series resistance element (e.g., resistance elements 444, 454) has a resistance value R, and the shunt resistance element (e.g., resistance elements 450, 452 in the shunt branch 441 of the ladder circuit) has twice the resistance (2R) in each half of the R-2R ladder circuit. For certain aspects, the least significant bit (LSB) may follow the R-2R ladder structure, while the most significant bit (MSB) may have a different resistance value in the resistor ladder circuit (e.g., according to a thermometer code).

[0057] Each current steering unit in the current steering unit 401 (e.g., current steering unit n, n is a positive integer) includes a current source coupled to the voltage rail Vdd, a positive switch coupled to the current source and configured to selectively provide a positive current (e.g., Ipos n) to the positive ladder node, and a negative switch coupled to the current source and configured to selectively provide a negative current (e.g., Ineg n) to the negative ladder node. For example, the supply current Isupply 0 (e.g., Isupply n, where n is 0) through the current source 430 can be guided via the positive switch 403 of the current steering unit 410 to the positive ladder node R2Rp <0> Similarly, Isupply 0 through current source 430 can be additionally directed via negative switch 404 to the negative ladder node R2Rn. <0> In a similar manner, the currents from the current sources of the other current steering units can be directed to the corresponding positive and negative ladder nodes (R2Rp) via the positive or negative switches in each current steering unit. <1> to R2Rp <k>, and R2Rm<1> to R2Rm<k>).

[0058] The control inputs to the positive switch 403 and the negative switch 404 can be complementary. In some aspects, the switches 403 and 404 can be implemented as p-type metal oxide semiconductor (PMOS) transistors, as illustrated. Thus, a logic high signal can be used to open the switch 403 or 404, and a logic low signal can be used to close the switch 403 or 404.

[0059] The output signal from the DAC 400 is in the form of a differential current at the positive and negative output nodes (labeled "outp" and "outm") of the resistor ladder circuit 402. To achieve high linearity, it is desirable to remove common-mode current from the DAC 400 (or at least along the transmit path (e.g., TX path 302)). It may be desirable to minimize (or at least reduce) variations in the output common-mode current over changes in process, voltage, and / or temperature (PVT) while keeping noise and offset contributions from the common-mode current removal scheme to a minimum (or at least substantially low). Some previously known common-mode current removal techniques suffer from significant variations in the output common-mode current over PVT variations and / or large differential noise and offset contributions from the current sink circuit.

[0060] Thus, aspects of the present disclosure provide a common-mode current removal scheme with reduced variation in PVT and lower noise and offset compared to some previously known techniques. The common-mode current removal scheme of the present disclosure is also power efficient, has a small lateral surface area (e.g., footprint), and has no significant impact on differential signal performance.

[0061] Example DAC with multi-path common-mode current removal scheme

[0062] Figure 5 An example digital-to-analog converter (DAC) circuit 502 with common-mode current removal circuitry according to certain aspects of the present disclosure is illustrated. As shown, in some aspects, the outputs of the DAC circuit 502 (e.g., positive output 516 labeled "outp" and negative output 518 labeled "outm") can be coupled to a filter 514 (e.g., a baseband filter such as BBF 312). The positive output 516 and the negative output 518 constitute the differential output (outp / outm) of the DAC circuit 502.

[0063] As illustrated, the DAC circuit 502 may generally include a plurality of current steering units 504a, ..., 504n (collectively referred to as "current steering units 504") and a resistor ladder circuit 506 coupled to the plurality of current steering units 504. The current steering unit 504 may be similar to Figure 4 The current steering unit 401 is provided, and each current steering unit can steer the current based on a single bit of a digital word arranged from the most significant bit (MSB) to the least significant bit (LSB), as shown. Figure 5 Only a single segment of the resistor ladder circuit 506 is shown in FIG. 1 , but the resistor ladder circuit 506 may be similar to Figure 4 The resistor ladder circuit 402 may be implemented as, for example, an R-2R ladder circuit, as described above.

[0064] The common mode current removal circuit of the DAC circuit 502 may include a first current sink 508 coupled between the shunt branch 441 of the resistor ladder circuit 506 and a reference potential node (eg, electrical ground) of the DAC circuit 502. The first current sink 508 may sink a current referred to as “I sink_R2R ” current. For some aspects, the first current sink 508 can be implemented as a short circuit between the shunt branch 441 and the reference potential node. Such a short circuit can be used to absorb as much common-mode current as possible from the resistor ladder circuit. In some aspects, the first current sink 508 can be coupled between the center of the shunt branch 441 in the section of the resistor ladder circuit 506 and the reference potential node. In some aspects, the first current sink 508 can be coupled between the reference potential node and a node 520 between two shunt resistor elements (e.g., resistor elements 450, 452) in the shunt branch 441 of the resistor ladder circuit 506.

[0065] The common-mode current removal circuit may also include a second current sink 510, which may be coupled between a positive output 516 of the DAC circuit 502 and a reference potential node. For certain aspects, the common-mode current removal circuit may further include a third current sink 512 coupled between a negative output 518 of the DAC circuit 502 and a reference potential node of the DAC circuit 502. The second current sink 510 may sink a current referred to as "I sinnkp ”, and the third current sink 512 can sink a current called “I sinkm ” current. Therefore, the second current sink 510 and the third current sink 512 can be part of the same current removal scheme, where a pair of current sinks are coupled to a differential output (outp / outm).

[0066] In this manner, the first current sink 508 can be configured to sink a first portion (eg, I sink_R2R ), and the second current sink 510 can be configured to sink a second portion of the common-mode current of the DAC circuit 502 (eg, I sinkp In other words, the first current sink 508 may be designed to sink as much common-mode current as possible, and the second current sink 510 (along with the third current sink 512 ) may be designed to remove the remainder of the common-mode current from the DAC circuit 502 .

[0067] Furthermore, the first current sink 508 can be configured such that the first portion of the common-mode current decreases as the resistance of the resistor ladder circuit 506 increases. Conversely, the second current sink 510 can be configured such that the second portion of the common-mode current increases as the resistance of the resistor ladder circuit 506 increases. In this way, the second portion of the common-mode current can offset at least a portion (e.g., a majority) of a variation in the first portion of the common-mode current due to at least one of a process, voltage, or temperature variation in the DAC circuit 502.

[0068] In one example, if the resistance of the resistor ladder circuit 506 increases due to a change in at least one of process, voltage, or temperature, the first current sink 508 may be used to sink less common mode current (ie, I sink_R2R Thus, the second current sink 510 (and in some cases, the third current sink 512) can sink a larger amount of common-mode current, such that the total amount of common-mode current removed from the DAC circuit 502 (I sink_tot ) remains roughly constant.

[0069] Figure 6 is an example of some aspects of the present disclosure Figure 5 Schematic diagram 600 of an example implementation of the second current sink 510 (and / or the third current sink 512) in the common-mode current removal scheme of FIG. As shown, the second current sink 510 (and / or the third current sink 512) may generally include a first current source 602, a first current mirror 604, a second current source 608, a second current mirror 610, and a third current mirror 620. For ease of explanation, the second current sink 510 is generally described below, but the reader should understand that the third current sink 512 can be added by simply adding a third branch to the third current mirror 620.

[0070] The first current source 602 may be implemented using any suitable current source circuit among various suitable current source circuits. Figure 6 In the example of , the first current source 602 may include a reference resistance element 612, a first transistor 614, an amplifier 616, and a second transistor 618. As shown, the reference resistance element 612 may have a resistance R and may be coupled between the drain of the first transistor 614 and the reference potential node (e.g., electrical ground) of the second current sink 510. The reference resistance element 612 may be a resistor type that is the same as the multiple resistance elements (e.g., resistance elements 444, 454) in the resistor ladder circuit 402 or 506. The amplifier 616 may have a first input coupled to a reference voltage source (generating a reference voltage labeled "Vref"), a second input coupled to the drain of the first transistor 614, and an output coupled to the gate of the first transistor 614. The reference voltage source may be implemented by any suitable stable reference voltage source, such as a bandgap reference. The gate of the second transistor 618 may be coupled to the output of the amplifier 616, and the drain of the second transistor 618 may be used as the output of the first current source 602. The sources of the first transistor 614 and the second transistor 618 may be coupled to a voltage rail Vdda.

[0071] During operation, the amplifier 616 drives the first transistor 614 to maintain a reference voltage Vref across the reference resistance element 612, thereby regulating a reference current I through the first transistor 614 and the reference resistance element 612. ref，a If the second transistor 618 is a copy of the first transistor 614, the amplifier 616 drives the second transistor 618 with the same output voltage to generate a similar reference current I through the second transistor 618. ref，b (I ref，b ≈I ref，a ).

[0072] The first current mirror 604 may have a first branch (e.g., including transistor 622) coupled to the first current source 602 (e.g., coupled to the drain of the second transistor 618), and a second branch (e.g., including transistor 624) coupled to the common node 606. The transistor 624 in the second branch of the first current mirror 604 may be a copy of the transistor 622 in the first branch. In this case, during operation, the second branch of the first current mirror 604 may copy the reference current I flowing in the first branch from the first current source 602. ref，b , to provide a mirror reference current I ref，c (≈I ref，b ≈I ref，a ).

[0073] The second current source 608 can provide another reference current I trim , which is likely to have been calibrated and thus may be independent of process, voltage, and temperature (PVT) variations. The second current mirror 610 may have a first branch (e.g., including transistor 626) coupled to the second current source 608 and a second branch (e.g., including transistor 628) coupled to the common node 606. The transistor 628 in the second branch of the second current mirror 610 may be a copy of the transistor 626 in the first branch. In this case, during operation, the second branch of the second current mirror 610 may replicate the reference current I sunk by the second current source 608 via the first branch. trim To provide a mirror reference current (equal to I trim ).

[0074] The third current mirror 620 can have a first branch (e.g., including transistor 630) coupled to the common node 606 and a second branch (e.g., including transistor 632) coupled to the positive output 516 (or the negative output 518 in the case of the third current sink 512) of the DAC circuit 502. According to certain aspects, the third current mirror 620 can have a gain "A" (e.g., illustrated by a ratio of 1:A) from the first branch of the third current mirror 620 to the second branch of the third current mirror 620. During operation, the first branch of the third current mirror 620 receives a reference current I trim and I ref，c The difference between the differential current ΔI (AI = I trim -I ref，c ≈I trim -V ref / R). The second branch of the third current mirror 620 can amplify the difference current ΔI flowing in the first branch from the common node 606 to provide a sink current (I sinkp,m ≈A(I trim -V ref / R)).

[0075] The second current sink 510 (and in some cases, the third current sink 512) can be designed to track the first current sink 508 across variations in PVT. As described above, the amount of current sunk by the second current sink 510 (or the third current sink 512) can be calculated as

[0076]

[0077] Among them A mirror is the mirror gain of the third current mirror 620, I trim is the current generated by the second current source 608, V ref is the reference voltage at the first input of amplifier 616 , and R is the resistance of reference resistive element 612 .

[0078] Furthermore, the total current absorbed by multiple current sinks in this hybrid common-mode current removal scheme can be calculated as

[0079]

[0080] Among them I sink,R2R is the current absorbed by the first current sink 508, V cm is the common mode voltage, and R R2R,eq is the equivalent resistance of the resistor ladder circuit 506. If one wishes to consider only the changes in the terms in the above equation, trim is independent of PVT, so the change in the intermediate term (Δ(A mirror *I trim )) will be equivalently 0. Therefore, the equation for the change in term can be written as follows:

[0081]

[0082] As a result, the PVT variation in the first current sink 508 will be offset (eg, using the second current sink 510 and the third current sink 512 ) if the following equation holds true such that ΔI sink,tot =0:

[0083]

[0084] In one example, the total amount of common-mode current to be absorbed may be 500 μA. In this case, if V cm is equal to 500mV and R R2R，eq is equal to 1.33kΩ, then I sink,R2R =376 μA (=500 mV / 1.33 kg). Therefore, the amount of current that the second current sink 510 (and / or the third current sink 512) should sink (eg, I sinkp，m ) is equal to 124 μA (=500 μA-376 μA) to absorb the remaining common mode current not absorbed by the first current sink 508. Therefore, if I trim is set to 50μA, then V ref =1.25V, the resistance value R of the reference resistor element 612 is set to 33.24kΩ, and A mirror is set to 10, the above formula is satisfied.

[0085] Compared to some other common mode current removal techniques, aspects of the present disclosure with the common mode removal scheme presented herein provide reduced noise, offset, and variation with PVT. In some cases, the scheme presented herein can have up to ten times less variation across PVT, up to 20% less offset, and up to 25% less noise than previously known techniques.

[0086] Example Transformation Operation

[0087] Figure 7 7 is a flow chart of example operations 700 for performing digital-to-analog conversion with common-mode current removal in a DAC circuit (e.g., DAC circuit 502) in accordance with certain aspects of the present disclosure. The DAC circuit generally includes a plurality of current steering cells (e.g., current steering cell 504) and a resistor ladder circuit (e.g., resistor ladder circuit 506) coupled to the plurality of current steering cells.

[0088] Operations 700 may generally involve, at block 702, sinking a first portion (eg, I ) of a common-mode current of a DAC circuit from a shunt branch (eg, shunt branch 441) of a resistor ladder circuit. sink_R2R Operation 700 may also involve, at block 704, sinking a second portion (eg, I ) of the common-mode current of the DAC circuit from a first output (eg, positive output 516) of the DAC circuit. sinkp ).

[0089] According to certain aspects, a first portion of the common-mode current may decrease as the resistance of the resistor ladder circuit increases, and a second portion of the common-mode current may increase as the resistance of the resistor ladder circuit increases. For certain aspects, the first portion of the common-mode current may increase as the resistance of the resistor ladder circuit decreases, and the second portion of the common-mode current may decrease as the resistance of the resistor ladder circuit decreases. The second portion of the common-mode current may offset at least a portion of a change in the first portion of the common-mode current due to at least one of a process, voltage, or temperature change in the DAC circuit.

[0090] According to certain aspects, operation 700 may involve sinking a third portion (eg, I ) of the common-mode current of the DAC circuit from a second output terminal (eg, negative output terminal 518) of the DAC circuit. sinkm ). In this case, the first output and the second output may constitute a differential output of the DAC circuit.

[0091] According to certain aspects, sinking the second portion of the common-mode current at block 704 may involve generating a first reference current (eg, I ref,a , which can be generated using the first current source 602); based on the generation of the first reference current, generating a second reference current (eg, I ref，b ); mirroring a second reference current in the second branch of the first current mirror (to generate I ref，c ); generating a third reference current (eg, I trim ); mirroring a third reference current in a second branch of a second current mirror; providing a difference current (e.g., a difference current ΔI) to a first branch of a third current mirror (e.g., third current mirror 620) as a difference between the mirrored third reference current and the mirrored second reference current; and mirroring the difference current in a second branch of the third current mirror, wherein a second portion of the common-mode current includes the mirrored difference current.

[0092] In some aspects, the mirror difference current involves a gain (eg, A) from the first branch of the third current mirror to the second branch of the third current mirror. mirror ) mirrors the difference current. For certain aspects, the third reference current is calibrated and is independent of process, voltage, and temperature variations.

[0093] Example aspects

[0094] In addition to the above-mentioned aspects, specific combinations of the aspects are also within the scope of the present disclosure, and the details of some of the specific combinations are as follows:

[0095] Aspect 1: A digital-to-analog converter (DAC) circuit, comprising: a plurality of current steering units; a resistor ladder circuit, the resistor ladder circuit being coupled to the plurality of current steering units; a first current sink, the first current sink being coupled between a shunt branch of the resistor ladder circuit and a reference potential node of the DAC circuit; and a second current sink, the second current sink being coupled between a first output of the DAC circuit and the reference potential node.

[0096] Aspect 2: A DAC circuit according to Aspect 1, wherein the first current sink is configured to sink a first portion of the common-mode current of the DAC circuit, and wherein the second current sink is configured to sink a second portion of the common-mode current of the DAC circuit.

[0097] Aspect 3: A DAC circuit according to Aspect 2, wherein the first current sink is configured so that the first part of the common-mode current decreases as the resistance of the resistor ladder circuit increases, and wherein the second current sink is configured so that the second part of the common-mode current increases as the resistance of the resistor ladder circuit increases.

[0098] Aspect 4: A DAC circuit according to Aspect 2 or 3, wherein the second current sink is configured so that the second portion of the common-mode current offsets at least a portion of a change in the first portion of the common-mode current due to at least one of process, voltage or temperature changes in the DAC circuit.

[0099] Aspect 5: According to the DAC circuit described in any one of the preceding aspects, the DAC circuit also includes a third current sink, which is coupled between the second output of the DAC circuit and the reference potential node of the DAC circuit, wherein the first output and the second output constitute the differential output of the DAC circuit.

[0100] Aspect 6: The DAC circuit according to any one of the preceding aspects, wherein the first current sink is coupled between a center of the shunt branch in a section of the resistor ladder circuit and the reference potential node of the DAC circuit.

[0101] Aspect 7: The DAC circuit according to any one of the preceding aspects, wherein the first current sink is coupled between the reference potential node and a node between two shunt resistance elements in the shunt branch of the resistor ladder circuit.

[0102] Aspect 8: A DAC circuit according to any one of the preceding aspects, wherein the second current sink comprises: a first current source; a first current mirror, the first current mirror having a first branch coupled to the first current source and a second branch coupled to a common node; a second current source; a second current mirror, the second current mirror having a first branch coupled to the second current source and a second branch coupled to the common node; and a third current mirror, the third current mirror having a first branch coupled to the common node and a second branch coupled to the first output of the DAC circuit.

[0103] Aspect 9: The DAC circuit according to aspect 8, wherein the third current mirror has a gain from the first branch of the third current mirror to the second branch of the third current mirror.

[0104] Aspect 10: A DAC circuit according to Aspect 8 or 9, wherein the first current source comprises: a reference resistance element; a first transistor; an amplifier having a first input coupled to a reference voltage source, a second input coupled to a drain of the first transistor, and an output coupled to a gate of the first transistor; and a second transistor having a gate coupled to the output of the amplifier and a drain coupled to the first branch of the first current mirror.

[0105] Aspect 11: The DAC circuit of aspect 10, wherein the reference resistance element is a same resistor type as a plurality of resistance elements in the resistor ladder circuit.

[0106] Aspect 12: The DAC circuit of any one of aspects 8 to 11, wherein the second current source is calibrated and is independent of process, voltage and temperature variations.

[0107] Aspect 13: The DAC circuit according to any one of the preceding aspects, wherein the first current sink is a short circuit between the shunt branch of the resistor ladder circuit and the reference potential node of the DAC circuit.

[0108] Aspect 14: A method of operating a digital-to-analog converter (DAC) circuit comprising a plurality of current steering units and a resistor ladder circuit coupled to the plurality of current steering units, the method comprising: absorbing a first portion of a common-mode current of the DAC circuit from a shunt branch of the resistor ladder circuit; and absorbing a second portion of the common-mode current of the DAC circuit from a first output of the DAC circuit.

[0109] Aspect 15: A method according to Aspect 14, wherein the first portion of the common-mode current decreases as the resistance of the resistor ladder circuit increases, and wherein the second portion of the common-mode current increases as the resistance of the resistor ladder circuit increases.

[0110] Aspect 16: A method according to Aspect 14 or 15, wherein the second portion of the common-mode current offsets at least a portion of a variation in the first portion of the common-mode current due to at least one of process, voltage, or temperature variations in the DAC circuit.

[0111] Aspect 17: According to the method described in any one of Aspects 14 to 16, the method also includes absorbing a third portion of the common-mode current of the DAC circuit from a second output of the DAC circuit, wherein the first output and the second output constitute a differential output of the DAC circuit.

[0112] Aspect 18: A method according to any one of Aspects 14 to 17, wherein absorbing the second part of the common-mode current includes: generating a first reference current; generating a second reference current in a first branch of a first current mirror based on the generation of the first reference current; mirroring the second reference current in the second branch of the first current mirror; generating a third reference current in the first branch of the second current mirror; mirroring the third reference current in the second branch of the second current mirror; providing a difference current as the difference between the mirrored third reference current and the mirrored second reference current to the first branch of the third current mirror; and mirroring the difference current in the second branch of the third current mirror, wherein the second part of the common-mode current includes the mirrored difference current.

[0113] Aspect 19: The method of aspect 18, wherein mirroring the difference current comprises mirroring the difference current with a gain from the first branch of the third current mirror to the second branch of the third current mirror.

[0114] Aspect 20: The method according to aspect 18 or 19, wherein the third reference current is calibrated and is independent of process, voltage and temperature variations.

[0115] in conclusion

[0116] A digital-to-analog converter (DAC) circuit is described herein for removing common-mode current with reduced variation across process, voltage, and / or temperature (PVT) changes. Certain aspects of the present disclosure provide a multi-path common-mode current removal scheme that can track PVT variations. In certain aspects, a first current sink may be configured to absorb a first portion of the common-mode current, and a second current sink may be configured to absorb a second portion of the common-mode current. The second portion of the common-mode current can offset or at least reduce variations in the first portion of the common-mode current due to at least one of process, voltage, or temperature.

[0117] The above description provides examples, but does not limit the scope, applicability or examples set forth in the claims. Without departing from the scope of the present disclosure, the functions and arrangements of the elements discussed may be changed. Each example may omit, replace or add each procedure or component as appropriate. For example, the method described may be performed in a different order than that described, and various steps may be added, omitted or combined. In addition, the features described for some examples may be combined in some other examples. For example, any number of aspects set forth herein may be used to implement a device or practice method. In addition, the scope of the present disclosure is intended to cover such devices or methods that are practiced using other structures, functionality, or structures and functionality in addition to or different from the various aspects of the present disclosure set forth herein. It should be understood that any aspect of the present disclosure disclosed herein may be embodied by one or more elements of the present invention. The word "exemplary" is used herein to mean "used as an example, instance, or illustration". Any aspect described herein as "exemplary" is not necessarily interpreted as being preferred or having advantages over other aspects.

[0118] The various operations of the above method can be performed by any suitable component capable of performing the corresponding function. The component may include various hardware and / or software components and / or modules, including but not limited to circuits, application specific integrated circuits (ASICs) or processors. Generally speaking, in the case of the operations illustrated in the accompanying drawings, these operations may have corresponding corresponding components plus functional components.

[0119] As used herein, a phrase referring to "at least one of" a list of items refers to any combination of those items (including single members). As an example, "at least one of a, b, or c" is intended to cover: a, b, c, ab, ac, bc, and abc, as well as any combination with multiple identical elements (e.g., aa, aaa, aab, aac, abb, acc, bb, bbb, bbc, cc, and ccc, or any other ordering of a, b, and c).

[0120] The methods disclosed herein include one or more steps or actions for implementing the described methods. The steps and / or actions of the methods may be interchangeable with each other without departing from the scope of the claims. In other words, unless a specific order of steps or actions is specified, the order and / or use of specific steps and / or actions may be modified without departing from the scope of the claims.

[0121] It is to be understood that the claims are not limited to the precise configuration and components illustrated above. Various modifications, changes and variations may be made in the arrangement, operation and details of the methods and apparatus described above without departing from the scope of the claims.< / k> < / k> < / k>

Claims

1. A digital-to-analog converter (DAC) circuit, the digital-to-analog converter (DAC) circuit comprising: multiple current steering units; a resistor ladder circuit coupled to the plurality of current steering units; a first current sink coupled between a shunt branch of the resistor ladder circuit and a reference potential node of the DAC circuit; and A second current sink is coupled between the first output of the DAC circuit and the reference potential node.

2. The DAC circuit of claim 1 , wherein the first current sink is configured to sink a first portion of a common-mode current of the DAC circuit, and wherein the second current sink is configured to sink a second portion of the common-mode current of the DAC circuit.

3. The DAC circuit of claim 2 , wherein the first current sink is configured such that the first portion of the common-mode current decreases as the resistance of the resistor ladder circuit increases, and wherein the second current sink is configured such that the second portion of the common-mode current increases as the resistance of the resistor ladder circuit increases.

4. The DAC circuit of claim 2 , wherein the second current sink is configured such that the second portion of the common-mode current offsets at least a portion of a variation in the first portion of the common-mode current due to at least one of process, voltage, or temperature variations in the DAC circuit.

5. The DAC circuit according to claim 1, further comprising a third current sink, the third current sink being coupled between the second output of the DAC circuit and the reference potential node of the DAC circuit, wherein the first output and the second output constitute a differential output of the DAC circuit. 6 . The DAC circuit of claim 1 , wherein the first current sink is coupled between a center of the shunt branch in a section of the resistor ladder circuit and the reference potential node of the DAC circuit.

7. The DAC circuit of claim 1, wherein the first current sink is coupled between the reference potential node and a node between two shunt resistance elements in the shunt branch of the resistor ladder circuit.

8. The DAC circuit of claim 1 , wherein the second current sink comprises: a first current source; a first current mirror having a first branch coupled to the first current source and having a second branch coupled to a common node; a second current source; a second current mirror having a first branch coupled to the second current source and having a second branch coupled to the common node; and A third current mirror has a first branch coupled to the common node and a second branch coupled to the first output of the DAC circuit.

9. The DAC circuit of claim 8, wherein the third current mirror has a gain from the first branch of the third current mirror to the second branch of the third current mirror.

10. The DAC circuit according to claim 8, wherein the first current source comprises: reference resistor element; a first transistor; an amplifier having a first input coupled to a reference voltage source, having a second input coupled to a drain of the first transistor, and having an output coupled to a gate of the first transistor; and A second transistor has a gate coupled to the output of the amplifier and a drain coupled to the first branch of the first current mirror.

11. The DAC circuit of claim 10, wherein the reference resistance element is a same resistor type as a plurality of resistance elements in the resistor ladder circuit.

12. The DAC circuit of claim 8, wherein the second current source is calibrated and is independent of process, voltage, and temperature variations.

13. The DAC circuit of claim 1, wherein the first current sink is a short circuit between the shunt branch of the resistor ladder circuit and the reference potential node of the DAC circuit.

14. A method of operating a digital-to-analog converter (DAC) circuit comprising a plurality of current steering units and a resistor ladder circuit coupled to the plurality of current steering units, the method comprising: sinking a first portion of the common-mode current of the DAC circuit from a shunt branch of the resistor ladder circuit; as well as A second portion of the common-mode current of the DAC circuit is sunk from a first output of the DAC circuit.

15. The method of claim 14, wherein the first portion of the common-mode current decreases as the resistance of the resistor ladder circuit increases, and wherein the second portion of the common-mode current increases as the resistance of the resistor ladder circuit increases.

16. The method of claim 14, wherein the second portion of the common-mode current cancels at least a portion of a variation in the first portion of the common-mode current due to at least one of process, voltage, or temperature variations in the DAC circuit.

17. The method of claim 14, further comprising sinking a third portion of the common-mode current of the DAC circuit from a second output of the DAC circuit, wherein the first output and the second output constitute a differential output of the DAC circuit.

18. The method of claim 14, wherein absorbing the second portion of the common-mode current comprises: generating a first reference current; generating a second reference current in a first branch of a first current mirror based on said generating of said first reference current; mirroring the second reference current in a second branch of the first current mirror; generating a third reference current in a first branch of a second current mirror; mirroring the third reference current in a second branch of the second current mirror; providing a difference current as a difference between the mirrored third reference current and the mirrored second reference current to a first branch of a third current mirror; as well as The difference current is mirrored in a second branch of the third current mirror, wherein the second portion of the common-mode current comprises the mirrored difference current.

19. The method of claim 18, wherein mirroring the difference current comprises mirroring the difference current with a gain from the first branch of the third current mirror to the second branch of the third current mirror.

20. The method of claim 18, wherein the third reference current is calibrated and is independent of process, voltage, and temperature variations.

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