A frequency measurement system for turbine speed governor

Abstract

The present application relates to a frequency measurement system for a turbine governor, comprising an FPGA chip, a gear frequency measurement unit, a residual pressure frequency measurement unit, an AC sampling frequency measurement unit, an IRIG‑B code pair functional unit and an Ether Cat communication unit. The gear frequency measurement unit, the residual pressure frequency measurement unit, the AC sampling frequency measurement unit and the IRIG‑B code pair functional unit are all connected to the FPGA chip. The FPGA chip expands the Ether Cat chip to achieve fast and accurate communication between the electrical control system of the turbine governor and the hydraulic system, reducing the transmission time and signal interference between the electrical control system of the turbine governor and the hydraulic system. The present application improves the frequency measurement accuracy and response time of the turbine control system, reduces system delay, improves the dynamic response time of the primary frequency regulation of the turbine, and improves the qualified rate of the primary frequency regulation of the turbine.

Description

Technical Field

[0001] The present application relates to the field of frequency measurement of a turbine governor, and in particular to a frequency measurement system of a turbine governor. Background Art

[0002] According to the requirements of the "Technical Regulations and Test Guidelines for Primary Frequency Regulation of Grid-connected Power Sources" (GB / T 40593-2021) and the "Grid Operation Guidelines" (GB / T 31464-2022), the speed regulation system of the axial-flow propeller-type hydropower station unit is affected by the unit characteristics. During the primary regulation, there are problems such as inaccurate response of the reset signal, reverse regulation of active power, and excessive active power regulation time, which lead to failure in the primary frequency regulation assessment. The accuracy, reliability and real-time performance of the frequency measurement of the turbine speed governor are seriously insufficient. At present, the turbine frequency measurement combines 2-way residual pressure with 2-way gear disc frequency measurement; the residual pressure frequency measurement adopts zero-crossing comparison pulse counting. This method not only has a long frequency sampling interval, but is also very sensitive to noise and drift. It also has low frequency measurement accuracy, slow response, and poor anti-interference, which results in the unit not being able to operate correctly and accurately under small disturbances and failing to pass the primary frequency regulation assessment. In actual operation, due to the low frequency detection accuracy and slow response time, the unit frequency measurement data is inconsistent with the PMU measurement system frequency referenced by the power grid, and the governor action time does not match the power grid demand, resulting in inaccurate response to the reset signal when the primary frequency regulation is activated, affecting the primary frequency regulation pass rate. Large axial flow propeller turbine units have characteristics such as a long static time for the relay in the governor hydraulic system, large unit rotational inertia, and slow blade following, which leads to delayed response to unit load regulation and power reverse regulation, resulting in incorrect power action direction during the primary frequency regulation assessment and failure of the primary frequency regulation.

[0003] During the reciprocal process between the turbine motor and the generator of the pumped storage unit, the turbine control system receives the state that the monitoring motor will enter when it transitions from one state to another. During the transition process, the speed governor control system cannot measure the motor power due to the small motor voltage and current signals. At the same time, the traditional method of 2-way gear frequency measurement cannot accurately measure the creep frequency and unit status. As a result, the turbine control system cannot accurately judge the working state of the motor during the transition process.

[0004] In the current industry solutions, in the turbine speed governor frequency measurement control chip, the sampling rate of the 32-bit ARM chip does not exceed 20K SPS when the three-phase AC voltage signal is sampled and processed by MOUBUS communication for external transmission, and multiple tasks cannot be processed in parallel; the 64-bit CPU implements Ether cat communication when running the operating system. Affected by hardware resources, the ADC chip and the CPU transmit data via the SPI bus in the three-phase AC voltage signal sampling, and the sampling rate does not exceed 15K SPS; according to the primary frequency modulation technical requirements, the turbine speed regulation frequency measurement accuracy is higher than 0.05%. According to engineering experience, the sampling rate of the three-phase AC voltage signal reaches 30-40K SPS, and the frequency measurement accuracy can be higher than 0.05%. Summary of the invention

[0005] The purpose of the embodiments of the present application is to provide a turbine governor frequency measurement system and method, which uses FPGA as the computing center, and simultaneously processes the synchronous frequency measurement of the three-phase AC voltage on the machine side and the EtherCAT signal transmission, thereby reducing the delay time and improving the dynamic response time of the primary frequency regulation of the turbine.

[0006] To achieve the above objectives, this application provides the following technical solutions:

[0007] The present application provides a turbine governor frequency measurement system, including an FPGA chip, a toothed disc frequency measurement unit, a residual pressure frequency measurement unit, an AC sampling frequency measurement unit, an IRIG-B code pair function unit, and an Ether Cat communication unit. The toothed disc frequency measurement unit, the residual pressure frequency measurement unit, the AC sampling frequency measurement unit, and the IRIG-B code pair function unit are all connected to the FPGA chip. The FPGA chip is connected to the FPGA chip through the Ether Cat communication unit. The Cat communication unit is connected to the RJ45 network interface. The gear disc signal collected by the gear disc frequency measurement unit is conditioned by the conditioning circuit and input into the D-type latch in one way, and directly input into the FPGA chip in the other way. The D-type latch is connected to the FPGA chip for communication. The A-phase signal of the machine-end voltage collected by the residual voltage frequency measurement unit is connected in series with the current-type voltage transformer after passing through the voltage-dividing resistor to realize the isolation and conversion of the machine-end voltage. The secondary side of the transformer uses an operational amplifier to sample the current to realize the conversion of the current signal into voltage. The voltage signal is rectified by the logic gate after passing through 3-4 levels of RC passive filtering and then outputs the PWM signal to the FPGA chip. The three-phase voltage of the machine end collected by the AC sampling frequency measurement unit is converted into 3.5V by the precision AC signal converter to directly transmit it to CL1616 to realize the signal change, and then input into the FPGA chip through the high-speed level converter.

[0008] The FPGA chip is also connected to a memory unit, a switch input and output unit, and a frequency hard-connect output unit.

[0009] The turbine speed governor frequency measurement system also includes a power supply unit. The 24V input power supply is converted into a 5V power supply after differential mode and common mode hardware protection, and supplies power through the DC chip EN and PG pins to control the FPGA chip power supply power-on timing requirements. 1.0V is the FPGA chip core power supply, 1.8V is the FPGA chip peripheral power supply, 1.5V is the FPGA chip and memory unit power supply, and 1.5V and 3.3V are output to the memory unit analog reference power supply VTT through LDO SY6355.

[0010] BANK0 and BANK1 of the FPGA chip are used for memory unit chip control. The memory unit data lines and address lines are divided into 2 groups and 1 control line group. The first group of data lines and address lines are connected to the DQ20 family and DQ19 family of BANK0 of the FPGA chip, and the second group of data lines and address lines are connected to the DQ18 family and DQ17 family of BANK1 of the FPGA chip. The control bus of the memory unit is connected to the DQ16 family of BANK1 of the FPGA chip.

[0011] The DQ0 family and DQ2 family of BNAK 7 of the FPGA chip drive the KSZ8081MNX of the Ether Cat communication unit to realize the transmission and reception of a single Ether Cat communication signal, and DQ1 is the KSZ8081MNX signal chip select; the GPIO pin of BANK 7 sends the EtherCat communication unit signal to the counting unit of the turbine speed governor control system as a frequency signal.

[0012] The D-type latch includes an inverter 74HC14 and a NAND gate CD4011. The FPGA chip sends a pulse enable signal to control the working state of the D-type latch composed of the inverter 74HC14 and the NAND gate CD4011, thereby realizing the working state monitoring and frequency measurement of the 2-way gear disc frequency measurement.

[0013] Compared with the prior art, the beneficial effects of the present invention are: improving the frequency measurement accuracy and response time of the turbine control system, reducing system delay, increasing the dynamic response time of the turbine primary frequency regulation, and improving the qualified rate of the turbine primary frequency regulation. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments of the present application will be briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying creative work.

[0015] Figure 1 is a system structure diagram of an embodiment of the present application;

[0016] Figure 2 is a structural diagram of the power supply system of the present application;

[0017] Figure 3 It is the DDR3 expansion diagram of the FPGA of this application;

[0018] Figure 4 It is a schematic diagram of the FPGA acquisition frequency output of this application;

[0019] Figure 5 It is a three-phase AC sampling schematic diagram of this application;

[0020] Figure 6 This is a schematic diagram of FPGA residual voltage frequency measurement in this application;

[0021] Figure 7 This is a schematic diagram of the FPGA gear frequency measurement of this application;

[0022] Figure 8 is a schematic diagram of a D-type latch circuit of the present application;

[0023] Fig. 9 It is the FPGA frequency measurement principle diagram of this application;

[0024] Fig.10 This is a schematic diagram of the IRIG-B code timing function unit of the present application. DETAILED DESCRIPTION

[0025] The technical solutions in the embodiments of the present application will be described below in conjunction with the drawings in the embodiments of the present application. It should be noted that similar reference numerals and letters represent similar items in the following drawings, so once an item is defined in one drawing, it does not need to be further defined and explained in the subsequent drawings.

[0026] The terms "comprises," "comprising," or any other variation thereof are intended to encompass non-exclusive inclusion, such that a process, method, article, or apparatus that includes a list of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or apparatus. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of additional identical elements in the process, method, article, or apparatus that includes the element.

[0027] like Figure 1As shown, the embodiment of the present application provides a turbine governor frequency measurement system, including an FPGA chip 1, a toothed disc frequency measurement unit 2, a residual pressure frequency measurement unit 3, an AC sampling frequency measurement unit 4, an IRIG-B code pair function unit 5 and an Ether Cat communication unit 6, wherein the toothed disc frequency measurement unit 2, the residual pressure frequency measurement unit 3, the AC sampling frequency measurement unit 4, and the IRIG-B code pair function unit 5 are all connected to the FPGA chip 1, and the FPGA chip 1 is connected to the FPGA chip 1 through the Ether Cat communication unit 6. The Cat communication unit 6 is connected to the RJ45 network interface 7. The gear disc signal collected by the gear disc frequency measurement unit 2 is input into the D-type latch after conditioning by the conditioning circuit, and the other way is directly input into the FPGA chip 1. The D-type latch is connected to the FPGA chip 1 for communication. The A-phase voltage signal collected by the residual voltage frequency measurement unit 3 is connected in series with the current type voltage transformer after passing through the voltage dividing resistor to realize the voltage isolation and conversion of the machine end. The secondary side of the transformer uses the operational amplifier to sample the current to realize the current signal conversion into voltage. The voltage signal is rectified by the logic gate after passing through the 4-level RC passive filtering and then outputs the PWM signal to the FPGA chip 1. The three-phase voltage collected by the AC sampling frequency measurement unit 4 is converted into 3.5V by the precision AC signal converter to directly transmit to the CL1616 to realize the signal change, and then input to the FPGA chip 1 through the high-speed level converter. The FPGA chip 1 adopts the GW2A-LV55UG484 model chip.

[0028] The FPGA chip 1 is also connected to a memory unit 8 , a switch input and output unit 9 , and a frequency hard contact output unit 10 .

[0029] like Figure 2 As shown, the turbine speed governor frequency measurement system also includes a power supply unit. The 24V input power supply is converted into a 5V power supply after differential mode and common mode hardware protection, and is supplied through the DC chip EN and PG pins to control the FPGA chip 1 power supply power-on timing requirements. 1.0V is the core power supply of the FPGA chip 1, 1.8V is the peripheral power supply of the FPGA chip 1, 1.5V is the power supply of the FPGA chip 1 and the memory unit 8, and 1.5V and 3.3V are output to the memory unit 8 analog reference power supply VTT through LDO SY6355.

[0030] FPGA computing unit and peripheral expansion,

[0031] like Figure 3 , the memory unit 8 of the FPGA chip is also the DDR3 expansion:

[0032] The sampling rate of the FPGA chip is 30-40K SPS, and at least 936Kb of data is collected per second; the Ether cat communication parallel tasks occupy at least 100KB of RAM; the integrated RAM of GW2A-LV55UG484 does not exceed 3000Kb; combined with the AC voltage sampling rate of the primary frequency modulation machine end of the FPGA chip, DDR3 is expanded, the calculation rate of the FPGA chip is increased, the delay time of the frequency measurement control system is reduced, and the dynamic response time of the primary frequency modulation of the turbine is improved.

[0033] BANK0 and BANK1 of the FPGA chip 1 are used for memory unit 8 chip control. The data lines and address lines of the memory unit 8 are divided into 2 groups and 1 control line group. The first group of data lines and address lines are connected to the DQ20 group and DQ19 group of BANK0 of the FPGA chip 1, and the second group of data lines and address lines are connected to the DQ18 group and DQ17 group of BANK1 of the FPGA chip 1. The control bus of the memory unit 8 is connected to the DQ16 group of BANK1 of the FPGA chip 1.

[0034] like Figure 4 The DQ0 family and DQ2 family of BNAK 7 of the FPGA chip 1 drive the KSZ8081MNX of the Ether Cat communication unit 6 to realize the signal reception and transmission of the Ether Cat communication unit 6, and DQ1 is the chip select of the KSZ8081MNX signal; the GPIO pin of BANK 7 sends the Ether Cat communication unit 6 signal to the counting unit of the turbine speed governor control system as a frequency signal.

[0035] like Figures 5 to 10 As shown,

[0036] Frequency measurement unit:

[0037] The frequency measurement unit includes three-phase AC sampling frequency measurement, residual voltage frequency measurement, and gear frequency measurement at the machine end. The phase difference of the three-phase AC voltage at the machine end is 6.67ms; the residual voltage frequency measurement is to measure the frequency of phase A at the machine end. When the power grid is linked to the primary frequency regulation, the frequencies of the three phases A, B, and C at the machine end may be adjusted first. When the frequencies of phases B and C change, the residual voltage frequency measurement delays at least 6.67ms. Gear frequency measurement is used to judge the switching, creep and status of the turbine speed governor; in the current solutions in the industry, the gear frequency measurement is affected by the installation position of the probe and the production and processing technology, and it is impossible to judge the creep of the generator and the status of the unit. In this solution, a D-type latch composed of 74HC14 and CD4011 is used to realize the coupling of 2-way gear frequency measurement to judge the creep and status of the unit.

[0038] FPGA machine-side three-phase AC sampling implementation solution:

[0039] The three-phase AC sampling implementation scheme at the machine end is mainly used when the voltage at the machine end is greater than 50V. In order to reduce the signal conversion delay, the three-phase AC at the machine end uses a precision AC signal converter to convert the 100V AC signal at the machine end into 3.5V and directly transmit it to CL1616 to realize signal change, reduce the signal conditioning circuit, and the RC filter delays the signal during the direct transmission process.

[0040] FPGA calculates continuous periodic three-phase AC sampling signals and uses numerical integration methods to calculate the values ​​of various interference quantities in the sampling waveform. The calculated values ​​are transformed by Fourier transform to calculate the harmonic components, and then the effective value is obtained by using the linear network superposition principle. The high-density sampling voltage value determines the state of the unit, and then the zero-crossing comparison is used to calculate the collected voltage frequency. In theory, the higher the sampling density, the more accurate the measurement effect. The FPGA sampling rate is 30-40K SPS, and the voltage continuously collects effective values. , Due to high-density sampling, the sampling points are dense, and discrete values ​​are used to equal continuous voltage sampling integration when collecting and processing data, that is, . Calculate the effective value of voltage sampling and determine the frequency measurement priority of the unit; use zero-crossing comparison to calculate the frequency of the three-phase voltage signal. When the frequency of one phase of the three-phase AC voltage signal on the FPGA computer side changes, quickly output the frequency measurement value. Its output frequency signal is 1-2 times faster than the residual voltage frequency measurement (reference time: 6.67ms), which improves the dynamic response time of frequency measurement.

[0041] FPGA residual voltage frequency measurement implementation solution:

[0042] The residual voltage frequency measurement uses zero-crossing comparison pulse counting. This method not only has a long frequency sampling interval, 3-4 levels of RC filtering, long signal delay, but is also sensitive to noise, RC filter capacitor ambient temperature, and a maximum signal drift of 5ms, resulting in low frequency measurement accuracy and slow response. Due to the wide range of machine-side voltage of 0.3V~150V, the FPGA residual voltage implementation solution is mainly used when the machine-side voltage is 0.3V~50V.

[0043] The A phase of the machine-end voltage passes through the voltage-dividing resistor and is connected in series with a current-type voltage transformer to achieve machine-end voltage isolation and conversion. The secondary side of the transformer uses an operational amplifier to sample the current to convert the current signal into voltage. The voltage signal passes through 3-4 levels of RC passive filtering and then is rectified by a logic gate to output a PWM signal to the GPIO pin of BANK5 of the FPGA to achieve residual voltage frequency measurement.

[0044] FPGA gear frequency measurement implementation solution:

[0045] FPGA gear frequency measurement converts the 24V gear signal into a 5V signal through optoelectronic isolation, and transmits the GPIO of BANK 5 of FPGA through logic gate waveform shaping and polarity conversion CP01 and CP02 signals to realize gear counting. The commonly used counting method of turbines is affected by the gear processing technology, which leads to the measurement of signal level and cannot be realized. In the FPGA gear frequency measurement scheme, logic gate shaping filtering is added to reduce interference in hardware and improve the accuracy of gear frequency measurement. When the unit is creeping, FPGA receives the turbine control system or monitors the unit status data through switch input, and calculates the creep frequency by combining the frequency counting of CP01 and CP02 of the unit and the coupling monitoring signal GJ.

[0046] The D-type latch has the function of state recording and control switching of the control state. The D-type latch is composed of the inverter 74HC14 and the NAND gate circuit CD4011. The turbine control system or monitoring unit state data CP_EN and CP_02 frequency measurement are transmitted to the FPGA after the logic gate 74HC08 takes the AND coupling. The FPGA sends a pulse enable signal to control the logic gate trigger. In order to achieve stable triggering of the latch, the 2-channel gear disk conditioning signal CP02 is logically inverted, so that the CP01 and CP02 signals have a phase difference, avoiding the deviation of the gear disk installation position and the gear disk processing process that causes the unit state determination to be unable to be realized. When it is a generator, the D-type latch input signal RS is a high level, and when it is a motor, the D-type latch input signal RS is a low level. After conditioning, RS can be transmitted to the turbine control system; the GJ signal is used by the FPGA to monitor the working state of the D-type latch.

[0047] FPGA frequency measurement implementation logic diagram:

[0048] The frequency of the FPGA frequency measurement scheme is measured by three-phase AC sampling at the machine end, residual voltage frequency measurement, and gear disc frequency measurement. According to the characteristics of the three frequency measurement schemes, FPGA selects and combines the three frequency measurement schemes to reduce the delay time and improve the dynamic response time of the turbine primary frequency regulation. FPGA frequency measurement implementation scheme logic diagram:

[0049] IRIG-B code timing function unit

[0050] The primary frequency modulation time uses the IRIG-B code source as the time reference. Aiming at the serious inadequacies in frequency measurement accuracy and real-time performance of the turbine speed governor, a turbine speed governor frequency measurement implementation scheme is proposed. The hardware and software support the IRIG-B code to achieve time synchronization between the turbine speed governor frequency measurement and the primary frequency modulation action of the power grid.

[0051] Since the IRIG-B source signal needs to be collected through outdoor equipment, TVS is added to the signal input end to prevent surge and lightning strikes. The IRIG-B differential signal is converted into a TTL signal through the HT26LS32ARZ. The TTL signal is transmitted to the FPGA through high-speed optical coupler isolation to achieve time resolution, realize the coordination of the governor frequency measurement scheme and the primary frequency regulation action of the turbine control system, and reduce the impact of time deviation on the primary frequency regulation qualification rate.

[0052] Switching input and output unit:

[0053] A frequency measurement implementation scheme for a turbine governor. A switch input and output unit cooperates with the turbine governor frequency measurement scheme to receive status signals from a monitoring center and a turbine control system. The FPGA of the turbine governor frequency measurement is used to process multiple parallel tasks and perform complex logic operations, thereby achieving consistency between the governor frequency measurement and the primary frequency regulation action of the turbine control system, reducing the delay time of the frequency measurement control system, and improving the dynamic response time of the primary frequency regulation of the turbine.

[0054] The above description is only an embodiment of the present application and is not intended to limit the protection scope of the present application. For those skilled in the art, the present application may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A frequency measurement system for a turbine speed governor, characterized in that: The invention comprises an FPGA chip (1), a toothed disc frequency measuring unit (2), a residual voltage frequency measuring unit (3), an AC sampling frequency measuring unit (4), an IRIG-B code pair functional unit (5) and an Ether Cat communication unit (6), wherein the toothed disc frequency measuring unit (2), the residual voltage frequency measuring unit (3), the AC sampling frequency measuring unit (4) and the IRIG-B code pair functional unit (5) are all connected to the FPGA chip (1), and the FPGA chip (1) is connected to the FPGA chip (1) via the Ether Cat communication unit (6). The Cat communication unit (6) is connected to the RJ45 network interface (7). The gear disc signal collected by the gear disc frequency measurement unit (2) is conditioned by the conditioning circuit and then input into the D-type latch in one way and directly input into the FPGA chip (1) in the other way. The D-type latch is in communication connection with the FPGA chip (1). The A-phase voltage signal of the machine end collected by the residual voltage frequency measurement unit (3) is connected in series with a current-type voltage transformer after passing through a voltage-dividing resistor to realize the isolation and conversion of the machine end voltage. The secondary side of the transformer uses an operational amplifier to sample the current to realize the conversion of the current signal into a voltage. The voltage signal is rectified by a logic gate after passing through a 4-level RC passive filter and then outputs a PWM signal to the FPGA chip (1). The three-phase voltage of the machine end collected by the AC sampling frequency measurement unit (4) is converted into 3.5V by a precision AC signal converter to directly transmit to the CL1616 to realize the signal change, and then is input into the FPGA chip (1) through a high-speed signal converter.

2. A turbine speed governor frequency measurement system according to claim 1, characterized in that: The FPGA chip (1) is also connected to a memory unit (8), a switch input and output unit (9) and a frequency hard contact output unit (10).

3. A turbine governor frequency measurement system according to claim 2, characterized in that: The turbine speed governor frequency measurement system also includes a power supply unit. The 24V input power of the power supply unit is converted into a 5V power supply after differential mode and common mode hardware protection, and supplies power through the EN and PG pins of the DC chip to control the power-on timing requirements of the FPGA chip (1). 1.0V is the core power supply of the FPGA chip (1), 1.8V is the peripheral power supply of the FPGA chip (1), 1.5V is the power supply of the FPGA chip (1) and the memory unit (8), and 1.5V and 3.3V are output to the analog reference power supply VTT of the memory unit (8) through LDO SY6355.

4. A turbine governor frequency measurement system according to claim 1, characterized in that: BANK0 and BANK1 of the FPGA chip (1) are used for memory unit (8) chip control. The data lines and address lines of the memory unit (8) are divided into two groups and one control line group. The first group of data lines and address lines are connected to the DQ20 group and the DQ19 group of BANK0 of the FPGA chip (1). The second group of data lines and address lines are connected to the DQ18 group and the DQ17 group of BANK1 of the FPGA chip (1). The control bus of the memory unit (8) is connected to the DQ16 group of BANK1 of the FPGA chip (1).

5. A turbine governor frequency measurement system according to claim 1, characterized in that: The DQ0 family and the DQ2 family of the BNAK 7 of the FPGA chip (1) drive the KSZ8081MNX of the Ether Cat communication unit (6) to realize the signal transmission and reception of the Ether Cat communication unit (6), and DQ1 is the KSZ8081MNX signal chip select; the GPIO pin of the BANK 7 will send the frequency signal to the counting unit of the turbine speed governor control system in the Ether Cat communication mode.

6. A frequency measurement system for a turbine speed governor according to claim 1, characterized in that: The D-type latch comprises an inverter 74HC14 and a NAND gate CD4011. The FPGA chip (1) sends a pulse enable signal to control the working state of the D-type latch composed of the inverter 74HC14 and the NAND gate CD4011, thereby realizing the working state monitoring and frequency measurement of the two-way gear disc frequency measurement.

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