Comparator chip test equipment and method
By providing a comparator chip testing equipment and method including a test chip plug-in section, a data update module and a controller, the problems of high testing costs and low automation in the prior art are solved, and more efficient and automated testing is achieved process.
Patent Information
- Application Number
- CN202411489593.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-10-24
- Publication Date
- 2025-02-07
AI Technical Summary
During the testing of existing comparator chips, different circuit boards and update test programs are required, resulting in high testing costs and low automation.
A test device and method for comparator chips are provided, including a test chip plug-in, a data update module and a controller. The test chip plug-in and unplug the comparator chip directly through the test chip plug-in. The data update module provides a start-up indication signal to automatically load or update the program, and the controller communicates with the comparator chip to adjust the test items.
It reduces the testing cost, simplifies the replacement process of comparator chips, and improves the degree of automation and efficiency of testing.
Smart Images
Figure CN119395502A_ABST
Abstract
Description
Technical Field
[0001] The present disclosure relates to the field of chip testing technology, and in particular to a testing device and method for a comparator chip. Background Art
[0002] A comparator chip is an integrated voltage comparator that can be used for waveform generation or conversion circuits. Usually, the analog parameters of the comparator chip are tested before it is put into use. The analog parameters of the comparator include: hysteresis, transmission delay, power consumption, offset voltage, etc.
[0003] In the existing comparator chip testing process, when testing different comparator chips, different circuit boards need to be replaced to test different comparator chips respectively, and the program running the comparator chip needs to be updated for each test. Therefore, how to reduce the testing cost of comparator chips and improve the degree of automation of testing has become an urgent problem to be solved. Summary of the invention
[0004] In order to solve the above technical problem or at least partially solve the above technical problem, the present disclosure provides a testing device and method for a comparator chip.
[0005] The present disclosure provides a test device for a comparator chip, comprising: a test chip plug-in portion, comprising a chip socket and a chip test circuit, the chip test circuit being electrically connected to the chip socket, and the chip socket being used for plugging and connecting with a comparator chip to be tested; a data update module, the data update module being electrically connected to the chip socket, and the data update module being used for providing a start indication signal so that the comparator chip to be tested starts a running program or starts an update program based on the start indication signal; and a controller, being used for communicating with the comparator chip to be tested to adjust the test items of the comparator chip to be tested.
[0006] Optionally, the data update module includes: a storage circuit for storing an update program; an update indication circuit for providing a start indication signal, the start indication signal being used to indicate a start mode of the comparator chip to be tested; the update indication circuit and the storage circuit are both connected to the comparator chip to be tested via a chip socket; the comparator chip to be tested is used to obtain the running program stored in the storage circuit according to the start indication signal.
[0007] Optionally, the update indication circuit includes a first indication terminal and a second indication terminal; the first indication terminal and the second indication terminal are used to output a level signal, and the comparator chip to be tested is used to obtain an update program from the storage circuit according to the level signal.
[0008] Optionally, the controller includes a host computer; the host computer is connected to the storage circuit via a chip socket, and the host computer is used to update the running program stored in the storage circuit through the comparator chip to be tested.
[0009] Optionally, the chip test circuit includes a signal input circuit; the signal generator is electrically connected to the chip socket through the signal input circuit, and the signal input circuit is used to output different test voltages provided by the signal generator to the positive terminal and / or negative terminal of the comparator chip to be tested.
[0010] Optionally, the chip test circuit also includes a relay group; the relay group is connected to the controller, and the signal input circuit is connected to the chip socket through the relay group; the relay group is used to control the on and off of one or more channels between the signal input circuit and the comparator chip to be tested according to the signal of the controller.
[0011] The present disclosure also provides a testing method for a comparator chip, which is applied to a testing device for the comparator chip of any of the above-mentioned items, and the method comprises: configuring a startup indication signal in a data update module based on a startup mode of the comparator chip to be tested; the comparator chip to be tested is configured to load a running program or load an update program based on the startup indication signal when inserted into a chip socket; wherein the update program is stored in the data update module; under each test item of the comparator chip to be tested, sending a control signal corresponding to the test item to the comparator chip to be tested, and sending a signal generation instruction corresponding to the test item to a signal generator; wherein the signal generator generates a corresponding test voltage based on the signal generation instruction; and obtaining test data generated by the comparator chip to be tested based on the test voltage corresponding to the test item.
[0012] Optionally, based on the startup mode of the comparator chip under test, a startup indication signal is configured in the data update module, including: when the startup mode corresponding to the comparator under test is the first mode, configuring the first mode signal in the data update module; when the startup mode corresponding to the comparator under test is the second mode, configuring the second mode signal in the data update module; wherein the comparator chip under test is configured to load and run the program from the storage unit of the comparator chip under test based on the first mode signal; and load the update program from the storage circuit of the data update module based on the second mode signal.
[0013] Optionally, after obtaining the test result generated by the comparator under test based on the test voltage corresponding to the test item, it also includes: generating a test report according to the test data corresponding to all the test items respectively; and sending a test exception message when there is a test result failure of at least one test item.
[0014] Optionally, based on the startup mode of the comparator chip to be tested, before configuring the startup indication signal in the data update module, it also includes: generating a corresponding update program based on multiple test items of the comparator chip to be tested; and writing the update program into the storage circuit of the data update module.
[0015] The present disclosure provides a comparator chip test device and method, the test device includes a test chip plug-in part, a data update module and a controller. The test chip plug-in part includes a chip socket and a chip test circuit. In the process of testing the comparator chip to be tested, the comparator chip to be tested can be directly replaced by plugging and unplugging the comparator chip to be tested from the chip socket. After the comparator chip to be tested is plugged into the chip socket, the comparator chip to be tested is connected to the data update module. The comparator chip to be tested starts the running program according to the start indication signal stored in the data update module when the comparator chip to be tested does not need to update the running program, or starts the update program when the comparator chip to be tested needs to update the running program, so as to update the running program of the comparator chip to be tested. Therefore, the present disclosure replaces the test circuit board of the comparator chip to be tested with the test chip plug-in part. During the test process, the comparator chip to be tested can directly test the test items set by the controller through the chip test circuit, and when replacing the comparator chip to be tested, it only needs to be directly plugged in and replaced, and there is no need to replace the test circuit board of the measured comparator chip. Therefore, there is no need to design and manufacture test circuit boards for different types of comparator chips, which reduces the test cost, and replacing the comparator chip to be tested by plugging and unplugging also simplifies the replacement process of the comparator chip to be tested, improving the efficiency of the test. And after replacing the comparator chip to be tested, the present disclosure will automatically start the running program or start the update program according to the start indication signal of the data update module, thereby improving the automation of the test. BRIEF DESCRIPTION OF THE DRAWINGS
[0016] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for use in the embodiments of the present invention are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.
[0017] Figure 1 A schematic diagram of the structure of a comparator chip testing device provided in an embodiment of the present disclosure.
[0018] Figure 2 A schematic structural diagram of a preferred comparator chip testing device provided in an embodiment of the present disclosure.
[0019] Figure 3 A flowchart of a comparator chip testing method provided in an embodiment of the present disclosure.
[0020] Figure 4 A flow chart of another comparator chip testing method provided in an embodiment of the present disclosure DETAILED DESCRIPTION
[0021] The features and exemplary embodiments of various aspects of the present invention will be described in detail below. In the detailed description below, many specific details are proposed to provide a comprehensive understanding of the present invention. However, it is obvious to those skilled in the art that the present invention can be implemented without the need for some of these specific details. The following description of the embodiments is only to provide a better understanding of the present invention by illustrating examples of the present invention.
[0022] It should be noted that, in the absence of conflict, the embodiments and features in the embodiments of the present application can be combined with each other. The embodiments will be described in detail below in conjunction with the accompanying drawings.
[0023] Figure 1 A schematic diagram of a comparator chip test device provided in an embodiment of the present disclosure, such as Figure 1 As shown, the test device comprises: a test chip plug-in portion 100, a data update module 200 and a controller 300. The controller 300 is used to communicate with the comparator chip to be tested to adjust the test items of the comparator chip to be tested.
[0024] The test chip plug-in portion 100 includes a chip socket 110 and a chip test circuit 120 . The chip test circuit 120 is electrically connected to the chip socket 110 . The chip socket 110 is used for plugging and connecting with the comparator chip to be tested.
[0025] Specifically, the controller 300 is electrically connected to the chip socket 110. During the process of testing the comparator chip to be tested, the comparator chip to be tested can be directly replaced by plugging and unplugging it from the chip socket 110. After the comparator chip to be tested is plugged into the chip socket 110, the comparator chip to be tested is electrically connected to the chip test circuit 120 through the chip socket 110, and the controller 300 communicates with the comparator chip to be tested through the chip socket 110. The controller 300 sends a control signal to the comparator chip to adjust the test items of the comparator chip to be tested. The comparator chip to be tested receives different test voltages sent by the controller 300 through the chip test circuit 120 to complete all test items of the comparator chip to be tested. The test items of the comparator chip to be tested include test power consumption, test offset, test hysteresis, test step response, and test ramp response. The present invention replaces the test circuit board of the comparator chip to be tested with the test chip plug-in part 100. During the testing process, the comparator chip to be tested can directly test the test items set by the controller 300 through the chip test circuit 120, and when replacing the comparator chip to be tested, it only needs to be directly plugged in and replaced, and there is no need to replace the test circuit board of the comparator chip to be tested. Therefore, there is no need to design and manufacture test circuit boards for different types of comparator chips, which reduces the testing cost. In addition, replacing the comparator chip to be tested by plugging in and out simplifies the replacement process of the comparator chip to be tested, thereby improving the testing efficiency.
[0026] The data updating module 200 is electrically connected to the chip socket 110 , and is used to provide a start indication signal so that the comparator chip to be tested starts a running program or starts an updating program based on the start indication signal.
[0027] Specifically, the data update module 200 stores the running program to be updated and can provide a start-up indication signal. The start-up indication signal includes a first mode signal and a second mode signal. The first mode signal is a signal indicating that the comparator chip to be tested does not need to update the running program and directly starts the existing running program. The second mode signal is a signal indicating that the comparator chip to be tested needs to update the running program and start the update program, which is the updated running program. After being placed in the chip socket 110, the comparator chip to be tested will receive the start-up indication signal provided by the data update module 200. When the comparator chip to be tested receives the first mode signal, the comparator chip to be tested will directly run the running program stored in the storage unit of the comparator chip to be tested. When the comparator chip to be tested receives the second mode signal, the comparator chip to be tested will replace the running program stored in the storage unit with the running program stored in the data update module 200, and run the updated running program. Therefore, after the comparator chip to be tested is placed in the chip socket 110, the present invention automatically obtains the start indication signal provided by the data update module 200, and starts the running program when there is no need to update the running program, or starts the update program when the running program needs to be updated, so as to update the running program of the comparator chip to be tested, thereby realizing the automatic running program or automatic update program of the comparator chip to be tested, and improving the degree of automation of the test.
[0028] In some embodiments, the data update module includes: a storage circuit for storing an update program; an update indication circuit for providing a start indication signal, the start indication signal being used to indicate a start mode of the comparator chip to be tested; the update indication circuit and the storage circuit are both connected to the comparator chip to be tested via a chip socket; the comparator chip to be tested is used to obtain the running program stored in the storage circuit according to the start indication signal.
[0029] Specifically, the comparator chip to be tested is electrically connected to the update indication circuit and the storage circuit through a chip socket, and the comparator chip to be tested obtains the start indication signal provided in the update indication circuit, and the start indication signal includes a first mode signal and a second mode signal. The first mode signal is a signal indicating that the comparator chip to be tested does not need to update the running program and starts the running program. The second mode signal is a signal indicating that the comparator chip to be tested needs to update the running program and starts the update program. The storage circuit stores the running program that the comparator chip to be tested needs to update. When the comparator chip to be tested receives the second mode signal, the comparator chip to be tested will directly replace the running program stored in the storage unit with the running program stored in the storage circuit. After being placed in the chip socket, the comparator chip to be tested will receive the start indication signal provided by the update indication circuit. When the comparator chip to be tested receives the first mode signal, the comparator chip to be tested will directly run the running program stored in the storage unit of the comparator chip to be tested. When the comparator chip to be tested receives the second mode signal, the comparator chip to be tested will replace the running program stored in the storage unit with the running program stored in the storage circuit, and run the updated running program. Therefore, after the comparator chip to be tested is placed in the chip socket, the present invention automatically obtains the start indication signal provided by the update indication circuit. The comparator chip to be tested starts the running program stored in its own storage unit without updating the running program, or downloads the running program stored in the storage circuit and starts it when the running program needs to be updated. This enables the comparator chip to automatically run the program or automatically update the program according to the start indication signal of the update indication circuit during the test, thereby improving the degree of automation of the test.
[0030] In some embodiments, the update indication circuit includes a first indication terminal and a second indication terminal; the first indication terminal and the second indication terminal are used to output level signals, and the comparator chip to be tested is used to obtain the update program from the storage circuit according to the level signal.
[0031] Exemplarily, the comparator chip to be tested is electrically connected to the first indication terminal and the second indication terminal respectively through a chip socket, and the comparator chip to be tested is provided with a first storage unit and a second storage unit respectively, and the memory of the first storage unit is smaller than the memory of the second storage unit, so the first storage unit is used to store an operating program with a smaller memory, and the second storage unit is used to store an operating program with a larger memory. The first indication terminal and the second indication terminal are both used to output level signals. When the first indication terminal and the second indication terminal both output low-level signals, the comparator chip to be tested directly runs the operating program stored in the first storage unit. When the first indication terminal outputs a low-level signal and the second indication terminal outputs a high-level signal, the comparator chip to be tested downloads the operating program stored in the storage circuit to the first storage unit. If the first storage unit stores an operating program, the original operating program in the first storage unit is overwritten, and the updated operating program in the first storage unit is run. When the first indication terminal outputs a high level signal and the second indication terminal outputs a low level signal, the comparator chip to be tested downloads the operating program stored in the storage circuit to the second storage unit. If the operating program is stored in the second storage unit, the original operating program in the second storage unit is overwritten, and the updated operating program in the second storage unit is run. Therefore, the present disclosure sets the level signals output by the first indication terminal and the second indication terminal of the update indication circuit, so that after the comparator chip to be tested is placed in the chip socket, it can determine whether the program needs to be updated according to the level signals output by the first indication terminal and the second indication terminal, thereby realizing that the comparator chip to be tested automatically runs the program or automatically updates the program according to the level signals output by the first indication terminal and the second indication terminal during the test process, thereby improving the degree of automation of the test.
[0032] It should be noted that the first indication terminal and the second indication terminal both output low-level signals, the first indication terminal outputs a low-level signal and the second indication terminal outputs a high-level signal, the first indication terminal outputs a high-level signal and the second indication terminal outputs a low-level signal, and the corresponding working modes of the comparator chip to be tested are only examples. The specific level signals output by the first indication terminal and the second indication terminal correspond to the working modes of the comparator chip to be tested which need to be set according to actual conditions and are not specifically limited here.
[0033] In some embodiments, the controller includes a host computer; the host computer is connected to the storage circuit via a chip socket, and the host computer is used to update the running program stored in the storage circuit through the comparator chip to be tested.
[0034] Specifically, after the comparator chip to be tested is placed in the chip socket, the host computer communicates with the storage circuit through the chip socket and the comparator chip to be tested, and the host computer replaces the running program stored in the storage circuit through the comparator chip to be tested. Therefore, during the test process, if a new comparator chip to be tested needs to be tested, the present disclosure does not need to set up a new hardware circuit to cope with the test, but directly uses the host computer to communicate with the storage circuit through the comparator chip to be tested to replace the program, thereby reducing the hardware cost of the test, and further reducing the cost of the entire test.
[0035] In some embodiments, the chip test circuit includes a signal input circuit; the signal generator is electrically connected to the chip socket through the signal input circuit, and the signal input circuit is used to output different test voltages provided by the signal generator to the positive terminal and / or negative terminal of the comparator chip to be tested.
[0036] Specifically, the signal generator is connected to the controller, and the controller can set the voltage output by the signal generator to provide different test voltages. The signal input circuit outputs different test voltages provided by the signal generator to the positive terminal and / or negative terminal of the comparator chip to be tested through two output terminals respectively, and the comparator chip to be tested outputs a level signal by comparing the magnitude of the voltage received by the positive terminal and the negative terminal. The chip test circuit also includes a signal output circuit, and the chip socket is connected to the oscilloscope through the signal output circuit, and the oscilloscope is also connected to the controller. When the voltage received at the positive terminal is greater than the voltage received at the negative terminal, the comparator chip to be tested outputs a high level signal to the oscilloscope through the signal output circuit; when the voltage received at the positive terminal is less than the voltage received at the negative terminal, the comparator chip to be tested outputs a low level signal to the oscilloscope through the signal output circuit. The oscilloscope can output the waveforms of the received high and low level signals to the controller, and the controller compares the received oscilloscope waveforms with the preset test standards to determine whether there is an abnormality in the comparator chip to be tested, and generates a test report based on the abnormal situation and sends it to the tester, thereby realizing automated testing of the comparator chip to be tested and improving the degree of automation of the test.
[0037] In some embodiments, the chip test circuit also includes a relay group; the relay group is connected to the controller, and the signal input circuit is connected to the chip socket through the relay group; the relay group is used to control the on and off of one or more channels between the signal input circuit and the comparator chip to be tested according to the signal of the controller.
[0038] Specifically, a plurality of comparator channels are provided in the comparator chip to be tested, and each comparator channel is connected to the signal input circuit through a chip socket and a relay in a relay group. When the controller needs to test a certain comparator channel, or to test a plurality of comparator channels simultaneously, the on-off of the relay group can be controlled to achieve on-off control of the signal input circuit and the comparator channel to be tested. The present invention controls the on-off of the relay group according to different test requirements through a controller, thereby achieving on-off control between one or more comparator channels of the comparator chip to be tested and the signal input circuit, without the need for manual setting of the test of the comparator chip to be tested, thereby improving the degree of automation of the test.
[0039] Figure 2 A schematic diagram of a preferred comparator chip testing device provided in an embodiment of the present disclosure is shown in FIG. Figure 2 As shown, the test equipment includes: a chip socket 110, a chip test circuit, a storage circuit 210, an update indication circuit 220, a power module 340 and a host computer 310, the update indication circuit 220 includes a first indication terminal 221 and a second indication terminal 222, the chip test circuit includes a signal input circuit 121, a signal output circuit 122, a relay group 123 and a chip working circuit 124.
[0040] The signal generator 320 is connected to the signal input circuit 121, the signal input circuit 121 is electrically connected to the chip socket 110 through the relay group 123, the chip socket 110 is connected to the oscilloscope 330 through the signal output circuit 122, and the host computer 310 is connected to the chip socket 110 in communication. The host computer 310 is also connected to the signal generator 320, the oscilloscope 330, the power module 340 and the relay group 123, and the power module 340 is used to supply power to the comparison chip to be tested. The chip socket 110 is respectively connected to the chip working circuit 124, the storage circuit 210, the first indication terminal 221 and the second indication terminal 222.
[0041] Specifically, the host computer 310 is electrically connected to the chip socket 110. During the process of testing the comparator chip to be tested, the comparator chip to be tested can be directly replaced by plugging and unplugging it from the chip socket 110. After the comparator chip to be tested is plugged into the chip socket 110, the comparator chip to be tested is electrically connected to the chip test circuit through the chip socket 110, and the host computer 310 communicates with the comparator chip to be tested through the chip socket 110. The host computer 310 sends a control signal to the comparator chip to be tested to adjust the test items of the comparator chip to be tested. The comparator chip to be tested completes the control signal sent by the host computer 310 through the chip test circuit to complete all the test items of the comparator chip to be tested. The test items of the comparator chip to be tested include test power consumption, test offset, test hysteresis, test step response, and test ramp response.
[0042] After the chip socket 110 is powered on, the comparator chip to be tested acquires the level signals of the first indication terminal 221 and the second indication terminal 222 of the update indication circuit 220, and determines the startup running program or the update running program of the comparator chip to be tested according to the acquired level signals. The comparator chip to be tested is respectively provided with a first storage unit and a second storage unit, and the memory of the first storage unit is smaller than the memory of the second storage unit, so the first storage unit is used to store the running program with a smaller memory, and the second storage unit is used to store the running program with a larger memory. When the first indication terminal and the second indication terminal both output low-level signals, the comparator chip to be tested directly runs the running program stored in the first storage unit. When the first indication terminal outputs a low-level signal and the second indication terminal outputs a high-level signal, the comparator chip to be tested downloads the update program stored in the storage circuit 210 to the first storage unit. If there is a running program in the first storage unit, the original running program in the first storage unit is overwritten, and the updated running program in the first storage unit is run. When the first indication terminal outputs a high-level signal and the second indication terminal outputs a low-level signal, the comparator chip under test will download the update program stored in the storage circuit 210 to the second storage unit. If there is an operating program in the second storage unit, the original operating program in the second storage unit will be overwritten, and the updated operating program in the second storage unit will be run, thereby completing the self-test process of the comparator chip under test.
[0043] After the self-test of the comparator chip under test is completed, the host computer 310 sends various control signals to the comparator chip under test and the signal generator 320 in sequence, and the oscilloscope 330 generates a waveform based on the result of comparing the voltage output by the comparator chip under test with the signal generator 320, and outputs it to the host computer 310.
[0044] First, a power consumption test is performed on the comparator chip to be tested. The host computer 310 controls the power supply module 340 to power on and collects the voltage and current of the comparator chip to be tested. When the product of the voltage and the current does not exceed the power consumption threshold, it is determined that the power consumption test of the comparator chip to be tested has failed.
[0045] In the second step, the comparator chip to be tested is subjected to an offset test. The host computer 310 controls the signal generator 320 to output a voltage to the comparator chip to be tested, and the oscilloscope 330 outputs a test waveform to the host computer 310 according to the comparison result of the comparator chip to be tested on the input voltage. Since the input reference offset refers to the offset or offset voltage that does not conform to the ideal situation at the input end of the comparator chip when the comparator chip is used. Therefore, during the test, the positive input end of the comparator chip to be tested is set to be 20mV higher than the voltage of the negative input end, or the positive input end of the comparator chip to be tested is set to be 20mV lower than the voltage of the negative input end. If the waveform of the output voltage of the comparator chip to be tested received by the oscilloscope 330 does not flip, the offset test fails.
[0046] The third step is to perform a hysteresis test on the comparator chip to be tested. Due to the high accuracy of the comparator chip, the fluctuations caused by noise interference will cause the output of the comparator chip to continuously jump near the threshold. In order to improve this shortcoming, a hysteresis effect is introduced to improve the performance of the comparator chip. This feature is called hysteresis. For example, if the offset index is 20mV, then after turning on the hysteresis, the index will become about 40mV. There are 4 levels of hysteresis here. The first level of hysteresis is 40mV, the second level is 60mV, the third level is 80mV, and the fourth level is 100mV. If the waveform of the output voltage of the comparator chip to be tested received by the oscilloscope 330 does not flip within the index, the hysteresis test fails.
[0047] The fourth step is to test the step response of the comparator chip to be tested. The step response is the response of the comparator chip to the step input signal. The step input signal is a signal that suddenly jumps from 0 to a non-zero value (usually 1) at a certain moment. Then the comparator chip will also reverse from outputting 0 to 1. When the delay from the midpoint of the flipping of the input signal output by the signal generator 320 to the midpoint of the flipping of the output signal of the comparator chip to be tested received by the oscilloscope 330 exceeds 60ns, the step response test fails.
[0048] The fifth step is to test the ramp response of the comparator chip to be tested. The ramp response describes the response characteristics of the output of the comparator chip changing with time when the input signal of the comparator chip increases from zero at a constant slope. There are two ramp input signals, with slopes of 1.65V / us and 8.25mV / us respectively; the output signal is a square wave signal that reverses from 0 to 1. When the time between the midpoint of the ramp input signal output by the signal generator 320 to the midpoint of the reverse output signal of the comparator chip to be tested and the time when the oscilloscope 330 receives the midpoint of the reverse output signal of the comparator chip to be tested exceeds 100ns, the ramp response test fails.
[0049] The present disclosure outputs control signals to signal generator 320 and comparator chip to be tested in sequence through host computer 310, to complete the test of each test item of comparator chip to be tested. And signal generator 320 is electrically connected to chip socket 110 through signal input circuit 121, and relay group 123 is also provided between signal input circuit 121 and chip socket 110, and relay group 123 is connected to host computer 310. Therefore, during the test, relay group 123 conducts one or more comparator channels of comparator chip to be tested according to the instruction of host computer 310, to complete the test of each comparator channel of comparator chip to be tested. Oscilloscope 330 is also connected to host computer 310, so host computer 310 can receive the test waveform generated by oscilloscope 330, and host computer 310 obtains test result according to test waveform, and sends the test result to the communication equipment of test personnel by forms such as mail, so that test personnel can understand the test situation at any time.
[0050] Therefore, the present disclosure replaces the test circuit board of the comparator chip to be tested by the chip socket 110 and the chip test circuit. During the test process, the comparator chip to be tested can directly test the test items set by the host computer 310 through the chip test circuit, and when replacing the comparator chip to be tested, it only needs to be directly plugged in and replaced, and there is no need to replace the test circuit board of the measured comparator chip, so there is no need to design and manufacture test circuit boards for different types of comparator chips, which reduces the test cost, and replacing the comparator chip to be tested by plugging and unplugging also simplifies the replacement process of the comparator chip to be tested, and improves the test efficiency. In addition, after the comparator chip to be tested is placed in the chip socket 110, the present disclosure automatically determines whether it is necessary to update the running program of the comparator chip to be tested according to the level signal output by the first indication terminal 221 and the second indication terminal 222 of the update indication circuit 220. When an update is required, the update program stored in the storage circuit 210 is directly downloaded to the comparator chip to be tested, or when an update is not required, the running program stored in the comparator chip to be tested is directly run, thereby realizing the automatic running program or automatic updating program of the comparator chip to be tested. In addition, the host computer 310 will automatically output control signals to each device without the need for the tester to operate, and the test results after the test will also be directly sent to the tester, without the need for the tester to actively download and obtain, thereby improving the degree of automation of the test.
[0051] Figure 3 A flow chart of a comparator chip testing method provided in an embodiment of the present disclosure is provided. The testing method is applied to the testing device of any of the above embodiments, such as Figure 2 As shown, the testing method includes: S410-S430.
[0052] S410 , configuring a start indication signal in a data update module based on a start mode of the comparator chip to be tested.
[0053] Specifically, the startup mode of the comparator chip to be tested is to start the running program or start the updating program. The controller configures a startup indication signal for indicating the running program in the data updating module according to the startup running program mode of the comparator chip to be tested. The controller configures a startup indication signal for indicating the updating program in the data updating module according to the startup updating program mode of the comparator chip to be tested. The comparator chip to be tested is configured to load the running program or load the updating program based on the startup indication signal when placed in the chip socket; wherein the updating program is stored in the data updating module. The present disclosure configures a startup indication signal in the data updating module based on the startup mode of the comparator chip to be tested, thereby realizing that after the comparator chip to be tested is placed in the chip socket, the comparator chip to be tested automatically obtains the startup indication signal provided by the data updating module, starts the running program when there is no need to update the running program, or starts the updating program when there is a need to update the running program, so as to update the running program of the comparator chip to be tested, thereby realizing the automatic running program or automatic updating program of the comparator chip to be tested, and improving the automation of the test.
[0054] S420, under each test item of the comparator chip to be tested, sending a control signal corresponding to the test item to the comparator chip to be tested, and sending a signal generation instruction corresponding to the test item to the signal generator, wherein the signal generator generates a corresponding test voltage based on the signal generation instruction.
[0055] Specifically, the controller sends control signals corresponding to the test items to the comparator chip under test in turn according to the test items of the comparator chip under test, and the comparator chip under test completes all the test items of the comparator chip under test through the chip test circuit according to the control signals sent by the controller. The test items of the comparator chip under test include test power consumption, test offset, test hysteresis, test step response and test ramp response. The controller also sends signal generation instructions corresponding to the test items to the signal generator, and the signal generator outputs two test voltages of different sizes to the positive and negative ends of the comparator chip under test according to the instructions.
[0056] S430, obtaining test data generated by the comparator chip under test based on the test voltage corresponding to the test item.
[0057] Specifically, the comparator chip to be tested is connected to the oscilloscope through a chip socket. In each test item, when the voltage received by the positive terminal of the comparator chip to be tested is greater than the voltage received by the negative terminal, the comparator chip to be tested outputs a high-level signal to the oscilloscope. When the voltage received by the positive terminal is less than the voltage received by the negative terminal, the comparator chip to be tested outputs a low-level signal to the oscilloscope, and the oscilloscope outputs waveforms as test data according to the received high and low level signals. The oscilloscope is also connected to a controller, and the oscilloscope can output the waveforms of the received high and low level signals to the controller, thereby, the controller realizes the acquisition of the test data generated by the comparator chip to be tested based on the test voltage corresponding to the test item through the oscilloscope. The controller compares the received test data according to the preset test standard, determines whether the comparator chip to be tested is abnormal according to the comparison result, and generates a test report according to the abnormal situation and sends it to the tester, thereby realizing the automated test of the comparator chip to be tested, and improving the automation of the test.
[0058] In some embodiments, based on the startup mode of the comparator chip to be tested, configuring the startup indication signal in the data update module includes: when the startup mode corresponding to the comparator to be tested is the first mode, configuring the first mode signal in the data update module. When the startup mode corresponding to the comparator to be tested is the second mode, configuring the second mode signal in the data update module.
[0059] The comparator chip under test is configured to load the running program from the storage unit of the comparator chip under test based on the first mode signal; and load the updating program from the storage circuit of the data updating module based on the second mode signal.
[0060] Specifically, the data update module includes an update indication circuit, the update indication circuit includes a first indication terminal and a second indication terminal, the update indication circuit is used to output a start indication signal through the first indication terminal and the second indication terminal, and the first indication terminal and the second indication terminal are used to output a level signal. The comparator chip to be tested is electrically connected to the first indication terminal and the second indication terminal through a chip socket, respectively. The comparator chip to be tested is provided with a first storage unit and a second storage unit, respectively. The memory of the first storage unit is smaller than the memory of the second storage unit. Therefore, the first storage unit is used to store an operating program with a smaller memory, and the second storage unit is used to store an operating program with a larger memory. The data update module stores the operating program that needs to be updated for the comparator chip to be tested.
[0061] The first indication terminal and the second indication terminal are both used to output level signals, and the first indication terminal and the second indication terminal both output low-level signals as the first mode signal. Under the first mode signal, the comparator chip to be tested directly runs the operating program stored in the first storage unit. The first indication terminal outputs a low-level signal, the second indication terminal outputs a high-level signal, and the first indication terminal outputs a high-level signal, and the second indication terminal outputs a low-level signal as the second mode signal. Under the second mode signal, and when the memory of the operating program to be updated is small, the comparator chip to be tested downloads the operating program stored in the data update module to the first storage unit. If the operating program is stored in the first storage unit, the original operating program in the first storage unit is overwritten, and the updated operating program in the first storage unit is run. Under the second mode signal, and when the memory of the operating program to be updated is large, the comparator chip to be tested downloads the operating program stored in the data update module to the second storage unit. If the operating program is stored in the second storage unit, the original operating program in the second storage unit is overwritten, and the updated operating program in the second storage unit is run. Therefore, after the comparator chip to be tested is placed in the chip socket, the present invention automatically obtains the first mode signal or the second mode signal stored in the data update module. The comparator chip to be tested directly starts the running program without updating the running program, or downloads the running program stored in the data update module and starts it when the running program needs to be updated. In this way, the comparator chip to be tested automatically runs the program or automatically updates the program according to the first mode signal or the second mode signal of the data update module during the test process, thereby improving the degree of automation of the test.
[0062] In some embodiments, after obtaining the test results generated by the comparator under test based on the test voltage corresponding to the test item, the testing method also includes: generating a test report according to the test data corresponding to all the test items respectively; and sending a test exception message when there is a test result failure of at least one test item.
[0063] Specifically, Figure 4 A flow chart of another comparator chip testing method provided in an embodiment of the present disclosure is shown as follows: Figure 4 As shown, the testing method includes: S510-S560.
[0064] S510 , generating a test report according to test data corresponding to the power consumption test of the comparator chip to be tested.
[0065] The power consumption test of the comparator chip to be tested is performed, and the test equipment also includes a power module, which is connected to the controller and the chip socket respectively, and is used to supply power to the comparator chip to be tested through the chip socket. The controller controls the power module to power on, and collects the voltage and current of the comparator chip to be tested. When the product of the voltage and current does not exceed the power consumption threshold, the controller determines that the power consumption test of the comparator chip to be tested has failed, and generates a test report for the test item.
[0066] S520 , generating a test report according to the test data corresponding to the offset test of the comparator chip to be tested.
[0067] When performing an offset test on the comparator chip to be tested, the controller controls the signal generator to output voltage to the comparator chip to be tested, and the oscilloscope outputs a test waveform to the controller based on the comparison result of the comparator chip to be tested on the input voltage. Input reference offset refers to an offset or offset voltage that does not conform to the ideal situation at the input end of the comparator chip when the comparator chip is used. Therefore, during the test, the positive input end of the comparator chip to be tested is set to be 20mV higher than the negative input end, or the positive input end of the comparator chip to be tested is set to be 20mV lower than the negative input end. If the waveform of the output voltage of the comparator chip to be tested received by the oscilloscope does not flip, the controller determines that the offset test has failed and generates a test report for the test item.
[0068] S530 , generating a test report according to the test data corresponding to the hysteresis test of the comparator chip to be tested.
[0069] When performing a hysteresis test on the comparator chip to be tested, due to the high precision of the comparator chip, the fluctuations caused by noise interference will cause the output of the comparator chip to continuously jump near the threshold. In order to improve this shortcoming, a hysteresis effect is introduced to improve the performance of the comparator chip. This feature is called hysteresis. For example, if the offset index is 20mV, then after turning on the hysteresis, the index will become about 40mV. There are 4 levels of hysteresis here. The first level of hysteresis is 40mV, the second level is 60mV, the third level is 80mV, and the fourth level is 100mV. If the waveform of the output voltage of the comparator chip to be tested received by the oscilloscope does not flip within the index, the controller determines that the hysteresis test has not passed and generates a test report for the test item.
[0070] S540 , generating a test report according to the test data corresponding to the step response test of the comparator chip to be tested.
[0071] The step response of the comparator chip to be tested is tested. The step response is the response of the comparator chip to the step input signal. The step input signal is a signal that suddenly jumps from 0 to a non-zero value (usually 1) at a certain moment. Then the comparator chip will also reverse from outputting 0 to 1. When the delay from the signal generator outputting the flip midpoint of the input signal of the comparator chip to be tested to the oscilloscope receiving the flip midpoint of the output signal of the comparator chip to be tested exceeds 60ns, the controller determines that the step response test fails and generates a test report for the test item.
[0072] S550 , generating a test report according to the test data corresponding to the ramp response test of the comparator chip to be tested.
[0073] The ramp response of the comparator chip to be tested is tested. The ramp response describes the response characteristics of the comparator chip output changing with time when the input signal of the comparator chip increases from zero at a constant slope. There are two ramp input signals, with slopes of 1.65V / us and 8.25mV / us respectively; the output signal is a square wave signal that reverses from 0 to 1. When the time between the midpoint of the ramp input signal output by the signal generator to the comparator chip to be tested and the midpoint of the output signal reversal received by the oscilloscope of the comparator chip to be tested exceeds 100ns, the controller determines that the ramp response test fails and generates a test report for this test item.
[0074] S560: When the test result of at least one test item is a failure, send a test exception message.
[0075] When the test result of one of the above test items is a test failure, that is, the test result is a failure, the controller sends the abnormal test message to the communication device of the tester through an email or the like, so that the tester can understand the test situation at any time. Therefore, the tester does not need to operate during the test process of the comparator chip to be tested in the present disclosure, and the test results after the test will also be directly sent to the tester, without the need for the tester to actively download and obtain them, thereby improving the degree of automation of the test.
[0076] In some embodiments, based on the startup mode of the comparator chip to be tested, before configuring the startup indication signal in the data update module, the testing method also includes: generating a corresponding update program based on multiple test items of the comparator chip to be tested; and writing the update program into the storage circuit of the data update module.
[0077] Specifically, each test item of the comparator chip to be tested has a corresponding test running program, so it is necessary to generate corresponding update programs for multiple test items of the comparator chip to be tested, so as to realize the update of the running program of the comparator chip to be tested. After the comparator chip to be tested is placed in the chip socket, the controller communicates with the storage circuit in the data update module through the chip socket and the comparator chip to be tested, and the controller can replace the running program stored in the storage circuit through the comparator chip to be tested, thereby realizing the writing of the update program according to different test items in the storage circuit. Therefore, during the test process, if it is necessary to test a new comparator chip to be tested, or different test items, there is no need to set up a new hardware circuit to cope with the test, but directly use the controller to communicate with the storage circuit through the comparator chip to be tested, thereby reducing the hardware cost of the test, and then the cost of the entire test can be reduced.
[0078] It should be noted that, in this article, relational terms such as "first" and "second" are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the existence of other identical elements in the process, method, article or device including the elements.
[0079] The above are only specific embodiments of the present disclosure, so that those skilled in the art can understand or implement the present disclosure. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein can be implemented in other embodiments without departing from the spirit or scope of the present disclosure. Therefore, the present disclosure will not be limited to these embodiments herein, but will conform to the widest scope consistent with the principles and novel features disclosed herein.
Claims
1. A comparator chip testing device, characterized in that: include: A test chip plug-in portion, comprising a chip socket and a chip test circuit, wherein the chip test circuit is electrically connected to the chip socket, and the chip socket is used for plugging and connecting with a comparator chip to be tested; A data update module, the data update module is electrically connected to the chip socket, and the data update module is used to provide a start indication signal so that the comparator chip to be tested starts a running program or starts an update program based on the start indication signal; The controller is used to communicate with the comparator chip to be tested so as to adjust the test items of the comparator chip to be tested.
2. The test device according to claim 1, characterized in that The data update module includes: a storage circuit for storing an update program; An update indication circuit is used to provide a start indication signal, wherein the start indication signal is used to indicate a start mode of the comparator chip to be tested; The update indication circuit and the storage circuit are both connected to the comparator chip to be tested via the chip socket; the comparator chip to be tested is used to obtain the running program stored in the storage circuit according to the start indication signal.
3. The testing device according to claim 2, characterized in that The update indication circuit includes a first indication terminal and a second indication terminal; The first indication terminal and the second indication terminal are used to output a level signal, and the comparator chip to be tested is used to obtain an update program from the storage circuit according to the level signal.
4. The testing device according to claim 2, characterized in that The controller includes a host computer; The host computer is connected to the storage circuit via the chip socket, and the host computer is used to update the running program stored in the storage circuit via the comparator chip to be tested.
5. The testing device according to claim 1, characterized in that The chip test circuit includes a signal input circuit; a signal generator is electrically connected to the chip socket through the signal input circuit, and the signal input circuit is used to output different test voltages provided by the signal generator to the positive terminal and / or negative terminal of the comparator chip to be tested.
6. The testing device according to claim 5, characterized in that The chip test circuit also includes a relay group; The relay group is connected to the controller, and the signal input circuit is connected to the chip socket through the relay group; The relay group is used to control the on / off of one or more channels between the signal input circuit and the comparator chip to be tested according to the signal of the controller.
7. A comparator chip testing method, characterized in that: A test device for a comparator chip according to any one of claims 1 to 6, wherein the method comprises: Based on the startup mode of the comparator chip to be tested, a startup indication signal is configured in the data update module; the comparator chip to be tested is configured to load a running program or load an update program based on the startup indication signal when placed in a chip socket; wherein the update program is stored in the data update module; Under each test item of the comparator chip to be tested, a control signal corresponding to the test item is sent to the comparator chip to be tested, and a signal generation instruction corresponding to the test item is sent to a signal generator; wherein the signal generator generates a corresponding test voltage based on the signal generation instruction; Acquire test data generated by the comparator chip under test based on the test voltage corresponding to the test item.
8. The testing method according to claim 7, characterized in that: The method of configuring a startup indication signal in a data update module based on the startup mode of the comparator chip to be tested includes: When the startup mode corresponding to the comparator to be tested is the first mode, configuring a first mode signal in the data update module; When the startup mode corresponding to the comparator to be tested is the second mode, configuring a second mode signal in the data update module; The comparator chip under test is configured to load a running program from a storage unit of the comparator chip under test based on a first mode signal; and to load an update program from a storage circuit of a data update module based on a second mode signal.
9. The testing method according to claim 7, characterized in that: After obtaining the test result generated by the comparator to be tested based on the test voltage corresponding to the test item, the method further includes: Generate a test report based on the test data corresponding to all test items; If the test result of at least one test item is a failure, a test exception message is sent.
10. The testing method according to claim 7, characterized in that: In the startup mode based on the comparator chip to be tested, before configuring the startup indication signal in the data update module, the method further includes: Based on a plurality of test items of the comparator chip to be tested, generating a corresponding update program; The update program is written into the storage circuit of the data update module.