Low-power-consumption wake-up circuit integrated in MCU

Abstract

The invention belongs to the technical field of microprocessors, and particularly relates to a low-power-consumption wake-up circuit integrated on an MCU. Comprising triggers DQ1-DQ6, NOT gates NOT1-NOT5, AND gates AND1-AND3, a three-state gate TS1, an exclusive-OR gate XOR1, a comparator CMP1 and a selector MUX1, wherein D ends of the triggers DQ1-DQ4 and output ends of the NOT gates NOT1-NOT4 are all connected to a data bus, a CLK end of the trigger DQ1 is connected to a write enable signal of the P0 register, a Q end of the trigger DQ1 is connected to an input end of the three-state gate TS1, an output end of the three-state gate TS1 is connected to a port, a CLK end of the trigger DQ2 is connected to a write enable signal of the P0IO register, and a Q end of the trigger DQ2 is connected to an output end of the P0IO register. The QN end of the trigger DQ2 and the input end of the NOT gate NOT1 are connected to the control end of the three-state gate TS1, and the control end of the NOT gate NOT1 is connected to a read enable signal of the P0IO register. According to the invention, through charging and discharging of the capacitor, the level of the port changes from high to low, so that a wake-up signal is generated. Periodic wake-up signals do not need to be generated by external equipment or internal programs, and power consumption of the whole system is reduced.

Description

Technical Field

[0001] The invention belongs to the technical field of microprocessors, and in particular relates to a low-power wake-up circuit integrated in an MCU. Background Art

[0002] In the fields of high-precision measurement, automatic control, etc., high requirements are placed on clock accuracy and power consumption. It is necessary to use a more accurate clock and control power consumption. Therefore, an external crystal oscillator is needed as the system master clock, and the system enters sleep mode when it is not working to reduce power consumption. As the system master clock, the external crystal oscillator needs to be set as the system master clock only when the oscillation is stable. The external crystal oscillator is generally a low-speed clock with a frequency of 32.768kHz, so it takes a long time to wait for the oscillation to stabilize. In some data acquisition and transmission or real-time monitoring fields, the MCU needs to be awakened periodically. Usually, an internal timer or RTC is used to wake up the system regularly. In a circuit powered by a battery, the power consumption requirement is extremely high, and the system power consumption needs to be reduced as much as possible.

[0003] The existing periodic timed wake-up circuit starts executing the program after the system main clock switches from the internal oscillation to the external crystal oscillator, configures the timer, uses the internal low-speed oscillation as the timer counting clock, and enters the sleep mode. At this time, the external crystal oscillator stops oscillating. Wait for the timer to count to the set value and generate a wake-up signal. After the wake-up signal is generated, the external crystal oscillator starts oscillating, waits for a certain period of time, and after the oscillation is stable, the circuit can use the external crystal oscillator as the system main clock. While waiting for the oscillation to stabilize, the entire system does not work.

[0004] However, during the microprocessor sleep period, the internal timer uses the internal low-speed oscillation as the clock count, which generates a certain amount of power consumption. The external crystal oscillator is used as the system main clock, waiting for the oscillation to stabilize, and the system starts working when the wake-up signal comes. This period of time is long, which generates a certain amount of power consumption and reduces the efficiency of code execution. Summary of the invention

[0005] The purpose of the present invention is to overcome the above-mentioned shortcomings of the prior art. The present invention provides a low-power wake-up circuit integrated in an MCU. By discharging the port capacitor, the circuit generates a periodic wake-up signal to wake up the circuit from sleep mode. After the wake-up signal arrives, the internal and external dual clocks are used to start the circuit to achieve an extremely low-power circuit wake-up design.

[0006] In order to solve the above technical problems, the present invention provides a low-power wake-up circuit integrated in an MCU, comprising: triggers DQ1-DQ6, NOT gates NOT1-NOT5, AND gates AND1-AND3, a tri-state gate TS1, an XOR gate XOR1, a comparator CMP1 and a selector MUX1; Among them, the D terminals of the triggers DQ1~DQ4 and the output terminals of the NOT gates NOT1~NOT4 are all connected to the data bus, the CLK terminal of the trigger DQ1 is connected to the write enable signal of the P0 register, the Q terminal of the trigger DQ1 is connected to the input terminal of the three-state gate TS1, the output terminal of the three-state gate TS1 is connected to the IO port of the MCU, the CLK terminal of the trigger DQ2 is connected to the write enable signal of the P0IO register, the QN terminal of the trigger DQ2 and the input terminal of the NOT gate NOT1 are connected to the control terminal of the three-state gate TS1, and the control terminal of the NOT gate NOT1 is connected to the read enable signal of the P0IO register. The control end of NOT gate NOT2 is connected to the read enable signal of P0 register, the CLK end of trigger DQ3 is connected to the write enable signal of IE0 register, the QN end of trigger DQ3 is connected to the input end of NOT gate NOT3, the control end of NOT gate NOT3 is connected to the read enable signal of IE0 register, the CLK end of trigger DQ4 is connected to the write enable signal of P0AN register, the Q end of trigger DQ4 is connected to the input end of NOT gate NOT5, the QN end of trigger DQ4 is connected to the input end of NOT gate NOT4, the control end of NOT gate NOT4 is connected to the read enable signal of P0AN register, and gate The three input ends of AND1 are respectively connected to the Q ends of trigger DQ1 and trigger DQ3, and the output end of XOR gate XOR1. The output end of AND gate AND1 outputs a level change interrupt wake-up signal. The two input ends of XOR gate XOR1 are respectively connected to the Q ends of trigger DQ5 and trigger DQ6. The Q end of trigger DQ5 is connected to the input end of NOT gate NOT2. The EN end of trigger DQ5 is connected to CLK3. The EN end of trigger DQ6 is connected to the read enable signal of P0 register. The output ends of NOT gate NOT5 and selector MUX1 are respectively connected to the two input ends of AND gate AND2. The output of the AND gate AND2 is connected to the D end of the trigger DQ5 and the trigger DQ6, the two input ends of the selector MUX1 are respectively connected to the inverting input end and the output end of the comparator CMP1, the control end of the selector MUX1 is connected to the ultra-low power wake-up enable signal ULPWKE and the first end of the ultra-low power current IULP, the non-inverting input end of the comparator CMP1 is connected to the DAC module output voltage VIL, the inverting input end of the comparator CMP1 is connected to the output end of the tri-state gate TS1 and the second end of the ultra-low power current IULP, and the ground end of the ultra-low power current IULP is grounded.

[0007] Preferably, the ultra-low power consumption current IULP is generated by a capacitor module, which includes: a PMOS tube P1, an NMOS tube N1, a capacitor C1, a resistor R1 and an AND gate AND3; the three input ends of the AND gate AND3 are respectively connected to the ultra-low power consumption wake-up enable signal ULPWKE, the sleep enable signal SLEEP and the inverting input end of the comparator CMP1, the output end of the AND gate AND3 is connected to the gate end of the PMOS tube P1, the source end of the PMOS tube P1 is connected to the power supply voltage VDD, the drain end of the PMOS tube P1 is connected to the ultra-low power consumption wake-up enable signal ULPWKE, one end of the capacitor C1 and the drain end of the NMOS tube N1, the gate end of the NMOS tube N1 is connected to the sleep enable signal SLEEP, the source end of the NMOS tube N1 is grounded, the other end of the capacitor C1 is connected to one end of the resistor R1, and the other end of the resistor R1 is grounded.

[0008] Preferably, a diode module is also included, and the diode module includes diodes D1~D2; the positive end of the diode D1 and the negative end of the diode D2 are connected to the port, the negative end of the diode D1 is connected to the power supply voltage VDD, and the positive end of the diode D2 is grounded.

[0009] Preferably, the P0 register is a data register having P00 to P07 ports, and when bit0 of the P0 register is written as 1, the P00 port outputs 1, and when bit0 of the P0 register is written as 0, the P00 port outputs 0; The IE0 register is the external port level change interrupt enable register. The P00 port is the port corresponding to the external interrupt 0 and is controlled by the bit 0 of the IE0 register. The P0IO register is the input and output direction control register of a group of ports in the P0 register. When bit0 of the P0IO register is 1, the P00 port is in input state, and when bit0 is 0, the P00 port is in output state. The P0AN register is a register that controls the P00 port to function as an analog input or a digital IO function. If bit0 of the P0AN register is 1, the P00 port functions as an analog input. If bit0 is 0, the P00 port functions as a digital IO function.

[0010] Preferably, different DAC module output voltage VIL values ​​are set through the DAC module integrated inside the MCU to dynamically adjust the timing wake-up time; that is, through the formula VIL = VDDexp (-t / RC); Among them, VDD is the power supply voltage, R and C are the resistance and capacitance values ​​integrated inside the MCU, and t is the set timer wake-up time.

[0011] Preferably, after the wake-up signal arrives, while the external crystal oscillator oscillation has not yet stabilized, the internal clock is used as the system master clock; after the external crystal oscillator oscillates stabilizes, the internal oscillation is switched to the external crystal oscillator as the system master clock.

[0012] Preferably, it also includes the working process of dual-speed clock startup: before entering sleep mode, turn on the dual-speed clock startup enable; the system wakes up from sleep mode; the internal oscillation starts working using the frequency set before sleep, and the system starts executing instructions at this frequency; while waking up, the external oscillation starts working, and the external oscillation counter starts counting, and when the count reaches 1023, the FLAG is set; after the FLAG is set, the system clock maintains a low level, waiting for the falling edge of the external oscillation to appear; switch the external oscillation as the system clock source.

[0013] Preferably, it also includes an ultra-low power consumption port wake-up working process: setting the P0 register to enable the P00 port output 1; setting the P0AN register to turn off the P00 port analog function; setting the P0IO register to turn on the P00 port digital output function; waiting for the capacitor C1 to be fully charged; enabling the ultra-low power consumption wake-up enable signal ULPWKE; setting the IE0 register to turn on the P00 port external interrupt 0 enable bit; setting the P0IO register to set the P00 port to input mode; entering the sleep mode and waiting for the system to wake up automatically.

[0014] Compared with the prior art, the present invention has the following beneficial effects: The present invention integrates a capacitor inside the port, and through the charging and discharging of the capacitor, the port level changes from high to low, thereby generating a wake-up signal. No external device or internal program is required to generate a periodic wake-up signal, thereby reducing the power consumption of the entire system. Moreover, before the external crystal oscillator oscillates stably, the internal oscillation is used as the system master clock to start executing the program. After the external crystal oscillator oscillates stably, the external crystal oscillator is switched as the system master clock, thereby reducing the delay between the external oscillation starting and the code execution. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 The present invention is a circuit diagram of a low-power wake-up circuit integrated in an MCU.

[0016] Figure 2 This is a non-overlapping timing diagram of the four internally generated CLK1~CLK4 of the present invention.

[0017] Figure 3 It is a waveform diagram of the dual-speed clock of the present invention. DETAILED DESCRIPTION

[0018] The present invention is further described in detail below in conjunction with the accompanying drawings and specific embodiments. The advantages and features of the present invention will become more apparent from the following description. It should be noted that the accompanying drawings are in very simplified form and in non-precise proportions, and are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention.

[0019] like Figure 1 As shown, an embodiment of the present invention provides a low-power wake-up circuit integrated in an MCU, including: triggers DQ1-DQ6, NOT gates NOT1-NOT5, AND gates AND1-AND3, a tri-state gate TS1, an XOR gate XOR1, a comparator CMP1 and a selector MUX1; Among them, the D ends of the triggers DQ1~DQ4 and the output ends of the NOT gates NOT1~NOT4 are all connected to the data bus, the CLK end of the trigger DQ1 is connected to the write enable signal of the P0 register, the Q end of the trigger DQ1 is connected to the input end of the three-state gate TS1, and the output end of the three-state gate TS1 is connected to the IO port of the MCU as the data output path of the ordinary IO port for communicating with external devices; the CLK end of the trigger DQ2 is connected to the write enable signal of the P0IO register, the QN end of the trigger DQ2 and the input end of the NOT gate NOT1 are connected to the control end of the three-state gate TS1, and the NOT gate NOT1 The control end is connected to the read enable signal of the P0IO register, the control end of the NOT gate NOT2 is connected to the read enable signal of the P0 register, the CLK end of the trigger DQ3 is connected to the write enable signal of the IE0 register, the QN end of the trigger DQ3 is connected to the input end of the NOT gate NOT3, the control end of the NOT gate NOT3 is connected to the read enable signal of the IE0 register, the CLK end of the trigger DQ4 is connected to the write enable signal of the P0AN register, the Q end of the trigger DQ4 is connected to the input end of the NOT gate NOT5, the QN end of the trigger DQ4 is connected to the input end of the NOT gate NOT4, and the control end of the NOT gate NOT4 is connected to P0A The read enable signal of the N register is connected. The three input ends of the AND gate AND1 are respectively connected to the Q ends of the trigger DQ1 and the trigger DQ3, and the output end of the XOR gate XOR1. The output end of the AND gate AND1 outputs a level change interrupt wake-up signal. The two input ends of the XOR gate XOR1 are respectively connected to the Q ends of the trigger DQ5 and the trigger DQ6. The Q end of the trigger DQ5 is connected to the input end of the NOT gate NOT2. The EN end of the trigger DQ5 is connected to CLK3. The EN end of the trigger DQ6 is connected to the read enable signal of the P0 register. The output ends of the NOT gate NOT5 and the selector MUX1 are respectively connected to the AND gate AN The two input ends of D2 and the output end of the AND gate AND2 are connected to the D ends of the trigger DQ5 and the trigger DQ6, the two input ends of the selector MUX1 are respectively connected to the inverting input end and the output end of the comparator CMP1, the control end of the selector MUX1 is connected to the ultra-low power wake-up enable signal ULPWKE and the first end of the ultra-low power current IULP, the non-inverting input end of the comparator CMP1 is connected to the DAC module output voltage VIL, the inverting input end of the comparator CMP1 is connected to the output end of the tri-state gate TS1 and the second end of the ultra-low power current IULP, and the ground end of the ultra-low power current IULP is grounded.

[0020] The ultra-low power consumption current IULP is generated by a capacitor module, which includes: a PMOS tube P1, an NMOS tube N1, a capacitor C1, a resistor R1 and an AND gate AND3; the three input ends of the AND gate AND3 are respectively connected to the ultra-low power consumption wake-up enable signal ULPWKE, the sleep enable signal SLEEP and the inverting input end of the comparator CMP1, the output end of the AND gate AND3 is connected to the gate end of the PMOS tube P1, the source end of the PMOS tube P1 is connected to the power supply voltage VDD, the drain end of the PMOS tube P1 is connected to the ultra-low power consumption wake-up enable signal ULPWKE, one end of the capacitor C1 and the drain end of the NMOS tube N1, the gate end of the NMOS tube N1 is connected to the sleep enable signal SLEEP, the source end of the NMOS tube N1 is grounded, the other end of the capacitor C1 is connected to one end of the resistor R1, and the other end of the resistor R1 is grounded.

[0021] It also includes a diode module, which includes diodes D1-D2; the positive end of the diode D1 and the negative end of the diode D2 are connected to the port, the negative end of the diode D1 is connected to the power supply voltage VDD, and the positive end of the diode D2 is grounded.

[0022] ULPWUE is the ultra-low power wake-up enable bit, which is valid at high level; IE0 register is the external port level change interrupt enable register, P00 port is external interrupt 0, which is controlled by bit0 of IE0 register; P0 register is the data register of P00~P07 ports. If bit0 is written as 1, P00 port outputs 1, and if bit0 is written as 0, P00 port outputs 0; P0IO register is the input and output direction control register of a group of ports of P0 register. When bit0 of P0IO is 1, P00 port acts as input state, and when bit0 is 0, P00 port acts as output state; bit0 of P0AN register is used to control P00 port to act as analog input function or digital IO function. If bit0 is 1, P00 port acts as analog input function, and if bit0 is 0, P00 port acts as digital IO function. V IL Output voltage of the DAC module.

[0023] It also includes the following working principles: ① Use the ultra-low power wake-up function. In normal working mode (SLEEP=0), turn on the ultra-low power wake-up enable (ULPWKE=1).

[0024] ② Write 0 to bit0 of P0AN and set the P00 port to digital IO function, that is, non-analog input function (DQ4 outputs 0, NOT1 outputs 1).

[0025] ③ Write 0 to bit0 of P0IO, set the P00 port to output state (the Q end of DQ2 outputs 0, QN outputs 1) and open the three-state gate TS1.

[0026] ④ Write 1 to bit0 of the P0 register and configure the P00 port to output 1 (the Q end of DQ1 outputs 1, and TS1 outputs 1).

[0027] ⑤At this time, AND3 outputs 0, turning on PMOS tube P1 to charge capacitor C1 in the capacitor module. Wait for capacitor C1 to be fully charged.

[0028] ⑥ Write 1 to bit0 of the IE0 register to enable the P00 port level change interrupt (the Q end of DQ3 outputs 1, and the QN end outputs 0), and the P00 port is configured as input mode (the Q end of DQ2 outputs 1, and QN outputs 0).

[0029] ⑦Execute the SLEEP command to enter sleep mode, and capacitor C1 starts to discharge.

[0030] ⑧When the voltage on the P00 port drops to V IL And below, it is determined that the level change of the falling edge occurs at the P00 port, and the comparator CMP1 outputs 1. At this time, the two-to-one selector MUX1 outputs 1. At this time, it is in digital input mode, and the output of NOT1 is 1. The output of AND gate AND2 is 1, and the Q end of DQ5 outputs 1 with the CLK3 clock sampling. The enable of the P0 register is the same phase clock of CLK1. The three devices DQ5, DQ1 and XOR1 form a handshake protocol. The Q end output of DQ5 and the Q end output of DQ6 will be set to 1 with a difference of two system clock times. The XOR gate XOR1 will output 1 of two clocks, which is the level change interrupt wake-up signal, which will generate an interrupt and wake up the device.

[0031] Read the status of the P00 port, read the P0IO register to enable, turn on NOT1, and write the QN data of DQ2 through inverter NOT1 to the data bus. Read the value of the P0 register, read the P0 register enable signal to set, turn on NOT2, and write the Q data of DQ4 through NOT2 to the data bus. Read the IE0 register, read the IE0 register enable to set, turn on NOT3, and write the QN data of DQ3 through inverter NOT3 to the data bus. Read the P0AN register, read the P0AN enable signal to set, turn on NOT4, and write the QN data of DQ4 through inverter NOT4 to the data bus.

[0032] Use port output 1 to charge the capacitor, and enter sleep mode. The discharge of the capacitor causes a level signal change at the port, which can be used as a wake-up signal. The ultra-low power wake-up function on port P00 allows a slowly falling voltage to generate a level change interrupt on P00 without consuming a lot of current. Enable this function control bit in the MCU register, which will generate a small sink current that can be used to discharge the capacitor on the P00 port.

[0033] The capacitor discharge time can be calculated using the formula: Vt=V0exp(-t / RC); where V0 is the voltage before the capacitor is discharged, Vt is the voltage at any time after discharge, R is the discharge resistance, and C is the capacitance value.

[0034] The charging time of the capacitor can be calculated using the following formula: Vt=Vu(1-exp(-t / RC)); where Vu is the voltage of the capacitor after it is fully charged, and Vt is the voltage at any time after charging.

[0035] like Figure 2 As shown in the figure, the system clock FSYS is provided by an external crystal oscillator or an internal oscillator. It is subdivided into four internally generated non-overlapping timings CLK1~CLK4, which constitute a complete instruction cycle. At CLK1 time, the program counter automatically increases by one and grabs a new instruction. CLK2~CLK4 complete the decoding and execution functions.

[0036] After the wake-up signal arrives, the internal clock is used as the system main clock while the external crystal oscillator is not yet stable. After the external crystal oscillator is stable, the internal oscillator is switched to the external crystal oscillator as the system main clock. This can minimize the delay between the external oscillator and code execution, further saving power consumption.

[0037] Different V IL Voltage value, dynamically adjust the timer wake-up time. Through the formula V IL =VDDexp(-t / RC), the power supply voltage VDD, the internal integrated RC value, and the desired timer wake-up time t can be calculated to get V IL The actual value is set by DAC.

[0038] like Figure 3 As shown in the figure, LIRC is the internal oscillator of the system, LXT is the low-speed oscillator connected to the chip, LXT_CNT is a 10-bit counter, FLAG is the overflow flag of LXT_CNT, PC is the microcontroller program register, and FSYS is the microcontroller system clock. Figure 3 The LXT cycle and LIRC cycle shown in the waveform are not a comparison of the actual cycle frequencies, but are just to facilitate understanding of the dual-speed clock wake-up process. The actual frequencies are very different, and the greater the frequency difference, the more power consumption is saved.

[0039] The working sequence of the above dual-speed clock startup is: before entering sleep mode, turn on the dual-speed clock startup enable; ①The system wakes up from sleep mode; ②The internal oscillation starts working at the frequency set before sleep, and the system starts executing instructions at this frequency; ③When waking up, the external oscillator starts working, and the external oscillator counter starts counting. When the count reaches 1023, FLAG is set. ④After FLAG is set, the system clock remains at a low level, waiting for the falling edge of the external oscillation; ⑤Switch external oscillator as the system clock source.

[0040] The above ultra-low power port wake-up working order is: ① Set the P0 register to enable the P00 port to output 1; ② Set the P0AN register to turn off the analog function of the P00 port; set POIO to turn on the digital output function of the P00 port; ③Wait for the capacitor to be fully charged; ④ Enable the ultra-low power wake-up enable bit ULPWUE; ⑤Set the IE0 register and turn on the P00 port external interrupt 0 enable bit; ⑥Set the P0IO register and set the P00 port to input mode; ⑦ Enter sleep mode and wait for the system to wake up automatically; The above description is only a description of the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention. Any changes or modifications made by a person skilled in the art in the field of the present invention based on the above disclosure shall fall within the scope of protection of the claims.

Claims

1. A low-power wake-up circuit integrated in an MCU, characterized in that: include: Triggers DQ1~DQ6, NOT gates NOT1~NOT5, AND gates AND1~AND3, tri-state gate TS1, XOR gate XOR1, comparator CMP1 and selector MUX1; Among them, the D terminals of the triggers DQ1~DQ4 and the output terminals of the NOT gates NOT1~NOT4 are all connected to the data bus, the CLK terminal of the trigger DQ1 is connected to the write enable signal of the P0 register, the Q terminal of the trigger DQ1 is connected to the input terminal of the three-state gate TS1, the output terminal of the three-state gate TS1 is connected to the IO port of the MCU, the CLK terminal of the trigger DQ2 is connected to the write enable signal of the P0IO register, the QN terminal of the trigger DQ2 and the input terminal of the NOT gate NOT1 are connected to the control terminal of the three-state gate TS1, and the NOT gate N The control end of OT1 is connected to the read enable signal of the P0IO register, the control end of the NOT gate NOT2 is connected to the read enable signal of the P0 register, the CLK end of the trigger DQ3 is connected to the write enable signal of the IE0 register, the QN end of the trigger DQ3 is connected to the input end of the NOT gate NOT3, the control end of the NOT gate NOT3 is connected to the read enable signal of the IE0 register, the CLK end of the trigger DQ4 is connected to the write enable signal of the P0AN register, the Q end of the trigger DQ4 is connected to the input end of the NOT gate NOT5, and the trigger D The QN end of Q4 is connected to the input end of the NOT gate NOT4, the control end of the NOT gate NOT4 is connected to the read enable signal of the P0AN register, the three input ends of the AND gate AND1 are respectively connected to the Q ends of the trigger DQ1 and the trigger DQ3, and the output end of the XOR gate XOR1, the output end of the AND gate AND1 outputs the level change interrupt wake-up signal, the two input ends of the XOR gate XOR1 are respectively connected to the Q ends of the trigger DQ5 and the trigger DQ6, the Q end of the trigger DQ5 is connected to the input end of the NOT gate NOT2, the EN end of the trigger DQ5 is connected to CLK3, the EN end of the trigger DQ6 is connected to the read enable signal of the P0 register, the output ends of the NOT gate NOT5 and the selector MUX1 are respectively connected to the two input ends of the AND gate AND2, the output end of the AND gate AND2 is connected to the D ends of the trigger DQ5 and the trigger DQ6, the two input ends of the selector MUX1 are respectively connected to the inverting input end and the output end of the comparator CMP1, the control end of the selector MUX1 is connected to the ultra-low power wake-up enable signal ULPWKE and the ultra-low power current I ULP The first end of the comparator CMP1 is connected to the DAC module output voltage V IL The inverting input of the comparator CMP1 is connected to the output of the tri-state gate TS1 and the ultra-low power current I ULP The second end, ultra-low power consumption current I ULP The ground terminal is grounded.

2. A low-power wake-up circuit integrated in an MCU as claimed in claim 1, characterized in that: The ultra-low power consumption current I ULP Generated by a capacitor module, the capacitor module includes: a PMOS tube P1, an NMOS tube N1, a capacitor C1, a resistor R1 and an AND gate AND3; the three input ends of the AND gate AND3 are respectively connected to the ultra-low power wake-up enable signal ULPWKE, the sleep enable signal SLEEP and the inverting input end of the comparator CMP1, the output end of the AND gate AND3 is connected to the gate end of the PMOS tube P1, the source end of the PMOS tube P1 is connected to the power supply voltage VDD, the drain end of the PMOS tube P1 is connected to the ultra-low power wake-up enable signal ULPWKE, one end of the capacitor C1 and the drain end of the NMOS tube N1, the gate end of the NMOS tube N1 is connected to the sleep enable signal SLEEP, the source end of the NMOS tube N1 is grounded, the other end of the capacitor C1 is connected to one end of the resistor R1, and the other end of the resistor R1 is grounded.

3. A low-power wake-up circuit integrated in an MCU as claimed in claim 1, characterized in that: It also includes a diode module, which includes diodes D1-D2; the positive end of the diode D1 and the negative end of the diode D2 are connected to the port, the negative end of the diode D1 is connected to the power supply voltage VDD, and the positive end of the diode D2 is grounded.

4. A low-power wake-up circuit integrated in an MCU as claimed in claim 1, characterized in that: The P0 register is a data register with P00~P07 ports. When bit0 of the P0 register is written as 1, the P00 port outputs 1. When bit0 of the P0 register is written as 0, the P00 port outputs 0. The IE0 register is the external port level change interrupt enable register. The P00 port is the port corresponding to the external interrupt 0 and is controlled by the bit 0 of the IE0 register. The P0IO register is the input and output direction control register of a group of ports in the P0 register. When bit0 of the P0IO register is 1, the P00 port is in input state, and when bit0 is 0, the P00 port is in output state. The P0AN register is a register that controls the P00 port to function as an analog input or a digital IO function. If bit0 of the P0AN register is 1, the P00 port functions as an analog input. If bit0 is 0, the P00 port functions as a digital IO function.

5. A low-power wake-up circuit integrated in an MCU as claimed in claim 1, characterized in that: Through the DAC module integrated in the MCU, set different DAC module output voltages V IL value to dynamically adjust the timer wake-up time; that is, through the formula V IL =VDDexp(-t / RC); Among them, VDD is the power supply voltage, R and C are the resistance and capacitance values ​​integrated inside the MCU, and t is the set timer wake-up time.

6. A low-power wake-up circuit integrated in an MCU as claimed in claim 1, characterized in that: After the wake-up signal arrives, while the external crystal oscillator is not yet stable, the internal clock is used as the system main clock; after the external crystal oscillator is stable, the internal oscillation is switched to the external crystal oscillator as the system main clock.

7. A low-power wake-up circuit integrated in an MCU as claimed in claim 6, characterized in that: It also includes the working process of dual-speed clock startup: before entering sleep mode, turn on the dual-speed clock startup enable; the system wakes up from sleep mode; the internal oscillation starts working using the frequency set before sleep, and the system starts executing instructions at this frequency; at the same time of waking up, the external oscillation starts working, and the external oscillation counter starts counting, and when the count reaches 1023, the FLAG is set; after the FLAG is set, the system clock remains at a low level, waiting for the falling edge of the external oscillation to appear; switch the external oscillation as the system clock source.

8. A low-power wake-up circuit integrated in an MCU as claimed in claim 2, characterized in that: It also includes the ultra-low power port wake-up working process: set the P0 register to enable the P00 port to output 1; set the P0AN register to turn off the P00 port analog function; set the P0IO register to turn on the P00 port digital output function; wait for capacitor C1 to be fully charged; enable the ultra-low power wake-up enable signal ULPWKE; set the IE0 register to turn on the P00 port external interrupt 0 enable bit; set the P0IO register to set the P00 port to input mode; enter sleep mode and wait for the system to wake up automatically.

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