Semiconductor stacking structure and preparation method thereof
By using the lithography process to remove the passivation layer and form an oxide layer on the test pad of the semiconductor stack structure, the problems of inaccurate detection and poor stability in the secondary test are solved, and higher test accuracy and stability are achieved.
Patent Information
- Application Number
- CN202411511959.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-10-28
- Publication Date
- 2025-02-07
AI Technical Summary
In the prior art, during secondary testing of the semiconductor stack structure, the passivation layer of the test pad is difficult to effectively remove, resulting in inaccurate detection and poor stability.
The passivation layer on the test pad is removed by lithography and an oxide layer is formed thereon. After the stacked structure is formed, the oxide layer is removed by wet etching to perform a secondary test.
It improves the accuracy and stability of the secondary test, avoids damage to the test pads by chemical grinding, and ensures the reliability of the test results.
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Figure CN119400720A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of semiconductor technology, and in particular, to a semiconductor stacking structure and a method for preparing the same. Background Art
[0002] With the continuous development of micro-nano technology, people continue to reduce the feature size and increase the number of transistors per unit area of the chip, thereby greatly improving the performance and integration of the chip. However, it is becoming increasingly difficult to reduce the current process line width, and three-dimensional electronic packaging will be the best choice to further improve the functional integration density of the chip. Three-dimensional electronic packaging can effectively solve many thorny problems in the current semiconductor industry, such as heterogeneous integration, reducing power consumption, size, delay and cost. Three-dimensional electronic packaging stacks multiple layers of interconnected vertical layers together through high-density vertical silicon vias, and can also stack multiple layers of chips that are incompatible with multiple processes together to achieve low-cost, low-parasitic integration.
[0003] Before stacking multiple wafers, each wafer needs to be tested to ensure that each wafer can work normally. After multiple wafers are stacked in sequence to form a stacked structure, the performance of the stacked structure is tested using the test pad of the top wafer. In the prior art, the test pad area is small and not enough to contact the probe during secondary testing. By increasing the test pad area for secondary testing, when multiple wafers are stacked to form a stacked structure, the height of the stacked structure is high, and the photolithography machine cannot be entered to etch the passivation layer on the test pad. In the prior art, chemical grinding is mostly used to remove the passivation layer. While chemical grinding removes the passivation layer, it is difficult to avoid damaging the test pad, which reduces the thickness of the test pad and is easily pierced by the probe during secondary testing. Summary of the invention
[0004] The purpose of the present application is to provide a semiconductor stacking structure and a preparation method thereof, which can improve the stability of secondary testing.
[0005] On the one hand, an embodiment of the present application provides a method for preparing a semiconductor stacking structure, including: providing multiple wafers that have completed a test in a first area, the test pad of the wafer also includes a second area, and the second area has a passivation layer; using a photolithography process to remove the passivation layer on the second area, and forming an oxide layer on the test pad; stacking multiple wafers in sequence to form a stacking structure; using a wet method to etch the oxide layer of the topmost wafer so that the second area of the topmost wafer is exposed; and testing the stacking structure a second time through the exposed second area.
[0006] As an practicable method, providing multiple wafers that have completed a test in a first area includes: providing multiple wafers, each wafer including at least one test pad, and a passivation layer is arranged on the test pad; using a photolithography process to remove part of the passivation layer so that the first area of the test pad is exposed; and a probe contacts the first area to perform a test on the wafer.
[0007] As an implementable method, a photolithography process is used to remove the passivation layer on the second area and form an oxide layer on the test pad, including: laying photoresist on the wafer and using a mask to expose the passivation layer corresponding to the second area of the test pad; etching the passivation layer corresponding to the second area to expose the second area; and depositing oxide on the wafer as the oxide layer.
[0008] As an practicable embodiment, the oxide is silicon oxide.
[0009] As an implementable manner, after providing a plurality of wafers that have completed a test in the first region, the method further includes: trimming the first region.
[0010] As an practicable manner, a wet process is used to etch and remove burrs from the first region.
[0011] As an practicable manner, stacking a plurality of wafers in sequence to form a stacked structure includes: stacking and connecting the plurality of wafers in sequence by a bonding process, and correspondingly connecting the test pads between two adjacent layers of wafers.
[0012] As an implementable manner, after the stack structure is tested for a second time through the exposed second area, the method further includes: trimming the second area.
[0013] As an implementable manner, the first area is adjacent to the second area.
[0014] On the other hand, an embodiment of the present application provides a semiconductor stacking structure, which is prepared by the above-mentioned semiconductor stacking structure preparation method, and includes a plurality of wafers stacked in sequence and connected, wherein the topmost wafer includes at least one test pad, and the test pad includes a first area and a second area.
[0015] The beneficial effects of the embodiments of the present application include:
[0016] The preparation method of the semiconductor stacking structure provided by the present application includes: providing a plurality of wafers that have completed a test in a first area, the test pad of the wafer also includes a second area, and the second area has a passivation layer; using a photolithography process to remove the passivation layer on the second area, and forming an oxide layer on the test pad; at this time, the wafers have not been stacked and are relatively thin, and the wafers can be placed in a photolithography machine, and the passivation layer on the second area is etched by the photolithography machine. Multiple wafers are stacked in sequence to form a stacking structure; the oxide layer of the top wafer is wet-etched to expose the second area of the top wafer; wet etching is used to expose the second area of the top wafer, and wet etching will not damage the test pad, and the stacking structure is tested twice through the exposed second area. Since the second area is previously covered by the oxide layer, it is protected by the oxide layer and will not be damaged during wet etching. In this way, during the secondary detection, the detection accuracy is better and the stability is higher. BRIEF DESCRIPTION OF THE DRAWINGS
[0017] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying creative work.
[0018] Figure 1 A flow chart of a method for preparing a semiconductor stacked structure provided in an embodiment of the present application;
[0019] Figure 2 One of the state diagrams of a semiconductor stack structure provided in an embodiment of the present application;
[0020] Figure 3 A second state diagram of a semiconductor stack structure provided in an embodiment of the present application;
[0021] Figure 4 A third state diagram of a semiconductor stack structure provided in an embodiment of the present application;
[0022] Figure 5 A fourth state diagram of a semiconductor stack structure provided in an embodiment of the present application;
[0023] Figure 6 A fifth state diagram of a semiconductor stack structure provided in an embodiment of the present application;
[0024] Figure 7 A sixth state diagram of a semiconductor stack structure provided in an embodiment of the present application;
[0025] Figure 8This is the seventh state diagram of a semiconductor stack structure provided in an embodiment of the present application.
[0026] Icon: 100 - wafer; 120 - test pad; 121 - first area; 122 - second area; 130 - passivation layer; 140 - oxide layer; 150 - photoresist. DETAILED DESCRIPTION
[0027] In order to make the purpose, technical solution and advantages of the embodiments of the present application clearer, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, rather than all the embodiments. The components of the embodiments of the present application described and shown in the drawings here can be arranged and designed in various different configurations.
[0028] Therefore, the following detailed description of the embodiments of the present application provided in the accompanying drawings is not intended to limit the scope of the present application for which protection is sought, but merely represents selected embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in the field without creative work are within the scope of protection of the present application.
[0029] It should be noted that similar reference numerals and letters denote similar items in the following drawings, and therefore, once an item is defined in one drawing, further definition and explanation thereof is not required in subsequent drawings.
[0030] In the process of preparing a semiconductor stack structure, each wafer in the stack structure needs to be tested once to ensure that each wafer can work normally. After the stack structure is formed, the stack structure needs to be tested again to ensure that the stacking process is accurate. The existing secondary test uses chemical grinding to remove the passivation layer on the test pad after the stack structure is formed, so that the test pad is exposed.
[0031] The present application provides a method for preparing a semiconductor stack structure, such as Figure 1 As shown, including:
[0032] S10: Figure 2 As shown, a plurality of wafers 100 that have completed a test in a first region 121 are provided, and the test pads 120 of the wafer 100 further include a second region 122, and a passivation layer 130 is provided on the second region 122;
[0033] A test is used to test the performance of each wafer 100 to ensure that each wafer 100 can work normally. Specifically, during the transportation and storage of the wafer 100, in order to prevent the test pad 120 from being damaged by the environment or the outside world, a passivation layer 130 is usually provided. During a test, a part of the test pad 120 (the first area 121) is exposed to allow the probe to contact the test pad 120. At this time, in order to continue to protect the second area 122, the passivation layer 130 on the second area 122 is not removed.
[0034] The specific material and hierarchical structure of the passivation layer 130 are not limited in the present embodiment, and can be a layer, or as shown in FIG. Figure 2 The two layers shown may be silicon nitride, silicon carbide, or the like.
[0035] S20: Figure 5 and Figure 6 As shown, the passivation layer 130 on the second region 122 is removed by a photolithography process, and an oxide layer 140 is formed on the test pad 120;
[0036] Specifically, the wafer 100 is placed in a photolithography machine for photolithography to remove the passivation layer 130 on the second area 122. At this time, since the wafer 100 is still a single-layer wafer 100 with a thin thickness, it can be easily entered into the photolithography machine, so that the passivation layer 130 can be removed by photolithography.
[0037] In addition, in order to protect the test pad 120, an oxide layer 140 may be formed on the test pad 120. Specifically, the oxide layer 140 may be wet etched in a subsequent process.
[0038] S30: Figure 7 As shown, a plurality of wafers 100 are stacked in sequence to form a stacked structure;
[0039] The multiple wafers 100 are stacked in sequence, so that the multiple wafers 100 are vertically connected to form a stacked structure.
[0040] S40: Figure 8 As shown, the oxide layer 140 of the top wafer 100 is wet-etched to expose the second region 122 of the top wafer 100;
[0041] The oxide layer 140 can be removed by wet etching, which is a full-surface etching. At this time, the passivation layer 130 and the surface of the test pad 120 on the surface of the wafer 100 are exposed. When wet etching is used, the test pad 120 will not be damaged, so that the test pad 120 is intact.
[0042] S50 : performing a secondary test on the stacked structure through the exposed second area 122 .
[0043] During the secondary test, since the second region 122 has not been in contact with the probe before and has not been damaged during the wet etching process, the detection accuracy is good and the stability is high.
[0044] Specifically, the embodiment of the present application etches the passivation layer 130 on the second area 122 using a photolithography machine before stacking multiple wafers 100 to avoid the area being too thick to enter the photolithography machine for photolithography after subsequent stacking; then, the entire layer of oxide layer 140 is laid to protect the test pad 120. When a secondary test is required, wet etching is used to remove the oxide layer 140 to expose the second area 122 for secondary testing. Therefore, the embodiment of the present application avoids the damage to the test pad 120 caused by chemical grinding in the prior art.
[0045] The preparation method of the semiconductor stacking structure provided in the present application includes: providing a plurality of wafers 100 that have completed a test in a first area 121, the test pad 120 of the wafer 100 also including a second area 122, and the second area 122 having a passivation layer 130; using a photolithography process to remove the passivation layer 130 on the second area 122, and forming an oxide layer 140 on the test pad 120; at this time, the wafers 100 have not been stacked yet and are relatively thin, and the wafers 100 can be placed in a photolithography machine, and the passivation layer 130 on the second area 122 can be etched using the photolithography machine. A plurality of wafers 100 are stacked in sequence to form a stacking structure; the oxide layer 140 of the top wafer 100 is wet-etched to expose the second region 122 of the top wafer 100; wet etching is used to expose the second region 122 of the top wafer 100, and the wet etching will not damage the test pad 120. The stacking structure is tested a second time through the exposed second region 122. Since the second region 122 is previously covered by the oxide layer 140, it is protected by the oxide layer 140 and will not be damaged during wet etching. Thus, during the secondary inspection, the detection accuracy is better and the stability is higher.
[0046] Optionally, providing a plurality of wafers 100 that have completed a test in the first area 121 includes:
[0047] S11: providing a plurality of wafers 100 , each wafer 100 comprising at least one test pad 120 , and a passivation layer 130 is disposed on the test pad 120 ;
[0048] At least one test pad 120 is disposed on the incoming wafer 100 . In order to protect the test pad 120 and the wafer 100 , a passivation layer 130 is formed on the upper surface of the wafer 100 , and the passivation layer 130 covers the test pad 120 .
[0049] S12: removing a portion of the passivation layer 130 by a photolithography process, so that the first area 121 of the test pad 120 is exposed;
[0050] One test is performed on each wafer 100 . At this time, the wafer 100 is relatively thin and can enter a photolithography machine to remove the passivation layer 130 on the first region 121 to expose the first region 121 .
[0051] S13 : The probe contacts the first region 121 to perform a test on the wafer 100 .
[0052] In one achievable manner of the embodiment of the present application, a photolithography process is used to remove the passivation layer 130 on the second region 122 and to form an oxide layer 140 on the test pad 120, including:
[0053] S21: Figure 4 As shown, a photoresist 150 is laid on the wafer 100 and a mask is used to expose the passivation layer 130 corresponding to the second area 122 of the test pad 120;
[0054] The passivation layer 130 corresponding to the second region 122 is exposed by using the photoresist 150 , so as to facilitate the subsequent etching of the passivation layer 130 corresponding to the second region 122 .
[0055] S22: etching the passivation layer 130 corresponding to the second region 122 to expose the second region 122;
[0056] The specific etching method is not limited in the embodiment of the present application, and those skilled in the art can perform etching according to actual conditions, for example, wet etching, dry etching, plasma etching, etc. At this time, the unetched photoresist 150 serves as an etching blocking structure, so that only the passivation layer 130 at the second region 122 is etched.
[0057] S23 : depositing oxide on the wafer 100 as the oxide layer 140 .
[0058] On the one hand, the oxide layer 140 serves as a protective layer for the test pad 120 . On the other hand, after a plurality of wafers 100 are subsequently stacked, the oxide layer 140 can be used to isolate two adjacent wafers 100 to improve the insulation between the plurality of wafers 100 .
[0059] Optionally, the oxide is silicon oxide.
[0060] Silicon oxide is a commonly used material in semiconductors, with a relatively mature preparation method and high purity.
[0061] In an achievable manner of the embodiment of the present application, after providing a plurality of wafers 100 that have completed a test in the first region, the method for preparing a semiconductor stacked structure further includes:
[0062] S11': Figure 3 As shown, the first region 121 is trimmed.
[0063] During a test, the probe will inevitably damage the metal in the first area 121, resulting in pits and protrusions in the first area 121, which is inconvenient for the subsequent exposure of the second area 122 and the setting of the oxide layer 140. In the embodiment of the present application, after a test, the first area 121 is corrected, so that the first area 121 is relatively flat, which can facilitate subsequent operations.
[0064] Optional, such as Figure 3 As shown, the first region 121 is etched and deburred using a wet process.
[0065] The burrs of the first region 121 are removed by a wet process, so that the surface of the first region 121 is relatively smooth.
[0066] In one achievable manner of the embodiment of the present application, stacking a plurality of wafers 100 in sequence to form a stacked structure includes:
[0067] S31': Figure 7 As shown, a plurality of wafers 100 are stacked and connected in sequence by a bonding process, and the test pads 120 between two adjacent layers of wafers 100 are connected correspondingly.
[0068] The bonding process is used to connect multiple wafers 100 in sequence, with good connection effect and without damaging each wafer 100. In addition, in order to achieve connectivity between each wafer 100, the test pads 120 between two adjacent layers of wafers 100 are connected accordingly, specifically, through silicon vias can be used for connection, wherein the through silicon vias pass through the bottom of the upper wafer 100 and the top of the lower wafer 100 to connect the two adjacent layers of wafers 100.
[0069] Optionally, after performing a secondary test on the stacked structure through the exposed second area 122, the method further includes:
[0070] S51 ′: trimming the second region 122 .
[0071] During the secondary test, the probe will inevitably damage the metal in the second area 122, resulting in pits and protrusions in the second area 122, which is inconvenient for subsequent packaging and processing. After the secondary test, the embodiment of the present application corrects the second area 122, so that the second area 122 is relatively flat, which can facilitate subsequent packaging and processing.
[0072] In one possible implementation of the embodiment of the present application, Figure 7 and Figure 8As shown, the first region 121 is adjacent to the second region 122 .
[0073] The first region 121 is adjacent to the second region 122, and can reduce the area of the test pad 120 on the basis of realizing the first test and the second test, thereby reducing the area occupied by the test pad 120, so that more test pads 120 can be accommodated on the wafer 100 of the same area, thereby improving the integration of the semiconductor stacking structure.
[0074] Among them, the embodiment of the present application does not limit the adjacency method of the first region 121 and the second region 122. For example, they can be adjacent along the first direction, along the second direction, or along an oblique direction, wherein the plane determined by the first direction and the second direction is perpendicular to the hierarchical direction of the semiconductor stacking structure.
[0075] The embodiment of the present application also discloses a semiconductor stacking structure, which is prepared by the above-mentioned method for preparing a semiconductor stacking structure, and includes a plurality of wafers 100 stacked and connected in sequence, wherein the top wafer 100 includes at least one test pad 120, and the test pad 120 includes a first area 121 and a second area 122. The first area 121 on the test pad 120 is used for sequential testing of each wafer 100, and the second area 122 of the top wafer 100 is used for secondary testing of the stacking structure, so that the primary test and the secondary test are in contact with different areas of the test pad 120, respectively, to improve the test accuracy. The specific structure and other beneficial effects of the semiconductor stacking structure have been described in detail in the aforementioned embodiments, and will not be repeated here.
[0076] The above description is only the preferred embodiment of the present application and is not intended to limit the present application. For those skilled in the art, the present application may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.
Claims
1. A method for preparing a semiconductor stacked structure, characterized in that: include: Providing a plurality of wafers that have completed a test in a first region, wherein the test pad of the wafer further includes a second region, and a passivation layer is formed on the second region; Using a photolithography process to remove the passivation layer on the second region, and forming an oxide layer on the test pad; stacking a plurality of wafers in sequence to form a stacked structure; Wet etching the oxide layer of the top wafer to expose the second region of the top wafer; The stacked structure is subjected to a secondary test by exposing the second area.
2. The method for preparing a semiconductor stacked structure according to claim 1, characterized in that: Providing a plurality of wafers that have completed a test in the first area includes: Providing a plurality of wafers, each of the wafers comprising at least one test pad, and a passivation layer is disposed on the test pad; Using a photolithography process to remove a portion of the passivation layer so that the first area of the test pad is exposed; A probe contacts the first region to perform a test on the wafer.
3. The method for preparing a semiconductor stacked structure according to claim 1, characterized in that: The method of removing the passivation layer on the second region by using a photolithography process and forming an oxide layer on the test pad includes: Laying photoresist on the wafer and using a mask to expose the passivation layer corresponding to the second area of the test pad; Etching the passivation layer corresponding to the second region to expose the second region; Oxide is deposited on the wafer as an oxide layer.
4. The method for preparing a semiconductor stacked structure according to claim 3, characterized in that: The oxide is silicon oxide.
5. The method for preparing a semiconductor stacked structure according to claim 1, characterized in that: After providing a plurality of wafers that have completed a test in the first area, the method further includes: The first region is trimmed.
6. The method for preparing a semiconductor stacked structure according to claim 1, characterized in that: The first region is etched and deburred using a wet process.
7. The method for preparing a semiconductor stacked structure according to claim 1, characterized in that: The step of stacking a plurality of wafers in sequence to form a stacked structure comprises: A bonding process is used to stack and connect multiple wafers in sequence, and the test pads between two adjacent layers of wafers are connected correspondingly.
8. The method for preparing a semiconductor stacked structure according to claim 1, characterized in that: After the stack structure is subjected to a secondary test by the exposed second area, the method further comprises: The second region is trimmed.
9. The method for preparing a semiconductor stacked structure according to claim 1, characterized in that: The first region is adjacent to the second region.
10. A semiconductor stack structure, characterized in that: The semiconductor stacking structure is prepared by the preparation method of any one of claims 1 to 9, comprising a plurality of wafers stacked in sequence and connected, wherein the top wafer comprises at least one test pad, and the test pad comprises a first area and a second area.