Semiconductor device and radio frequency module

Abstract

The invention discloses a semiconductor device which comprises a substrate, a chip and a sealing ring, the chip and the sealing ring are formed on the substrate, the sealing ring surrounds the chip, a first area and a second area are defined on the substrate where the sealing ring is located, the second area and the first area are arranged in the direction away from the chip, the substrate of the first area is a table top, and the substrate of the second area is provided with at least one step. The step closest to the first area is a first step; the sealing ring comprises at least two inorganic passivation layers and at least one metal layer, the two inorganic passivation layers are respectively a first inorganic passivation layer and a second inorganic passivation layer, the metal layer is a first metal layer, the first metal layer is located on the table top, the first inorganic passivation layer covers the table top and at least part of the first step and defines a first opening, and the second inorganic passivation layer covers the second step and defines a second opening. The first metal layer is in contact with the substrate through the first opening, the second inorganic passivation layer covers the first inorganic passivation layer and the first metal layer, and the capability of preventing water vapor from entering the chip can be improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing technology, and in particular to a semiconductor device and a radio frequency module. Background Art

[0002] In the semiconductor manufacturing process, a semiconductor chip including semiconductor active devices and interconnection structures arranged on the devices can be formed on a semiconductor substrate through processes such as photolithography, etching and deposition. Usually, multiple chips are formed on the same wafer, and each chip is divided by a criss-crossing scribe line area. The wafer is cut along the scribe line area to form multiple independent chips (die), and then these chips are assembled in semiconductor packaging structures with different functions.

[0003] When a wafer is cut into individual chips, the chip area around the cutting path will be impacted by mechanical (wheel cutter) or thermal expansion (laser cutting), resulting in local cracks and fragments on the cut section of the separated chips. This phenomenon is particularly obvious at the intersection of the cutting path area. In addition, cracks at the rough chip edge are easy to extend to the inside of the chip, resulting in chip degradation or failure. In addition, the side of the cut chip will be exposed, and water vapor may invade the inside of the chip from here, affecting the chip performance. To solve the above problems, a seal ring is used in the prior art to protect the chip. The seal ring is generally composed of a passivation layer and a metal layer stack. On the one hand, the seal ring can release the stress caused by wafer cutting to prevent chip cracking. On the other hand, it can also block the penetration of water vapor or chemical damage such as the diffusion of acid-containing substances, alkali-containing substances or pollution sources.

[0004] However, in the existing structure, the contact surface between the sealing ring and the substrate is a plane. When performing reliability tests such as bHAST, water vapor and the like can easily penetrate into the chip from the flat contact surface, thereby affecting the performance of the chip. Summary of the invention

[0005] The technical problem to be solved by the present invention is to provide a semiconductor device and a radio frequency module, which can improve the ability to prevent water vapor from entering the interior of the chip.

[0006] To solve the above technical problems, the technical solution of the present invention is:

[0007] A semiconductor device comprises: a substrate, and a chip and a sealing ring formed on the substrate, the sealing ring surrounds the chip, the substrate where the sealing ring is located defines a first area and a second area, the first area and the second area are arranged in a direction away from the chip, the substrate in the first area is a table, the substrate in the second area has at least one step, and the step closest to the first area is the first step;

[0008] The sealing ring includes at least two inorganic passivation layers and at least one metal layer, wherein the two inorganic passivation layers are respectively a first inorganic passivation layer and a second inorganic passivation layer, and the metal layer is a first metal layer, which is located on the table surface.

[0009] The first inorganic passivation layer covers the table and the first step and defines a first opening. The first metal layer contacts the substrate through the first opening. The second inorganic passivation layer covers the first inorganic passivation layer and the first metal layer.

[0010] Furthermore, each step in the second zone is composed of a top surface, an inclined surface and a bottom surface, the inclined surface connects the top surface and the bottom surface, the horizontal plane of the top surface is higher than the horizontal plane of the bottom surface, and the depth range from the top surface to the bottom surface is

[0011] Furthermore, the inclination angle of the step slope is 90-160 degrees.

[0012] Furthermore, the depth from the top surface to the bottom surface of the first step is greater than the thickness of the first inorganic passivation layer.

[0013] Furthermore, the substrate of the second region has multiple steps, the inclination angle of the first step slope closest to the first region is greater than the inclination angles of the other step slopes, or the inclination angle of the step slope farthest from the first region is greater than the inclination angles of the other step slopes.

[0014] Further, the substrate of the second region has a plurality of steps, a first step closest to the first region has a depth greater than depths of other steps, or a step farthest from the first region has a depth greater than depths of other steps.

[0015] Furthermore, the total height of the steps in the second region is 0.2-1 μm.

[0016] Furthermore, the first metal layer extends to cover a portion of the first inorganic passivation layer adjacent to the first opening, and the second inorganic passivation layer extends to cover the substrate in the second region.

[0017] Furthermore, the sealing ring also includes an organic passivation layer, and the organic passivation layer partially covers the inorganic passivation layer.

[0018] Furthermore, the organic passivation layer is composed of two layers, namely a first organic passivation layer and a second organic passivation layer, the inorganic passivation layer also includes a third inorganic passivation layer, the second inorganic passivation layer, the first organic passivation layer, the second organic passivation layer and the third inorganic passivation layer are stacked in sequence, the material of the first inorganic passivation layer, the second inorganic passivation layer and the third inorganic passivation layer is SiN or SiO2, and the material of the first organic passivation layer and the second organic passivation layer is PI or BCB.

[0019] Furthermore, the sealing ring further includes a protective passivation layer, which covers the organic passivation layer and the inorganic passivation layer not covered by the organic passivation layer.

[0020] Further, a first inorganic passivation layer, a second inorganic passivation layer and an organic passivation layer are sequentially stacked in the first region.

[0021] Furthermore, the sealing ring also includes a protective passivation layer, and the protective passivation layer covers the inorganic passivation layer.

[0022] Furthermore, the chip is one or more of a metal-oxide semiconductor field effect transistor, a diode, a filter, a heterojunction bipolar transistor, a pseudo modulation doped heterojunction field effect transistor or a high electron mobility transistor.

[0023] Furthermore, the ratio of the total height of the steps in the second region to the total height of the substrate is less than or equal to 10%.

[0024] A radio frequency module comprises the aforementioned semiconductor device.

[0025] The stepped interface of the present invention can extend the path for water vapor to enter the device, improve the chip's ability to resist water vapor intrusion, and thus enhance the reliability of the protected device. In addition, the multi-layer metal itself can also increase the water vapor protection effect, and its specific number of layers matches the number of metal layers in the current process. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 is a schematic structural diagram of Embodiment 1 of the present invention;

[0027] Figure 2 yes Figure 1 A partial enlarged view of the middle A;

[0028] Figure 3 It is a schematic diagram of the position of the chip and the sealing ring of the present invention;

[0029] Figure 4 is a structural diagram of Embodiment 2 of the present invention;

[0030] Figure 5 is a schematic diagram of the structure of Embodiment 3 of the present invention;

[0031] Figure 6 is a schematic structural diagram of a fourth embodiment of the present invention;

[0032] Figure 7 is a structural diagram of Embodiment 5 of the present invention;

[0033] Figure 8 It is a schematic diagram of the steps of the present invention.

[0034] Description of symbols

[0035] Substrate 1 First area S1 Second area S2 Sealing ring 2 Chip 9

[0036] First step 11 Top surface 111 Inclined surface 112 Bottom surface 113 Second step 12 Third step 13 First inorganic passivation layer 21 Second inorganic passivation layer 22 First organic passivation layer 23

[0037] Second organic passivation layer 24 Third inorganic passivation layer 25 Protective passivation layer 26

[0038] The first metal layer 27 , the second metal layer 28 , and the third metal layer 29 . DETAILED DESCRIPTION

[0039] The present invention is further described in detail below in conjunction with the accompanying drawings and examples. It is particularly pointed out that the following examples are only used to illustrate the present invention, but do not limit the scope of the present invention. Similarly, the following examples are only some embodiments of the present invention rather than all embodiments, and all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present invention.

[0040] In addition, the directional terms mentioned in the present invention, such as the directions or positional relationships such as up, down, front, back, left, right, inside, outside, and side, are based on the directions or positional relationships shown in the drawings, or are the directions or positional relationships in which the application product is usually placed when in use. They are only for the convenience of description and cannot be understood as limitations on the present invention. In each of the drawings, units with similar structures are represented by the same reference numerals. For the sake of clarity, the various parts in the drawings are not drawn to scale. In addition, some well-known parts may not be shown in the drawings.

[0041] A semiconductor device comprises: a substrate 1, and a chip 9 and a sealing ring 2 formed on the substrate, wherein the sealing ring surrounds the chip 9, and the substrate where the sealing ring 2 is located defines a first area S1 and a second area S2, wherein the substrate of the first area S1 is a table, and the substrate of the second area S2 has at least one step, and the step closest to the first area is a first step 11.

[0042] The sealing ring 2 includes at least two passivation layers and at least one metal layer. The two passivation layers are respectively a first inorganic passivation layer 21 and a second inorganic passivation layer 22 . The metal layer is a first metal layer 27 . The first metal layer 27 is located on the table surface.

[0043] The first inorganic passivation layer 21 covers the table and the first step 11 and defines a first opening. The first metal layer 27 contacts the substrate 1 through the first opening and extends to cover a portion of the first inorganic passivation layer 21 adjacent to the first opening. The second inorganic passivation layer 22 covers the first inorganic passivation layer 21 and the first metal layer 27 and extends to the substrate of the second region S2.

[0044] Furthermore, each step of the second area S2 is composed of a top surface, an inclined surface and a bottom surface, the inclined surface connects the top surface and the bottom surface, the horizontal plane of the top surface is higher than the horizontal plane of the bottom surface, and the depth range from the top surface to the bottom surface is

[0045] The first step 11 is composed of a top surface 111, an inclined surface 112 and a bottom surface 113. The depth from the top surface 111 to the bottom surface 113 is greater than the thickness of the first inorganic passivation layer 21. If it is less than the thickness of the first inorganic passivation layer 21, the metal connection will be completely wrapped by the dielectric and no step can be formed. If the depth is too deep, it is easy to over-etch and cause problems in subsequent processes.

[0046] Furthermore, the inclination angle of the step slope is 90-160 degrees. If it is less than 90 degrees, it may cause the inorganic passivation layer to be fractured, and if it is greater than 160 degrees, the effect of preventing water vapor from intruding will be affected. The preferred range is 110° to 145°.

[0047] Further, the substrate of the second region S2 has a plurality of steps, and the inclination angle θ1 of the inclined surface 111 of the first step 11 is greater than the inclination angles of the inclined surfaces of other steps. Figure 8 As shown, the substrate of the second zone has three steps, the first step 11, the second step 12 and the third step 13 are arranged in the direction away from the first zone S1, and the inclination angle θ1 of the inclined surface 111 of the first step 11 is greater than the inclination angle θ2 of the inclined surface of the second step 12 and the inclination angle θ3 of the inclined surface of the third step 13 (i.e., θ1>θ2 and θ1>θ3). When water vapor invades along this path, it first passes through the step with a steep angle and then the step with a gentle angle, which affects the speed of water vapor climbing and slows down the speed of water vapor invading the first step. Preferably, along the direction away from the first zone S1, the inclination angle of the step inclined surface gradually decreases (i.e., θ1>θ2>θ3).

[0048] Alternatively, the substrate of the second region S2 has multiple steps, and the inclination angle of the step slope farthest from the first region is greater than the inclination angles of the other step slopes. When water vapor invades along this path, the first steeper inclination angle increases the climbing obstacle of water vapor.

[0049] Preferably, along the direction away from the first area S1 , the inclination angle of the step slope gradually increases (ie θ1 < θ2 < θ3 ).

[0050] Furthermore, the substrate of the second region S2 has a plurality of steps, and the depth d1 of the first step 11 closest to the first region S1 is greater than the depths of the other steps. Figure 8As shown, the substrate of the second zone S2 has three steps, the first step 11, the second step 12 and the third step 13 are arranged in the direction away from the first zone, and the depth d1 of the first step 11 is greater than the depth d2 of the second step 12 and the depth d3 of the third step 13 (i.e., d1>d2 and d1>d3). When water vapor invades along this path, the first step 11 is the last step, and the deeper step can increase the obstacle for water vapor to climb up. Preferably, the depth of the step gradually decreases in the direction away from the first zone S1 (i.e., d1>d2>d3).

[0051] Alternatively, the substrate of the second region S2 has multiple steps, and the depth of the step farthest from the first region is greater than the depths of the other steps. When water vapor invades along this path, the first deeper step increases the climbing obstacle of water vapor. Preferably, the depth of the step gradually increases along the direction away from the first region S1 (i.e., d1<d2<d3).

[0052] Furthermore, the total height of the steps in the second region S2 is 0.2-1 μm. Preferably, it accounts for less than 10% of the total height of the substrate. Therefore, etching to form the steps in the second region S2 does not affect the performance of the substrate. Figure 6 As shown, the ratio of the total height N2 of the steps of the second region S2 to the total height N1 of the substrate 1 is less than or equal to 10%, that is, N2 / N1≤10%.

[0053] Furthermore, the first metal layer 27 extends to cover a portion of the first inorganic passivation layer 21 adjacent to the first opening. This design makes it more difficult for water vapor to invade. Of course, it may not extend to cover the first inorganic passivation layer 21 according to the process requirements of the actual product.

[0054] In order to further prevent the intrusion of water vapor, the second inorganic passivation layer 22 may be extended to cover the substrate in the second region S2 .

[0055] Furthermore, the sealing ring 2 also includes an organic passivation layer, which partially covers the inorganic passivation layer. The main function of the organic passivation layer is to control electrical properties, resist chemical corrosion and release stress. The material of the organic passivation layer is PI (polyimide) or BCB (benzocyclobutene). For example, the first inorganic passivation layer 21, the second inorganic passivation layer 22 and the organic passivation layer are sequentially stacked in the first area S1. The organic passivation layer is located in the first area S1 closer to the chip. The main purpose is to release stress and resist corrosion. It can be formed in the same step with certain structures in the chip, which is beneficial to the process.

[0056] Further, the sealing ring 2 further includes a protective passivation layer 26, which covers the inorganic passivation layer. The material of the protective passivation layer 26 is PBO. The material of the inorganic passivation layer is SiN or SiO2. Alternatively, according to the structural characteristics of the device, the protective passivation layer 26 covers the inorganic passivation layer and the organic passivation layer.

[0057] According to the actual needs of customers, the chip of the present invention is at least one or more of a metal-oxide semiconductor field effect transistor, a diode, a filter, a heterojunction bipolar transistor, a pseudo-modulation doped heterojunction field effect transistor or a high electron mobility transistor.

[0058] Embodiment 1

[0059] like Figure 1 , Figure 2 and Figure 3 As shown, a semiconductor device comprises: a substrate 1, and a chip 9 and a sealing ring 2 formed on the substrate 1, wherein the sealing ring 2 surrounds the chip 9. In this embodiment, the chip 9 is a high electron mobility transistor (HEMT).

[0060] The substrate where the sealing ring 2 is located defines a first area S1 and a second area S2. The substrate of the first area S1 is a table, and the substrate of the second area S2 has a first step 11. The first step 11 is closest to the first area S1.

[0061] The sealing ring 2 includes three inorganic passivation layers, two organic passivation layers and two metal layers, the three inorganic passivation layers are respectively a first inorganic passivation layer 21, a second inorganic passivation layer 22 and a third inorganic passivation layer 25, the two organic passivation layers are respectively a first organic passivation layer 23 and a second organic passivation layer 24, the two metal layers are a first metal layer 27 and a second metal layer 28, and the first metal layer 27 is located on the table surface.

[0062] The first inorganic passivation layer 21 covers the mesa and the first step 11 and defines a first opening. The first metal layer 27 contacts the substrate 1 via the first opening and extends to cover a portion of the first inorganic passivation layer 21 adjacent to the first opening.

[0063] The second inorganic passivation layer 22 covers the first inorganic passivation layer 21 and the first metal layer 27 and extends to the substrate in the second region S2 . A second opening is defined in the second inorganic passivation layer 22 . The second metal layer 28 contacts the first metal layer 27 via the second opening.

[0064] The first organic passivation layer 23 covers a portion of the second inorganic passivation layer 22 , and the second metal layer 28 covers a portion of the second inorganic passivation layer 22 and a portion of the first organic passivation layer 23 .

[0065] The second organic passivation layer 24 is stacked on a portion of the first organic passivation layer 23 not covered by the second metal layer 28 , and covers a portion of the second metal layer 28 .

[0066] The third inorganic passivation layer 25 covers the second organic passivation layer 24 , the second metal layer 28 and a portion of the second inorganic passivation layer 22 and extends onto the second region S2 of the substrate.

[0067] like Figure 2 As shown, the first step 11 comprises a top surface 111, an inclined surface 112 and a bottom surface 113, wherein the inclined surface 112 connects the top surface 111 and the bottom surface 113, the horizontal plane of the top surface 111 is higher than the horizontal plane of the bottom surface 113, and the depth d1 from the top surface 111 to the bottom surface 113 is The thickness h of the first inorganic passivation layer 21 is (ie, d1>h), the inclination angle θ1 of the step slope 112 is 120 degrees.

[0068] Embodiment 2

[0069] like Figure 4 As shown, a semiconductor device includes: a substrate 1, and a chip 9 and a sealing ring 2 formed on the substrate 1, the sealing ring 2 surrounds the chip 9. In this embodiment, the chip 9 includes a heterojunction bipolar transistor (HBT) and a pseudo modulation doped heterojunction field effect transistor (pHEMT), and forms a BIHEMT.

[0070] The substrate where the sealing ring 2 is located defines a first area S1 and a second area S2. The substrate in the first area S1 is a table, and the substrate in the second area S2 has steps.

[0071] The substrate of the second region S2 has a second step 11, a second step 12 and a third step 13, and the first step 11, the second step 12 and the third step 13 are arranged in a direction away from the first region S1 (i.e. Figure 4 The first direction is shown in Figure 1).

[0072] The sealing ring 2 includes three inorganic passivation layers, two organic passivation layers, a metal layer and a protective passivation layer 26. The three inorganic passivation layers are respectively a first inorganic passivation layer 21, a second inorganic passivation layer 22 and a third inorganic passivation layer 25, the two organic passivation layers are respectively a first organic passivation layer 23 and a second organic passivation layer 24, the one metal layer is a first metal layer 27, and the first metal layer 27 is located on the table surface.

[0073] The first inorganic passivation layer 21 covers the terrace, the first step 11 and part of the second step 12 and defines a first opening. The first metal layer 27 contacts the substrate 1 through the first opening and extends to cover part of the first inorganic passivation layer 21 adjacent to the first opening.

[0074] The second inorganic passivation layer 22 covers the first inorganic passivation layer 21, the first metal layer 27 and a portion of the second step 12 not covered by the first inorganic passivation layer 21; the first organic passivation layer 23 covers a portion of the second inorganic passivation layer 22, the second organic passivation layer 24 covers the first organic passivation layer 23, the third inorganic passivation layer 25 covers the second organic passivation layer 24, a portion of the first organic passivation layer 23, a portion of the second inorganic passivation layer 22 and the third step 13, and the protective passivation layer 26 covers the third inorganic passivation layer 25 and extends to the second region S2 substrate.

[0075] In this embodiment, h is θ1 is 160°, θ2 is 140°, θ3 is 120°, and d1 is d2 is d3 is (i.e., θ1>θ2>θ3, d1>d2>d3, d1>h). The total height of the steps in the second zone is The thickness of the thinned substrate is 75-100 μm, which accounts for less than 10% of the total height of the substrate. Therefore, etching to form the step of the second region does not affect the performance of the substrate.

[0076] In this embodiment, the path for water vapor intrusion needs to pass through the first step 11, the second step 12 and the third step 13. Compared with the first embodiment, the path for water vapor to enter is extended. The stepped interface can enhance the chip's ability to resist water vapor intrusion, thereby improving the chip's reliability.

[0077] In particular, the product of Example 2 was subjected to the bHAST temperature and humidity bias high accelerated stress test (Bias Highly Accelerated Stress Test), which had a good effect. The BHAST test is a highly accelerated life bias aging test system, which is suitable for IC packaging, semiconductors, microelectronic chips, magnetic materials and other electronic parts to perform high pressure, high temperature, unsaturated / saturated humidity and heat accelerated life reliability tests. This test system is used to quickly expose product defects and weak links in the product design stage and test the sealing and aging performance of its products.

[0078] Embodiment 3

[0079] like Figure 5 As shown, a semiconductor device includes: a substrate 1, and a chip 9 and a sealing ring 2 formed on the substrate 1, wherein the sealing ring 2 surrounds the chip 9. In this embodiment, the chip 9 is a diode.

[0080] The substrate where the sealing ring 2 is located defines a first area S1 and a second area S2. The substrate in the first area S1 is a table, and the substrate in the second area S2 has steps.

[0081] The substrate of the second region S2 has a second step 11 , a second step 12 , and a third step 13 , and the first step 11 , the second step 12 , and the third step 13 are arranged in a direction away from the first region S1 .

[0082] The sealing ring 2 includes three inorganic passivation layers, two organic passivation layers, three metal layers and a protective passivation layer 26. The three inorganic passivation layers are respectively a first inorganic passivation layer 21, a second inorganic passivation layer 22 and a third inorganic passivation layer 25. The two organic passivation layers are respectively a first organic passivation layer 23 and a second organic passivation layer 24. The three metal layers are a first metal layer 27, a second metal layer 28 and a third metal layer 29.

[0083] The first inorganic passivation layer 21 covers the terrace, the first step 11 and part of the second step 12 and defines a first opening. The first metal layer 27 contacts the substrate 1 through the first opening and extends to cover part of the first inorganic passivation layer 21 adjacent to the first opening.

[0084] The second inorganic passivation layer 22 covers the second step 12 , and a second opening is defined on the second inorganic passivation layer 22 . The second metal layer 28 contacts the first metal layer 27 via the second opening.

[0085] The first organic passivation layer 23 covers a portion of the second inorganic passivation layer 22 , and the second metal layer 28 covers a portion of the second inorganic passivation layer 22 and a portion of the first organic passivation layer 23 .

[0086] The second organic passivation layer 24 is stacked on the portion of the first organic passivation layer 23 not covered by the second metal layer 28 and covers a portion of the second metal layer 28 . The third metal layer 29 covers a portion of the second organic passivation layer 24 and a portion of the second metal layer 23 .

[0087] The third inorganic passivation layer 25 covers the second organic passivation layer 24 , the third metal layer 29 , the second inorganic passivation layer 22 and the third step 13 .

[0088] The protective passivation layer 26 covers the third inorganic passivation layer 25 and extends onto the second region S2 of the substrate.

[0089] In this embodiment, h is θ1 is 100°, θ2 is 130°, θ3 is 150°, and d1 is d2 is d3 is

[0090] In this embodiment, multi-layer metal can actually further enhance the protection effect, and on the other hand it matches the number of metal layers of the current process.

[0091] Embodiment 4

[0092] like Figure 6 As shown, a semiconductor device comprises: a substrate 1, and a chip 9 and a sealing ring 2 formed on the substrate 1, wherein the sealing ring 2 surrounds the chip 9. In this embodiment, the chip 9 is a filter.

[0093] The substrate where the sealing ring 2 is located defines a first area S1 and a second area S2. The substrate in the first area S1 is a table, and the substrate in the second area S2 has steps.

[0094] The substrate of the second region S2 has a second step 11 and a second step 12 , and the first step 11 and the second step 12 are arranged in a direction away from the first region S1 .

[0095] The sealing ring 2 includes two passivation layers, a metal layer and a protective passivation layer 26 . The two passivation layers are respectively a first inorganic passivation layer 21 and a second inorganic passivation layer 22 . The metal layer is a first metal layer 27 .

[0096] The first inorganic passivation layer 21 covers the terrace, the first step 11 and part of the second step 12 and defines a first opening. The first metal layer 27 contacts the substrate 1 through the first opening and extends to cover part of the first inorganic passivation layer 21 adjacent to the first opening.

[0097] The second inorganic passivation layer 22 covers the second step 12 , and the protective passivation layer 26 covers the second inorganic passivation layer 22 and extends onto the second region S2 of the substrate.

[0098] In this embodiment, h is θ1 is 95°, θ2 is 110°, and d1 is d2 is

[0099] Embodiment 5

[0100] like Figure 7 As shown, a semiconductor device includes: a substrate 1, and a chip 9 and a sealing ring 2 formed on the substrate 1, wherein the sealing ring 2 surrounds the chip 9. In this embodiment, the chip 9 is a metal-oxide semiconductor field effect transistor (MOSFET).

[0101] The substrate where the sealing ring 2 is located defines a first area S1 and a second area S2. The substrate in the first area S1 is a table, and the substrate in the second area S2 has a second step 11 and a second step 12. The first step 11 and the second step 12 are arranged in a direction away from the first area S1.

[0102] The sealing ring 2 includes two inorganic passivation layers, one organic passivation layer, one metal layer and a protective passivation layer 26, the two inorganic passivation layers are respectively a first inorganic passivation layer 21 and a second inorganic passivation layer 22, the one organic passivation layer is a first organic passivation layer 23, the one metal layer is a first metal layer 27, and the first metal layer 27 is located on the table surface.

[0103] The first inorganic passivation layer 21 covers the mesa and the first step 11 and defines a first opening. The first metal layer 27 contacts the substrate 1 via the first opening and extends to cover a portion of the first inorganic passivation layer 21 adjacent to the first opening.

[0104] The second inorganic passivation layer 22 covers the first inorganic passivation layer 21 and the first metal layer 27 and extends onto the substrate in the second region S2 .

[0105] The first organic passivation layer 23 covers a portion of the second inorganic passivation layer 22 .

[0106] The protective passivation layer 26 covers the first organic passivation layer 23 and the second inorganic passivation layer 22 and extends onto the second region S2 of the substrate.

[0107] In this embodiment, h is θ1 is 135°, θ2 is 90°, and d1 is d2 is

[0108] Some embodiments of the present invention further provide a radio frequency module, including the semiconductor device provided by any of the above embodiments. The radio frequency module is, for example, an integrated radio frequency switch and filter, so as to be applied to communication equipment, such as a mobile phone, a WiFi wireless routing device, etc.

Claims

1. A semiconductor device, characterized in that: include: A substrate, and a chip and a sealing ring formed on the substrate, the sealing ring surrounds the chip, the substrate where the sealing ring is located defines a first area and a second area, the second area and the first area are arranged in a direction away from the chip, the substrate in the first area is a table, the substrate in the second area has at least one step, and the step closest to the first area is the first step; The sealing ring includes at least two inorganic passivation layers and at least one metal layer, wherein the two inorganic passivation layers are respectively a first inorganic passivation layer and a second inorganic passivation layer, and the metal layer is a first metal layer, which is located on the table surface. The first inorganic passivation layer covers the table and at least a portion of the first step and defines a first opening. The first metal layer contacts the substrate via the first opening. The second inorganic passivation layer covers the first inorganic passivation layer and the first metal layer.

2. A semiconductor device according to claim 1, characterized in that: Each step in the second zone consists of a top surface, an inclined surface and a bottom surface. The inclined surface connects the top surface and the bottom surface. The horizontal plane of the top surface is higher than the horizontal plane of the bottom surface. The depth range from the top surface to the bottom surface is 3. A semiconductor device according to claim 2, characterized in that: The inclination angle of the step slope is 90-160 degrees.

4. A semiconductor device according to claim 2, characterized in that: in, The depth from the top surface to the bottom surface of the first step is greater than the thickness of the first inorganic passivation layer.

5. A semiconductor device according to claim 1, characterized in that The substrate in the second region has multiple steps, the inclination angle of the step slope closest to the first region is greater than the inclination angles of other step slopes, or the inclination angle of the step slope farthest from the first region is greater than the inclination angles of other step slopes.

6. A semiconductor device according to claim 1, characterized in that: The substrate in the second region has a plurality of steps, and a depth of a step closest to the first region is greater than depths of other steps, or a depth of a step farthest from the first region is greater than depths of other steps.

7. A semiconductor device according to claim 1, characterized in that: The total height of the steps in the second region is 0.2-1 μm.

8. A semiconductor device according to claim 1, characterized in that: The first metal layer extends to cover a portion of the first inorganic passivation layer adjacent to the first opening, and the second inorganic passivation layer extends to cover the substrate in the second region.

9. A semiconductor device according to claim 1, characterized in that: The sealing ring also includes an organic passivation layer, and the organic passivation layer partially covers the inorganic passivation layer.

10. A semiconductor device according to claim 9, characterized in that: The organic passivation layer consists of two layers, namely the first organic passivation layer and the second organic passivation layer, the inorganic passivation layer also includes a third inorganic passivation layer, the second inorganic passivation layer, the first organic passivation layer, the second organic passivation layer and the third inorganic passivation layer are stacked in sequence, the material of the first inorganic passivation layer, the second inorganic passivation layer and the third inorganic passivation layer is SiN or SiO2, and the material of the first organic passivation layer and the second organic passivation layer is PI or BCB.

11. A semiconductor device according to claim 9, characterized in that: The sealing ring further includes a protective passivation layer, which covers the organic passivation layer and the inorganic passivation layer not covered by the organic passivation layer.

12. A semiconductor device according to claim 9, characterized in that: A first inorganic passivation layer, a second inorganic passivation layer, and an organic passivation layer are sequentially stacked in the first region.

13. A semiconductor device according to claim 1, characterized in that: The sealing ring also includes a protective passivation layer, which covers the inorganic passivation layer.

14. A semiconductor device according to claim 1, characterized in that: The chip is one or more of a metal-oxide semiconductor field effect transistor, a diode, a filter, a heterojunction bipolar transistor, a pseudo modulation doped heterojunction field effect transistor or a high electron mobility transistor.

15. A semiconductor device according to claim 1, characterized in that: The ratio of the total step height of the second region to the total height of the substrate is less than or equal to 10%.

16. A radio frequency module, characterized in that: Comprising the semiconductor device according to any one of claims 1 to 15.

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