Substrate structure, semiconductor structure and preparation method of substrate structure
By designing grooves through multiple parts in the substrate structure, the heat dissipation performance of the substrate structure is improved, and the problem of poor heat dissipation of the silicon substrate device overlying the insulating layer is solved, thereby avoiding device performance degradation due to heat accumulation.
Patent Information
- Application Number
- CN202310926371.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-07-26
- Publication Date
- 2025-02-07
AI Technical Summary
Devices using an insulating layer covered with silicon substrates have the problem of poor heat dissipation, which leads to excessive heat accumulation, affecting device performance, especially the decay of drain current in the saturated region.
A substrate structure is designed, including a base substrate, an insulating layer and a growth substrate, on which a plurality of grooves at least partially penetrate the grooves are opened, with different depths and opening widths to improve heat dissipation performance.
By reducing the average thickness of the substrate structure, the heat dissipation performance is improved, the problem of excessive heat accumulation in the semiconductor structure is avoided, and the problem of drain current fading in the saturated region caused by heat accumulation is solved.
Smart Images
Figure CN119400760A_ABST
Abstract
Description
Technical Field
[0001] The present disclosure relates to the field of semiconductor technology, and in particular to a substrate structure, a semiconductor structure, and a method for preparing the substrate structure. Background Art
[0002] With the continuous advancement of integrated circuit manufacturing technology, the size of semiconductor devices is becoming smaller and smaller, and with it comes a lot of problems when the device size approaches the physical limit. This has led the industry to look for solutions other than simply reducing the size of the device to further improve device performance. Silicon on insulator (SOI) has been widely studied and used by the industry as an important development direction. Compared with traditional bulk silicon materials, the characteristic of SOI is that there is an insulating layer under a very thin single crystal silicon layer on the surface, mainly using silicon oxide as the insulating material. Under the insulating layer is the traditional bulk silicon material, which serves to provide mechanical support for the structure above. The SOI structure greatly reduces the leakage current of the device without changing the size of the device, thereby greatly improving the device performance.
[0003] However, compared with devices that do not use an insulating layer-coated silicon substrate, devices that use an insulating layer-coated silicon substrate generally have a problem of poor heat dissipation. Excessive heat accumulation may cause the saturation-region drain current (Idsat) to decay. In addition, devices that use an insulating layer-coated silicon substrate may also be affected by the backside bias effect (also known as the substrate bias effect), thereby changing the breakdown voltage of the metal-oxide-semiconductor field-effect transistor (MOSFET). Summary of the invention
[0004] The purpose of the present disclosure is to provide a diode structure, a HEMT structure, a substrate structure and a preparation method thereof, which can improve the heat dissipation performance of the substrate structure.
[0005] According to one aspect of the present disclosure, there is provided a substrate structure, the substrate structure comprising:
[0006] A base substrate, an insulating layer and a growth substrate sequentially disposed on the base substrate;
[0007] A plurality of grooves are provided, wherein the plurality of grooves are opened on a side of the base substrate away from the growth substrate, the plurality of grooves at least partially penetrate the base substrate, and at least two of the plurality of grooves have different depths or opening widths.
[0008] Optionally, the density of the grooves located in the central area of the base substrate is greater than the density of the grooves located in the edge area of the base substrate.
[0009] Optionally, the depth and / or opening width of the plurality of grooves gradually decreases in a direction from the center to the edge of the base substrate.
[0010] Optionally, the substrate structure includes a plurality of unit areas, each of the unit areas includes at least two sub-unit areas, and each of the sub-unit areas includes at least one groove;
[0011] In one unit area, the sizes of the grooves in each of the sub-unit areas are different.
[0012] Optionally, the groove includes a first portion located in the base substrate, a second portion located in the insulating layer, and a third portion located in the growth substrate;
[0013] Wherein, the opening width of the first portion of the groove is greater than the opening widths of the second portion and the third portion.
[0014] Optionally, in a direction from the base substrate to the growth substrate,
[0015] The opening widths of the first part, the second part and the third part remain unchanged;
[0016] Or, the opening widths of the first part, the second part and the third part gradually decrease;
[0017] Or, the opening width of the first part gradually decreases, and the opening width of the third part remains unchanged;
[0018] Alternatively, the opening width of the first portion remains unchanged, and the opening width of the third portion gradually decreases.
[0019] Optionally, the groove passes through the base substrate and the insulating layer, and the bottom of the groove is located on the surface of the growth substrate close to the base substrate;
[0020] Or, the groove passes through the base substrate and the insulating layer, and the groove partially passes through the growth substrate;
[0021] Alternatively, the groove passes through the base substrate, the insulating layer and the growth substrate.
[0022] Optionally, the growth substrate is a super junction structure, the super junction structure includes an n-type semiconductor structure and a p-type semiconductor structure, and the n-type semiconductor structure and the p-type semiconductor structure are alternately distributed along a direction parallel to the growth substrate.
[0023] Optionally, the substrate structure further includes:
[0024] A protection layer is disposed on a side of the base substrate facing away from the growth substrate, wherein the protection layer has openings for exposing the silicon-on-insulator, and the openings correspond to the grooves one by one.
[0025] Optionally, the substrate structure further includes:
[0026] The heat dissipation layer covers the inner wall of the groove.
[0027] According to another aspect of the present disclosure, a semiconductor structure is further provided, comprising:
[0028] The substrate structure described in any one of the above items;
[0029] and a device structure formed on the substrate structure, wherein the device structure is located on a side of the growth substrate away from the base substrate,
[0030] The semiconductor structure is any one of a high electron mobility transistor device, a vertical power device, a radio frequency device and a light emitting diode device.
[0031] According to another aspect of the present disclosure, there is also provided a method for preparing a substrate structure, comprising:
[0032] providing a bottom substrate;
[0033] forming an insulating layer and a growth substrate on the base substrate in sequence;
[0034] A plurality of grooves are formed on a side of the base substrate away from the growth substrate. The plurality of grooves at least partially penetrate the base substrate. Among the plurality of grooves, at least two grooves have different depths or opening widths.
[0035] Optionally, the depths or opening widths of the plurality of grooves gradually decrease in a direction from the center to the edge of the base substrate.
[0036] Optionally, the density of the grooves located in the central area of the base substrate is greater than the density of the grooves located in the edge area of the base substrate.
[0037] Optionally, the substrate structure includes a plurality of unit areas, each of the unit areas includes at least two sub-unit areas, and each of the sub-unit areas includes at least one groove;
[0038] In one unit area, the sizes of the grooves in each of the sub-unit areas are different.
[0039] Optionally, the groove includes a first portion located in the base substrate, a second portion located in the insulating layer, and a third portion located in the growth substrate;
[0040] Wherein, the opening width of the first portion of the groove is greater than the opening widths of the second portion and the third portion.
[0041] Optionally, in a direction from the base substrate to the growth substrate,
[0042] The opening widths of the first part, the second part and the third part gradually decrease;
[0043] Or, the opening width of the first part gradually decreases, and the opening width of the third part remains unchanged;
[0044] Alternatively, the opening width of the first portion remains unchanged, and the opening width of the third portion gradually decreases.
[0045] Optionally, the groove passes through the base substrate and the insulating layer, and the bottom of the groove is located on the surface of the growth substrate close to the base substrate;
[0046] Or, the groove passes through the base substrate and the insulating layer, and the groove partially passes through the growth substrate;
[0047] Alternatively, the groove passes through the base substrate, the insulating layer and the growth substrate.
[0048] Optionally, a super junction structure is formed in the growth substrate, the super junction structure comprising an n-type semiconductor structure and a p-type semiconductor structure, and the n-type semiconductor structure and the p-type semiconductor structure are alternately distributed along a direction parallel to the growth substrate.
[0049] Optionally, forming a groove that at least partially penetrates the base substrate comprises:
[0050] forming a protective layer on a side of the base substrate facing away from the growth substrate;
[0051] forming an opening on the protective layer to expose the base substrate;
[0052] The bottom substrate is etched using the protective layer forming the opening as a mask to form the groove.
[0053] Optionally, after forming the groove on the side of the base substrate away from the growth substrate, the method further comprises:
[0054] A heat dissipation layer covering an inner wall of the groove is formed in the groove.
[0055] The substrate structure, semiconductor structure and method for preparing the substrate structure of the embodiments disclosed herein are such that, since the substrate structure is provided with a groove that at least partially penetrates the bottom substrate, the average thickness of the substrate structure is reduced, thereby improving the heat dissipation performance of the substrate structure. When the substrate structure is applied to the semiconductor structure, it is possible to avoid excessive heat accumulation in the semiconductor structure, thereby solving the problem of saturation region drain current decay caused by excessive heat accumulation. BRIEF DESCRIPTION OF THE DRAWINGS
[0056] Figure 1 It is a schematic diagram after forming a protective layer in the first embodiment of the present disclosure.
[0057] Figure 2-Figure 13 It is a schematic diagram after the groove is formed in the first embodiment of the present disclosure.
[0058] Fig.14 It is a schematic diagram of the substrate structure prepared in Example 2 of the present disclosure.
[0059] Fig.15 It is a schematic diagram of the substrate structure prepared in Example 3 of the present disclosure.
[0060] Fig.16 It is a schematic diagram of the substrate structure prepared in Example 4 of the present disclosure.
[0061] Fig.17 It is a schematic diagram of the semiconductor structure prepared in Example 5 of the present disclosure.
[0062] Fig.18 It is a schematic diagram of the semiconductor structure prepared in Example 6 of the present disclosure.
[0063] Explanation of the reference numerals: 100, unit area; 100a, sub-unit area; 101, bottom substrate; 102, insulating layer; 103, growth substrate; 1031, n-type semiconductor structure; 1032, p-type semiconductor structure; 104, groove; 104a, first part; 104b, second part; 104c, third part; 2, heterojunction structure; 201, channel layer; 202, barrier layer; 3, gate; 4, source; 5, drain; 6, protective layer; 601, opening; 7, nucleation layer; 8, heat dissipation layer; 9, buffer layer; 10, first electrode; 11, second electrode. DETAILED DESCRIPTION
[0064] Exemplary embodiments will be described in detail herein, examples of which are shown in the accompanying drawings. When the following description refers to the drawings, the same numbers in different drawings represent the same or similar elements unless otherwise indicated. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present disclosure. Instead, they are merely examples of devices consistent with some aspects of the present disclosure as detailed in the appended claims.
[0065] The terms used in the present disclosure are only for the purpose of describing specific embodiments and are not intended to limit the present disclosure. Unless otherwise defined, the technical terms or scientific terms used in the present disclosure should be understood by people with ordinary skills in the field to which the present disclosure belongs. The words "first", "second" and similar words used in the present disclosure specification and claims do not indicate any order, quantity or importance, but are only used to distinguish different components. Similarly, words such as "one" or "one" do not indicate a quantity limit, but indicate that there is at least one. "Multiple" or "several" means two and more than two. Unless otherwise specified, words such as "front", "rear", "lower" and / or "upper" are only for the convenience of explanation and are not limited to one position or one spatial orientation. Words such as "include" or "comprise" mean that the elements or objects appearing in front of "include" or "comprise" include the elements or objects listed after "include" or "comprise" and their equivalents, and do not exclude other elements or objects. Words such as "connect" or "connected" are not limited to physical or mechanical connections, and can include electrical connections, whether direct or indirect. As used in this disclosure and the appended claims, the singular forms "a", "an", "said", and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It should also be understood that the term "and / or" as used herein refers to and encompasses any or all possible combinations of one or more of the associated listed items.
[0066] Embodiment 1
[0067] Embodiment 1 of the present disclosure provides a substrate structure and a method for preparing the substrate structure. Figure 1 It is a schematic diagram after the protective layer 6 is formed in the first embodiment of the present disclosure. Figure 2-Figure 13 It is a schematic diagram after the groove 104 is formed in the first embodiment of the present disclosure. Figure 2 yes Figure 5 The method for preparing the substrate structure may include steps S100 to S110, wherein:
[0068] Step S100 , providing a base substrate 101 , and sequentially forming an insulating layer 102 and a growth substrate 103 on the base substrate 101 .
[0069] Step S110 , forming a groove 104 on a side of the base substrate 101 away from the growth substrate 103 , wherein the groove 104 at least partially penetrates the base substrate 101 .
[0070] The substrate structure prepared in this embodiment has a groove 104 that at least partially penetrates the bottom substrate 101, which is equivalent to reducing the average thickness of the substrate structure, thereby improving the heat dissipation performance of the substrate structure; when the substrate structure is applied to a semiconductor structure, it can avoid excessive heat accumulation in the semiconductor structure and solve the problem of saturation region drain current decay caused by excessive heat accumulation.
[0071] The following is a detailed description of each step of the method for preparing the substrate structure of the embodiment of the present disclosure:
[0072] In step S100, the base substrate 101 may be 100-type single crystal silicon, and the growth substrate 103 may be 111-type single crystal silicon. The insulating layer 102 is located between the base substrate 101 and the growth substrate 103, and its material may be an insulating material, such as SiO2. In other embodiments, the base substrate 101 may also be any one of SiC, AlN, Al2O3 or a ceramic substrate, and the growth substrate may be any one of SiC, AlN or Al2O3, which is not limited in this embodiment.
[0073] In step S110, a groove 104 is formed on a side of the base substrate 101 away from the growth substrate 103, and the groove 104 at least partially penetrates the base substrate 101. The groove 104 at least partially penetrates the base substrate 101, that is, the groove 104 may only partially penetrate the base substrate 101; or, the groove 104 penetrates the base substrate 101, and the bottom of the groove 104 stays on the surface of the insulating layer 102 close to the base substrate 101; or, the groove 104 penetrates the base substrate 101 and the insulating layer 102, and the bottom of the groove 104 is located on the surface of the growth substrate 103 close to the base substrate 101; or, the groove 104 penetrates the base substrate 101 and the insulating layer 102, and the groove 104 partially penetrates the growth substrate 103; or, the groove 104 completely penetrates the base substrate 101, the insulating layer 102 and the growth substrate 103. The present invention does not limit the depth of the groove 104. Among them, if Figure 2 As shown, the groove 104 is equivalent to a through hole that penetrates the base substrate 101, the insulating layer 102 and the growth substrate 103. Figure 3 As shown, the groove 104 penetrates the base substrate 101 and the insulating layer 102 and partially penetrates the growth substrate 103, that is, the bottom of the groove 104 extends into the growth substrate 103; of course, as shown in FIG. Figure 4 As shown, the groove 104 may only partially penetrate the base substrate 101. It can be understood that when the depth of the groove 104 is different, its heat dissipation capacity is also different.
[0074] The number of the grooves 104 can be multiple, and the multiple grooves 104 can be distributed at intervals, and further, the multiple grooves 104 can be evenly distributed. Figure 8 As shown, Figure 8 This is a bottom view of the substrate in an optional embodiment, in which the density of the grooves 104 located in the central area of the bottom substrate 101 is greater than the density of the grooves 104 located in the edge area of the bottom substrate 101. The depths of the multiple grooves 104 can be the same. Of course, there can also be at least two grooves 104 with different depths among the multiple grooves 104. For example, the depths of the grooves 104 are different. The cross-sectional shape of the groove 104 can be a polygon, such as a bar, triangle, square, rectangle, trapezoid, etc. Of course, the cross-sectional shape of the groove 104 can also be a circle, an ellipse, etc., and the cross-section is parallel to the surface of the bottom substrate 101. In some embodiments, in the direction from the substrate 101 to the growth substrate 103, the opening width of the groove 104 remains unchanged or gradually decreases. Optionally, among the multiple grooves 104, there are at least two grooves 104 with different depths or opening widths. As Fig. 9 As shown, Fig. 9 In an optional embodiment Figure 5 In the AA cross-sectional view of the structure shown, the depth and / or opening width of the plurality of grooves 104 gradually decreases in the direction from the center to the edge of the base substrate 101. This approach can balance the thermal uniformity of the substrate structure during the epitaxial growth process to improve the crystal quality of the semiconductor layer of the device structure formed on the substrate structure, thereby improving the performance of the device structure.
[0075] like Figures 10 to 13 As shown, in an optional embodiment, the groove 104 includes a first portion 104a located in the base substrate 101, a second portion 104b located in the insulating layer 102, and a third portion 104c located in the growth substrate 103. The opening width of the first portion 104a of the groove 104 is greater than the opening widths of the second portion 104b and the third portion 104c. Fig.10 As shown, in the direction from the base substrate 101 to the growth substrate 103, the opening widths of the first portion 104a, the second portion 104b and the third portion 104c remain unchanged. Fig.11 As shown, in the direction from the base substrate 101 to the growth substrate 103, the opening widths of the first portion 104a, the second portion 104b and the third portion 104c gradually decrease. Fig.12 As shown, in the direction from the base substrate 101 to the growth substrate 103, the opening width of the first portion 104a gradually decreases, and the opening width of the third portion 104c remains unchanged. Fig.13 As shown, optionally, in the direction from the base substrate 101 to the growth substrate 103, the opening width of the first portion 104a remains unchanged, and the opening width of the third portion 104c gradually decreases.
[0076] like Figure 6 to Figure 7 As shown, Figure 7 for Figure 6 BB cross-sectional view of the structure shown. In an optional embodiment, the substrate structure includes a plurality of unit areas 100, each unit area 100 includes at least two sub-unit areas 100a, and each sub-unit area 100a includes at least one groove 104. In a unit area 100, the sizes of the grooves 104 in each sub-unit area 100a are different. The size of the sub-unit area 100a refers to: the percentage of the total volume of the grooves 104 of a sub-unit area 100a to the volume of the substrate block material of the sub-unit area 100a. In some embodiments, in a sub-unit area 100a, the depths of the grooves 104 of each sub-unit area 100a are different, and / or the widths are different, and / or the opening densities are different, so as to adjust the different sizes of each sub-unit area 100a.
[0077] Specifically, the above-mentioned step S110 may include: forming a protective layer 6 on the side of the base substrate 101 facing away from the growth substrate 103; forming an opening 601 exposing the base substrate 101 on the protective layer 6; using the protective layer 6 with the opening 601 as a mask, etching the base substrate 101 to form a groove 104. The material of the protective layer 6 may be an insulating material, such as SiO2 or SiN. The mask may be prepared by vapor deposition. The opening 601 may be formed by a photolithography process. The present disclosure may etch the silicon on insulator 1 by a wet etching process, and the formed groove 104 is connected to the opening 601. The number of the openings 601 may be multiple, so as to form multiple grooves 104 corresponding to the multiple openings 601.
[0078] Embodiment 2
[0079] Fig.14 Schematic diagram of the substrate structure prepared in the second embodiment of the present disclosure. The substrate structure and the method for preparing the substrate structure in the second embodiment of the present disclosure are substantially the same as those in the first embodiment of the present disclosure, except that a superjunction structure is prepared in the growth substrate 103, and the superjunction structure includes an n-type semiconductor structure 1031 and a p-type semiconductor structure 1032, and the n-type semiconductor structure 1031 and the p-type semiconductor structure 1032 are alternately distributed along a direction parallel to the growth substrate 103, so as to improve the vertical integration voltage of the device structure formed on the substrate structure.
[0080] Embodiment 3
[0081] Fig.15It is a schematic diagram of the substrate structure prepared by the third embodiment of the present disclosure. The substrate structure and the method for preparing the substrate structure of the third embodiment of the present disclosure are roughly the same as the substrate structure and the method for preparing the substrate structure of any embodiment in the first or second embodiment of the present disclosure, except that the substrate structure also includes a nucleation layer 7 and a buffer layer 9. The nucleation layer 7 is arranged on the side of the growth substrate 103 facing away from the base substrate 101, and the buffer layer 9 is arranged on the side of the nucleation layer 7 facing away from the base substrate 101. The buffer layer 9 can be an n-type buffer layer 9, and of course, it can also be a p-type buffer layer 9. The material of the buffer layer 9 can be a III-V group compound, such as AlN, GaN, AlGaN, AlInGaN, etc. The buffer layer 9 can be formed by epitaxial growth. In other embodiments, the provision of the nucleation layer 7 is optional, that is, the buffer layer 9 can be directly formed on the substrate structure.
[0082] Embodiment 4
[0083] Fig.16 Schematic diagram of the substrate structure prepared by the fourth embodiment of the present disclosure. The substrate structure and the method for preparing the substrate structure of the fourth embodiment of the present disclosure are substantially the same as the substrate structure and the method for preparing the substrate structure of any one of the first to third embodiments of the present disclosure, except that the preparation method may further include: forming a heat dissipation layer 8 covering the inner wall of the groove 104 to further improve the heat dissipation performance of the substrate structure. The material of the heat dissipation layer 8 may be AlN, GaN, AlGaN, AlInGaN, etc. Among them, the heat dissipation layer 8 may be formed by epitaxial growth.
[0084] Embodiment 5
[0085] Fig.17 Schematic diagram of the semiconductor structure of the fifth embodiment of the present disclosure. The semiconductor structure of the fifth embodiment of the present disclosure includes the substrate structure of any one of the first to fourth embodiments of the present disclosure. The semiconductor structure provided in this embodiment is a high electron mobility transistor device, and the semiconductor structure also includes a device structure formed on a growth substrate 103, and the device structure includes a heterojunction structure 2, a gate 3, a source 4, and a drain 5. The heterojunction structure 2 is arranged on the side of the growth substrate 103 facing away from the bottom substrate 101, and the heterojunction structure 2 includes a source region, a drain region, and a gate region located between the source region and the drain region. The gate 3 is located on the gate region. The source 4 is located on the source region. The drain 5 is located on the drain region. The heterojunction structure 2 may include a channel layer 201 and a barrier layer 202. The channel layer 201 is located between the barrier layer 202 and the substrate structure. For a substrate structure provided with a buffer layer 9, the heterojunction structure 2 may be arranged on the buffer layer 9.
[0086] Embodiment 6
[0087] Fig.18: is a schematic diagram of a semiconductor structure of the sixth embodiment of the present disclosure. The semiconductor structure of the sixth embodiment of the present disclosure includes the substrate structure of any one of the first to fourth embodiments of the present disclosure. The semiconductor structure provided in this embodiment is a diode structure, and the semiconductor structure also includes a device structure formed on a growth substrate 103, and the device structure includes a heterojunction structure 2, a first electrode 10, and a second electrode 11. The heterojunction structure 2 is arranged on the side of the growth substrate 103 facing away from the bottom substrate 101; the first electrode 10 and the second electrode 11 are located on the heterojunction structure 2, and the first electrode 10 is in Schottky contact with the heterojunction structure 2, and the second electrode 11 is in ohmic contact with the heterojunction structure 2. The heterojunction structure 2 may include a channel layer 201 and a barrier layer 202. The channel layer 201 is located between the barrier layer 202 and the substrate structure. For a substrate structure provided with a buffer layer 9, the heterojunction structure 2 may be arranged on the buffer layer 9. In other embodiments, the semiconductor structure may also be any one of a high electron mobility transistor device, a vertical power device, a radio frequency device, and a light emitting diode device.
[0088] The above is only a preferred embodiment of the present disclosure and does not limit the present disclosure in any form. Although the present disclosure has been disclosed as a preferred embodiment as above, it is not used to limit the present disclosure. Any technician familiar with this profession can make some changes or modify the technical contents disclosed above into equivalent embodiments without departing from the scope of the technical solution of the present disclosure. However, any simple modification, equivalent change and modification made to the above embodiments based on the technical essence of the present disclosure without departing from the content of the technical solution of the present disclosure are still within the scope of the technical solution of the present disclosure.
Claims
1. A substrate structure, characterized in that: include: A base substrate, an insulating layer and a growth substrate sequentially disposed on the base substrate; A plurality of grooves are provided, wherein the plurality of grooves are opened on a side of the base substrate away from the growth substrate, the plurality of grooves at least partially penetrate the base substrate, and at least two of the plurality of grooves have different depths or opening widths.
2. The substrate structure according to claim 1, characterized in that: The density of the grooves located in the central area of the base substrate is greater than the density of the grooves located in the edge area of the base substrate.
3. The substrate structure according to claim 1, characterized in that: The depths and / or opening widths of the plurality of grooves gradually decrease in a direction from the center to the edge of the base substrate.
4. The substrate structure according to claim 1, characterized in that: The substrate structure includes a plurality of unit areas, each of the unit areas includes at least two sub-unit areas, and each of the sub-unit areas includes at least one groove; In one unit area, the sizes of the grooves in each of the sub-unit areas are different.
5. The substrate structure according to claim 1, characterized in that: The groove includes a first portion located in the base substrate, a second portion located in the insulating layer, and a third portion located in the growth substrate; Wherein, the opening width of the first portion of the groove is greater than the opening widths of the second portion and the third portion.
6. The substrate structure according to claim 5, characterized in that: In a direction from the base substrate to the growth substrate, The opening widths of the first part, the second part and the third part remain unchanged; Or, the opening widths of the first part, the second part and the third part gradually decrease; Or, the opening width of the first part gradually decreases, and the opening width of the third part remains unchanged; Alternatively, the opening width of the first portion remains unchanged, and the opening width of the third portion gradually decreases.
7. The substrate structure according to claim 1, characterized in that: The groove passes through the base substrate and the insulating layer, and the bottom of the groove is located on the surface of the growth substrate close to the base substrate; Or, the groove passes through the base substrate and the insulating layer, and the groove partially passes through the growth substrate; Alternatively, the groove passes through the base substrate, the insulating layer and the growth substrate.
8. The substrate structure according to claim 1, characterized in that: The growth substrate is a super junction structure, and the super junction structure includes an n-type semiconductor structure and a p-type semiconductor structure, and the n-type semiconductor structure and the p-type semiconductor structure are alternately distributed along a direction parallel to the growth substrate.
9. The substrate structure according to claim 1, characterized in that: The substrate structure further comprises: A protection layer is disposed on a side of the base substrate facing away from the growth substrate, wherein the protection layer has openings for exposing the silicon-on-insulator, and the openings correspond to the grooves one by one.
10. The substrate structure according to claim 1, characterized in that: The substrate structure further comprises: The heat dissipation layer covers the inner wall of the groove.
11. A semiconductor structure, characterized in that: include: The substrate structure according to any one of claims 1 to 10; and a device structure formed on the substrate structure, wherein the device structure is located on a side of the growth substrate away from the base substrate, The semiconductor structure is any one of a high electron mobility transistor device, a vertical power device, a radio frequency device and a light emitting diode device.
12. A method for preparing a substrate structure, characterized in that: include: providing a bottom substrate; forming an insulating layer and a growth substrate on the base substrate in sequence; A plurality of grooves are formed on a side of the base substrate away from the growth substrate. The plurality of grooves at least partially penetrate the base substrate. Among the plurality of grooves, at least two grooves have different depths or opening widths.
13. The method for preparing a substrate structure according to claim 12, characterized in that: The depths or opening widths of the plurality of grooves gradually decrease in a direction from the center to the edge of the base substrate.
14. The method for preparing a substrate structure according to claim 12, characterized in that: The density of the grooves located in the central area of the base substrate is greater than the density of the grooves located in the edge area of the base substrate.
15. The method for preparing a substrate structure according to claim 12, characterized in that: The substrate structure includes a plurality of unit areas, each of the unit areas includes at least two sub-unit areas, and each of the sub-unit areas includes at least one groove; In one unit area, the sizes of the grooves in each of the sub-unit areas are different.
16. The method for preparing a substrate structure according to claim 12, characterized in that: The groove includes a first portion located in the base substrate, a second portion located in the insulating layer, and a third portion located in the growth substrate; Wherein, the opening width of the first portion of the groove is greater than the opening widths of the second portion and the third portion.
17. The method for preparing a substrate structure according to claim 16, characterized in that: In a direction from the base substrate to the growth substrate, The opening widths of the first part, the second part and the third part gradually decrease; Or, the opening width of the first part gradually decreases, and the opening width of the third part remains unchanged; Alternatively, the opening width of the first portion remains unchanged, and the opening width of the third portion gradually decreases.
18. The method for preparing a substrate structure according to claim 12, characterized in that: The groove passes through the base substrate and the insulating layer, and the bottom of the groove is located on the surface of the growth substrate close to the base substrate; Or, the groove passes through the base substrate and the insulating layer, and the groove partially passes through the growth substrate; Alternatively, the groove passes through the base substrate, the insulating layer and the growth substrate.
19. The method for preparing a substrate structure according to claim 12, characterized in that: A super junction structure is formed in the growth substrate, wherein the super junction structure includes an n-type semiconductor structure and a p-type semiconductor structure, and the n-type semiconductor structure and the p-type semiconductor structure are alternately distributed along a direction parallel to the growth substrate.
20. The method for preparing a substrate structure according to claim 12, characterized in that: Forming a groove at least partially penetrating the base substrate includes: forming a protective layer on a side of the base substrate facing away from the growth substrate; forming an opening on the protective layer to expose the base substrate; The bottom substrate is etched using the protective layer forming the opening as a mask to form the groove.
21. The method for preparing a substrate structure according to claim 12, characterized in that: After forming a groove on a side of the base substrate away from the growth substrate, the method further comprises: A heat dissipation layer covering an inner wall of the groove is formed in the groove.