Synchronous frequency division method and system applied to navigation chip

Abstract

The invention discloses a synchronous frequency division method and system applied to a navigation chip. The synchronous frequency division system comprises a baseband sub-system, a clock frequency division module and a clock domain conversion module, the clock frequency division module is used for carrying out frequency division processing on a baseband clock to generate frequency division clocks for each functional module of the baseband sub-system; and the clock domain conversion module is used for finishing processing from a baseband clock to a frequency division clock for each functional module in the baseband sub-system. According to the scheme provided by the invention, on the premise that the time service precision requirement is met, the frequency configuration flexibility of each functional module in the navigation chip baseband subsystem is improved, the power consumption of the chip is reduced, and the requirements of various application scenes are met.

Description

Technical Field

[0001] The present invention relates to the technical field of navigation chips, and in particular to a synchronous frequency division method and system applied to navigation chips. Background Art

[0002] With the development of navigation systems, the number of frequencies and satellites that need to be supported in navigation chips has gradually increased, resulting in increasing power consumption of navigation chips. Therefore, there are higher requirements for low-power design of navigation chips in product design. At the same time, there are different power consumption application distinctions for different application scenarios: in consumer or low-cost application scenarios, extreme power consumption reduction design is required; in multi-mode and multi-frequency navigation application scenarios, higher processing performance is required. In traditional navigation chip design, each module in the baseband unit is at the same working clock, which makes the chip application inflexible and increases the power consumption of the chip. Summary of the invention

[0003] In order to solve the technical problem, the embodiments of the present invention provide a synchronous frequency division method and system applied to a navigation chip.

[0004] The technical solution of the embodiment of the present invention is achieved as follows: The embodiment of the present invention provides a synchronous frequency division system applied to a navigation chip, the synchronous frequency division system comprising a baseband subsystem, a clock frequency division module and a clock domain conversion module; the clock frequency division module is used to perform frequency division processing on a baseband clock to generate a frequency division clock for each functional module of the baseband subsystem; the clock domain conversion module is used to complete the processing of the baseband clock to the frequency division clock for each functional module in the baseband subsystem; Among them, the clock division module includes a first clock division module, a second clock division module, a third clock division module, a fourth clock division module and a fifth clock division module; the first clock division module is used to divide the baseband clock to generate a preprocessing clock; the second clock division module is used to divide the baseband clock to generate a capture clock; the third clock division module is used to divide the baseband clock to generate a tracking clock; the fourth clock division module is used to divide the baseband clock to generate an acceleration clock; the fifth clock division module is used to divide the baseband clock to generate an APB clock; wherein the preprocessing clock, the capture clock, the tracking clock, the acceleration clock and the APB clock are in the same clock group as the baseband clock.

[0005] Among them, the clock domain conversion module includes an apb_syn module, a req_syn module and a sdat_syn module; the apb_syn module is used to implement the clock domain conversion processing from the baseband clock to the apb clock for the apb interface; the req_syn module is used to implement the clock domain conversion processing from the baseband clock to the divided clock of each functional module for the req interface; the sdat_syn module is used to implement the clock domain conversion processing from the baseband clock to the divided clock of each functional module for the sampling point interface.

[0006] In one embodiment, the baseband subsystem includes four functional modules, an interface adapter module connected to the functional modules, and an asynchronous clock conversion module, wherein the four functional modules include a data preprocessing module, a capture module, a tracking module, and a baseband accelerator module; the interface adapter module includes an apb distribution interface adapter module, an axi_req conversion interface adapter module, and a req distribution interface adapter module; the asynchronous clock conversion module is used to convert the sampling point clock into a baseband clock; the data preprocessing module is used to perform format conversion, narrowband anti-interference, low-pass filtering, and downsampling processing on the sampling point data; wherein the narrowband anti-interference processing is multi-channel time division multiplexing; the capture module is used to perform preprocessing The processed data is captured to obtain the Doppler frequency and peak code phase of the current satellite; the tracking module is used to perform multi-frequency and multi-channel tracking processing on the capture results; wherein the tracking processing is multi-frequency time division multiplexing; the baseband accelerator module is used to perform hardware accelerated calculations on the fixed computing units required in the navigation and positioning solution process; the apb distribution interface adapter module is used to distribute the connected apb interface to the corresponding functional module in the baseband subsystem; the axi_req conversion interface adapter module is used to convert the connected axi interface into a req interface; the req distribution interface adapter module is used to distribute the converted req interface to the corresponding functional module in the baseband subsystem.

[0007] In one embodiment, the number of the req_syn modules is 3, which are respectively connected to the capture module, the tracking module and the baseband accelerator module, and are respectively used to implement clock domain conversion processing from the baseband clock to the capture clock, the tracking clock and the acceleration clock for the req interface; the number of the dat_syn modules is 2, which are respectively connected to the capture module and the tracking module, and are respectively used to implement clock domain conversion processing from the baseband clock to the capture clock and the tracking clock for the sampling point interface.

[0008] An embodiment of the present invention also provides a synchronous frequency division method applied to a navigation chip, which is applied to the synchronous frequency division system described above. The method includes: using a clock division module to divide the baseband clock to generate a divided clock for each functional module of the baseband subsystem; using a clock domain conversion module to complete the processing of the baseband clock to the divided clock for each functional module in the baseband subsystem.

[0009] In one embodiment, the clock domain conversion module includes an apb_syn module, and the clock domain conversion module is used to complete the processing of the baseband clock to the divided clock for each functional module in the baseband subsystem, including: inputting the apb request, address, type and data of the baseband clock domain into the apb clock domain; detecting the apb request completion signal in the apb clock domain, and after detecting the apb request completion signal, clearing the apb request of the apb clock domain, and synchronizing the apb request completion signal to the baseband clock domain, generating the apb request completion signal of the baseband clock domain, and clearing the request completion signal of the apb clock domain at the same time.

[0010] In one embodiment, the clock domain conversion module includes a req_syn module, and the clock domain conversion module is used to complete the processing of the baseband clock to the divided-frequency clock for each functional module in the baseband subsystem, including: obtaining data in the baseband clock domain, generating a write enable in the baseband clock domain, and writing the data into the cache; updating the write pointer in the baseband clock domain according to the write enable; obtaining a read pointer. According to the write pointer and the read pointer, the combinational logic generates a cache empty signal; when it is determined that the cache is not empty, the combinational logic generates a read cache request; according to the read cache request, the read pointer is updated in the divided-frequency clock; in the divided-frequency clock domain, after judging that the read cache request is valid, the data in the divided-frequency clock domain is output.

[0011] In one embodiment, the clock domain conversion module includes an sdat_syn module, and the clock domain conversion module is used to complete the processing of the baseband clock to the divided frequency clock for each functional module in the baseband subsystem, including: obtaining data in the baseband clock domain, generating a write enable in the baseband clock domain, and writing the data into a cache; updating a write pointer in the baseband clock domain according to the write enable; obtaining a read pointer. According to the write pointer and the read pointer, the combinational logic generates a cache empty signal; when it is determined that the cache is not empty, the combinational logic generates a read cache request; according to the read cache request, the read pointer is updated in the divided frequency clock; in the divided frequency clock domain, after judging that the read cache request is valid, the data in the divided frequency clock domain is output.

[0012] In one embodiment, the divided clock includes a preprocessing clock, a capture clock, a tracking clock, an acceleration clock and an APB clock; the clock division module is used to divide the baseband clock to generate divided clocks for each functional module of the baseband subsystem, including: in a low-power application scenario, the preprocessing clock is configured to be divided by 4, the capture clock is configured to be divided by 4, the tracking clock is configured to be divided by 3, and the baseband accelerator clock is configured to be divided by 2; in a high-performance application scenario, the preprocessing clock is configured to be divided by 2, the capture clock is configured to be divided by 4, the tracking clock is configured to be divided by 1, and the baseband accelerator clock is configured to be divided by 1; in an application scenario with a startup time requirement, the preprocessing clock is configured to be divided by 4, the capture clock is configured to be divided by 1, the tracking clock is configured to be divided by 3, and the baseband accelerator clock is configured to be divided by 2.

[0013] The synchronous frequency division method and system for a navigation chip provided in the embodiments of the present invention can improve the flexibility of the frequency configuration of each module in the baseband subsystem of the navigation chip, reduce the power consumption of the chip, and meet the needs of various application scenarios while meeting the timing accuracy requirements. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 It is a schematic diagram of the structural framework of the baseband subsystem in the prior art; Figure 2 It is a structural schematic diagram of a synchronous frequency division system applied to a navigation chip according to an embodiment of the present invention; Figure 3 It is a schematic diagram of a structural refinement framework of a synchronous frequency division system applied to a navigation chip according to an embodiment of the present invention; Figure 4 The figure is a flow chart of a synchronous frequency division method applied to a navigation chip according to an embodiment of the present invention. DETAILED DESCRIPTION

[0015] Before introducing the solution of this embodiment, the solution in the prior art is first introduced.

[0016] In the baseband subsystem of the navigation chip, there are four main functional modules according to their functions: data preprocessing module, capture module, tracking module, baseband accelerator module; it also includes apb distribution interface adapter module, axi_req conversion interface adapter module, req distribution interface adapter module. In a typical design, except for the asynchronous clock conversion of the sampling point, all other modules work under the standard input baseband clock. The block diagram is as follows Figure 1 As shown: The baseband processing module is mainly divided into four parts: 1. Data preprocessing module, which performs data format conversion, narrowband anti-interference, low-pass filtering, downsampling and other processing. The narrowband anti-interference processing is multi-channel time division multiplexing; 2. Capture module, which captures and processes the navigation signal to obtain the Doppler frequency and peak code phase of the current satellite; 3. Tracking module, which performs multi-frequency and multi-channel tracking processing on the captured results of the navigation signal, and its tracking processing is multi-frequency time division multiplexing; 4. The baseband accelerator module performs hardware acceleration calculations on the fixed computing units required for navigation and positioning solutions.

[0017] The clock is divided into two parts: 1. The sampling point interface uses the sampling point clock domain of 62MHz. After being processed by the asynchronous conversion module, the sampling point interface is converted to a faster baseband clock; 2. The remaining modules all use baseband clocks, and the baseband clock frequency is configured by software according to requirements.

[0018] This design has the following defects: 1. In order to meet the performance of narrowband anti-interference processing in data preprocessing, or the performance of multi-frequency time division multiplexing in tracking processing, or the performance requirements of capture, the baseband clock needs to work at the maximum value of all clock frequencies, resulting in the need to configure a large baseband clock, such as 500MHz; 2. If the data preprocessing module and the tracking module use asynchronous clocks with different frequencies, an additional level of asynchronous clock conversion will be required, which will increase the time uncertainty of the sampling point transmission and reduce the timing accuracy.

[0019] Therefore, when designing a baseband subsystem, using this design method will increase the power consumption of the baseband and reduce the flexibility of system application.

[0020] Based on this, the embodiment of the present invention provides a flexible and configurable synchronous frequency division design scheme, which can improve the flexibility of the frequency configuration of each module in the navigation chip baseband subsystem while meeting the timing accuracy requirements, reduce the power consumption of the chip, and meet the needs of various application scenarios.

[0021] The present invention will be described in further detail below with reference to the accompanying drawings and embodiments.

[0022] The embodiment of the present invention provides a synchronous frequency division system applied to a navigation chip, such as Figure 2 As shown, the synchronous frequency division system 200 includes a baseband subsystem 201, a clock frequency division module 202 and a clock domain conversion module 203; The clock frequency division module 202 is used to perform frequency division processing on the baseband clock to generate a frequency division clock for each functional module of the baseband subsystem 201; The clock domain conversion module 203 is used to complete the processing of the baseband clock to the divided frequency clock for each functional module in the baseband subsystem 201.

[0023] In order to reduce the power consumption of the baseband subsystem 201 in the navigation chip and improve the flexibility of the system application, this embodiment first divides the clock domain for the functional modules of the baseband subsystem 201, introduces a corresponding number of clock frequency division modules 202, and performs corresponding frequency division processing on the baseband clock; then the functional module clock of the baseband subsystem 201 is modified to the clock after each frequency division; finally, the clock domain conversion module 203 of the apb interface, axi interface and sampling point interface is added. The block diagram of the design baseband unit is as follows: Figure 3 shown.

[0024] Specifically, Figure 3 As shown, in one embodiment, the baseband subsystem 201 includes four functional modules, an interface adapter module connected to the functional modules, and an asynchronous clock conversion module, wherein the four functional modules include a data preprocessing module, a capture module, a tracking module, and a baseband accelerator module; the interface adapter module includes an apb distribution interface adapter module, an axi_req conversion interface adapter module, and a req distribution interface adapter module; the asynchronous clock conversion module is used to convert the sampling point clock into a baseband clock; the data preprocessing module is used to perform format conversion, narrowband anti-interference, low-pass filtering, and down-sampling processing on the sampling point data; wherein the narrowband anti-interference processing is multi-channel time division multiplexing; the capture module is used to The pre-processed data is captured to obtain the Doppler frequency and peak code phase of the current satellite; the tracking module is used to perform multi-frequency and multi-channel tracking processing on the capture results; wherein the tracking processing is multi-frequency time division multiplexing; the baseband accelerator module is used to perform hardware accelerated calculations on the fixed computing units required in the navigation and positioning solution process; the apb distribution interface adapter module is used to distribute the connected apb interface to the corresponding functional modules in the baseband subsystem; the axi_req conversion interface adapter module is used to convert the connected axi interface into a req interface; the req distribution interface adapter module is used to distribute the converted req interface to the corresponding functional modules in the baseband subsystem.

[0025] The clock frequency division module includes a first clock frequency division module (i.e. Figure 3 clk_div0 in), the second clock division module, (ie Figure 3 clk_div1 in the third clock division module (i.e. Figure 3 clk_div2 in), the fourth clock division module (i.e. Figure 3 clk_div3 in) and the fifth clock division module (i.e. Figure 3 clk_div4 in (clk_div4); Among them, the first clock division module is used to divide the baseband clock to generate a preprocessing clock; the second clock division module is used to divide the baseband clock to generate a capture clock; the third clock division module is used to divide the baseband clock to generate a tracking clock; the fourth clock division module is used to divide the baseband clock to generate an acceleration clock; the fifth clock division module is used to divide the baseband clock to generate an APB clock; wherein the preprocessing clock, the capture clock, the tracking clock, the acceleration clock and the APB clock are the same clock group as the baseband clock.

[0026] The clock domain conversion module includes an apb_syn module, a req_syn module and a sdat_syn module; the apb_syn module is used to implement clock domain conversion processing from a baseband clock to an apb clock for an apb interface; the req_syn module is used to implement clock domain conversion processing from a baseband clock to a divided clock of each functional module for a req interface; the sdat_syn module is used to implement clock domain conversion processing from a baseband clock to a divided clock of each functional module for a sampling point interface.

[0027] exist Figure 3 In the embodiment, the number of the req_syn modules is 3, which are respectively connected to the capture module, the tracking module and the baseband accelerator module, and are respectively used to implement the clock domain conversion processing from the baseband clock to the capture clock, the tracking clock and the acceleration clock for the req interface; the number of the dat_syn modules is 2, which are respectively connected to the capture module and the tracking module, and are respectively used to implement the clock domain conversion processing from the baseband clock to the capture clock and the tracking clock for the sampling point interface.

[0028] Based on the above structural block diagram, an embodiment of the present invention provides a synchronous frequency division method applied to a navigation chip, which is applied to the above-mentioned synchronous frequency division system, such as Figure 4 As shown, the method includes: Step S1001: using a clock frequency division module to perform frequency division processing on a baseband clock to generate a frequency division clock for each functional module of the baseband subsystem; Step S1002: using a clock domain conversion module to complete the processing of the baseband clock to the divided frequency clock for each functional module in the baseband subsystem.

[0029] The design method of synchronous frequency division in the navigation chip proposed in this embodiment introduces the idea of ​​synchronous frequency division into the baseband unit, uses different frequency division clocks for each module, and includes the following key technologies: 1. Analyze the operating frequency requirements of each baseband module, divide the clock domain of the baseband unit, and introduce the corresponding divider to generate the divided clock of each module from the input baseband clock; 2. For the internal apb interface transmission path, the apb_syn module is introduced to solve the synchronous clock domain conversion of the apb interface from the baseband clock to the divided clock; 3. For the internal axi interface transmission path, the axi_req_syn module is introduced to solve the clock domain conversion of the axi interface from the baseband clock to the divided clock; 4. For the transmission path of the baseband sampling point, the sdat_syn module is introduced to synchronize the different frequency division clocks of the baseband clock; 5. In the back-end design, the different frequency-divided clocks generated by the baseband clock are set in the same clock domain for timing convergence and analysis to meet the requirements of synchronous clock; 6. On the application side, the firmware configures different frequency division coefficients for each baseband module according to different scenarios, achieving the ultimate power consumption reduction goal while meeting the application scenarios.

[0030] The synchronous frequency division design method proposed in this embodiment can reduce the power consumption of the chip and provide flexibility in system application while meeting application requirements.

[0031] This embodiment innovatively introduces four modules based on the traditional design: 1. Add five clock division modules, all of which have baseband clock as input and generate five clocks as output: preprocessing clock, capture clock, tracking clock, accelerator clock, and apb clock. These five clocks and the baseband clock are in the same clock group, and timing convergence and analysis are performed according to the synchronous clock. The coefficients of the five clock divisions are software configured, and the configuration range is 1 to 16 divisions. After generating five clocks, modify the working clock of each functional module to the corresponding divided clock, so that each functional module can work at different frequencies. At the same time, each functional module is in a clock group, which is a synchronous clock domain.

[0032] 2. For the apb interface, the apb_sync module is introduced to complete the conversion of the apb interface from the baseband clock to the apb clock.

[0033] The processing flow is divided into 5 parts: 1. Since the source clock domain and the destination clock domain are in the same clock group, the apb request of the source clock can be directly output to the destination clock domain; 2. In the destination clock domain, the combinational logic is used to detect whether the request of the destination apb interface is completed; 3. After detecting that the request of the destination apb interface is completed, a request completion signal is generated. This signal is a level signal under the destination clock domain and will not be self-cleared; at the same time, the apb request output by the destination clock domain is cleared to indicate that the request transmission of the destination apb interface has been completed; 4. Synchronize the apb request completion signal of the destination clock domain to the source clock domain to generate the request completion signal of the source apb interface. Because the source clock and the destination clock are in the same clock group, the synchronization here is directly processed by sampling across clock domains; 5. After the request of the source apb interface is completed, the request completion signal of the destination clock domain is cleared, and the apb request processing of the source clock domain is completed.

[0034] That is, in one embodiment, the clock domain conversion module includes an apb_syn module, and the clock domain conversion module is used to complete the processing of the baseband clock to the divided clock for each functional module in the baseband subsystem, including: inputting the apb request, address, type and data of the baseband clock domain into the apb clock domain; detecting the apb request completion signal in the apb clock domain, and after detecting the apb request completion signal, clearing the apb request of the apb clock domain, and synchronizing the apb request completion signal to the baseband clock domain, generating the apb request completion signal of the baseband clock domain, and clearing the request completion signal of the apb clock domain at the same time.

[0035] This processing can realize the clock domain conversion of the APB interface in the synchronous clock domain with extremely small logic resources and extremely high APB conversion efficiency, and has extremely strong promotion value.

[0036] 3. For the req interface, the req_sync module is introduced to complete the conversion of the req interface from the baseband clock domain to each destination clock domain.

[0037] The processing flow is divided into 6 parts: 1. For the input data of the source clock domain, determine whether the data is valid under the source clock. If it is valid, generate the write enable of the source clock domain and write the data into the cache. The cache is a register array under the source clock, and the depth can be configured to 2, so as to realize data cache processing with minimal resources; 2. When the write enable is determined to be valid, the write pointer is cumulatively updated in the source clock domain. To ensure the consistency of the write pointer and the write cache data, the write pointer register operates in the source clock domain; 3. According to the write pointer and the read pointer, the cache empty signal flag is obtained through combinatorial logic calculation. The write pointer is the register in the source clock domain, and the read pointer is the register in the destination clock domain. The two clocks are in the same clock group and are in a synchronous relationship. Combinatorial logic calculation can be performed directly without causing problems such as metastable states. 4. When it is determined that the cache is not empty, a cache read request is generated through combinational logic; 5. According to the read request, the read pointer is cumulatively updated in the destination clock domain. To ensure the consistency of the read pointer and the read cache data, the read pointer register works in the destination clock domain; 6. In the destination clock domain, after judging that the read request is valid, the data corresponding to the read pointer is read from the cache and output. The write operation of the cache is in the source clock domain, and the read operation is in the destination clock domain. The two clocks are in the same clock group and are synchronous. Therefore, the cache can be read directly in the destination clock domain without causing problems such as metastability.

[0038] That is, in one embodiment, the clock domain conversion module includes a req_syn module, and the clock domain conversion module is used to complete the processing of the baseband clock to the divided frequency clock for each functional module in the baseband subsystem, including: obtaining data in the baseband clock domain, generating a write enable in the baseband clock domain, and writing the data into the cache; updating the write pointer in the baseband clock domain according to the write enable; obtaining the read pointer. According to the write pointer and the read pointer, the combinational logic generates a cache empty signal; when it is determined that the cache is not empty, the combinational logic generates a read cache request; according to the read cache request, the read pointer is updated under the divided frequency clock; in the divided frequency clock domain, after judging that the read cache request is valid, the data in the divided frequency clock domain is output.

[0039] This processing utilizes the synchronization characteristics of the source clock domain and the destination clock domain, and can realize data conversion between the two clocks with extremely small cache and extremely small conversion delay, thereby improving the efficiency of clock domain conversion and avoiding the uncertainty caused by clock domain conversion. It has extremely strong promotion value.

[0040] Fourth, for the sampling point interface, the sdat_sync module is introduced to complete the conversion of the sampling point interface from the baseband clock domain to each destination clock domain. Its processing flow is consistent with that of the req_sync module.

[0041] That is, in one embodiment, the clock domain conversion module includes an sdat_syn module, and the clock domain conversion module is used to complete the processing of the baseband clock to the divided frequency clock for each functional module in the baseband subsystem, including: obtaining data in the baseband clock domain, generating a write enable in the baseband clock domain, and writing the data into the cache; updating the write pointer in the baseband clock domain according to the write enable; obtaining the read pointer. According to the write pointer and the read pointer, the combinational logic generates a cache empty signal; when it is determined that the cache is not empty, the combinational logic generates a read cache request; according to the read cache request, the read pointer is updated under the divided frequency clock; in the divided frequency clock domain, after judging that the read cache request is valid, the data in the divided frequency clock domain is output.

[0042] Based on the above design, when the chip is used, the software configures the frequency division coefficient of each clock domain according to different scenarios. Refer to the following scenarios: 1. For low-power application scenarios, the baseband clock is 500M, the preprocessing clock is configured as 4-division, the clock is 125M; the capture clock is configured as 4-division 125M; the tracking clock is configured as 3-division 167M, and the baseband accelerator clock is configured as 2-division 250M; at this time, the working clock of each module is the minimum value that meets the requirements, achieving the goal of reducing power consumption; 2. For high-performance application scenarios, the baseband clock is 500M, the preprocessing clock is configured as 2-division, the clock is 250M; the capture clock is configured as 4-division 125M; the tracking clock is configured as 1-division 500M, and the baseband accelerator clock is configured as 1-division 500M. Under the premise of meeting the tracking performance, the power consumption of the capture module can be reduced; 3. For application scenarios with high requirements for startup time, the baseband clock is 500M, the preprocessing clock is configured as 4-division, the clock is 125M; the capture clock is configured as 1-division 500M; the tracking clock is configured as 3-division 167M, and the baseband accelerator clock is configured as 2-division 250M. On the premise of meeting the requirements for fast satellite capture, the capture module is configured to the maximum operating clock frequency, and the operating frequencies of other modules are reduced to reduce the power consumption of the chip.

[0043] That is, in one embodiment, the divided clock includes a preprocessing clock, a capture clock, a tracking clock, an acceleration clock and an APB clock; the clock division module is used to divide the baseband clock to generate divided clocks for each functional module of the baseband subsystem, including: in a low-power application scenario, the preprocessing clock is configured to be divided by 4, the capture clock is configured to be divided by 4, the tracking clock is configured to be divided by 3, and the baseband accelerator clock is configured to be divided by 2; in a high-performance application scenario, the preprocessing clock is configured to be divided by 2, the capture clock is configured to be divided by 4, the tracking clock is configured to be divided by 1, and the baseband accelerator clock is configured to be divided by 1; in an application scenario with a startup time requirement, the preprocessing clock is configured to be divided by 4, the capture clock is configured to be divided by 1, the tracking clock is configured to be divided by 3, and the baseband accelerator clock is configured to be divided by 2.

[0044] In summary, the design method of introducing synchronous frequency division for the baseband subsystem in the navigation chip can reduce the working clock frequency of some modules under the premise of meeting the different frequency requirements of the working clock of each module in various scenarios, thereby reducing the power consumption of the chip; at the same time, because the working clocks of each module are synchronized, it can also solve the uncertainty of the transmission of sampling points between different modules, thereby ensuring the timing accuracy. Therefore, this method has great promotion value in the design of navigation chips.

[0045] It should also be noted that the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, commodity or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, commodity or device. In the absence of more restrictions, the elements defined by the sentence "comprises a ..." do not exclude the existence of other identical elements in the process, method, commodity or device including the elements.

[0046] The above are only embodiments of the present application and are not intended to limit the present application. For those skilled in the art, the present application may have various changes and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application should be included within the scope of the claims of the present application.

Claims

1. A synchronous frequency division system applied to a navigation chip, characterized in that: The synchronous frequency division system includes a baseband subsystem, a clock frequency division module and a clock domain conversion module; The clock frequency division module is used to perform frequency division processing on the baseband clock to generate frequency division clocks for each functional module of the baseband subsystem; The clock domain conversion module is used to complete the processing of the baseband clock to the divided frequency clock for each functional module in the baseband subsystem; Wherein, the clock frequency division module includes a first clock frequency division module, a second clock frequency division module, a third clock frequency division module, a fourth clock frequency division module and a fifth clock frequency division module; The first clock frequency division module is used to perform frequency division processing on the baseband clock to generate a preprocessing clock; the second clock frequency division module is used to perform frequency division processing on the baseband clock to generate a capture clock; the third clock frequency division module is used to perform frequency division processing on the baseband clock to generate a tracking clock; the fourth clock frequency division module is used to perform frequency division processing on the baseband clock to generate an acceleration clock; the fifth clock frequency division module is used to perform frequency division processing on the baseband clock to generate an apb clock; wherein the preprocessing clock, the capture clock, the tracking clock, the acceleration clock and the apb clock are in the same clock group as the baseband clock; Wherein, the clock domain conversion module includes an apb_syn module, a req_syn module and a sdat_syn module; The apb_syn module is used to implement clock domain conversion processing from baseband clock to apb clock for the apb interface; The req_syn module is used to implement clock domain conversion processing from the baseband clock to the divided clock of each functional module for the req interface; The sdat_syn module is used to implement clock domain conversion processing from the baseband clock to the divided clocks of each functional module for the sampling point interface.

2. The synchronous frequency division system for navigation chip according to claim 1, characterized in that: The baseband subsystem includes four functional modules, an interface adapter module connected to the functional modules, and an asynchronous clock conversion module. The four functional modules include a data preprocessing module, a capture module, a tracking module, and a baseband accelerator module; the interface adapter module includes an apb distribution interface adapter module, an axi_req conversion interface adapter module, and a req distribution interface adapter module; The asynchronous clock conversion module is used to convert the sampling point clock into a baseband clock; The data preprocessing module is used to perform format conversion, narrowband anti-interference, low-pass filtering and down-sampling processing on the sampling point data; wherein the narrowband anti-interference processing is multi-channel time division multiplexing; The capture module is used to capture the preprocessed data to obtain the Doppler frequency and peak code phase of the current satellite; The tracking module is used to perform multi-frequency and multi-channel tracking processing on the capture results; wherein the tracking processing is multi-frequency time division multiplexing; The baseband accelerator module is used to perform hardware accelerated calculations on fixed computing units required in the navigation and positioning solution process; The apb distribution interface adapter module is used to distribute the accessed apb interface to the corresponding functional module in the baseband subsystem; The axi_req conversion interface adapter module is used to convert the connected axi interface into a req interface; The req distribution interface adaptation module is used to distribute the converted req interface to the corresponding functional module in the baseband subsystem.

3. The synchronous frequency division system for navigation chip according to claim 2, characterized in that: The number of the req_syn modules is 3, which are respectively connected to the capture module, the tracking module and the baseband accelerator module, and are respectively used to implement clock domain conversion processing from the baseband clock to the capture clock, the tracking clock and the acceleration clock for the req interface; The number of the dat_syn modules is two, which are connected to the capture module and the tracking module respectively, and are used to implement clock domain conversion processing from the baseband clock to the capture clock and the tracking clock for the sampling point interface respectively.

4. A synchronous frequency division method applied to a navigation chip, characterized in that: The synchronous frequency division system applied to any one of claims 1 to 3, the method comprising: Using a clock frequency division module to perform frequency division processing on the baseband clock to generate a frequency division clock for each functional module of the baseband subsystem; The clock domain conversion module is used to complete the processing of the baseband clock to the divided frequency clock for each functional module in the baseband subsystem.

5. The synchronous frequency division method applied to a navigation chip according to claim 4, characterized in that: The clock domain conversion module includes an apb_syn module, and uses the clock domain conversion module to complete the processing of the baseband clock to the divided frequency clock for each functional module in the baseband subsystem, including: Input the apb request, address, type and data of the baseband clock domain to the apb clock domain; An apb request completion signal is detected in the apb clock domain. After the apb request completion signal is detected, the apb request of the apb clock domain is cleared, and the apb request completion signal is synchronized to the baseband clock domain to generate the apb request completion signal of the baseband clock domain, and the request completion signal of the apb clock domain is cleared at the same time.

6. The synchronous frequency division method for a navigation chip according to claim 4, characterized in that: The clock domain conversion module includes a req_syn module, and uses the clock domain conversion module to complete the processing of the baseband clock to the divided frequency clock for each functional module in the baseband subsystem, including: Acquire data in a baseband clock domain, generate a write enable in the baseband clock domain, and write the data into a cache; According to the write enable, updating the write pointer in the baseband clock domain; Obtain a read pointer, and generate a cache empty signal by combining logic according to the write pointer and the read pointer; When it is determined that the cache is not empty, the combinational logic generates a cache read request; According to the read cache request, updating the read pointer under the divided clock; In the frequency-divided clock domain, after determining that the read cache request is valid, the data in the frequency-divided clock domain is output.

7. The synchronous frequency division method for a navigation chip according to claim 4, characterized in that: The clock domain conversion module includes an sdat_syn module, and uses the clock domain conversion module to complete the processing of the baseband clock to the divided frequency clock for each functional module in the baseband subsystem, including: Acquire data in a baseband clock domain, generate a write enable in the baseband clock domain, and write the data into a cache; According to the write enable, updating the write pointer in the baseband clock domain; Obtain a read pointer, and generate a cache empty signal by combining logic according to the write pointer and the read pointer; When it is determined that the cache is not empty, the combinational logic generates a cache read request; According to the read cache request, updating the read pointer under the divided clock; In the frequency-divided clock domain, after determining that the read cache request is valid, the data in the frequency-divided clock domain is output.

8. The synchronous frequency division method applied to a navigation chip according to claim 4, characterized in that: The frequency-divided clock includes a preprocessing clock, a capture clock, a tracking clock, an acceleration clock and an apb clock; The clock frequency division module is used to perform frequency division processing on the baseband clock to generate the frequency division clock for each functional module of the baseband subsystem, including: In low-power application scenarios, configure the preprocessing clock to be divided by 4, the capture clock to be divided by 4, the tracking clock to be divided by 3, and the baseband accelerator clock to be divided by 2; In high-performance application scenarios, configure the preprocessing clock to be divided by 2, the capture clock to be divided by 4, the tracking clock to be divided by 1, and the baseband accelerator clock to be divided by 1; In application scenarios with startup time requirements, configure the preprocessing clock to be divided by 4, the capture clock to be divided by 1, the tracking clock to be divided by 3, and the baseband accelerator clock to be divided by 2.

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