Encryption module, scrambling timestamp generation method and ultra-bandwidth communication system
By reducing the clock frequency of the AES-128 encryption module and increasing the random waiting time, combined with the generation of masquerading AES codewords, the problems of power consumption peak and bypass attack in the UWB system are solved, and the stability and security of the system are improved.
Patent Information
- Application Number
- CN202411512179.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-10-28
- Publication Date
- 2025-02-07
AI Technical Summary
The high clock frequency and periodic encryption operation of the STS part in the existing UWB system lead to peak power consumption, which is easily exploited by bypass attacks, affecting system stability and security.
By reducing the clock frequency of the AES-128 encryption module, increasing the random wait time, and performing fake AES codeword generation during each round of STS codeword output/match, confusing power consumption changes.
It significantly improves the resistance of UWB's STS system to bypass attacks, avoids power consumption peaks, and improves the stability and security of the system.
Smart Images
Figure CN119402856A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of ultra-wideband communication, and in particular to an encryption module, a method for generating a scrambled timestamp, and an ultra-wideband communication system. Background Art
[0002] Ultra-Wideband (UWB) is a short-range wireless communication technology that features high data rate, low power consumption and high positioning accuracy. With the rapid development of wireless communication technology, UWB technology has been widely used in the fields of Internet of Things, smart home, industrial automation and medical treatment.
[0003] Scrambled Timestamp Sequence (STS) is a key technology introduced by 802.15.4z. It is generated by using the symmetric encryption algorithm AES-128 (Advanced Encryption Standard) with a 128-bit key length and a deterministic random bit generator (DRBG). The introduction of STS improves the security and time synchronization accuracy in UWB communication. Figure 1 The figure shows the location of STS in the UWB packet. In 802.15.4z, the process of generating STS codewords in the UWB system is as follows: Figure 2 As shown, StsVCounter and the 32-bit counter constitute the lower 32 bits of the AES plaintext, StsVUpper96 is the upper 96 bits of the AES plaintext, and the AES plaintext and the 128-bit StS Key perform AES-128 operations to obtain a 128-bit pseudo-random number for the transmission / reception process. The 128-bit pseudo-random number can also be called an AEC-128 codeword. Usually, multiple rounds of STS codewords are generated continuously in one round of UWB transmission / reception. During the multiple rounds of generation, StsVUpper96, StsVCounter and Sts Key will not change, and the 32-bit counter will advance by 1 before the next round of codeword generation, thereby achieving the purpose of deterministic randomness. The processing flow of the UWB system for STS is as follows: Figure 3As shown, the 128-bit pseudo-random number is processed by an extended increment function to generate an extended code chip (512 chips) for STS as the basic STS data. The STS segment consists of multiple 512 chips units, and the STS segments are separated by "Gap". Gap represents the time interval without signal transmission, which is intended to avoid inter-symbol interference and increase signal randomness. Since the UWB limit pulse repetition frequency (PRF) is as high as 499.2MHz under the 802.15.4z regulation, this will make the overall clock frequency of the UWB transmission layer higher, which will pose a greater challenge to the design stability of the low-cost old process. The STS part has to perform an AES operation once for every 128-bit transmission, which will bring about a large instantaneous power consumption, causing the power consumption of the entire system to change periodically with an obvious peak value. This power consumption change will affect the system stability and transmission security. At the same time, the periodically changing peak power consumption can be easily exploited by side-channel attacks. Summary of the invention
[0004] In view of some or all of the problems in the prior art, the present invention provides an encryption module in a first aspect, comprising:
[0005] A calculation submodule, which is used to generate an AES codeword based on the AES plaintext and the key;
[0006] A counting submodule, which is used to determine the number of times the AES code word is generated;
[0007] a control submodule, which is used to control the calculation submodule to control the AES codeword generation time; and
[0008] The synchronization submodule is used for clock synchronization between the encryption module and other modules.
[0009] Furthermore, the clock frequency of the encryption module is lower than 500 MHz.
[0010] Furthermore, controlling the AES codeword generation time includes:
[0011] After detecting the STS segment interval, wait for a random time length and control the calculation submodule to start generating AES code words.
[0012] Furthermore, the control submodule is also used for:
[0013] Determine whether the remaining time of the previous round of codeword output is greater than the time required to generate a round of AES codewords. If greater, control the calculation submodule to generate the next round of AES codewords or disguised AES codewords.
[0014] Based on the encryption module as described above, the second aspect of the present invention provides a method for generating a scrambled timestamp, comprising:
[0015] After the STS interval is generated, wait for a random time and generate a round of AES codewords through the encryption module;
[0016] Processing the AES codeword by an STS codeword output / matching module to form an STS codeword;
[0017] Wait for a random time, generate an AES codeword again, and form an STS code chip, repeat this step multiple times to obtain multiple STS code chips; and
[0018] The multiple STS code chips are grouped into an STS segment and inserted into an STS interval to form a scrambled time stamp.
[0019] Furthermore, the generation method further comprises:
[0020] During the formation of the STS code chip, a random number of pseudo AES codewords are generated.
[0021] Furthermore, the generation method further comprises:
[0022] The AES codeword is sent to the STS codeword output / matching module through the synchronization submodule.
[0023] Furthermore, the generation method further comprises:
[0024] Before generating an AES codeword, determine whether the remaining time meets the time required to generate one round of AES codewords.
[0025] Based on the generation method as described above, the third aspect of the present invention provides an ultra-wideband communication system, which adopts the generation method of the scrambled timestamp as described above.
[0026] The present invention provides an encryption module, a method for generating a scrambled timestamp, and an ultra-wideband communication system. By increasing the random waiting time, the encryption process loses its periodicity and no longer matches the codeword period. The disguised codeword can confuse the power consumption changes of the entire STS process. At the same time, due to the extension of a single encryption cycle, the AES-128 encryption module will not have an obvious power consumption peak. These changes significantly improve the UWB STS system's resistance to side-channel attacks and the stability of the entire system. BRIEF DESCRIPTION OF THE DRAWINGS
[0027] To further illustrate the above and other advantages and features of various embodiments of the present invention, a more specific description of various embodiments of the present invention will be presented with reference to the accompanying drawings. It will be understood that these drawings only depict typical embodiments of the present invention and are therefore not to be considered as limiting the scope thereof. In the accompanying drawings, for clarity, identical or corresponding parts will be represented by identical or similar reference numerals.
[0028] Figure 1Shows the location of the STS defined in the 802.15.4z protocol in the UWB packet;
[0029] Figure 2 A schematic diagram showing a process of generating STS codewords in a UWB system defined in the 802.15.4z protocol;
[0030] Figure 3 A schematic diagram showing the processing flow of the UWB system for STS defined in the 802.15.4z protocol;
[0031] Figure 4 A schematic diagram of a partial process of the UWB system STS based on the 802.15.4z protocol in the prior art is shown;
[0032] Figure 5 A timing diagram of the STS part of the UWB system based on the 802.15.4z protocol in the prior art is shown;
[0033] Figure 6 A schematic diagram showing the structure of an encryption module according to an embodiment of the present invention;
[0034] Figure 7 A schematic diagram showing a flow chart of a method for generating a scrambled timestamp according to an embodiment of the present invention; and
[0035] Figure 8 A schematic diagram showing a timing diagram of generating a scrambled timestamp according to an embodiment of the present invention. DETAILED DESCRIPTION
[0036] In the following description, the present invention is described with reference to various embodiments. However, those skilled in the art will recognize that various embodiments can be implemented without one or more specific details or with other replacement and / or additional methods, materials or components. In other cases, well-known structures, materials or operations are not shown or described in detail to avoid blurring the inventive point of the present invention. Similarly, for the purpose of explanation, specific quantities, materials and configurations are set forth to provide a comprehensive understanding of embodiments of the present invention. However, the present invention is not limited to these specific details. In addition, it should be understood that the various embodiments shown in the drawings are illustrative representations and are not necessarily drawn in correct proportions.
[0037] In this specification, reference to "one embodiment" or "the embodiment" means that a particular feature, structure, or characteristic described in conjunction with the embodiment is included in at least one embodiment of the present invention. The phrase "in one embodiment" appearing in various places in this specification does not necessarily all refer to the same embodiment.
[0038] In the present application, the term "configuration" refers to the setting of the shape, structure, material and / or function of the target object to achieve the desired technical effect, wherein "configuration" includes a variety of alternative technical means for achieving the technical effect, which become obvious under the teaching of the present application.
[0039] In current application scenarios such as car smart keys and anti-lost device positioning, the security can be improved by adding the STS mechanism, but security attacks against this mechanism are also inevitable. As a non-invasive general attack method, the side-channel attack (SCA) poses a huge challenge to current security-focused systems. A side-channel attack is a cryptanalysis attack method that does not directly target the mathematical structure of the encryption algorithm, but infers keys or other sensitive information by monitoring and analyzing the physical characteristics of the encryption device when performing encryption operations. The AES-128 encryption used by the STS sequence can easily identify characteristics through power consumption and time, thereby inferring sensitive data such as keys. Specifically, Figure 4 The following is a flow chart of the STS part of the UWB system based on the 802.15.4z protocol in the prior art. In this process, the AES-128 encryption module runs at the same clock frequency as the rest of the UWB system. Under the usual pipeline scheme, a set of 128-bit codewords only takes less than 20 clock cycles to generate, which is much smaller than the 512 cycles required for the STS Gap interval and each chip unit. Figure 5 This is a rough timing diagram of the above process. Since the AES-128 encryption module only works in the codeword generation phase, this will cause the power consumption of the entire system to change periodically with obvious peaks. The periodically changing peak power consumption can be easily exploited by side-channel attacks, thus making the introduction of STS for security purposes ineffective.
[0040] For high-security or old process scenarios, the present invention optimizes the key modules of the STS generation part to improve the stability and security of the STS part. Specifically, the AES-128 encryption module is modified to avoid side-channel attacks on the STS sequence and improve the security and stability of the system. The changes are mainly reflected in the following points: reducing the clock frequency of the AES-128 encryption module to extend the time required for a single encryption; adding a random waiting time before starting each AES-128 encryption; and performing a random number of disguised AES-128 codeword generation during each round of STS codeword output / matching.
[0041] The technical solution of the present invention is further described below in conjunction with the accompanying drawings of the embodiments.
[0042] Figure 6 FIG. 2 is a schematic diagram showing the structure of an encryption module according to an embodiment of the present invention. Figure 6 As shown, an encryption module includes a calculation submodule 601, a counting submodule 602, a control submodule 603 and a synchronization submodule 604. The calculation submodule 601 is used to generate an AES codeword based on an AES plaintext and a key, the counting submodule 602 is used to record the number of times the AES codeword is generated, the control submodule 603 is used to control the calculation submodule to control the AES codeword generation time, and the synchronization submodule 604 performs clock synchronization between the encryption module and other modules.
[0043] The calculation submodule 601 is basically the same as the AES-128 codeword generation method in the prior art, and can be implemented, for example, by a deterministic random bit generator (DRBG). Figure 2 As shown, phyHrpUwbStsVCounter and the counting submodule 602 constitute the lower 32 bits of the AES plaintext, phyHrpUwbStsVUpper96 is used as the upper 96 bits of the AES plaintext, and the 128-bit AES plaintext (Value V) and the 128-bit phyHrpUwbStsKey perform AES-128 operations to obtain 128-bit ciphertext, i.e., the AES codeword. Usually, multiple rounds of STS codewords are continuously generated in one round of UWB transmission / reception, and the counting submodule 602 advances by 1 before the next round of codeword generation, thereby achieving the purpose of deterministic randomness. The counting submodule 602 is a 32-bit counter.
[0044] As mentioned above, in an embodiment of the present invention, in order to make the encryption process not match the codeword period and lose periodicity, a random waiting time is added before each start of AES-128 encryption. In addition, in one embodiment of the present invention, a random number of disguised AES codewords are generated. In order to achieve the above purpose, in an embodiment of the present invention, a control submodule 603 is added to the encryption module. The control submodule 603 is used to control when to start calculating and generating AES codewords and / or disguised AES codewords. Specifically, in one embodiment of the present invention, after detecting the STS segment interval, the control submodule 603 waits for a random time, and then controls the calculation submodule to start generating AES codewords. The actual market should not be greater than the difference between the remaining time of the previous round of codeword output and the time required for generating AES codewords in one round. If the remaining time of the previous round of codeword output is not enough for a round of AES codeword generation, wait until the previous round of codeword output ends and then re-judge. In another embodiment of the present invention, if the above conditions can still be met after the first AES codeword output in each STS code chip unit is completed, the generation of disguised codewords is allowed. In an embodiment of the present invention, the length of the random duration should ensure that at least one AES codeword is generated during each STS codeword processing period. In addition, since the processing time of the encryption module for a single round of codewords is relatively fixed, when the remaining time after the STS codeword output / matching module processes the current codeword is insufficient for generating a disguised codeword, a signal needs to be sent to the encryption module to keep the encryption module waiting. At the same time, when the disguised codeword is generated, the write enable should be disabled to prevent it from being transmitted to the asynchronous FIFO for output, that is, the synchronization submodule 604.
[0045] As mentioned above, in order to avoid obvious power consumption peaks, in an embodiment of the present invention, the cycle of a single encryption is lengthened, which is mainly achieved by reducing the clock frequency of the encryption module. The codeword output of the encryption module after frequency reduction needs to be synchronized with the rest of the STS through an asynchronous FIFO. That is, in the subsequent STS code chip generation process, the AES codeword generated by the encryption module needs to be transmitted from the slow clock domain of the encryption module to the fast clock domain of other STS modules. To achieve this purpose, in an embodiment of the present invention, the synchronization submodule 604 is provided in the encryption module. In one embodiment of the present invention, the AES codeword is transmitted from the synchronization submodule to the STS codeword output / matching module using a two-stage synchronizer. The signal used for status notification from the fast clock domain to the slow clock domain is guaranteed by the state signal of the finite state machine of the entire STS process, wherein the state signal is a level signal, not a pulse signal. In one embodiment of the present invention, the clock frequency of the encryption module is lower than the clock frequency of other STS modules, for example, lower than the clock frequency of the UWB transmitting module. Typically, the clock frequency of the UWB transmitting module can reach 500 MHz, so the clock frequency of the encryption module should be lower than 500 MHz, preferably, lower than 100 MHz.
[0046] Based on the encryption module as described above, Figure 7 A schematic diagram showing a flow chart of a method for generating a scrambled timestamp according to an embodiment of the present invention is shown. Figure 7 As shown, a method for generating a scrambled timestamp includes:
[0047] After the encryption module detects the STS interval, it waits for a random time and generates a round of AES codewords, wherein the clock frequency of the encryption module is lower than that of the STS codeword output / matching module;
[0048] The AES codeword is processed by the STS codeword output / matching module to form an STS codeword. Since the encryption module clock frequency is lower than that of the STS codeword output / matching module, the AES codeword needs to be sent to the STS codeword output / matching module through the synchronization submodule;
[0049] After the STS codeword is processed, it is fed back to the encryption module, and the value of the counting submodule of the encryption module is increased by one. At the same time, it is determined whether the current STS segment has ended. If it has not ended, it waits for a random time again, generates an AES codeword, and sends it to the STS codeword output / matching module through the synchronization submodule to form an STS code piece until the STS segment ends. In one embodiment of the present invention, during the STS codeword output / matching period, if there is sufficient time left, a random number of disguised AES codewords can be generated; and
[0050] Finally, multiple STS code chips are combined into an STS segment and inserted into the STS interval to form a scrambled timestamp, ending the STS process.
[0051] The present invention also provides an ultra-wideband communication system, which includes the encryption module as described above, and uses the generation method as described above to generate a scrambled timestamp.
[0052] Figure 8 FIG. 2 is a schematic diagram showing a timing diagram of generating a scrambled timestamp according to an embodiment of the present invention. Figure 8 As shown, according to the encryption module and the method for generating the scrambled timestamp described in the embodiments of the present invention, the encryption process can lose its periodicity and no longer match the codeword period. The disguised codeword can confuse the power consumption changes of the entire STS process. At the same time, due to the extension of the single encryption cycle, the AES-128 encryption module will not have an obvious power consumption peak. These changes significantly improve the resistance of the UWB STS system to side-channel attacks and the stability of the entire system.
[0053] Although various embodiments of the present invention are described above, it should be understood that they are presented as examples only and not as limitations. It is obvious to those skilled in the relevant art that various combinations, modifications and changes can be made thereto without departing from the spirit and scope of the present invention. Therefore, the breadth and scope of the present invention disclosed herein should not be limited by the exemplary embodiments disclosed above, but should only be defined according to the attached claims and their equivalents.
Claims
1. An encryption module, characterized in that: include: A calculation submodule, configured to generate an AES codeword based on the AES plaintext and the key; A counting submodule, configured to record the number of times the AES codeword is generated; A control submodule, configured to control the calculation submodule to control the AES codeword generation time; as well as The synchronization submodule is configured to synchronize the clocks of the encryption module with those of other modules.
2. The encryption module according to claim 1, wherein: The clock frequency of the encryption module is lower than 500 MHz.
3. The encryption module according to claim 1, wherein: The clock frequency of the encryption module is lower than 100 MHz.
4. The encryption module according to claim 1, wherein: Controlling the AES codeword generation time includes: After detecting the STS segment interval, wait for a random time; and The calculation submodule is controlled to start generating AES code words.
5. The encryption module according to claim 1, wherein: The control submodule is further configured as follows: Determine whether the remaining time of the previous round of codeword output is greater than the time required to generate a round of AES codewords. If so, control the calculation submodule to generate the next round of AES codewords or disguised AES codewords.
6. A method for generating a scrambled timestamp, characterized in that: Includes steps: After the STS interval starts, wait for a random time and generate a round of AES codewords through the encryption module, wherein the clock frequency of the encryption module is lower than that of the STS codeword output / matching module; Processing the AES codeword by an STS codeword output / matching module to form an STS codeword; Wait for a random time, generate AES codeword again, and form STS code chips. Repeat this step multiple times to obtain multiple STS code chips. as well as The multiple STS code chips are grouped into an STS segment and inserted into an STS interval to form a scrambled time stamp.
7. The generation method according to claim 6, characterized in that: Also includes the steps: During the formation of the STS code chip, a random number of pseudo AES codewords are generated.
8. The generation method according to claim 6, characterized in that: Also includes the steps: The AES codeword is sent to the STS codeword output / matching module through the synchronization submodule.
9. The generation method according to claim 7, characterized in that: Also includes the steps: Before generating an AES codeword, determine whether the remaining time meets the time required to generate one round of AES codewords.
10. An ultra-wideband communication system, characterized in that: The scrambled timestamp is generated by using the scrambled timestamp generation method as described in any one of claims 6 to 9.