Heterojunction bipolar transistor and preparation method thereof

Abstract

The invention discloses a heterojunction bipolar transistor and a preparation method thereof. The heterojunction bipolar transistor comprises a semiconductor epitaxial structure, a base electrode, an emitter electrode and a collector electrode, the semiconductor epitaxial structure comprises a collector region, a base region and an emitter region which are sequentially stacked in the first direction, the base electrode is electrically connected with the base region, the emitter electrode is electrically connected with the emitter region, and the collector region is electrically connected with the collector region. The collector electrode is electrically connected with the collector region, the base region comprises a first base region and a second base region, the first base region is arranged on the collector region in a stacked mode, the second base region and the emitter region are arranged on the first base region, the base electrode is arranged on the second base region, and the collector electrode is electrically connected with the collector region. The doping type of the second base region is the same as that of the first base region, and the doping concentration of the second base region is greater than that of the first base region. According to the invention, the ohmic contact resistance of the p-type base region is reduced through the base region formed by secondary epitaxy.

Description

Technical Field

[0001] The present invention relates to a heterojunction bipolar transistor (HBT) and a preparation method thereof, and in particular to a group III nitride heterojunction bipolar transistor (HBT) with low etching damage and a high conductivity base region and a preparation method thereof, belonging to the technical field of semiconductor electronic devices. Background Art

[0002] As one of the typical representatives of III-nitride semiconductors, i.e., the third-generation semiconductors, GaN has the advantages of wide bandgap, high breakdown field strength, and high operating temperature. The HBT device based on the n-(Al)GaN / p-(In)GaN / n-GaN heterojunction has the advantages of high linearity, high power density, and high threshold voltage stability. It can meet the current communication field's demand for high transmission rate and large pulse width of RF PA. Therefore, it has broad application prospects in consumer electronics, 5G base stations, radar communications and other fields. In practical applications, the large base resistance limits the output power and operating frequency of the device, so reducing the base resistance is an urgent problem to be solved. Contact resistance + body resistance, body resistance is reduced by repairing

[0003] like Figure 1 The figure shows a typical npn-type GaN HBT device structure. In the preparation process, dry etching is usually used to remove part of the n-type emitter region to expose the p-type base region. This process will introduce donor-type nitrogen (N) vacancy defects in the base region to compensate for the majority holes in the base region, increase the contact resistance and lateral expansion resistance of the device base region, and lead to high knee voltage and large on-resistance of the device, which seriously affects the output power, maximum oscillation frequency, and reliability of the device. In addition, the etching damage caused by dry etching on the surface of the base region will increase the surface recombination of minority carriers in the base region, thereby reducing the base-collector current and causing a significant decrease in the current gain of the device. Therefore, how to solve the etching damage on the surface of the base region caused by dry etching in the preparation of HBT has become the key to improving the performance of nitride semiconductor HBT devices.

[0004] At present, there are usually two ways to solve the impact of base etching damage on GaN HBT. One is to use alkaline solutions such as tetramethylammonium hydroxide (TMAH) and potassium hydroxide (KOH) to corrode the surface damage layer of p-type GaN-based materials to achieve the purpose of repairing partial etching damage. The second is to use SiO2 on the p-type base material. 2 As a patterned mask, it is used to selectively grow n-type emitter material.

[0005] However, the repair effect of alkaline solution on etching damage is limited and the repair effect is not ideal. Specifically, the etched epitaxial wafer is immersed in an alkaline solution such as TMAH and KOH for a period of time under heating conditions to remove some surface damage. However, dry etching creates an N vacancy damage layer of about tens of nanometers near the p-(In)GaN surface, and the process gas used for dry etching, such as BCl 3 The plasma generated by the electric field will produce an ion implantation effect in the etching area under the action of electric field acceleration, so that a certain dose of etching gas atoms such as B, Cl, etc. exist within tens of nanometers near the surface. These etching damages and implanted ions will compensate for the majority holes in p-(In)GaN, but it is difficult to completely remove them by wet etching.

[0006] Secondary epitaxy will introduce high concentrations of impurities and vacancy defects at the pn junction interface between the emitter and base regions, causing leakage at the pn junction and significantly affecting the reliability of the device. 2 The n-type emitter region is selectively grown on the p-type base region using dielectrics as masks. This solution has problems such as contamination by impurities such as Si, O, and C at the secondary epitaxial interface and poor material quality, which can easily lead to leakage of the emitter-base pn junction, increasing the power consumption of the device during operation. Summary of the invention

[0007] The main purpose of the present invention is to provide a heterojunction bipolar transistor and a method for preparing the same, thereby overcoming the deficiencies in the prior art.

[0008] In order to achieve the above-mentioned invention object, the technical solution adopted by the present invention includes:

[0009] On the one hand, the present invention provides a heterojunction bipolar transistor, including a semiconductor epitaxial structure and a base, an emitter and a collector. The semiconductor epitaxial structure includes a collector region, a base region and an emitter region stacked in sequence along a first direction, the base is electrically connected to the base region, the emitter is electrically connected to the emitter region, and the collector is electrically connected to the collector region. The base region includes a first base region and a second base region, the first base region is stacked on the collector region, the second base region and the emitter region are arranged on the first base region, and the base is arranged on the second base region, wherein the second base region has the same doping type as the first base region, and the doping concentration of the second base region is greater than the doping concentration of the first base region.

[0010] On the other hand, the present invention also provides a method for preparing a heterojunction bipolar transistor, including the steps of preparing a semiconductor epitaxial structure and preparing a base, an emitter and a collector matched with the semiconductor epitaxial structure, wherein the semiconductor epitaxial structure includes a collector region, a base region and an emitter region stacked in sequence along a first direction, the base is electrically connected to the base region, the emitter is electrically connected to the emitter region, the collector is electrically connected to the collector region, the base region includes a first base region and a second base region, and the steps of preparing the semiconductor epitaxial structure include:

[0011] The first base region is formed on the collector region, and the second base region and the emitter region are formed on the first base region, wherein the second base region has the same doping type as the first base region and the doping concentration of the second base region is greater than the doping concentration of the first base region, wherein the base is electrically connected to the second base region.

[0012] Compared with the prior art, the advantages of the present invention include:

[0013] 1) A heterojunction bipolar transistor provided by the present invention exposes a first base region by dry etching, and then a second base region is secondary epitaxially grown as an ohmic contact layer. To ensure that the base realizes ohmic contact, the second base region of the secondary epitaxial growth is heavily doped (1×10 19 -5×10 20 cm -3 ), thereby reducing the ohmic contact resistance of the p-type base region, wherein the secondary epitaxy is to convert the Schottky contact of the base into an ohmic contact, and the heavy doping is to reduce the contact resistance.

[0014] 2) A heterojunction bipolar transistor provided by the present invention repairs etching damage through in-situ heat treatment, and uses active N atoms at high temperature to fill donor-type N vacancies introduced in the p-type base region by dry etching, thereby reducing self-compensation of the p-type base region, greatly reducing the base resistance of the HBT, and improving the current driving capability of the device.

[0015] 3) The heterojunction bipolar transistor provided by the present invention prepares GaN HBT into a vertical structure device, which solves the heat dissipation problem of the device and further improves the power density of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 It is a schematic diagram of the structure of an npn-type GaN HBT device in the prior art;

[0017] Figure 2 A schematic diagram of the epitaxial structure of an npn-type GaN HBT provided in a typical implementation case of the present invention;

[0018] Figure 3It is a schematic diagram of the structure of an npn-type GaN HBT after the emission region is defined in a typical implementation case of the present invention;

[0019] Figure 4 This is a schematic diagram of the structure after the secondary epitaxial ohmic contact layer is formed on the entire surface in a typical implementation case of the present invention;

[0020] Figure 5 It is a schematic structural diagram of the deposition of mask patterns before the secondary epitaxial ohmic contact layer in a typical implementation case of the present invention;

[0021] Figure 6 It is a schematic diagram of the structure of an npn-type GaN HBT after a secondary epitaxial ohmic contact layer in a typical implementation case of the present invention;

[0022] Figure 7 It is a schematic diagram of the structure of an npn-type GaN HBT after collector region window etching in a typical implementation case of the present invention;

[0023] Figure 8 It is a schematic diagram of the structure of an npn-type GaN HBT prepared based on secondary epitaxy and MOCVD repair etching damage technology in a typical implementation case of the present invention;

[0024] Fig. 9 It is a schematic diagram of the structure of the isolation layer deposition and window opening in a typical implementation case of the present invention;

[0025] Fig.10 It is a schematic diagram of the structure of bonding a GaN HBT device to a transfer substrate in a typical implementation case of the present invention;

[0026] Fig.11 It is a schematic diagram of the structure after the substrate is removed and the collector electrode is deposited in a typical implementation case of the present invention;

[0027] Fig.12 It is a schematic diagram of the structure of connecting the lead pad to the base in a typical implementation case of the present invention;

[0028] Fig.13 This is a schematic diagram of the epitaxial structure after the collector region mesa is formed in Comparative Example 1. DETAILED DESCRIPTION

[0029] In view of the deficiencies in the prior art, the inventor of this case has proposed the technical solution of the present invention after long-term research and extensive practice. The technical solution, its implementation process and principle will be further explained as follows.

[0030] On the one hand, the present invention provides a heterojunction bipolar transistor, including a semiconductor epitaxial structure and a base, an emitter and a collector. The semiconductor epitaxial structure includes a collector region, a base region and an emitter region stacked in sequence along a first direction, the base is electrically connected to the base region, the emitter is electrically connected to the emitter region, and the collector is electrically connected to the collector region. The base region includes a first base region and a second base region, the first base region is stacked on the collector region, the second base region and the emitter region are arranged on the first base region, and the base is arranged on the second base region, wherein the second base region has the same doping type as the first base region, and the doping concentration of the second base region is greater than the doping concentration of the first base region.

[0031] The base of a conventional GaN-based HBT device that does not include a second base region is a Schottky contact, which will generate an additional large voltage drop when the base is working. In order to eliminate this additional voltage drop, the present invention sets a second base region, the main function of which is to eliminate the N vacancy etching damage at the base, convert the Schottky contact into an ohmic contact, so as to reduce the operating voltage of the base and improve the output capacity of the device.

[0032] Furthermore, the doping concentration of the second base region is 1×10 19 -5×10 20 cm -3 .

[0033] Furthermore, the doping concentration of the first base region is 5×10 18 -3×10 19 cm -3 .

[0034] Furthermore, the ratio of the thickness of the second base region to the thickness of the first base region is 0.1-2.

[0035] Furthermore, the thickness of the second base region is 50-200 nm.

[0036] Furthermore, the surface of the first base region has a first mesa, a groove-shaped structure and a second mesa arranged in sequence along a second direction, the second base region is arranged on the first mesa, the emitter region is arranged on the second mesa, and the second direction intersects with the first direction.

[0037] The reason for the groove structure on the surface of the base region is that after the secondary epitaxial contact layer is formed on the entire surface, the emitter region is buried under the ohmic contact layer, which makes it impossible to deposit the emitter metal. Therefore, the ohmic contact layer on the emitter region needs to be removed by etching. To ensure that the ohmic contact layer is completely etched away, a certain depth of overetching is required, so a groove structure is left in the base region.

[0038] Further, in the first direction, the height of the second table surface is greater than, less than or equal to the height of the first table surface.

[0039] Furthermore, a height difference between the second mesa and the first mesa is within ±200 nm.

[0040] Furthermore, in the first direction, a ratio of the depth of the groove structure to the thickness of the first base region is 0.01-0.8.

[0041] Furthermore, in the second direction, the width of the groove-like structure is 0.2-5 μm.

[0042] Furthermore, the collector region and the emitter region are of a first doping type, and the first base region and the second base region are of a second doping type.

[0043] Furthermore, one of the first doping type and the second doping type is p-type, and the other is n-type.

[0044] Furthermore, the materials of the collector region, the first base region and the emitter region all include III-V compounds.

[0045] Furthermore, the material of the second base region includes III-V compounds, metal oxides or diamond.

[0046] On the other hand, the present invention also provides a method for preparing a heterojunction bipolar transistor, including the steps of preparing a semiconductor epitaxial structure and preparing a base, an emitter and a collector matched with the semiconductor epitaxial structure, wherein the semiconductor epitaxial structure includes a collector region, a base region and an emitter region stacked in sequence along a first direction, the base is electrically connected to the base region, the emitter is electrically connected to the emitter region, the collector is electrically connected to the collector region, the base region includes a first base region and a second base region, and the steps of preparing the semiconductor epitaxial structure include:

[0047] The first base region is formed on the collector region, and the second base region and the emitter region are formed on the first base region, wherein the second base region has the same doping type as the first base region and the doping concentration of the second base region is greater than the doping concentration of the first base region, wherein the base is electrically connected to the second base region.

[0048] Furthermore, the step of preparing the semiconductor epitaxial structure includes:

[0049] Prepare a collector region and a first base region stacked in sequence along the first direction;

[0050] forming a groove-shaped structure on the surface of the first base region, wherein the groove-shaped structure separates the surface of the first base region into a first table surface and a second table surface spaced apart along a second direction, wherein the second direction intersects the first direction;

[0051] The second base region is formed on the first mesa, and the emitter region is formed on the second mesa.

[0052] Furthermore, in the first direction, the ratio of the depth of the groove structure to the thickness of the base region is 0.01-0.8.

[0053] Furthermore, in the second direction, the width of the groove-like structure is 0.2-5 μm.

[0054] Furthermore, the step of preparing the semiconductor epitaxial structure includes:

[0055] forming a collector region, a first base region and an emitter region sequentially stacked along the first direction;

[0056] Etching and removing a portion of the emitter region to expose a first region and a second region on the surface of the first base region, and etching and removing a portion of the first base region located in the second region to form the groove structure in the second region of the first base region;

[0057] The second base region is formed in a first area of ​​the first base region.

[0058] Furthermore, the step of preparing the semiconductor epitaxial structure further includes: repairing a first area on the surface of the first base region by an in-situ heat treatment repair method;

[0059] Furthermore, the doping concentration of the second base region is 1×10 19 -5×10 20 cm -3 .

[0060] Furthermore, the doping concentration of the first base region is 5×10 18 -3×10 19 cm -3 .

[0061] Furthermore, the ratio of the thickness of the second base region to the thickness of the first base region is 0.1-2.

[0062] Furthermore, the thickness of the second base region is 50-200 nm.

[0063] Furthermore, the collector region and the emitter region are of a first doping type, and the first base region and the second base region are of a second doping type.

[0064] Furthermore, one of the first doping type and the second doping type is p-type, and the other is n-type.

[0065] Furthermore, the materials of the collector region, the first base region and the emitter region all include III-V compounds.

[0066] Furthermore, the material of the second base region includes III-V compounds, metal oxides or diamond.

[0067] The technical solution, its implementation process and principles, etc. will be further explained below in conjunction with the accompanying drawings and specific implementation cases. Unless otherwise specified, the semiconductor epitaxial equipment and process conditions such as metal organic chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE), hydride vapor phase epitaxy (HVPE), inductively coupled plasma etching (ICP), ion beam etching (IBE), reactive ion etching (RIE), atomic layer etching (ALE), etc., and the metal deposition equipment and process conditions used in the present invention may be known to those skilled in the art, unless otherwise specified.

[0068] In a typical embodiment, a method for preparing a heterojunction bipolar transistor may include the following steps:

[0069] 1) A buffer layer 102, a first semiconductor layer 103, a second semiconductor layer 104, a third semiconductor layer 105 and a fourth semiconductor layer 106 are sequentially stacked on the substrate 101 to form a semiconductor epitaxial structure of an npn-type HBT, such as Figure 2 As shown, the first semiconductor layer 103 and the second semiconductor layer 104 serve together as a collector region, and the third semiconductor layer 103 is a first base region.

[0070] Specifically, the material of the substrate 101 can be sapphire (Al 2 O 3 ), SiC, GaN, A1N, ZnO, Si, GaP, InP or Ge, etc.

[0071] Specifically, the buffer layer 102, the first semiconductor layer 103, the second semiconductor layer 104, the third semiconductor layer 105 and the fourth semiconductor layer 106 can be formed by deposition, and the deposition method can be metal organic chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE), hydride vapor phase epitaxy (HVPE) and the like.

[0072] Specifically, the first semiconductor layer 103 may be a III-V compound semiconductor and may be doped with a first dopant. For example, the material of the first semiconductor layer 103 may be In x1 Aly1 Ga 1-x1-y1 The semiconductor material composed of N (0≤x1≤1, 0≤y1≤1, 0≤x1+y1≤1) has good conductivity, and the first dopant can be an n-type dopant such as Si, Ge, Sn, Se or Te. When the first dopant is an n-type dopant, the first semiconductor layer 103 doped with the first dopant is an n-type semiconductor layer.

[0073] Specifically, the second semiconductor layer 104 may be a III-V compound semiconductor and may be doped with a first dopant. For example, the material of the second semiconductor layer 104 may be In x2 Al y2 Ga 1-x2-y2 The semiconductor material composed of N (0≤x2≤1, 0≤y2≤1, 0≤x2+y2≤1) has good voltage resistance. When the first dopant is an n-type dopant, the second semiconductor layer 104 doped with the first dopant can be an n-type semiconductor layer.

[0074] Specifically, the third semiconductor layer 105 may be a III-V compound semiconductor and may be doped with a second dopant. For example, the material of the third semiconductor layer 105 may be In x3 Al y3 Ga 1-x3-y3 The semiconductor material composed of N (0≤x3≤1, 0≤y3≤1, 0≤x3+y3≤1) has good conductivity and a long minority carrier lifetime. In addition, the second dopant can be a p-type dopant such as Mg, Zn, Ca, Sr or Ba. When the second dopant is a p-type dopant, the third semiconductor layer 105 doped with the second dopant can be a p-type semiconductor layer.

[0075] Specifically, the third semiconductor layer 105 includes any one of a uniform dopant In / Al / Ga content structure, a uniform dopant gradient In / Al / Ga content, a gradient dopant uniform In / Al / Ga content, or a superlattice structure, and the structure of the third semiconductor layer 105 is not limited thereto.

[0076] Specifically, the fourth semiconductor layer 106 may be a III-V compound semiconductor and may be doped with a first dopant. For example, the material of the fourth semiconductor layer 106 is In x4 Al y4 Ga 1-x4-y4 The semiconductor material composed of N (0≤x4≤1, 0≤y4≤1, 0≤x4+y4≤1) has good conductivity. When the first dopant is an n-type dopant, the fourth semiconductor layer 106 doped with the first dopant can be an n-type semiconductor layer.

[0077] 2) etching and removing a portion of the third semiconductor layer 105 and the fourth semiconductor layer 106 to form a base region terrace (i.e., the aforementioned first terrace), such as Figure 3 shown.

[0078] Specifically, the etching process may be selected from inductively coupled plasma etching (ICP), ion beam etching (IBE), reactive ion etching (RIE), atomic layer etching (ALE), etc.

[0079] 3) An ohmic contact layer 107 is formed on the base region terrace as a second base region, such as Figure 6 shown.

[0080] Specifically, the ohmic contact layer 107 may be formed by MOCVD, CVD, MBE, HVPE, sputtering, ion-assisted deposition (IAD), pulsed laser deposition (PLD), or the like.

[0081] Specifically, the material of the ohmic contact layer 107 may be a III-V compound semiconductor material, a metal oxide, or diamond, and may be doped with a second dopant. x Al y Ga 1-x-y N (0≤x≤1, 0≤y≤1, 0≤x+y≤1), NiO, ZnO or diamond, etc. In order to achieve good ohmic contact, the ohmic contact layer 107 needs to be heavily doped. Specifically, the doping concentration of the second dopant of the ohmic contact layer 107 is 1×10 19 -5×10 20 em -3 .

[0082] Specifically, an ohmic contact layer 107 may be formed on the entire surface of the epitaxial structure, such as Figure 4 As shown, a portion of the ohmic contact layer 107 is then etched away to form Figure 6 Alternatively, a mask 108 covering the fourth semiconductor layer 106 and a portion of the third semiconductor layer 105 may be formed on the surface of the epitaxial structure, as shown in FIG. Figure 5 As shown, an ohmic contact layer 107 is then formed on the surface of the epitaxial structure, and the mask is removed to form Figure 6 The structure shown in FIG. 1 is made of SiO 2 、Si x O y 、Si 3 N 4， 、Si x N y， 、SiO x N y 、Al 2 O 3, TiO 2 Or AlN, etc., the material selection of the mask 108 matches the deposition process of the ohmic contact layer 107.

[0083] 4) Fabricate a base 130, an emitter 140, and a collector 150, and electrically connect the base 130 to the ohmic contact layer 107, the emitter 140 to the fourth semiconductor layer 106, and the collector 150 to the first semiconductor layer 103, as shown in FIG. Figure 8 shown.

[0084] Specifically, step 4 may include:

[0085] 4.1) Etching and removing a portion of the ohmic contact layer 107, the third semiconductor layer 105, the second semiconductor layer 104, and the first semiconductor layer 103 to form a collector region terrace, such as Figure 7 Alternatively, the substrate 101 and the buffer layer 102 may be removed and the first semiconductor layer 103 may be directly exposed. Figure 7 It can be seen that the etched areas of the ohmic contact layer 107 , the third semiconductor layer 105 , the second semiconductor layer 104 , and the first semiconductor layer 103 are distributed around the reserved areas;

[0086] 4.2) A base electrode 130 is formed on the ohmic contact layer 107 , an emitter electrode 140 is formed on the fourth semiconductor layer 106 , and a collector electrode 150 is formed on the first semiconductor layer 103 .

[0087] Specifically, the material of the base 130, the emitter 140, and the collector 150 can be one metal material selected from Ag, Ni, Cr, Ti, Al, Rh, Pd, Ir, Sn, In, Ru, Mg, Zn, Pt, Mo, and ITO, or an alloy formed by two or more metal materials, so as to achieve low-resistance ohmic contact.

[0088] Specifically, the base 130, the emitter 140 and the collector 150 can be prepared simultaneously or separately. In addition, the materials of the base 130, the emitter 140 and the collector 150 can be the same or different.

[0089] In order to remove the ohmic contact layer covering the emitter area, there are two production methods: 1. Deposit the ohmic contact layer on the entire surface, and remove the ohmic contact layer on the side wall of the mesa and the emitter area by etching to avoid leakage caused by the ohmic contact layer; 2. Selectively deposit the ohmic contact layer, and deposit a mask dielectric on the side wall of the mesa and the p-type and n-type layers close to the side wall, and use the mask dielectric to deposit the ohmic contact layer only in the p-type base electrode area.

[0090] It should be noted that the process of repairing etching damage by in-situ heat treatment can be completed before etching to the collector area mesa, or can be completed after etching to the collector area mesa, and the present invention is not limited thereto.

[0091] The present invention can be used for GaN HBT devices such as vertical structures and flip-chip structures that require high power and good heat dissipation performance.

[0092] It should be noted that the above scheme may also include more subsequent device processing techniques, such as depositing a passivation layer on the non-metallic area of ​​the device, and further leading the emitter, base, and collector metals to the coplanar waveguide wire structure after depositing the dielectric layer to form a RF performance test structure.

[0093] Example 1 (Full-surface secondary epitaxial deposition of an ohmic contact layer followed by dry etching to expose the emitter region to prepare a high-performance GaN HBT)

[0094] A method for preparing a heterojunction bipolar transistor comprises the following steps:

[0095] 1) Sequential growth of n-GaN / p-In on a silicon (111) substrate 0.05 Ga 0.95 The epitaxial structure of the npn-type HBT of N / n-GaN includes an AlN / AlGaN buffer layer, a 1μm non-intentionally doped GaN buffer layer, and a Si doping concentration of 2×10 18 cm -3 The n-type GaN collector region and Si doping concentration are 5×10 17 cm -3 The drift region and Mg doping concentration are 1×10 19 cm -3 p-type In 0.05 Ga 0.95 The doping concentration of N-base region and Si is 2×10 19 cm -3 The n-type GaN emitter region, such as Figure 2 shown.

[0096] It should be noted that when epitaxially growing GaN thin films on Si substrates, it is necessary to first grow a buffer layer to adjust the stress of the epitaxial layer, and then grow the epitaxial layer of the device. In this way, the material quality can be improved, thereby improving the device performance.

[0097] 2) After obtaining the complete epitaxial structure of npn-type HBT, the n-type GaN emitter region and p-type In are removed by ICP etching. 0.05 Ga 0.95 A part of the N base region forms a base mesa, such as Figure 3 shown.

[0098] 3) Deposit 50nm of Mg doping concentration of 6×10 19 cm -3 p-type In 0.05 Ga 0.95 N ohmic contact layer, such as Figure 4 shown.

[0099] 4) Remove p-type In by ICP etching 0.05 Ga 0.95 N ohmic contact layer, In 0.05 Ga 0.95 The N-base region, drift region and part of the n-type GaN collector region form the collector region table, such as Figure 7 shown.

[0100] 5) In heavily doped p-type In 0.05 Ga 0.95 A Ni / Au metal electrode with a thickness of 20 / 50nm is deposited on the N ohmic contact layer to achieve a low-resistance base ohmic contact, and a Cr / Au ohmic contact electrode with a thickness of 20 / 100nm is deposited on the n-type GaN emitter region and the n-type GaN collector region, respectively. Figure 8 shown.

[0101] In order to expose the n-type GaN emitter region, the p-type In 0.05 Ga 0.95 N ohmic contact layer and part of p-type In 0.05 Ga 0.95 The N-base region and the n-type GaN emitter region form an emitter window region, such as Figure 6 In addition, the etching process can be completed before or after etching to form the collector area mesa, and the present invention is not limited thereto. After etching, MOCVD in-situ heat treatment can be used to 3 The etching damage can be repaired in an environment, but the present invention is not limited to this.

[0102] It should be noted that because the emitter metal needs to be deposited on the n-type emitter region, if the p-type ohmic contact layer covers the emitter region, the emitter metal cannot be deposited directly on the emitter region. Therefore, it is necessary to use an etching method to remove the p-type ohmic contact layer covering the n-type emitter region. The purpose of over-etching is to ensure that the p-type ohmic contact layer is removed cleanly and does not affect the emitter contact quality.

[0103] In this embodiment, the secondary epitaxial heavily doped p-type ohmic contact layer can convert the traditional Schottky contact base into an ohmic contact base, eliminating the additional voltage drop caused by the Schottky contact; in addition, the in-situ heat treatment allows the active N atoms to fill the donor-type N vacancy defects, greatly reducing the base resistance. Finally, the turn-on voltage of the GaN HBT prepared in this embodiment is reduced from 6V to 3.4V, and the output current density is increased by nearly three orders of magnitude (0.2kA / cm 2 Increased to 14kA / cm 2 ).

[0104] Example 2 (Preparation of high performance GaN HBT by selectively depositing an ohmic contact layer)

[0105] A method for preparing a heterojunction bipolar transistor comprises the following steps:

[0106] 1) Using MOCVD process, n-GaN / p-In are grown sequentially on silicon (111) substrate 0.05 Ga 0.95 The epitaxial structure of the npn-type HBT of N / n-GaN includes an AlN / AlGaN buffer layer, a 1 μm thick unintentionally doped GaN buffer layer, and a Si doping concentration of 2×10 18 em -3 The n-type GaN collector region and Si lightly doped concentration are 5×10 17 em -3 The drift region and Mg doping concentration are 1×10 19 cm -3 p-type In 0.05 Ga 0.95 The doping concentration of N-base region and Si is 2×10 19 cm -3 The n-type GaN emitter region, such as Figure 2 shown.

[0107] 2) After obtaining the complete epitaxial structure of npn-type HBT, the n-type GaN emitter region and p-type In are removed by ICP etching. 0.05 Ga 0.95 A part of the N base region forms a base mesa, such as Figure 3 shown.

[0108] 3) In the preparation of p-type In 0.05 Ga 0.95 Before the N ohmic contact layer, SiO 2 Mask, such as Figure 5 shown.

[0109] 4) In SiO 2With the help of the mask, the p-type In 0.05 Ga 0.95 The N-base region is not covered by SiO 2 The area covered by the mask is deposited to form a 50nm thick Mg doping concentration of 6×10 19 cm -3 p-type In 0.05 Ga 0.95 N ohmic contact layer, then remove SiO 2 Mask, such as Figure 6 shown.

[0110] Before preparing the electrode, it is necessary to remove the SiO on the n-type GaN emitter region. 2 Mask, remove SiO 2 After masking, MOCVD in-situ heat treatment can be used. 3 The etching damage can be repaired in an environment, but the present invention is not limited thereto.

[0111] 5) Remove p-type In by ICP etching process 0.05 Ga 0.95 N ohmic contact layer, p-type In 0.05 Ga 0.95 The N-base region, drift region and part of the n-type GaN collector region form the collector region table, such as Figure 7 shown.

[0112] 6) In heavily doped p-type In 0.05 Ga 0.95 A Ni / Au metal electrode with a thickness of 20 / 50nm is deposited on the N ohmic contact layer to achieve a low-resistance base ohmic contact, and a Cr / Au ohmic contact electrode with a thickness of 20 / 100nm is deposited on the n-type GaN emitter region and the n-type GaN collector region, respectively. Figure 8 shown.

[0113] In this embodiment, the secondary epitaxial heavily doped p-type ohmic contact layer can convert the traditional Schottky contact base into an ohmic contact base, eliminating the additional voltage drop caused by the Schottky contact; in addition, the in-situ heat treatment allows the active N atoms to fill the donor-type N vacancy defects, greatly reducing the base resistance. The results show that the GaN HBT prepared in this embodiment also has a lower turn-on voltage and a higher output current density, and the turn-on voltage and output current density are close to those in Example 1.

[0114] Example 3 (Vertical Structure High Power GaN HBT)

[0115] This embodiment is a vertical structure GaN HBT prepared on the basis of Embodiment 1 or Embodiment 2. The vertical structure GaN HBT process is described below, but the present invention is not limited thereto. The present invention can be used in other GaN HBT devices including flip-chip structures that require high power and good heat dissipation.

[0116] 1) Optionally, a layer for connecting to the lead pad 180 (such as Fig.12 ) is connected to the conductive metal, which is optional (not shown in the figure) and can also be directly electrically connected to the pad 180 through the base electrode 130, but the present invention is not limited to this.

[0117] 2) Depositing an insulating layer (also referred to as an isolation layer, the same below) 109, the insulating layer 109 covers the base electrode 130, the emitter electrode 140 and the exposed epitaxial structure (including the sidewall of the mesa). The insulating layer 109 can be made of SiO 2 、Si x O y 、Si 3 N 4 、Si x N y 、SiO x N y 、Al 2 O 3 、TiO 2 , AlN and other insulating materials, the insulating layer can effectively achieve electrical isolation between the electrodes.

[0118] 3) Opening a window on the insulating layer 109 to expose the upper surface of the emitter region electrode 140 for electrically connecting the emitter region electrode 140 to the bonding substrate 170, such as Fig. 9 shown.

[0119] 4) Depositing a bonding barrier layer and a bonding layer 160 on the insulating layer 109 and the exposed emitter region electrode 140, and bonding with the bonding substrate 170 through a bonding process to achieve electrical connection. The bonding substrate can be made of AuSn, AgSn, CuSn, AuIn, NiSn, AuAu, AuSi, AlGe, etc., and the bonding layer can be made of Si, Ge, Cu, Mo, SiC, GaN, GaAs, MoCu alloy, etc. Fig.10 As shown, the present invention is not limited thereto.

[0120] 5) After bonding, the substrate 101 is removed by laser stripping, mechanical grinding, chemical etching or dry etching, and the exposed buffer layer 102 is removed by wet treatment or dry etching.

[0121] 6) Depositing collector region electrode 150 on n-type collector region 103, such as Fig.11As shown, the material of the collector region electrode 150 may be one or a combination of two or more materials including Ag, Ni, Cr, Ti, Al, Rh, Pd, Ir, Sn, In, Ru, Mg, Zn, Pt, Mo, ITO, etc. to achieve low-resistance ohmic contact.

[0122] 7) Make the base connection pad 180, the base electrode current is injected into the base 130 through the pad 180, and the emitter electrode current is injected into the emitter electrode 140 through the bonding substrate 170. After the device is bonded to the substrate 170, the heat generated in the working state can be conducted away through the bonding metal 160, which can greatly improve the device power and thermal stability.

[0123] In this embodiment, the vertical structure solves the heat dissipation problem of the device and further improves the device performance. The results show that the output current of the GaN HBT is increased by nearly two times to 30kA / cm 2 .

[0124] Comparative Example 1

[0125] A method for preparing a heterojunction bipolar transistor comprises the following steps:

[0126] 1) Sequential growth of n-GaN / p-In on a silicon (111) substrate 0.05 Ga 0.95 The epitaxial structure of the npn-type HBT of N / n-GaN includes an AlN / AlGaN buffer layer, a 1μm non-intentionally doped GaN buffer layer, and a Si doping concentration of 2×10 18 cm -3 The n-type GaN collector region and Si doping concentration are 5×10 17 cm -3 The drift region and Mg doping concentration are 1×10 19 cm -3 p-type In 0.05 Ga 0.95 N-base region, Si doping concentration is 2×10 19 cm -3 The n-type GaN emitter region, such as Figure 2 shown.

[0127] 2) After obtaining the complete npn-type HBT epitaxial structure, the n-type GaN emitter region and the p-type In are removed by ICP etching. 0.05 Ga 0.95 A part of the N base region forms a base mesa, such as Figure 3 shown.

[0128] 3) Remove In by ICP etching 0.05 Ga 0.95The N-base region, drift region and part of the n-type GaN collector region form the collector region table, such as Fig.13 shown.

[0129] 4) In 0.05 Ga 0.95 A Ni / Au metal electrode with a thickness of 20 / 50 nm is deposited on the N-base region, and a Cr / Au ohmic contact electrode with a thickness of 20 / 100 nm is deposited on the n-type GaN emitter region and the n-type GaN collector region, respectively.

[0130] In this comparative example, due to the etching damage, donor-type N vacancy defects are generated in the base region, which increases the base resistance and generates an additional Schottky barrier voltage drop at the base. The results show that the turn-on voltage of the GaN HBT prepared in this comparative example is 6V, and the output current density is 0.2kA / cm 2 .

[0131] Comparative Example 2

[0132] A method for preparing a heterojunction bipolar transistor comprises the following steps:

[0133] 1) Sequential growth of n-GaN / p-In on a silicon (111) substrate 0.05 Ga 0.95 The epitaxial structure of the npn-type HBT of N / n-GaN includes an AlN / AlGaN buffer layer, a 1μm unintentionally doped GaN buffer layer, and a Si doping concentration of 2×10 18 cm -3 The n-type GaN collector region and Si doping concentration are 5×10 17 cm -3 The drift region and Mg doping concentration are 1×10 19 cm -3 p-type In 0.05 Ga 0.95 The doping concentration of N-base region and Si is 2×10 19 cm -3 The n-type GaN emitter region, such as Figure 2 shown.

[0134] 2) After obtaining the complete npn-type HBT epitaxial structure, the n-type GaN emitter region and the p-type In are removed by ICP etching. 0.05 Ga 0.95 A part of the N base region forms a base mesa, such as Figure 3 shown.

[0135] 3) Deposit 50nm of Mg doping concentration of 6×10 19 cm -3 p-type In 0.05 Ga0.95 N ohmic contact layer, such as Figure 4 shown.

[0136] 4) In order to expose the n-type GaN emitter region, the p-type In 0.05 Ga 0.95 N ohmic contact layer and part of p-type In 0.05 Ga 0.95 The N-base region and the n-type GaN emitter region form an emitter window region, such as Figure 6 After etching, the etching damage was repaired by using a rapid annealing furnace at 500°C in an oxygen environment for 1 minute.

[0137] 5) Remove p-type In by ICP etching 0.05 Ga 0.95 N ohmic contact layer, In 0.05 Ga 0.95 The N-base region, drift region and part of the n-type GaN collector region form the collector region table, such as Figure 7 shown.

[0138] 6) In heavily doped p-type In 0.05 Ga 0.95 A Ni / Au metal electrode with a thickness of 20 / 50nm is deposited on the N ohmic contact layer to achieve a low-resistance base ohmic contact, and a Cr / Au ohmic contact electrode with a thickness of 20 / 100nm is deposited on the n-type GaN emitter region and the n-type GaN collector region, respectively. Figure 8 shown.

[0139] In this comparative case, since the in-situ heat treatment step is carried out in an oxygen environment, the donor-type N vacancies cannot be effectively filled, and the base resistance is still large. The results show that the turn-on voltage of the GaN HBT prepared in this comparative example is 5V, and the output current density is 1kA / cm 2 .

[0140] The heterojunction bipolar transistor provided by the present invention exposes a first base region by dry etching, and then a second base region is secondary epitaxially grown as an ohmic contact layer. To ensure that the base realizes ohmic contact, the second base region of the secondary epitaxial growth is heavily doped (1×10 19 -5×10 20 cm -3 ), thereby reducing the ohmic contact resistance of the p-type base region.

[0141] A heterojunction bipolar transistor provided by the present invention repairs etching damage by in-situ heat treatment, and uses active N atoms at high temperature to fill donor-type N vacancies introduced in the p-type base region by dry etching, thereby reducing self-compensation of the p-type base region, greatly reducing the base resistance of the HBT, and improving the current driving capability of the device.

[0142] The invention provides a heterojunction bipolar transistor, in which GaN HBT is prepared into a vertical structure device, thereby solving the heat dissipation problem of the device and further improving the power density of the device.

[0143] It should be understood that the above embodiments are only for illustrating the technical concept and features of the present invention, and their purpose is to enable people familiar with the technology to understand the content of the present invention and implement it accordingly, and they cannot be used to limit the protection scope of the present invention. Any equivalent changes or modifications made according to the spirit of the present invention should be included in the protection scope of the present invention.

Claims

1. A heterojunction bipolar transistor, comprising a semiconductor epitaxial structure and a base, an emitter and a collector, wherein the semiconductor epitaxial structure comprises a collector region, a base region and an emitter region stacked in sequence along a first direction, the base is electrically connected to the base region, the emitter is electrically connected to the emitter region, and the collector is electrically connected to the collector region, characterized in that: The base region includes a first base region and a second base region, the first base region is stacked on the collector region, the second base region and the emitter region are arranged on the first base region, and the base is arranged on the second base region, wherein the second base region has the same doping type as the first base region, and the doping concentration of the second base region is greater than the doping concentration of the first base region.

2. The heterojunction bipolar transistor according to claim 1, characterized in that: The doping concentration of the second base region is 1×10 19 -5×10 20 cm -3 ; Preferably, the doping concentration of the first base region is 5×10 18 -3×10 19 cm -3 . Preferably, the ratio of the thickness of the second base region to the thickness of the first base region is 0.1-2. Preferably, the thickness of the second base region is 50-200 nm.

3. The heterojunction bipolar transistor according to claim 1 or 2, characterized in that: The first base region comprises a first mesa, a groove-shaped structure and a second mesa arranged in sequence along a second direction, the second base region is arranged on the first mesa, the emitter region is arranged on the second mesa, and the second direction intersects with the first direction; Preferably, in the first direction, the height of the second mesa is greater than, less than or equal to the height of the first mesa; preferably, the height difference between the second mesa and the first mesa is within ±200 nm; Preferably, in the first direction, the ratio of the depth of the groove structure to the thickness of the first base region is 0.01-0.8; Preferably, in the second direction, the width of the groove-like structure is 0.2-5 μm.

4. The heterojunction bipolar transistor according to claim 1, characterized in that: The collector region and the emitter region are of a first doping type, and the first base region and the second base region are of a second doping type; Preferably, one of the first doping type and the second doping type is p-type, and the other is n-type.

5. The heterojunction bipolar transistor according to claim 1, characterized in that: The materials of the collector region, the first base region and the emitter region all include III-V compounds; Preferably, the material of the second base region includes III-V compounds, metal oxides or diamond.

6. A method for preparing a heterojunction bipolar transistor, comprising the steps of preparing a semiconductor epitaxial structure and preparing a base, an emitter and a collector matched with the semiconductor epitaxial structure, wherein the semiconductor epitaxial structure comprises a collector region, a base region and an emitter region stacked in sequence along a first direction, the base is electrically connected to the base region, the emitter is electrically connected to the emitter region, and the collector is electrically connected to the collector region, characterized in that: The base region includes a first base region and a second base region, and the steps of preparing the semiconductor epitaxial structure include: The first base region is formed on the collector region, and the second base region and the emitter region are formed on the first base region, wherein the second base region has the same doping type as the first base region and the doping concentration of the second base region is greater than the doping concentration of the first base region, wherein the base is electrically connected to the second base region.

7. The preparation method according to claim 6, characterized in that: The steps of preparing the semiconductor epitaxial structure include: Prepare a collector region and a first base region stacked in sequence along the first direction; forming a groove-shaped structure on the surface of the first base region, wherein the groove-shaped structure separates the surface of the first base region into a first mesa and a second mesa spaced apart along a second direction, wherein the second direction intersects the first direction; forming the second base region on the first mesa, and forming the emitter region on the second mesa; Preferably, in the first direction, the ratio of the depth of the groove structure to the thickness of the first base region is 0.01-0.8; Preferably, in the second direction, the width of the groove-like structure is 0.2-5 μm.

8. The preparation method according to claim 6, characterized in that: The steps of preparing the semiconductor epitaxial structure include: forming a collector region, a first base region and an emitter region sequentially stacked along the first direction; Etching and removing a portion of the emitter region to expose a first region and a second region on the surface of the first base region, and etching and removing a portion of the first base region located in the second region to form the groove structure in the second region of the first base region; forming the second base region in a first area of ​​the first base region; Preferably, the step of preparing the semiconductor epitaxial structure further comprises: repairing the first area on the surface of the first base region by an in-situ heat treatment repair method.

9. The preparation method according to claim 6, characterized in that: The doping concentration of the second base region is 1×10 19 -5×10 20 cm -3 ; Preferably, the doping concentration of the first base region is 5×10 18 -3×10 19 cm -3 . Preferably, the ratio of the thickness of the second base region to the thickness of the first base region is 0.1-2. Preferably, the thickness of the second base region is 50-200 nm.

10. The preparation method according to claim 6, characterized in that: The collector region and the emitter region are of a first doping type, and the first base region and the second base region are of a second doping type; Preferably, one of the first doping type and the second doping type is p-type, and the other is n-type; Preferably, the materials of the collector region, the first base region and the emitter region all include III-V compounds; Preferably, the material of the second base region includes III-V compounds, metal oxides or diamond.

Images